ioat_hw.h revision 289912
1287117Scem/*- 2287117Scem * Copyright (C) 2012 Intel Corporation 3287117Scem * All rights reserved. 4287117Scem * 5287117Scem * Redistribution and use in source and binary forms, with or without 6287117Scem * modification, are permitted provided that the following conditions 7287117Scem * are met: 8287117Scem * 1. Redistributions of source code must retain the above copyright 9287117Scem * notice, this list of conditions and the following disclaimer. 10287117Scem * 2. Redistributions in binary form must reproduce the above copyright 11287117Scem * notice, this list of conditions and the following disclaimer in the 12287117Scem * documentation and/or other materials provided with the distribution. 13287117Scem * 14287117Scem * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15287117Scem * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16287117Scem * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17287117Scem * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18287117Scem * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19287117Scem * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20287117Scem * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21287117Scem * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22287117Scem * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23287117Scem * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24287117Scem * SUCH DAMAGE. 25287117Scem */ 26287117Scem 27287117Scem__FBSDID("$FreeBSD: head/sys/dev/ioat/ioat_hw.h 289912 2015-10-24 23:46:32Z cem $"); 28287117Scem 29287117Scem#ifndef __IOAT_HW_H__ 30287117Scem#define __IOAT_HW_H__ 31287117Scem 32287117Scem#define IOAT_MAX_CHANNELS 32 33287117Scem 34287117Scem#define IOAT_CHANCNT_OFFSET 0x00 35287117Scem 36287117Scem#define IOAT_XFERCAP_OFFSET 0x01 37289732Scem/* Only bits [4:0] are valid. */ 38289732Scem#define IOAT_XFERCAP_VALID_MASK 0x1f 39287117Scem 40287117Scem#define IOAT_GENCTRL_OFFSET 0x02 41287117Scem 42287117Scem#define IOAT_INTRCTRL_OFFSET 0x03 43287117Scem#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 44287117Scem 45287117Scem#define IOAT_ATTNSTATUS_OFFSET 0x04 46287117Scem 47287117Scem#define IOAT_CBVER_OFFSET 0x08 48287117Scem 49287117Scem#define IOAT_VER_3_0 0x30 50287117Scem#define IOAT_VER_3_3 0x33 51287117Scem 52287117Scem#define IOAT_INTRDELAY_OFFSET 0x0C 53287117Scem 54287117Scem#define IOAT_CS_STATUS_OFFSET 0x0E 55287117Scem 56287117Scem#define IOAT_DMACAPABILITY_OFFSET 0x10 57287117Scem 58287117Scem/* DMA Channel Registers */ 59287117Scem#define IOAT_CHANCTRL_OFFSET 0x80 60287117Scem#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 61287117Scem#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 62287117Scem#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 63287117Scem#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 64287117Scem#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 65287117Scem#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 66287117Scem#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 67287117Scem#define IOAT_CHANCTRL_INT_REARM 0x0001 68287117Scem#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 69287117Scem IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 70287117Scem 71287117Scem#define IOAT_CHANCMD_OFFSET 0x84 72287117Scem#define IOAT_CHANCMD_RESET 0x20 73287117Scem#define IOAT_CHANCMD_SUSPEND 0x04 74287117Scem 75287117Scem#define IOAT_DMACOUNT_OFFSET 0x86 76287117Scem 77287117Scem#define IOAT_CHANSTS_OFFSET_LOW 0x88 78287117Scem#define IOAT_CHANSTS_OFFSET_HIGH 0x8C 79287117Scem#define IOAT_CHANSTS_OFFSET 0x88 80287117Scem 81287117Scem#define IOAT_CHANSTS_STATUS 0x7ULL 82287117Scem#define IOAT_CHANSTS_ACTIVE 0x0 83287117Scem#define IOAT_CHANSTS_IDLE 0x1 84287117Scem#define IOAT_CHANSTS_SUSPENDED 0x2 85287117Scem#define IOAT_CHANSTS_HALTED 0x3 86287117Scem 87287117Scem#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL 88287117Scem#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL 89287117Scem 90287117Scem#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) 91287117Scem 92287117Scem#define IOAT_CHAINADDR_OFFSET_LOW 0x90 93287117Scem#define IOAT_CHAINADDR_OFFSET_HIGH 0x94 94287117Scem 95287117Scem#define IOAT_CHANCMP_OFFSET_LOW 0x98 96287117Scem#define IOAT_CHANCMP_OFFSET_HIGH 0x9C 97287117Scem 98287117Scem#define IOAT_CHANERR_OFFSET 0xA8 99287117Scem 100289912Scem#define IOAT_CHANERR_XSADDERR (1 << 0) 101289912Scem#define IOAT_CHANERR_XDADDERR (1 << 1) 102289912Scem#define IOAT_CHANERR_NDADDERR (1 << 2) 103289912Scem#define IOAT_CHANERR_DERR (1 << 3) 104289912Scem#define IOAT_CHANERR_CHADDERR (1 << 4) 105289912Scem#define IOAT_CHANERR_CCMDERR (1 << 5) 106289912Scem#define IOAT_CHANERR_CUNCORERR (1 << 6) 107289912Scem#define IOAT_CHANERR_DUNCORERR (1 << 7) 108289912Scem#define IOAT_CHANERR_RDERR (1 << 8) 109289912Scem#define IOAT_CHANERR_WDERR (1 << 9) 110289912Scem#define IOAT_CHANERR_DCERR (1 << 10) 111289912Scem#define IOAT_CHANERR_DXSERR (1 << 11) 112289912Scem#define IOAT_CHANERR_CMPADDERR (1 << 12) 113289912Scem#define IOAT_CHANERR_INTCFGERR (1 << 13) 114289912Scem#define IOAT_CHANERR_SEDERR (1 << 14) 115289912Scem#define IOAT_CHANERR_UNAFFERR (1 << 15) 116289912Scem#define IOAT_CHANERR_CXPERR (1 << 16) 117289912Scem/* Reserved. (1 << 17) */ 118289912Scem#define IOAT_CHANERR_DCNTERR (1 << 18) 119289912Scem#define IOAT_CHANERR_DIFFERR (1 << 19) 120289912Scem#define IOAT_CHANERR_GTVERR (1 << 20) 121289912Scem#define IOAT_CHANERR_ATVERR (1 << 21) 122289912Scem#define IOAT_CHANERR_RTVERR (1 << 22) 123289912Scem#define IOAT_CHANERR_BBERR (1 << 23) 124289912Scem#define IOAT_CHANERR_RDIFFERR (1 << 24) 125289912Scem#define IOAT_CHANERR_RGTVERR (1 << 25) 126289912Scem#define IOAT_CHANERR_RATVERR (1 << 26) 127289912Scem#define IOAT_CHANERR_RRTVERR (1 << 27) 128289912Scem 129287117Scem#define IOAT_CFG_CHANERR_INT_OFFSET 0x180 130287117Scem#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184 131287117Scem 132287117Scem#define IOAT_MIN_ORDER 4 133287117Scem#define IOAT_MAX_ORDER 16 134287117Scem 135287117Scem#endif /* __IOAT_HW_H__ */ 136