ioat_hw.h revision 287117
1219974Smav/*- 2219974Smav * Copyright (C) 2012 Intel Corporation 3234601Smav * All rights reserved. 4219974Smav * 5219974Smav * Redistribution and use in source and binary forms, with or without 6219974Smav * modification, are permitted provided that the following conditions 7219974Smav * are met: 8219974Smav * 1. Redistributions of source code must retain the above copyright 9219974Smav * notice, this list of conditions and the following disclaimer. 10219974Smav * 2. Redistributions in binary form must reproduce the above copyright 11219974Smav * notice, this list of conditions and the following disclaimer in the 12219974Smav * documentation and/or other materials provided with the distribution. 13219974Smav * 14219974Smav * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15219974Smav * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16219974Smav * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17219974Smav * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18219974Smav * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19219974Smav * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20219974Smav * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21219974Smav * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22219974Smav * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23219974Smav * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24219974Smav * SUCH DAMAGE. 25219974Smav */ 26219974Smav 27219974Smav__FBSDID("$FreeBSD: head/sys/dev/ioat/ioat_hw.h 287117 2015-08-24 19:32:03Z cem $"); 28219974Smav 29219974Smav#ifndef __IOAT_HW_H__ 30219974Smav#define __IOAT_HW_H__ 31219974Smav 32219974Smav#define IOAT_MAX_CHANNELS 32 33219974Smav 34219974Smav#define IOAT_CHANCNT_OFFSET 0x00 35219974Smav 36219974Smav#define IOAT_XFERCAP_OFFSET 0x01 37219974Smav 38219974Smav#define IOAT_GENCTRL_OFFSET 0x02 39219974Smav 40219974Smav#define IOAT_INTRCTRL_OFFSET 0x03 41219974Smav#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 42219974Smav 43219974Smav#define IOAT_ATTNSTATUS_OFFSET 0x04 44219974Smav 45219974Smav#define IOAT_CBVER_OFFSET 0x08 46219974Smav 47219974Smav#define IOAT_VER_3_0 0x30 48219974Smav#define IOAT_VER_3_3 0x33 49219974Smav 50219974Smav#define IOAT_INTRDELAY_OFFSET 0x0C 51219974Smav 52219974Smav#define IOAT_CS_STATUS_OFFSET 0x0E 53219974Smav 54219974Smav#define IOAT_DMACAPABILITY_OFFSET 0x10 55219974Smav 56219974Smav/* DMA Channel Registers */ 57219974Smav#define IOAT_CHANCTRL_OFFSET 0x80 58219974Smav#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 59219974Smav#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 60219974Smav#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 61219974Smav#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 62219974Smav#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 63219974Smav#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 64219974Smav#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 65219974Smav#define IOAT_CHANCTRL_INT_REARM 0x0001 66219974Smav#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 67219974Smav IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 68219974Smav 69219974Smav#define IOAT_CHANCMD_OFFSET 0x84 70219974Smav#define IOAT_CHANCMD_RESET 0x20 71219974Smav#define IOAT_CHANCMD_SUSPEND 0x04 72219974Smav 73219974Smav#define IOAT_DMACOUNT_OFFSET 0x86 74219974Smav 75219974Smav#define IOAT_CHANSTS_OFFSET_LOW 0x88 76219974Smav#define IOAT_CHANSTS_OFFSET_HIGH 0x8C 77219974Smav#define IOAT_CHANSTS_OFFSET 0x88 78219974Smav 79219974Smav#define IOAT_CHANSTS_STATUS 0x7ULL 80219974Smav#define IOAT_CHANSTS_ACTIVE 0x0 81219974Smav#define IOAT_CHANSTS_IDLE 0x1 82219974Smav#define IOAT_CHANSTS_SUSPENDED 0x2 83219974Smav#define IOAT_CHANSTS_HALTED 0x3 84219974Smav 85219974Smav#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL 86219974Smav#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL 87219974Smav 88219974Smav#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) 89219974Smav 90219974Smav#define IOAT_CHAINADDR_OFFSET_LOW 0x90 91219974Smav#define IOAT_CHAINADDR_OFFSET_HIGH 0x94 92219974Smav 93219974Smav#define IOAT_CHANCMP_OFFSET_LOW 0x98 94219974Smav#define IOAT_CHANCMP_OFFSET_HIGH 0x9C 95219974Smav 96219974Smav#define IOAT_CHANERR_OFFSET 0xA8 97219974Smav 98219974Smav#define IOAT_CFG_CHANERR_INT_OFFSET 0x180 99219974Smav#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184 100219974Smav 101219974Smav#define IOAT_MIN_ORDER 4 102219974Smav#define IOAT_MAX_ORDER 16 103219974Smav 104219974Smav#endif /* __IOAT_HW_H__ */ 105219974Smav