ioat.c revision 290229
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ioat/ioat.c 290229 2015-10-31 20:38:06Z cem $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <sys/ioccom.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/module.h> 39#include <sys/mutex.h> 40#include <sys/rman.h> 41#include <sys/sbuf.h> 42#include <sys/sysctl.h> 43#include <sys/time.h> 44#include <dev/pci/pcireg.h> 45#include <dev/pci/pcivar.h> 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <machine/stdarg.h> 49 50#include "ioat.h" 51#include "ioat_hw.h" 52#include "ioat_internal.h" 53 54#define IOAT_INTR_TIMO (hz / 10) 55#define IOAT_REFLK (&ioat->submit_lock) 56 57static int ioat_probe(device_t device); 58static int ioat_attach(device_t device); 59static int ioat_detach(device_t device); 60static int ioat_setup_intr(struct ioat_softc *ioat); 61static int ioat_teardown_intr(struct ioat_softc *ioat); 62static int ioat3_attach(device_t device); 63static int ioat_start_channel(struct ioat_softc *ioat); 64static int ioat_map_pci_bar(struct ioat_softc *ioat); 65static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 66 int error); 67static void ioat_interrupt_handler(void *arg); 68static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 69static int chanerr_to_errno(uint32_t); 70static void ioat_process_events(struct ioat_softc *ioat); 71static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 72static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 73static void ioat_free_ring(struct ioat_softc *, uint32_t size, 74 struct ioat_descriptor **); 75static void ioat_free_ring_entry(struct ioat_softc *ioat, 76 struct ioat_descriptor *desc); 77static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 78 int mflags); 79static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 80static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 81 uint32_t index); 82static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 83 uint32_t size, boolean_t need_dscr, int mflags); 84static int ring_grow(struct ioat_softc *, uint32_t oldorder, 85 struct ioat_descriptor **); 86static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 87 struct ioat_descriptor **); 88static void ioat_halted_debug(struct ioat_softc *, uint32_t); 89static void ioat_timer_callback(void *arg); 90static void dump_descriptor(void *hw_desc); 91static void ioat_submit_single(struct ioat_softc *ioat); 92static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 93 int error); 94static int ioat_reset_hw(struct ioat_softc *ioat); 95static void ioat_setup_sysctl(device_t device); 96static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 97static inline struct ioat_softc *ioat_get(struct ioat_softc *, 98 enum ioat_ref_kind); 99static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 100static inline void _ioat_putn(struct ioat_softc *, uint32_t, 101 enum ioat_ref_kind, boolean_t); 102static inline void ioat_putn(struct ioat_softc *, uint32_t, 103 enum ioat_ref_kind); 104static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106static void ioat_drain_locked(struct ioat_softc *); 107 108#define ioat_log_message(v, ...) do { \ 109 if ((v) <= g_ioat_debug_level) { \ 110 device_printf(ioat->device, __VA_ARGS__); \ 111 } \ 112} while (0) 113 114MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 115SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 116 117static int g_force_legacy_interrupts; 118SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 119 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 120 121int g_ioat_debug_level = 0; 122SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 123 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 124 125/* 126 * OS <-> Driver interface structures 127 */ 128static device_method_t ioat_pci_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, ioat_probe), 131 DEVMETHOD(device_attach, ioat_attach), 132 DEVMETHOD(device_detach, ioat_detach), 133 { 0, 0 } 134}; 135 136static driver_t ioat_pci_driver = { 137 "ioat", 138 ioat_pci_methods, 139 sizeof(struct ioat_softc), 140}; 141 142static devclass_t ioat_devclass; 143DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 144 145/* 146 * Private data structures 147 */ 148static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 149static int ioat_channel_index = 0; 150SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 151 "Number of IOAT channels attached"); 152 153static struct _pcsid 154{ 155 u_int32_t type; 156 const char *desc; 157} pci_ids[] = { 158 { 0x34308086, "TBG IOAT Ch0" }, 159 { 0x34318086, "TBG IOAT Ch1" }, 160 { 0x34328086, "TBG IOAT Ch2" }, 161 { 0x34338086, "TBG IOAT Ch3" }, 162 { 0x34298086, "TBG IOAT Ch4" }, 163 { 0x342a8086, "TBG IOAT Ch5" }, 164 { 0x342b8086, "TBG IOAT Ch6" }, 165 { 0x342c8086, "TBG IOAT Ch7" }, 166 167 { 0x37108086, "JSF IOAT Ch0" }, 168 { 0x37118086, "JSF IOAT Ch1" }, 169 { 0x37128086, "JSF IOAT Ch2" }, 170 { 0x37138086, "JSF IOAT Ch3" }, 171 { 0x37148086, "JSF IOAT Ch4" }, 172 { 0x37158086, "JSF IOAT Ch5" }, 173 { 0x37168086, "JSF IOAT Ch6" }, 174 { 0x37178086, "JSF IOAT Ch7" }, 175 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 176 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 177 178 { 0x3c208086, "SNB IOAT Ch0" }, 179 { 0x3c218086, "SNB IOAT Ch1" }, 180 { 0x3c228086, "SNB IOAT Ch2" }, 181 { 0x3c238086, "SNB IOAT Ch3" }, 182 { 0x3c248086, "SNB IOAT Ch4" }, 183 { 0x3c258086, "SNB IOAT Ch5" }, 184 { 0x3c268086, "SNB IOAT Ch6" }, 185 { 0x3c278086, "SNB IOAT Ch7" }, 186 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 187 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 188 189 { 0x0e208086, "IVB IOAT Ch0" }, 190 { 0x0e218086, "IVB IOAT Ch1" }, 191 { 0x0e228086, "IVB IOAT Ch2" }, 192 { 0x0e238086, "IVB IOAT Ch3" }, 193 { 0x0e248086, "IVB IOAT Ch4" }, 194 { 0x0e258086, "IVB IOAT Ch5" }, 195 { 0x0e268086, "IVB IOAT Ch6" }, 196 { 0x0e278086, "IVB IOAT Ch7" }, 197 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 198 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 199 200 { 0x2f208086, "HSW IOAT Ch0" }, 201 { 0x2f218086, "HSW IOAT Ch1" }, 202 { 0x2f228086, "HSW IOAT Ch2" }, 203 { 0x2f238086, "HSW IOAT Ch3" }, 204 { 0x2f248086, "HSW IOAT Ch4" }, 205 { 0x2f258086, "HSW IOAT Ch5" }, 206 { 0x2f268086, "HSW IOAT Ch6" }, 207 { 0x2f278086, "HSW IOAT Ch7" }, 208 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 209 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 210 211 { 0x0c508086, "BWD IOAT Ch0" }, 212 { 0x0c518086, "BWD IOAT Ch1" }, 213 { 0x0c528086, "BWD IOAT Ch2" }, 214 { 0x0c538086, "BWD IOAT Ch3" }, 215 216 { 0x6f508086, "BDXDE IOAT Ch0" }, 217 { 0x6f518086, "BDXDE IOAT Ch1" }, 218 { 0x6f528086, "BDXDE IOAT Ch2" }, 219 { 0x6f538086, "BDXDE IOAT Ch3" }, 220 221 { 0x00000000, NULL } 222}; 223 224/* 225 * OS <-> Driver linkage functions 226 */ 227static int 228ioat_probe(device_t device) 229{ 230 struct _pcsid *ep; 231 u_int32_t type; 232 233 type = pci_get_devid(device); 234 for (ep = pci_ids; ep->type; ep++) { 235 if (ep->type == type) { 236 device_set_desc(device, ep->desc); 237 return (0); 238 } 239 } 240 return (ENXIO); 241} 242 243static int 244ioat_attach(device_t device) 245{ 246 struct ioat_softc *ioat; 247 int error; 248 249 ioat = DEVICE2SOFTC(device); 250 ioat->device = device; 251 252 error = ioat_map_pci_bar(ioat); 253 if (error != 0) 254 goto err; 255 256 ioat->version = ioat_read_cbver(ioat); 257 if (ioat->version < IOAT_VER_3_0) { 258 error = ENODEV; 259 goto err; 260 } 261 262 error = ioat3_attach(device); 263 if (error != 0) 264 goto err; 265 266 error = pci_enable_busmaster(device); 267 if (error != 0) 268 goto err; 269 270 error = ioat_setup_intr(ioat); 271 if (error != 0) 272 goto err; 273 274 error = ioat_reset_hw(ioat); 275 if (error != 0) 276 goto err; 277 278 ioat_process_events(ioat); 279 ioat_setup_sysctl(device); 280 281 ioat->chan_idx = ioat_channel_index; 282 ioat_channel[ioat_channel_index++] = ioat; 283 ioat_test_attach(); 284 285err: 286 if (error != 0) 287 ioat_detach(device); 288 return (error); 289} 290 291static int 292ioat_detach(device_t device) 293{ 294 struct ioat_softc *ioat; 295 296 ioat = DEVICE2SOFTC(device); 297 298 ioat_test_detach(); 299 300 mtx_lock(IOAT_REFLK); 301 ioat->quiescing = TRUE; 302 ioat_channel[ioat->chan_idx] = NULL; 303 304 ioat_drain_locked(ioat); 305 mtx_unlock(IOAT_REFLK); 306 307 ioat_teardown_intr(ioat); 308 callout_drain(&ioat->timer); 309 310 pci_disable_busmaster(device); 311 312 if (ioat->pci_resource != NULL) 313 bus_release_resource(device, SYS_RES_MEMORY, 314 ioat->pci_resource_id, ioat->pci_resource); 315 316 if (ioat->ring != NULL) 317 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 318 319 if (ioat->comp_update != NULL) { 320 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 321 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 322 ioat->comp_update_map); 323 bus_dma_tag_destroy(ioat->comp_update_tag); 324 } 325 326 bus_dma_tag_destroy(ioat->hw_desc_tag); 327 328 return (0); 329} 330 331static int 332ioat_teardown_intr(struct ioat_softc *ioat) 333{ 334 335 if (ioat->tag != NULL) 336 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 337 338 if (ioat->res != NULL) 339 bus_release_resource(ioat->device, SYS_RES_IRQ, 340 rman_get_rid(ioat->res), ioat->res); 341 342 pci_release_msi(ioat->device); 343 return (0); 344} 345 346static int 347ioat_start_channel(struct ioat_softc *ioat) 348{ 349 uint64_t status; 350 uint32_t chanerr; 351 int i; 352 353 ioat_acquire(&ioat->dmaengine); 354 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 355 ioat_release(&ioat->dmaengine); 356 357 for (i = 0; i < 100; i++) { 358 DELAY(1); 359 status = ioat_get_chansts(ioat); 360 if (is_ioat_idle(status)) 361 return (0); 362 } 363 364 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 365 ioat_log_message(0, "could not start channel: " 366 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 367 IOAT_CHANERR_STR); 368 return (ENXIO); 369} 370 371/* 372 * Initialize Hardware 373 */ 374static int 375ioat3_attach(device_t device) 376{ 377 struct ioat_softc *ioat; 378 struct ioat_descriptor **ring; 379 struct ioat_descriptor *next; 380 struct ioat_dma_hw_descriptor *dma_hw_desc; 381 int i, num_descriptors; 382 int error; 383 uint8_t xfercap; 384 385 error = 0; 386 ioat = DEVICE2SOFTC(device); 387 ioat->capabilities = ioat_read_dmacapability(ioat); 388 389 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 390 IOAT_DMACAP_STR); 391 392 xfercap = ioat_read_xfercap(ioat); 393 ioat->max_xfer_size = 1 << xfercap; 394 395 /* TODO: need to check DCA here if we ever do XOR/PQ */ 396 397 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 398 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 399 callout_init(&ioat->timer, 1); 400 401 /* Establish lock order for Witness */ 402 mtx_lock(&ioat->submit_lock); 403 mtx_lock(&ioat->cleanup_lock); 404 mtx_unlock(&ioat->cleanup_lock); 405 mtx_unlock(&ioat->submit_lock); 406 407 ioat->is_resize_pending = FALSE; 408 ioat->is_completion_pending = FALSE; 409 ioat->is_reset_pending = FALSE; 410 ioat->is_channel_running = FALSE; 411 412 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 413 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 414 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 415 &ioat->comp_update_tag); 416 417 error = bus_dmamem_alloc(ioat->comp_update_tag, 418 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 419 if (ioat->comp_update == NULL) 420 return (ENOMEM); 421 422 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 423 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 424 0); 425 if (error != 0) 426 return (error); 427 428 ioat->ring_size_order = IOAT_MIN_ORDER; 429 430 num_descriptors = 1 << ioat->ring_size_order; 431 432 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 433 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 434 sizeof(struct ioat_dma_hw_descriptor), 1, 435 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 436 &ioat->hw_desc_tag); 437 438 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 439 M_ZERO | M_WAITOK); 440 if (ioat->ring == NULL) 441 return (ENOMEM); 442 443 ring = ioat->ring; 444 for (i = 0; i < num_descriptors; i++) { 445 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 446 if (ring[i] == NULL) 447 return (ENOMEM); 448 449 ring[i]->id = i; 450 } 451 452 for (i = 0; i < num_descriptors - 1; i++) { 453 next = ring[i + 1]; 454 dma_hw_desc = ring[i]->u.dma; 455 456 dma_hw_desc->next = next->hw_desc_bus_addr; 457 } 458 459 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 460 461 ioat->head = ioat->hw_head = 0; 462 ioat->tail = 0; 463 ioat->last_seen = 0; 464 return (0); 465} 466 467static int 468ioat_map_pci_bar(struct ioat_softc *ioat) 469{ 470 471 ioat->pci_resource_id = PCIR_BAR(0); 472 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 473 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 474 475 if (ioat->pci_resource == NULL) { 476 ioat_log_message(0, "unable to allocate pci resource\n"); 477 return (ENODEV); 478 } 479 480 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 481 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 482 return (0); 483} 484 485static void 486ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 487{ 488 struct ioat_softc *ioat = arg; 489 490 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 491 ioat->comp_update_bus_addr = seg[0].ds_addr; 492} 493 494static void 495ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 496{ 497 bus_addr_t *baddr; 498 499 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 500 baddr = arg; 501 *baddr = segs->ds_addr; 502} 503 504/* 505 * Interrupt setup and handlers 506 */ 507static int 508ioat_setup_intr(struct ioat_softc *ioat) 509{ 510 uint32_t num_vectors; 511 int error; 512 boolean_t use_msix; 513 boolean_t force_legacy_interrupts; 514 515 use_msix = FALSE; 516 force_legacy_interrupts = FALSE; 517 518 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 519 num_vectors = 1; 520 pci_alloc_msix(ioat->device, &num_vectors); 521 if (num_vectors == 1) 522 use_msix = TRUE; 523 } 524 525 if (use_msix) { 526 ioat->rid = 1; 527 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 528 &ioat->rid, RF_ACTIVE); 529 } else { 530 ioat->rid = 0; 531 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 532 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 533 } 534 if (ioat->res == NULL) { 535 ioat_log_message(0, "bus_alloc_resource failed\n"); 536 return (ENOMEM); 537 } 538 539 ioat->tag = NULL; 540 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 541 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 542 if (error != 0) { 543 ioat_log_message(0, "bus_setup_intr failed\n"); 544 return (error); 545 } 546 547 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 548 return (0); 549} 550 551static boolean_t 552ioat_model_resets_msix(struct ioat_softc *ioat) 553{ 554 u_int32_t pciid; 555 556 pciid = pci_get_devid(ioat->device); 557 switch (pciid) { 558 /* BWD: */ 559 case 0x0c508086: 560 case 0x0c518086: 561 case 0x0c528086: 562 case 0x0c538086: 563 /* BDXDE: */ 564 case 0x6f508086: 565 case 0x6f518086: 566 case 0x6f528086: 567 case 0x6f538086: 568 return (TRUE); 569 } 570 571 return (FALSE); 572} 573 574static void 575ioat_interrupt_handler(void *arg) 576{ 577 struct ioat_softc *ioat = arg; 578 579 ioat_process_events(ioat); 580} 581 582static int 583chanerr_to_errno(uint32_t chanerr) 584{ 585 586 if (chanerr == 0) 587 return (0); 588 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 589 return (EFAULT); 590 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 591 return (EIO); 592 /* This one is probably our fault: */ 593 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 594 return (EIO); 595 return (EIO); 596} 597 598static void 599ioat_process_events(struct ioat_softc *ioat) 600{ 601 struct ioat_descriptor *desc; 602 struct bus_dmadesc *dmadesc; 603 uint64_t comp_update, status; 604 uint32_t completed, chanerr; 605 int error; 606 607 mtx_lock(&ioat->cleanup_lock); 608 609 completed = 0; 610 comp_update = *ioat->comp_update; 611 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 612 613 CTR0(KTR_IOAT, __func__); 614 615 if (status == ioat->last_seen) 616 goto out; 617 618 while (1) { 619 desc = ioat_get_ring_entry(ioat, ioat->tail); 620 dmadesc = &desc->bus_dmadesc; 621 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 622 623 if (dmadesc->callback_fn != NULL) 624 dmadesc->callback_fn(dmadesc->callback_arg, 0); 625 626 completed++; 627 ioat->tail++; 628 if (desc->hw_desc_bus_addr == status) 629 break; 630 } 631 632 ioat->last_seen = desc->hw_desc_bus_addr; 633 634 if (ioat->head == ioat->tail) { 635 ioat->is_completion_pending = FALSE; 636 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 637 ioat_timer_callback, ioat); 638 } 639 640out: 641 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 642 mtx_unlock(&ioat->cleanup_lock); 643 644 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 645 wakeup(&ioat->tail); 646 647 if (!is_ioat_halted(comp_update)) 648 return; 649 650 /* 651 * Fatal programming error on this DMA channel. Flush any outstanding 652 * work with error status and restart the engine. 653 */ 654 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 655 mtx_lock(&ioat->submit_lock); 656 mtx_lock(&ioat->cleanup_lock); 657 ioat->quiescing = TRUE; 658 659 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 660 ioat_halted_debug(ioat, chanerr); 661 662 while (ioat_get_active(ioat) > 0) { 663 desc = ioat_get_ring_entry(ioat, ioat->tail); 664 dmadesc = &desc->bus_dmadesc; 665 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 666 667 if (dmadesc->callback_fn != NULL) 668 dmadesc->callback_fn(dmadesc->callback_arg, 669 chanerr_to_errno(chanerr)); 670 671 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 672 ioat->tail++; 673 } 674 675 /* Clear error status */ 676 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 677 678 mtx_unlock(&ioat->cleanup_lock); 679 mtx_unlock(&ioat->submit_lock); 680 681 ioat_log_message(0, "Resetting channel to recover from error\n"); 682 error = ioat_reset_hw(ioat); 683 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 684} 685 686/* 687 * User API functions 688 */ 689bus_dmaengine_t 690ioat_get_dmaengine(uint32_t index) 691{ 692 struct ioat_softc *sc; 693 694 if (index >= ioat_channel_index) 695 return (NULL); 696 697 sc = ioat_channel[index]; 698 if (sc == NULL || sc->quiescing) 699 return (NULL); 700 701 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 702} 703 704void 705ioat_put_dmaengine(bus_dmaengine_t dmaengine) 706{ 707 struct ioat_softc *ioat; 708 709 ioat = to_ioat_softc(dmaengine); 710 ioat_put(ioat, IOAT_DMAENGINE_REF); 711} 712 713void 714ioat_acquire(bus_dmaengine_t dmaengine) 715{ 716 struct ioat_softc *ioat; 717 718 ioat = to_ioat_softc(dmaengine); 719 mtx_lock(&ioat->submit_lock); 720 CTR0(KTR_IOAT, __func__); 721} 722 723void 724ioat_release(bus_dmaengine_t dmaengine) 725{ 726 struct ioat_softc *ioat; 727 728 ioat = to_ioat_softc(dmaengine); 729 CTR0(KTR_IOAT, __func__); 730 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 731 mtx_unlock(&ioat->submit_lock); 732} 733 734static struct ioat_descriptor * 735ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 736 uint32_t size, uint64_t src, uint64_t dst, 737 bus_dmaengine_callback_t callback_fn, void *callback_arg, 738 uint32_t flags) 739{ 740 struct ioat_generic_hw_descriptor *hw_desc; 741 struct ioat_descriptor *desc; 742 int mflags; 743 744 mtx_assert(&ioat->submit_lock, MA_OWNED); 745 746 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 747 flags & ~DMA_ALL_FLAGS)); 748 if ((flags & DMA_NO_WAIT) != 0) 749 mflags = M_NOWAIT; 750 else 751 mflags = M_WAITOK; 752 753 if (size > ioat->max_xfer_size) { 754 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 755 __func__, ioat->max_xfer_size, (unsigned)size); 756 return (NULL); 757 } 758 759 if (ioat_reserve_space(ioat, 1, mflags) != 0) 760 return (NULL); 761 762 desc = ioat_get_ring_entry(ioat, ioat->head); 763 hw_desc = desc->u.generic; 764 765 hw_desc->u.control_raw = 0; 766 hw_desc->u.control_generic.op = op; 767 hw_desc->u.control_generic.completion_update = 1; 768 769 if ((flags & DMA_INT_EN) != 0) 770 hw_desc->u.control_generic.int_enable = 1; 771 772 hw_desc->size = size; 773 hw_desc->src_addr = src; 774 hw_desc->dest_addr = dst; 775 776 desc->bus_dmadesc.callback_fn = callback_fn; 777 desc->bus_dmadesc.callback_arg = callback_arg; 778 return (desc); 779} 780 781struct bus_dmadesc * 782ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 783 void *callback_arg, uint32_t flags) 784{ 785 struct ioat_dma_hw_descriptor *hw_desc; 786 struct ioat_descriptor *desc; 787 struct ioat_softc *ioat; 788 789 CTR0(KTR_IOAT, __func__); 790 ioat = to_ioat_softc(dmaengine); 791 792 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 793 callback_arg, flags); 794 if (desc == NULL) 795 return (NULL); 796 797 hw_desc = desc->u.dma; 798 hw_desc->u.control.null = 1; 799 ioat_submit_single(ioat); 800 return (&desc->bus_dmadesc); 801} 802 803struct bus_dmadesc * 804ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 805 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 806 void *callback_arg, uint32_t flags) 807{ 808 struct ioat_dma_hw_descriptor *hw_desc; 809 struct ioat_descriptor *desc; 810 struct ioat_softc *ioat; 811 812 CTR0(KTR_IOAT, __func__); 813 ioat = to_ioat_softc(dmaengine); 814 815 if (((src | dst) & (0xffffull << 48)) != 0) { 816 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 817 __func__); 818 return (NULL); 819 } 820 821 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 822 callback_arg, flags); 823 if (desc == NULL) 824 return (NULL); 825 826 hw_desc = desc->u.dma; 827 if (g_ioat_debug_level >= 3) 828 dump_descriptor(hw_desc); 829 830 ioat_submit_single(ioat); 831 return (&desc->bus_dmadesc); 832} 833 834struct bus_dmadesc * 835ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 836 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 837 uint32_t flags) 838{ 839 struct ioat_fill_hw_descriptor *hw_desc; 840 struct ioat_descriptor *desc; 841 struct ioat_softc *ioat; 842 843 CTR0(KTR_IOAT, __func__); 844 ioat = to_ioat_softc(dmaengine); 845 846 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 847 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 848 __func__); 849 return (NULL); 850 } 851 852 if ((dst & (0xffffull << 48)) != 0) { 853 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 854 __func__); 855 return (NULL); 856 } 857 858 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 859 callback_fn, callback_arg, flags); 860 if (desc == NULL) 861 return (NULL); 862 863 hw_desc = desc->u.fill; 864 if (g_ioat_debug_level >= 3) 865 dump_descriptor(hw_desc); 866 867 ioat_submit_single(ioat); 868 return (&desc->bus_dmadesc); 869} 870 871/* 872 * Ring Management 873 */ 874static inline uint32_t 875ioat_get_active(struct ioat_softc *ioat) 876{ 877 878 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 879} 880 881static inline uint32_t 882ioat_get_ring_space(struct ioat_softc *ioat) 883{ 884 885 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 886} 887 888static struct ioat_descriptor * 889ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 890{ 891 struct ioat_generic_hw_descriptor *hw_desc; 892 struct ioat_descriptor *desc; 893 int error, busdmaflag; 894 895 error = ENOMEM; 896 hw_desc = NULL; 897 898 if ((mflags & M_WAITOK) != 0) 899 busdmaflag = BUS_DMA_WAITOK; 900 else 901 busdmaflag = BUS_DMA_NOWAIT; 902 903 desc = malloc(sizeof(*desc), M_IOAT, mflags); 904 if (desc == NULL) 905 goto out; 906 907 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 908 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 909 if (hw_desc == NULL) 910 goto out; 911 912 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 913 desc->u.generic = hw_desc; 914 915 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 916 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 917 busdmaflag); 918 if (error) 919 goto out; 920 921out: 922 if (error) { 923 ioat_free_ring_entry(ioat, desc); 924 return (NULL); 925 } 926 return (desc); 927} 928 929static void 930ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 931{ 932 933 if (desc == NULL) 934 return; 935 936 if (desc->u.generic) 937 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 938 ioat->hw_desc_map); 939 free(desc, M_IOAT); 940} 941 942/* 943 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 944 * for 'num_descs'. 945 * 946 * If mflags contains M_WAITOK, blocks until enough space is available. 947 * 948 * Returns zero on success, or an errno on error. If num_descs is beyond the 949 * maximum ring size, returns EINVAl; if allocation would block and mflags 950 * contains M_NOWAIT, returns EAGAIN. 951 * 952 * Must be called with the submit_lock held; returns with the lock held. The 953 * lock may be dropped to allocate the ring. 954 * 955 * (The submit_lock is needed to add any entries to the ring, so callers are 956 * assured enough room is available.) 957 */ 958static int 959ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 960{ 961 struct ioat_descriptor **new_ring; 962 uint32_t order; 963 int error; 964 965 mtx_assert(&ioat->submit_lock, MA_OWNED); 966 error = 0; 967 968 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 969 error = EINVAL; 970 goto out; 971 } 972 if (ioat->quiescing) { 973 error = ENXIO; 974 goto out; 975 } 976 977 for (;;) { 978 if (ioat_get_ring_space(ioat) >= num_descs) 979 goto out; 980 981 order = ioat->ring_size_order; 982 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 983 if ((mflags & M_WAITOK) != 0) { 984 msleep(&ioat->tail, &ioat->submit_lock, 0, 985 "ioat_rsz", 0); 986 continue; 987 } 988 989 error = EAGAIN; 990 break; 991 } 992 993 ioat->is_resize_pending = TRUE; 994 for (;;) { 995 mtx_unlock(&ioat->submit_lock); 996 997 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 998 TRUE, mflags); 999 1000 mtx_lock(&ioat->submit_lock); 1001 KASSERT(ioat->ring_size_order == order, 1002 ("is_resize_pending should protect order")); 1003 1004 if (new_ring == NULL) { 1005 KASSERT((mflags & M_WAITOK) == 0, 1006 ("allocation failed")); 1007 error = EAGAIN; 1008 break; 1009 } 1010 1011 error = ring_grow(ioat, order, new_ring); 1012 if (error == 0) 1013 break; 1014 } 1015 ioat->is_resize_pending = FALSE; 1016 wakeup(&ioat->tail); 1017 if (error) 1018 break; 1019 } 1020 1021out: 1022 mtx_assert(&ioat->submit_lock, MA_OWNED); 1023 return (error); 1024} 1025 1026static struct ioat_descriptor ** 1027ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1028 int mflags) 1029{ 1030 struct ioat_descriptor **ring; 1031 uint32_t i; 1032 int error; 1033 1034 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1035 1036 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1037 if (ring == NULL) 1038 return (NULL); 1039 1040 if (need_dscr) { 1041 error = ENOMEM; 1042 for (i = size / 2; i < size; i++) { 1043 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1044 if (ring[i] == NULL) 1045 goto out; 1046 ring[i]->id = i; 1047 } 1048 } 1049 error = 0; 1050 1051out: 1052 if (error != 0 && ring != NULL) { 1053 ioat_free_ring(ioat, size, ring); 1054 ring = NULL; 1055 } 1056 return (ring); 1057} 1058 1059static void 1060ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1061 struct ioat_descriptor **ring) 1062{ 1063 uint32_t i; 1064 1065 for (i = 0; i < size; i++) { 1066 if (ring[i] != NULL) 1067 ioat_free_ring_entry(ioat, ring[i]); 1068 } 1069 free(ring, M_IOAT); 1070} 1071 1072static struct ioat_descriptor * 1073ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1074{ 1075 1076 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1077} 1078 1079static int 1080ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1081 struct ioat_descriptor **newring) 1082{ 1083 struct ioat_descriptor *tmp, *next; 1084 struct ioat_dma_hw_descriptor *hw; 1085 uint32_t oldsize, newsize, head, tail, i, end; 1086 int error; 1087 1088 CTR0(KTR_IOAT, __func__); 1089 1090 mtx_assert(&ioat->submit_lock, MA_OWNED); 1091 1092 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1093 error = EINVAL; 1094 goto out; 1095 } 1096 1097 oldsize = (1 << oldorder); 1098 newsize = (1 << (oldorder + 1)); 1099 1100 mtx_lock(&ioat->cleanup_lock); 1101 1102 head = ioat->head & (oldsize - 1); 1103 tail = ioat->tail & (oldsize - 1); 1104 1105 /* Copy old descriptors to new ring */ 1106 for (i = 0; i < oldsize; i++) 1107 newring[i] = ioat->ring[i]; 1108 1109 /* 1110 * If head has wrapped but tail hasn't, we must swap some descriptors 1111 * around so that tail can increment directly to head. 1112 */ 1113 if (head < tail) { 1114 for (i = 0; i <= head; i++) { 1115 tmp = newring[oldsize + i]; 1116 1117 newring[oldsize + i] = newring[i]; 1118 newring[oldsize + i]->id = oldsize + i; 1119 1120 newring[i] = tmp; 1121 newring[i]->id = i; 1122 } 1123 head += oldsize; 1124 } 1125 1126 KASSERT(head >= tail, ("invariants")); 1127 1128 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1129 if (head < oldsize) { 1130 i = oldsize - 1; 1131 end = newsize; 1132 } else { 1133 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1134 i = head; 1135 end = newsize + (head - oldsize) + 1; 1136 } 1137 1138 /* 1139 * Fix up hardware ring, being careful not to trample the active 1140 * section (tail -> head). 1141 */ 1142 for (; i < end; i++) { 1143 KASSERT((i & (newsize - 1)) < tail || 1144 (i & (newsize - 1)) >= head, ("trampling snake")); 1145 1146 next = newring[(i + 1) & (newsize - 1)]; 1147 hw = newring[i & (newsize - 1)]->u.dma; 1148 hw->next = next->hw_desc_bus_addr; 1149 } 1150 1151 free(ioat->ring, M_IOAT); 1152 ioat->ring = newring; 1153 ioat->ring_size_order = oldorder + 1; 1154 ioat->tail = tail; 1155 ioat->head = head; 1156 error = 0; 1157 1158 mtx_unlock(&ioat->cleanup_lock); 1159out: 1160 if (error) 1161 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1162 return (error); 1163} 1164 1165static int 1166ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1167 struct ioat_descriptor **newring) 1168{ 1169 struct ioat_dma_hw_descriptor *hw; 1170 struct ioat_descriptor *ent, *next; 1171 uint32_t oldsize, newsize, current_idx, new_idx, i; 1172 int error; 1173 1174 CTR0(KTR_IOAT, __func__); 1175 1176 mtx_assert(&ioat->submit_lock, MA_OWNED); 1177 1178 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1179 error = EINVAL; 1180 goto out_unlocked; 1181 } 1182 1183 oldsize = (1 << oldorder); 1184 newsize = (1 << (oldorder - 1)); 1185 1186 mtx_lock(&ioat->cleanup_lock); 1187 1188 /* Can't shrink below current active set! */ 1189 if (ioat_get_active(ioat) >= newsize) { 1190 error = ENOMEM; 1191 goto out; 1192 } 1193 1194 /* 1195 * Copy current descriptors to the new ring, dropping the removed 1196 * descriptors. 1197 */ 1198 for (i = 0; i < newsize; i++) { 1199 current_idx = (ioat->tail + i) & (oldsize - 1); 1200 new_idx = (ioat->tail + i) & (newsize - 1); 1201 1202 newring[new_idx] = ioat->ring[current_idx]; 1203 newring[new_idx]->id = new_idx; 1204 } 1205 1206 /* Free deleted descriptors */ 1207 for (i = newsize; i < oldsize; i++) { 1208 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1209 ioat_free_ring_entry(ioat, ent); 1210 } 1211 1212 /* Fix up hardware ring. */ 1213 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1214 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1215 hw->next = next->hw_desc_bus_addr; 1216 1217 free(ioat->ring, M_IOAT); 1218 ioat->ring = newring; 1219 ioat->ring_size_order = oldorder - 1; 1220 error = 0; 1221 1222out: 1223 mtx_unlock(&ioat->cleanup_lock); 1224out_unlocked: 1225 if (error) 1226 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1227 return (error); 1228} 1229 1230static void 1231ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1232{ 1233 struct ioat_descriptor *desc; 1234 1235 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1236 IOAT_CHANERR_STR); 1237 if (chanerr == 0) 1238 return; 1239 1240 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1241 1242 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1243 dump_descriptor(desc->u.raw); 1244 1245 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1246 dump_descriptor(desc->u.raw); 1247} 1248 1249static void 1250ioat_timer_callback(void *arg) 1251{ 1252 struct ioat_descriptor **newring; 1253 struct ioat_softc *ioat; 1254 uint32_t order; 1255 1256 ioat = arg; 1257 ioat_log_message(1, "%s\n", __func__); 1258 1259 if (ioat->is_completion_pending) { 1260 ioat_process_events(ioat); 1261 return; 1262 } 1263 1264 /* Slowly scale the ring down if idle. */ 1265 mtx_lock(&ioat->submit_lock); 1266 order = ioat->ring_size_order; 1267 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1268 mtx_unlock(&ioat->submit_lock); 1269 goto out; 1270 } 1271 ioat->is_resize_pending = TRUE; 1272 mtx_unlock(&ioat->submit_lock); 1273 1274 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1275 M_NOWAIT); 1276 1277 mtx_lock(&ioat->submit_lock); 1278 KASSERT(ioat->ring_size_order == order, 1279 ("resize_pending protects order")); 1280 1281 if (newring != NULL) 1282 ring_shrink(ioat, order, newring); 1283 1284 ioat->is_resize_pending = FALSE; 1285 mtx_unlock(&ioat->submit_lock); 1286 1287out: 1288 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1289 callout_reset(&ioat->timer, 10 * hz, 1290 ioat_timer_callback, ioat); 1291} 1292 1293/* 1294 * Support Functions 1295 */ 1296static void 1297ioat_submit_single(struct ioat_softc *ioat) 1298{ 1299 1300 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1301 atomic_add_rel_int(&ioat->head, 1); 1302 atomic_add_rel_int(&ioat->hw_head, 1); 1303 1304 if (!ioat->is_completion_pending) { 1305 ioat->is_completion_pending = TRUE; 1306 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1307 ioat_timer_callback, ioat); 1308 } 1309} 1310 1311static int 1312ioat_reset_hw(struct ioat_softc *ioat) 1313{ 1314 uint64_t status; 1315 uint32_t chanerr; 1316 unsigned timeout; 1317 int error; 1318 1319 mtx_lock(IOAT_REFLK); 1320 ioat->quiescing = TRUE; 1321 ioat_drain_locked(ioat); 1322 mtx_unlock(IOAT_REFLK); 1323 1324 status = ioat_get_chansts(ioat); 1325 if (is_ioat_active(status) || is_ioat_idle(status)) 1326 ioat_suspend(ioat); 1327 1328 /* Wait at most 20 ms */ 1329 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1330 timeout < 20; timeout++) { 1331 DELAY(1000); 1332 status = ioat_get_chansts(ioat); 1333 } 1334 if (timeout == 20) { 1335 error = ETIMEDOUT; 1336 goto out; 1337 } 1338 1339 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1340 1341 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1342 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1343 1344 /* 1345 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1346 * that can cause stability issues for IOAT v3. 1347 */ 1348 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1349 4); 1350 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1351 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1352 1353 /* 1354 * BDXDE and BWD models reset MSI-X registers on device reset. 1355 * Save/restore their contents manually. 1356 */ 1357 if (ioat_model_resets_msix(ioat)) { 1358 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1359 pci_save_state(ioat->device); 1360 } 1361 1362 ioat_reset(ioat); 1363 1364 /* Wait at most 20 ms */ 1365 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1366 DELAY(1000); 1367 if (timeout == 20) { 1368 error = ETIMEDOUT; 1369 goto out; 1370 } 1371 1372 if (ioat_model_resets_msix(ioat)) { 1373 ioat_log_message(1, "device resets registers; restored\n"); 1374 pci_restore_state(ioat->device); 1375 } 1376 1377 /* Reset attempts to return the hardware to "halted." */ 1378 status = ioat_get_chansts(ioat); 1379 if (is_ioat_active(status) || is_ioat_idle(status)) { 1380 /* So this really shouldn't happen... */ 1381 ioat_log_message(0, "Device is active after a reset?\n"); 1382 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1383 error = 0; 1384 goto out; 1385 } 1386 1387 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1388 if (chanerr != 0) { 1389 mtx_lock(&ioat->cleanup_lock); 1390 ioat_halted_debug(ioat, chanerr); 1391 mtx_unlock(&ioat->cleanup_lock); 1392 error = EIO; 1393 goto out; 1394 } 1395 1396 /* 1397 * Bring device back online after reset. Writing CHAINADDR brings the 1398 * device back to active. 1399 * 1400 * The internal ring counter resets to zero, so we have to start over 1401 * at zero as well. 1402 */ 1403 ioat->tail = ioat->head = ioat->hw_head = 0; 1404 ioat->last_seen = 0; 1405 1406 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1407 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1408 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1409 error = 0; 1410 1411out: 1412 mtx_lock(IOAT_REFLK); 1413 ioat->quiescing = FALSE; 1414 mtx_unlock(IOAT_REFLK); 1415 1416 if (error == 0) 1417 error = ioat_start_channel(ioat); 1418 1419 return (error); 1420} 1421 1422static int 1423sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1424{ 1425 struct ioat_softc *ioat; 1426 struct sbuf sb; 1427 uint64_t status; 1428 int error; 1429 1430 ioat = arg1; 1431 1432 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1433 1434 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1435 switch (status) { 1436 case IOAT_CHANSTS_ACTIVE: 1437 sbuf_printf(&sb, "ACTIVE"); 1438 break; 1439 case IOAT_CHANSTS_IDLE: 1440 sbuf_printf(&sb, "IDLE"); 1441 break; 1442 case IOAT_CHANSTS_SUSPENDED: 1443 sbuf_printf(&sb, "SUSPENDED"); 1444 break; 1445 case IOAT_CHANSTS_HALTED: 1446 sbuf_printf(&sb, "HALTED"); 1447 break; 1448 case IOAT_CHANSTS_ARMED: 1449 sbuf_printf(&sb, "ARMED"); 1450 break; 1451 default: 1452 sbuf_printf(&sb, "UNKNOWN"); 1453 break; 1454 } 1455 error = sbuf_finish(&sb); 1456 sbuf_delete(&sb); 1457 1458 if (error != 0 || req->newptr == NULL) 1459 return (error); 1460 return (EINVAL); 1461} 1462 1463static int 1464sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1465{ 1466 struct ioat_descriptor *desc; 1467 struct ioat_softc *ioat; 1468 int error, arg; 1469 1470 ioat = arg1; 1471 1472 arg = 0; 1473 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1474 if (error != 0 || req->newptr == NULL) 1475 return (error); 1476 1477 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1478 if (error != 0) 1479 return (error); 1480 1481 if (arg != 0) { 1482 ioat_acquire(&ioat->dmaengine); 1483 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1484 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1485 0); 1486 if (desc == NULL) 1487 error = ENOMEM; 1488 else 1489 ioat_submit_single(ioat); 1490 ioat_release(&ioat->dmaengine); 1491 } 1492 return (error); 1493} 1494 1495static int 1496sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1497{ 1498 struct ioat_softc *ioat; 1499 int error, arg; 1500 1501 ioat = arg1; 1502 1503 arg = 0; 1504 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1505 if (error != 0 || req->newptr == NULL) 1506 return (error); 1507 1508 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1509 if (error != 0) 1510 return (error); 1511 1512 if (arg != 0) 1513 error = ioat_reset_hw(ioat); 1514 1515 return (error); 1516} 1517 1518static void 1519dump_descriptor(void *hw_desc) 1520{ 1521 int i, j; 1522 1523 for (i = 0; i < 2; i++) { 1524 for (j = 0; j < 8; j++) 1525 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1526 printf("\n"); 1527 } 1528} 1529 1530static void 1531ioat_setup_sysctl(device_t device) 1532{ 1533 struct sysctl_oid_list *par; 1534 struct sysctl_ctx_list *ctx; 1535 struct sysctl_oid *tree; 1536 struct ioat_softc *ioat; 1537 1538 ioat = DEVICE2SOFTC(device); 1539 ctx = device_get_sysctl_ctx(device); 1540 tree = device_get_sysctl_tree(device); 1541 par = SYSCTL_CHILDREN(tree); 1542 1543 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1544 &ioat->version, 0, "HW version (0xMM form)"); 1545 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1546 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1547 1548 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1549 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1550 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 0, 1551 "SW descriptor head pointer index"); 1552 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 0, 1553 "SW descriptor tail pointer index"); 1554 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "hw_head", CTLFLAG_RD, 1555 &ioat->hw_head, 0, "HW DMACOUNT"); 1556 1557 SYSCTL_ADD_UQUAD(ctx, par, OID_AUTO, "last_completion", CTLFLAG_RD, 1558 ioat->comp_update, "HW addr of last completion"); 1559 1560 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1561 &ioat->is_resize_pending, 0, "resize pending"); 1562 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_completion_pending", CTLFLAG_RD, 1563 &ioat->is_completion_pending, 0, "completion pending"); 1564 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1565 &ioat->is_reset_pending, 0, "reset pending"); 1566 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1567 &ioat->is_channel_running, 0, "channel running"); 1568 1569 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_reset", 1570 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1571 "Set to non-zero to reset the hardware"); 1572 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_error", 1573 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1574 "Set to non-zero to inject a recoverable hardware error"); 1575 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "chansts", 1576 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1577 "String of the channel status"); 1578} 1579 1580static inline struct ioat_softc * 1581ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1582{ 1583 uint32_t old; 1584 1585 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1586 1587 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1588 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1589 1590#ifdef INVARIANTS 1591 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1592 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1593#endif 1594 1595 return (ioat); 1596} 1597 1598static inline void 1599ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1600{ 1601 1602 _ioat_putn(ioat, n, kind, FALSE); 1603} 1604 1605static inline void 1606ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1607{ 1608 1609 _ioat_putn(ioat, n, kind, TRUE); 1610} 1611 1612static inline void 1613_ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1614 boolean_t locked) 1615{ 1616 uint32_t old; 1617 1618 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1619 1620 if (n == 0) 1621 return; 1622 1623#ifdef INVARIANTS 1624 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1625 KASSERT(old >= n, ("refcnt kind underflow")); 1626#endif 1627 1628 /* Skip acquiring the lock if resulting refcnt > 0. */ 1629 for (;;) { 1630 old = ioat->refcnt; 1631 if (old <= n) 1632 break; 1633 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1634 return; 1635 } 1636 1637 if (locked) 1638 mtx_assert(IOAT_REFLK, MA_OWNED); 1639 else 1640 mtx_lock(IOAT_REFLK); 1641 1642 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1643 KASSERT(old >= n, ("refcnt error")); 1644 1645 if (old == n) 1646 wakeup(IOAT_REFLK); 1647 if (!locked) 1648 mtx_unlock(IOAT_REFLK); 1649} 1650 1651static inline void 1652ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1653{ 1654 1655 ioat_putn(ioat, 1, kind); 1656} 1657 1658static void 1659ioat_drain_locked(struct ioat_softc *ioat) 1660{ 1661 1662 mtx_assert(IOAT_REFLK, MA_OWNED); 1663 while (ioat->refcnt > 0) 1664 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1665} 1666