ioat.c revision 293390
1266692Sgshapiro/*- 238032Speter * Copyright (C) 2012 Intel Corporation 338032Speter * All rights reserved. 438032Speter * 538032Speter * Redistribution and use in source and binary forms, with or without 638032Speter * modification, are permitted provided that the following conditions 738032Speter * are met: 838032Speter * 1. Redistributions of source code must retain the above copyright 938032Speter * notice, this list of conditions and the following disclaimer. 1038032Speter * 2. Redistributions in binary form must reproduce the above copyright 1138032Speter * notice, this list of conditions and the following disclaimer in the 1238032Speter * documentation and/or other materials provided with the distribution. 1338032Speter * 1438032Speter * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1538032Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1638032Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1738032Speter * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1838032Speter * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1938032Speter * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2038032Speter * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2138032Speter * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2238032Speter * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2338032Speter * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2438032Speter * SUCH DAMAGE. 2564562Sgshapiro */ 2638032Speter 2738032Speter#include <sys/cdefs.h> 2838032Speter__FBSDID("$FreeBSD: head/sys/dev/ioat/ioat.c 293390 2016-01-07 23:02:15Z cem $"); 2938032Speter 30168515Sgshapiro#include <sys/param.h> 3138032Speter#include <sys/systm.h> 3238032Speter#include <sys/bus.h> 3338032Speter#include <sys/conf.h> 3438032Speter#include <sys/ioccom.h> 3538032Speter#include <sys/kernel.h> 3638032Speter#include <sys/lock.h> 3738032Speter#include <sys/malloc.h> 3838032Speter#include <sys/module.h> 3938032Speter#include <sys/mutex.h> 4038032Speter#include <sys/rman.h> 4138032Speter#include <sys/sbuf.h> 4238032Speter#include <sys/sysctl.h> 4338032Speter#include <sys/time.h> 4438032Speter#include <dev/pci/pcireg.h> 4538032Speter#include <dev/pci/pcivar.h> 4638032Speter#include <machine/bus.h> 4738032Speter#include <machine/resource.h> 4838032Speter#include <machine/stdarg.h> 4938032Speter 5064562Sgshapiro#include "ioat.h" 5138032Speter#include "ioat_hw.h" 5238032Speter#include "ioat_internal.h" 5338032Speter 5438032Speter#define IOAT_INTR_TIMO (hz / 10) 5538032Speter#define IOAT_REFLK (&ioat->submit_lock) 5698121Sgshapiro 5738032Speterstatic int ioat_probe(device_t device); 5838032Speterstatic int ioat_attach(device_t device); 5938032Speterstatic int ioat_detach(device_t device); 6038032Speterstatic int ioat_setup_intr(struct ioat_softc *ioat); 6138032Speterstatic int ioat_teardown_intr(struct ioat_softc *ioat); 6238032Speterstatic int ioat3_attach(device_t device); 6338032Speterstatic int ioat_start_channel(struct ioat_softc *ioat); 6438032Speterstatic int ioat_map_pci_bar(struct ioat_softc *ioat); 6538032Speterstatic void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 6638032Speter int error); 6738032Speterstatic void ioat_interrupt_handler(void *arg); 6838032Speterstatic boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 6938032Speterstatic int chanerr_to_errno(uint32_t); 7038032Speterstatic void ioat_process_events(struct ioat_softc *ioat); 7138032Speterstatic inline uint32_t ioat_get_active(struct ioat_softc *ioat); 7264562Sgshapirostatic inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 73168515Sgshapirostatic void ioat_free_ring(struct ioat_softc *, uint32_t size, 7438032Speter struct ioat_descriptor **); 7538032Speterstatic void ioat_free_ring_entry(struct ioat_softc *ioat, 7638032Speter struct ioat_descriptor *desc); 7764562Sgshapirostatic struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 7864562Sgshapiro int mflags); 7990792Sgshapirostatic int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 80244833Sgshapirostatic struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 81244833Sgshapiro uint32_t index); 82244833Sgshapirostatic struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 83244833Sgshapiro uint32_t size, boolean_t need_dscr, int mflags); 84244833Sgshapirostatic int ring_grow(struct ioat_softc *, uint32_t oldorder, 85244833Sgshapiro struct ioat_descriptor **); 8690792Sgshapirostatic int ring_shrink(struct ioat_softc *, uint32_t oldorder, 87102528Sgshapiro struct ioat_descriptor **); 88147078Sgshapirostatic void ioat_halted_debug(struct ioat_softc *, uint32_t); 89203004Sgshapirostatic void ioat_timer_callback(void *arg); 9038032Speterstatic void dump_descriptor(void *hw_desc); 9138032Speterstatic void ioat_submit_single(struct ioat_softc *ioat); 92157001Sgshapirostatic void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 93157001Sgshapiro int error); 94168515Sgshapirostatic int ioat_reset_hw(struct ioat_softc *ioat); 95244833Sgshapirostatic void ioat_setup_sysctl(device_t device); 9638032Speterstatic int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 97110560Sgshapirostatic inline struct ioat_softc *ioat_get(struct ioat_softc *, 9890792Sgshapiro enum ioat_ref_kind); 9964562Sgshapirostatic inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 10064562Sgshapirostatic inline void _ioat_putn(struct ioat_softc *, uint32_t, 101261363Sgshapiro enum ioat_ref_kind, boolean_t); 10298121Sgshapirostatic inline void ioat_putn(struct ioat_softc *, uint32_t, 10364562Sgshapiro enum ioat_ref_kind); 10438032Speterstatic inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106static void ioat_drain_locked(struct ioat_softc *); 107 108#define ioat_log_message(v, ...) do { \ 109 if ((v) <= g_ioat_debug_level) { \ 110 device_printf(ioat->device, __VA_ARGS__); \ 111 } \ 112} while (0) 113 114MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 115SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 116 117static int g_force_legacy_interrupts; 118SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 119 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 120 121int g_ioat_debug_level = 0; 122SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 123 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 124 125/* 126 * OS <-> Driver interface structures 127 */ 128static device_method_t ioat_pci_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, ioat_probe), 131 DEVMETHOD(device_attach, ioat_attach), 132 DEVMETHOD(device_detach, ioat_detach), 133 { 0, 0 } 134}; 135 136static driver_t ioat_pci_driver = { 137 "ioat", 138 ioat_pci_methods, 139 sizeof(struct ioat_softc), 140}; 141 142static devclass_t ioat_devclass; 143DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 144MODULE_VERSION(ioat, 1); 145 146/* 147 * Private data structures 148 */ 149static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 150static int ioat_channel_index = 0; 151SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 152 "Number of IOAT channels attached"); 153 154static struct _pcsid 155{ 156 u_int32_t type; 157 const char *desc; 158} pci_ids[] = { 159 { 0x34308086, "TBG IOAT Ch0" }, 160 { 0x34318086, "TBG IOAT Ch1" }, 161 { 0x34328086, "TBG IOAT Ch2" }, 162 { 0x34338086, "TBG IOAT Ch3" }, 163 { 0x34298086, "TBG IOAT Ch4" }, 164 { 0x342a8086, "TBG IOAT Ch5" }, 165 { 0x342b8086, "TBG IOAT Ch6" }, 166 { 0x342c8086, "TBG IOAT Ch7" }, 167 168 { 0x37108086, "JSF IOAT Ch0" }, 169 { 0x37118086, "JSF IOAT Ch1" }, 170 { 0x37128086, "JSF IOAT Ch2" }, 171 { 0x37138086, "JSF IOAT Ch3" }, 172 { 0x37148086, "JSF IOAT Ch4" }, 173 { 0x37158086, "JSF IOAT Ch5" }, 174 { 0x37168086, "JSF IOAT Ch6" }, 175 { 0x37178086, "JSF IOAT Ch7" }, 176 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 177 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 178 179 { 0x3c208086, "SNB IOAT Ch0" }, 180 { 0x3c218086, "SNB IOAT Ch1" }, 181 { 0x3c228086, "SNB IOAT Ch2" }, 182 { 0x3c238086, "SNB IOAT Ch3" }, 183 { 0x3c248086, "SNB IOAT Ch4" }, 184 { 0x3c258086, "SNB IOAT Ch5" }, 185 { 0x3c268086, "SNB IOAT Ch6" }, 186 { 0x3c278086, "SNB IOAT Ch7" }, 187 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 188 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 189 190 { 0x0e208086, "IVB IOAT Ch0" }, 191 { 0x0e218086, "IVB IOAT Ch1" }, 192 { 0x0e228086, "IVB IOAT Ch2" }, 193 { 0x0e238086, "IVB IOAT Ch3" }, 194 { 0x0e248086, "IVB IOAT Ch4" }, 195 { 0x0e258086, "IVB IOAT Ch5" }, 196 { 0x0e268086, "IVB IOAT Ch6" }, 197 { 0x0e278086, "IVB IOAT Ch7" }, 198 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 199 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 200 201 { 0x2f208086, "HSW IOAT Ch0" }, 202 { 0x2f218086, "HSW IOAT Ch1" }, 203 { 0x2f228086, "HSW IOAT Ch2" }, 204 { 0x2f238086, "HSW IOAT Ch3" }, 205 { 0x2f248086, "HSW IOAT Ch4" }, 206 { 0x2f258086, "HSW IOAT Ch5" }, 207 { 0x2f268086, "HSW IOAT Ch6" }, 208 { 0x2f278086, "HSW IOAT Ch7" }, 209 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 210 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 211 212 { 0x0c508086, "BWD IOAT Ch0" }, 213 { 0x0c518086, "BWD IOAT Ch1" }, 214 { 0x0c528086, "BWD IOAT Ch2" }, 215 { 0x0c538086, "BWD IOAT Ch3" }, 216 217 { 0x6f508086, "BDXDE IOAT Ch0" }, 218 { 0x6f518086, "BDXDE IOAT Ch1" }, 219 { 0x6f528086, "BDXDE IOAT Ch2" }, 220 { 0x6f538086, "BDXDE IOAT Ch3" }, 221 222 { 0x6f208086, "BDX IOAT Ch0" }, 223 { 0x6f218086, "BDX IOAT Ch1" }, 224 { 0x6f228086, "BDX IOAT Ch2" }, 225 { 0x6f238086, "BDX IOAT Ch3" }, 226 { 0x6f248086, "BDX IOAT Ch4" }, 227 { 0x6f258086, "BDX IOAT Ch5" }, 228 { 0x6f268086, "BDX IOAT Ch6" }, 229 { 0x6f278086, "BDX IOAT Ch7" }, 230 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 231 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 232 233 { 0x00000000, NULL } 234}; 235 236/* 237 * OS <-> Driver linkage functions 238 */ 239static int 240ioat_probe(device_t device) 241{ 242 struct _pcsid *ep; 243 u_int32_t type; 244 245 type = pci_get_devid(device); 246 for (ep = pci_ids; ep->type; ep++) { 247 if (ep->type == type) { 248 device_set_desc(device, ep->desc); 249 return (0); 250 } 251 } 252 return (ENXIO); 253} 254 255static int 256ioat_attach(device_t device) 257{ 258 struct ioat_softc *ioat; 259 int error; 260 261 ioat = DEVICE2SOFTC(device); 262 ioat->device = device; 263 264 error = ioat_map_pci_bar(ioat); 265 if (error != 0) 266 goto err; 267 268 ioat->version = ioat_read_cbver(ioat); 269 if (ioat->version < IOAT_VER_3_0) { 270 error = ENODEV; 271 goto err; 272 } 273 274 error = ioat3_attach(device); 275 if (error != 0) 276 goto err; 277 278 error = pci_enable_busmaster(device); 279 if (error != 0) 280 goto err; 281 282 error = ioat_setup_intr(ioat); 283 if (error != 0) 284 goto err; 285 286 error = ioat_reset_hw(ioat); 287 if (error != 0) 288 goto err; 289 290 ioat_process_events(ioat); 291 ioat_setup_sysctl(device); 292 293 ioat->chan_idx = ioat_channel_index; 294 ioat_channel[ioat_channel_index++] = ioat; 295 ioat_test_attach(); 296 297err: 298 if (error != 0) 299 ioat_detach(device); 300 return (error); 301} 302 303static int 304ioat_detach(device_t device) 305{ 306 struct ioat_softc *ioat; 307 308 ioat = DEVICE2SOFTC(device); 309 310 ioat_test_detach(); 311 312 mtx_lock(IOAT_REFLK); 313 ioat->quiescing = TRUE; 314 ioat_channel[ioat->chan_idx] = NULL; 315 316 ioat_drain_locked(ioat); 317 mtx_unlock(IOAT_REFLK); 318 319 ioat_teardown_intr(ioat); 320 callout_drain(&ioat->timer); 321 322 pci_disable_busmaster(device); 323 324 if (ioat->pci_resource != NULL) 325 bus_release_resource(device, SYS_RES_MEMORY, 326 ioat->pci_resource_id, ioat->pci_resource); 327 328 if (ioat->ring != NULL) 329 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 330 331 if (ioat->comp_update != NULL) { 332 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 333 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 334 ioat->comp_update_map); 335 bus_dma_tag_destroy(ioat->comp_update_tag); 336 } 337 338 bus_dma_tag_destroy(ioat->hw_desc_tag); 339 340 return (0); 341} 342 343static int 344ioat_teardown_intr(struct ioat_softc *ioat) 345{ 346 347 if (ioat->tag != NULL) 348 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 349 350 if (ioat->res != NULL) 351 bus_release_resource(ioat->device, SYS_RES_IRQ, 352 rman_get_rid(ioat->res), ioat->res); 353 354 pci_release_msi(ioat->device); 355 return (0); 356} 357 358static int 359ioat_start_channel(struct ioat_softc *ioat) 360{ 361 uint64_t status; 362 uint32_t chanerr; 363 int i; 364 365 ioat_acquire(&ioat->dmaengine); 366 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 367 ioat_release(&ioat->dmaengine); 368 369 for (i = 0; i < 100; i++) { 370 DELAY(1); 371 status = ioat_get_chansts(ioat); 372 if (is_ioat_idle(status)) 373 return (0); 374 } 375 376 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 377 ioat_log_message(0, "could not start channel: " 378 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 379 IOAT_CHANERR_STR); 380 return (ENXIO); 381} 382 383/* 384 * Initialize Hardware 385 */ 386static int 387ioat3_attach(device_t device) 388{ 389 struct ioat_softc *ioat; 390 struct ioat_descriptor **ring; 391 struct ioat_descriptor *next; 392 struct ioat_dma_hw_descriptor *dma_hw_desc; 393 int i, num_descriptors; 394 int error; 395 uint8_t xfercap; 396 397 error = 0; 398 ioat = DEVICE2SOFTC(device); 399 ioat->capabilities = ioat_read_dmacapability(ioat); 400 401 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 402 IOAT_DMACAP_STR); 403 404 xfercap = ioat_read_xfercap(ioat); 405 ioat->max_xfer_size = 1 << xfercap; 406 407 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 408 IOAT_INTRDELAY_SUPPORTED) != 0; 409 if (ioat->intrdelay_supported) 410 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 411 412 /* TODO: need to check DCA here if we ever do XOR/PQ */ 413 414 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 415 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 416 callout_init(&ioat->timer, 1); 417 418 /* Establish lock order for Witness */ 419 mtx_lock(&ioat->submit_lock); 420 mtx_lock(&ioat->cleanup_lock); 421 mtx_unlock(&ioat->cleanup_lock); 422 mtx_unlock(&ioat->submit_lock); 423 424 ioat->is_resize_pending = FALSE; 425 ioat->is_completion_pending = FALSE; 426 ioat->is_reset_pending = FALSE; 427 ioat->is_channel_running = FALSE; 428 429 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 430 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 431 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 432 &ioat->comp_update_tag); 433 434 error = bus_dmamem_alloc(ioat->comp_update_tag, 435 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 436 if (ioat->comp_update == NULL) 437 return (ENOMEM); 438 439 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 440 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 441 0); 442 if (error != 0) 443 return (error); 444 445 ioat->ring_size_order = IOAT_MIN_ORDER; 446 447 num_descriptors = 1 << ioat->ring_size_order; 448 449 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 450 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 451 sizeof(struct ioat_dma_hw_descriptor), 1, 452 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 453 &ioat->hw_desc_tag); 454 455 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 456 M_ZERO | M_WAITOK); 457 if (ioat->ring == NULL) 458 return (ENOMEM); 459 460 ring = ioat->ring; 461 for (i = 0; i < num_descriptors; i++) { 462 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 463 if (ring[i] == NULL) 464 return (ENOMEM); 465 466 ring[i]->id = i; 467 } 468 469 for (i = 0; i < num_descriptors - 1; i++) { 470 next = ring[i + 1]; 471 dma_hw_desc = ring[i]->u.dma; 472 473 dma_hw_desc->next = next->hw_desc_bus_addr; 474 } 475 476 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 477 478 ioat->head = ioat->hw_head = 0; 479 ioat->tail = 0; 480 ioat->last_seen = 0; 481 return (0); 482} 483 484static int 485ioat_map_pci_bar(struct ioat_softc *ioat) 486{ 487 488 ioat->pci_resource_id = PCIR_BAR(0); 489 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 490 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 491 492 if (ioat->pci_resource == NULL) { 493 ioat_log_message(0, "unable to allocate pci resource\n"); 494 return (ENODEV); 495 } 496 497 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 498 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 499 return (0); 500} 501 502static void 503ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 504{ 505 struct ioat_softc *ioat = arg; 506 507 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 508 ioat->comp_update_bus_addr = seg[0].ds_addr; 509} 510 511static void 512ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 513{ 514 bus_addr_t *baddr; 515 516 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 517 baddr = arg; 518 *baddr = segs->ds_addr; 519} 520 521/* 522 * Interrupt setup and handlers 523 */ 524static int 525ioat_setup_intr(struct ioat_softc *ioat) 526{ 527 uint32_t num_vectors; 528 int error; 529 boolean_t use_msix; 530 boolean_t force_legacy_interrupts; 531 532 use_msix = FALSE; 533 force_legacy_interrupts = FALSE; 534 535 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 536 num_vectors = 1; 537 pci_alloc_msix(ioat->device, &num_vectors); 538 if (num_vectors == 1) 539 use_msix = TRUE; 540 } 541 542 if (use_msix) { 543 ioat->rid = 1; 544 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 545 &ioat->rid, RF_ACTIVE); 546 } else { 547 ioat->rid = 0; 548 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 549 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 550 } 551 if (ioat->res == NULL) { 552 ioat_log_message(0, "bus_alloc_resource failed\n"); 553 return (ENOMEM); 554 } 555 556 ioat->tag = NULL; 557 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 558 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 559 if (error != 0) { 560 ioat_log_message(0, "bus_setup_intr failed\n"); 561 return (error); 562 } 563 564 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 565 return (0); 566} 567 568static boolean_t 569ioat_model_resets_msix(struct ioat_softc *ioat) 570{ 571 u_int32_t pciid; 572 573 pciid = pci_get_devid(ioat->device); 574 switch (pciid) { 575 /* BWD: */ 576 case 0x0c508086: 577 case 0x0c518086: 578 case 0x0c528086: 579 case 0x0c538086: 580 /* BDXDE: */ 581 case 0x6f508086: 582 case 0x6f518086: 583 case 0x6f528086: 584 case 0x6f538086: 585 return (TRUE); 586 } 587 588 return (FALSE); 589} 590 591static void 592ioat_interrupt_handler(void *arg) 593{ 594 struct ioat_softc *ioat = arg; 595 596 ioat->stats.interrupts++; 597 ioat_process_events(ioat); 598} 599 600static int 601chanerr_to_errno(uint32_t chanerr) 602{ 603 604 if (chanerr == 0) 605 return (0); 606 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 607 return (EFAULT); 608 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 609 return (EIO); 610 /* This one is probably our fault: */ 611 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 612 return (EIO); 613 return (EIO); 614} 615 616static void 617ioat_process_events(struct ioat_softc *ioat) 618{ 619 struct ioat_descriptor *desc; 620 struct bus_dmadesc *dmadesc; 621 uint64_t comp_update, status; 622 uint32_t completed, chanerr; 623 int error; 624 625 mtx_lock(&ioat->cleanup_lock); 626 627 completed = 0; 628 comp_update = *ioat->comp_update; 629 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 630 631 CTR0(KTR_IOAT, __func__); 632 633 if (status == ioat->last_seen) 634 goto out; 635 636 while (1) { 637 desc = ioat_get_ring_entry(ioat, ioat->tail); 638 dmadesc = &desc->bus_dmadesc; 639 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 640 641 if (dmadesc->callback_fn != NULL) 642 dmadesc->callback_fn(dmadesc->callback_arg, 0); 643 644 completed++; 645 ioat->tail++; 646 if (desc->hw_desc_bus_addr == status) 647 break; 648 } 649 650 ioat->last_seen = desc->hw_desc_bus_addr; 651 652 if (ioat->head == ioat->tail) { 653 ioat->is_completion_pending = FALSE; 654 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 655 ioat_timer_callback, ioat); 656 } 657 658 ioat->stats.descriptors_processed += completed; 659 660out: 661 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 662 mtx_unlock(&ioat->cleanup_lock); 663 664 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 665 wakeup(&ioat->tail); 666 667 if (!is_ioat_halted(comp_update)) 668 return; 669 670 ioat->stats.channel_halts++; 671 672 /* 673 * Fatal programming error on this DMA channel. Flush any outstanding 674 * work with error status and restart the engine. 675 */ 676 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 677 mtx_lock(&ioat->submit_lock); 678 mtx_lock(&ioat->cleanup_lock); 679 ioat->quiescing = TRUE; 680 681 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 682 ioat_halted_debug(ioat, chanerr); 683 ioat->stats.last_halt_chanerr = chanerr; 684 685 while (ioat_get_active(ioat) > 0) { 686 desc = ioat_get_ring_entry(ioat, ioat->tail); 687 dmadesc = &desc->bus_dmadesc; 688 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 689 690 if (dmadesc->callback_fn != NULL) 691 dmadesc->callback_fn(dmadesc->callback_arg, 692 chanerr_to_errno(chanerr)); 693 694 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 695 ioat->tail++; 696 ioat->stats.descriptors_processed++; 697 ioat->stats.descriptors_error++; 698 } 699 700 /* Clear error status */ 701 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 702 703 mtx_unlock(&ioat->cleanup_lock); 704 mtx_unlock(&ioat->submit_lock); 705 706 ioat_log_message(0, "Resetting channel to recover from error\n"); 707 error = ioat_reset_hw(ioat); 708 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 709} 710 711/* 712 * User API functions 713 */ 714bus_dmaengine_t 715ioat_get_dmaengine(uint32_t index) 716{ 717 struct ioat_softc *sc; 718 719 if (index >= ioat_channel_index) 720 return (NULL); 721 722 sc = ioat_channel[index]; 723 if (sc == NULL || sc->quiescing) 724 return (NULL); 725 726 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 727} 728 729void 730ioat_put_dmaengine(bus_dmaengine_t dmaengine) 731{ 732 struct ioat_softc *ioat; 733 734 ioat = to_ioat_softc(dmaengine); 735 ioat_put(ioat, IOAT_DMAENGINE_REF); 736} 737 738int 739ioat_get_hwversion(bus_dmaengine_t dmaengine) 740{ 741 struct ioat_softc *ioat; 742 743 ioat = to_ioat_softc(dmaengine); 744 return (ioat->version); 745} 746 747size_t 748ioat_get_max_io_size(bus_dmaengine_t dmaengine) 749{ 750 struct ioat_softc *ioat; 751 752 ioat = to_ioat_softc(dmaengine); 753 return (ioat->max_xfer_size); 754} 755 756int 757ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 758{ 759 struct ioat_softc *ioat; 760 761 ioat = to_ioat_softc(dmaengine); 762 if (!ioat->intrdelay_supported) 763 return (ENODEV); 764 if (delay > ioat->intrdelay_max) 765 return (ERANGE); 766 767 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 768 ioat->cached_intrdelay = 769 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 770 return (0); 771} 772 773uint16_t 774ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 775{ 776 struct ioat_softc *ioat; 777 778 ioat = to_ioat_softc(dmaengine); 779 return (ioat->intrdelay_max); 780} 781 782void 783ioat_acquire(bus_dmaengine_t dmaengine) 784{ 785 struct ioat_softc *ioat; 786 787 ioat = to_ioat_softc(dmaengine); 788 mtx_lock(&ioat->submit_lock); 789 CTR0(KTR_IOAT, __func__); 790} 791 792int 793ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 794{ 795 struct ioat_softc *ioat; 796 int error; 797 798 ioat = to_ioat_softc(dmaengine); 799 ioat_acquire(dmaengine); 800 801 error = ioat_reserve_space(ioat, n, mflags); 802 if (error != 0) 803 ioat_release(dmaengine); 804 return (error); 805} 806 807void 808ioat_release(bus_dmaengine_t dmaengine) 809{ 810 struct ioat_softc *ioat; 811 812 ioat = to_ioat_softc(dmaengine); 813 CTR0(KTR_IOAT, __func__); 814 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 815 mtx_unlock(&ioat->submit_lock); 816} 817 818static struct ioat_descriptor * 819ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 820 uint32_t size, uint64_t src, uint64_t dst, 821 bus_dmaengine_callback_t callback_fn, void *callback_arg, 822 uint32_t flags) 823{ 824 struct ioat_generic_hw_descriptor *hw_desc; 825 struct ioat_descriptor *desc; 826 int mflags; 827 828 mtx_assert(&ioat->submit_lock, MA_OWNED); 829 830 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 831 flags & ~DMA_ALL_FLAGS)); 832 if ((flags & DMA_NO_WAIT) != 0) 833 mflags = M_NOWAIT; 834 else 835 mflags = M_WAITOK; 836 837 if (size > ioat->max_xfer_size) { 838 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 839 __func__, ioat->max_xfer_size, (unsigned)size); 840 return (NULL); 841 } 842 843 if (ioat_reserve_space(ioat, 1, mflags) != 0) 844 return (NULL); 845 846 desc = ioat_get_ring_entry(ioat, ioat->head); 847 hw_desc = desc->u.generic; 848 849 hw_desc->u.control_raw = 0; 850 hw_desc->u.control_generic.op = op; 851 hw_desc->u.control_generic.completion_update = 1; 852 853 if ((flags & DMA_INT_EN) != 0) 854 hw_desc->u.control_generic.int_enable = 1; 855 856 hw_desc->size = size; 857 hw_desc->src_addr = src; 858 hw_desc->dest_addr = dst; 859 860 desc->bus_dmadesc.callback_fn = callback_fn; 861 desc->bus_dmadesc.callback_arg = callback_arg; 862 return (desc); 863} 864 865struct bus_dmadesc * 866ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 867 void *callback_arg, uint32_t flags) 868{ 869 struct ioat_dma_hw_descriptor *hw_desc; 870 struct ioat_descriptor *desc; 871 struct ioat_softc *ioat; 872 873 CTR0(KTR_IOAT, __func__); 874 ioat = to_ioat_softc(dmaengine); 875 876 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 877 callback_arg, flags); 878 if (desc == NULL) 879 return (NULL); 880 881 hw_desc = desc->u.dma; 882 hw_desc->u.control.null = 1; 883 ioat_submit_single(ioat); 884 return (&desc->bus_dmadesc); 885} 886 887struct bus_dmadesc * 888ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 889 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 890 void *callback_arg, uint32_t flags) 891{ 892 struct ioat_dma_hw_descriptor *hw_desc; 893 struct ioat_descriptor *desc; 894 struct ioat_softc *ioat; 895 896 CTR0(KTR_IOAT, __func__); 897 ioat = to_ioat_softc(dmaengine); 898 899 if (((src | dst) & (0xffffull << 48)) != 0) { 900 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 901 __func__); 902 return (NULL); 903 } 904 905 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 906 callback_arg, flags); 907 if (desc == NULL) 908 return (NULL); 909 910 hw_desc = desc->u.dma; 911 if (g_ioat_debug_level >= 3) 912 dump_descriptor(hw_desc); 913 914 ioat_submit_single(ioat); 915 return (&desc->bus_dmadesc); 916} 917 918struct bus_dmadesc * 919ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 920 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 921 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 922{ 923 struct ioat_dma_hw_descriptor *hw_desc; 924 struct ioat_descriptor *desc; 925 struct ioat_softc *ioat; 926 927 CTR0(KTR_IOAT, __func__); 928 ioat = to_ioat_softc(dmaengine); 929 930 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 931 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 932 __func__); 933 return (NULL); 934 } 935 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 936 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 937 __func__); 938 return (NULL); 939 } 940 941 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 942 callback_fn, callback_arg, flags); 943 if (desc == NULL) 944 return (NULL); 945 946 hw_desc = desc->u.dma; 947 if (src2 != src1 + PAGE_SIZE) { 948 hw_desc->u.control.src_page_break = 1; 949 hw_desc->next_src_addr = src2; 950 } 951 if (dst2 != dst1 + PAGE_SIZE) { 952 hw_desc->u.control.dest_page_break = 1; 953 hw_desc->next_dest_addr = dst2; 954 } 955 956 if (g_ioat_debug_level >= 3) 957 dump_descriptor(hw_desc); 958 959 ioat_submit_single(ioat); 960 return (&desc->bus_dmadesc); 961} 962 963struct bus_dmadesc * 964ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 965 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 966 uint32_t flags) 967{ 968 struct ioat_fill_hw_descriptor *hw_desc; 969 struct ioat_descriptor *desc; 970 struct ioat_softc *ioat; 971 972 CTR0(KTR_IOAT, __func__); 973 ioat = to_ioat_softc(dmaengine); 974 975 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 976 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 977 __func__); 978 return (NULL); 979 } 980 981 if ((dst & (0xffffull << 48)) != 0) { 982 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 983 __func__); 984 return (NULL); 985 } 986 987 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 988 callback_fn, callback_arg, flags); 989 if (desc == NULL) 990 return (NULL); 991 992 hw_desc = desc->u.fill; 993 if (g_ioat_debug_level >= 3) 994 dump_descriptor(hw_desc); 995 996 ioat_submit_single(ioat); 997 return (&desc->bus_dmadesc); 998} 999 1000/* 1001 * Ring Management 1002 */ 1003static inline uint32_t 1004ioat_get_active(struct ioat_softc *ioat) 1005{ 1006 1007 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1008} 1009 1010static inline uint32_t 1011ioat_get_ring_space(struct ioat_softc *ioat) 1012{ 1013 1014 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1015} 1016 1017static struct ioat_descriptor * 1018ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1019{ 1020 struct ioat_generic_hw_descriptor *hw_desc; 1021 struct ioat_descriptor *desc; 1022 int error, busdmaflag; 1023 1024 error = ENOMEM; 1025 hw_desc = NULL; 1026 1027 if ((mflags & M_WAITOK) != 0) 1028 busdmaflag = BUS_DMA_WAITOK; 1029 else 1030 busdmaflag = BUS_DMA_NOWAIT; 1031 1032 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1033 if (desc == NULL) 1034 goto out; 1035 1036 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1037 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1038 if (hw_desc == NULL) 1039 goto out; 1040 1041 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1042 desc->u.generic = hw_desc; 1043 1044 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1045 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1046 busdmaflag); 1047 if (error) 1048 goto out; 1049 1050out: 1051 if (error) { 1052 ioat_free_ring_entry(ioat, desc); 1053 return (NULL); 1054 } 1055 return (desc); 1056} 1057 1058static void 1059ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1060{ 1061 1062 if (desc == NULL) 1063 return; 1064 1065 if (desc->u.generic) 1066 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1067 ioat->hw_desc_map); 1068 free(desc, M_IOAT); 1069} 1070 1071/* 1072 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1073 * for 'num_descs'. 1074 * 1075 * If mflags contains M_WAITOK, blocks until enough space is available. 1076 * 1077 * Returns zero on success, or an errno on error. If num_descs is beyond the 1078 * maximum ring size, returns EINVAl; if allocation would block and mflags 1079 * contains M_NOWAIT, returns EAGAIN. 1080 * 1081 * Must be called with the submit_lock held; returns with the lock held. The 1082 * lock may be dropped to allocate the ring. 1083 * 1084 * (The submit_lock is needed to add any entries to the ring, so callers are 1085 * assured enough room is available.) 1086 */ 1087static int 1088ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1089{ 1090 struct ioat_descriptor **new_ring; 1091 uint32_t order; 1092 int error; 1093 1094 mtx_assert(&ioat->submit_lock, MA_OWNED); 1095 error = 0; 1096 1097 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1098 error = EINVAL; 1099 goto out; 1100 } 1101 if (ioat->quiescing) { 1102 error = ENXIO; 1103 goto out; 1104 } 1105 1106 for (;;) { 1107 if (ioat_get_ring_space(ioat) >= num_descs) 1108 goto out; 1109 1110 order = ioat->ring_size_order; 1111 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1112 if ((mflags & M_WAITOK) != 0) { 1113 msleep(&ioat->tail, &ioat->submit_lock, 0, 1114 "ioat_rsz", 0); 1115 continue; 1116 } 1117 1118 error = EAGAIN; 1119 break; 1120 } 1121 1122 ioat->is_resize_pending = TRUE; 1123 for (;;) { 1124 mtx_unlock(&ioat->submit_lock); 1125 1126 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1127 TRUE, mflags); 1128 1129 mtx_lock(&ioat->submit_lock); 1130 KASSERT(ioat->ring_size_order == order, 1131 ("is_resize_pending should protect order")); 1132 1133 if (new_ring == NULL) { 1134 KASSERT((mflags & M_WAITOK) == 0, 1135 ("allocation failed")); 1136 error = EAGAIN; 1137 break; 1138 } 1139 1140 error = ring_grow(ioat, order, new_ring); 1141 if (error == 0) 1142 break; 1143 } 1144 ioat->is_resize_pending = FALSE; 1145 wakeup(&ioat->tail); 1146 if (error) 1147 break; 1148 } 1149 1150out: 1151 mtx_assert(&ioat->submit_lock, MA_OWNED); 1152 return (error); 1153} 1154 1155static struct ioat_descriptor ** 1156ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1157 int mflags) 1158{ 1159 struct ioat_descriptor **ring; 1160 uint32_t i; 1161 int error; 1162 1163 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1164 1165 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1166 if (ring == NULL) 1167 return (NULL); 1168 1169 if (need_dscr) { 1170 error = ENOMEM; 1171 for (i = size / 2; i < size; i++) { 1172 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1173 if (ring[i] == NULL) 1174 goto out; 1175 ring[i]->id = i; 1176 } 1177 } 1178 error = 0; 1179 1180out: 1181 if (error != 0 && ring != NULL) { 1182 ioat_free_ring(ioat, size, ring); 1183 ring = NULL; 1184 } 1185 return (ring); 1186} 1187 1188static void 1189ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1190 struct ioat_descriptor **ring) 1191{ 1192 uint32_t i; 1193 1194 for (i = 0; i < size; i++) { 1195 if (ring[i] != NULL) 1196 ioat_free_ring_entry(ioat, ring[i]); 1197 } 1198 free(ring, M_IOAT); 1199} 1200 1201static struct ioat_descriptor * 1202ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1203{ 1204 1205 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1206} 1207 1208static int 1209ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1210 struct ioat_descriptor **newring) 1211{ 1212 struct ioat_descriptor *tmp, *next; 1213 struct ioat_dma_hw_descriptor *hw; 1214 uint32_t oldsize, newsize, head, tail, i, end; 1215 int error; 1216 1217 CTR0(KTR_IOAT, __func__); 1218 1219 mtx_assert(&ioat->submit_lock, MA_OWNED); 1220 1221 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1222 error = EINVAL; 1223 goto out; 1224 } 1225 1226 oldsize = (1 << oldorder); 1227 newsize = (1 << (oldorder + 1)); 1228 1229 mtx_lock(&ioat->cleanup_lock); 1230 1231 head = ioat->head & (oldsize - 1); 1232 tail = ioat->tail & (oldsize - 1); 1233 1234 /* Copy old descriptors to new ring */ 1235 for (i = 0; i < oldsize; i++) 1236 newring[i] = ioat->ring[i]; 1237 1238 /* 1239 * If head has wrapped but tail hasn't, we must swap some descriptors 1240 * around so that tail can increment directly to head. 1241 */ 1242 if (head < tail) { 1243 for (i = 0; i <= head; i++) { 1244 tmp = newring[oldsize + i]; 1245 1246 newring[oldsize + i] = newring[i]; 1247 newring[oldsize + i]->id = oldsize + i; 1248 1249 newring[i] = tmp; 1250 newring[i]->id = i; 1251 } 1252 head += oldsize; 1253 } 1254 1255 KASSERT(head >= tail, ("invariants")); 1256 1257 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1258 if (head < oldsize) { 1259 i = oldsize - 1; 1260 end = newsize; 1261 } else { 1262 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1263 i = head; 1264 end = newsize + (head - oldsize) + 1; 1265 } 1266 1267 /* 1268 * Fix up hardware ring, being careful not to trample the active 1269 * section (tail -> head). 1270 */ 1271 for (; i < end; i++) { 1272 KASSERT((i & (newsize - 1)) < tail || 1273 (i & (newsize - 1)) >= head, ("trampling snake")); 1274 1275 next = newring[(i + 1) & (newsize - 1)]; 1276 hw = newring[i & (newsize - 1)]->u.dma; 1277 hw->next = next->hw_desc_bus_addr; 1278 } 1279 1280 free(ioat->ring, M_IOAT); 1281 ioat->ring = newring; 1282 ioat->ring_size_order = oldorder + 1; 1283 ioat->tail = tail; 1284 ioat->head = head; 1285 error = 0; 1286 1287 mtx_unlock(&ioat->cleanup_lock); 1288out: 1289 if (error) 1290 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1291 return (error); 1292} 1293 1294static int 1295ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1296 struct ioat_descriptor **newring) 1297{ 1298 struct ioat_dma_hw_descriptor *hw; 1299 struct ioat_descriptor *ent, *next; 1300 uint32_t oldsize, newsize, current_idx, new_idx, i; 1301 int error; 1302 1303 CTR0(KTR_IOAT, __func__); 1304 1305 mtx_assert(&ioat->submit_lock, MA_OWNED); 1306 1307 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1308 error = EINVAL; 1309 goto out_unlocked; 1310 } 1311 1312 oldsize = (1 << oldorder); 1313 newsize = (1 << (oldorder - 1)); 1314 1315 mtx_lock(&ioat->cleanup_lock); 1316 1317 /* Can't shrink below current active set! */ 1318 if (ioat_get_active(ioat) >= newsize) { 1319 error = ENOMEM; 1320 goto out; 1321 } 1322 1323 /* 1324 * Copy current descriptors to the new ring, dropping the removed 1325 * descriptors. 1326 */ 1327 for (i = 0; i < newsize; i++) { 1328 current_idx = (ioat->tail + i) & (oldsize - 1); 1329 new_idx = (ioat->tail + i) & (newsize - 1); 1330 1331 newring[new_idx] = ioat->ring[current_idx]; 1332 newring[new_idx]->id = new_idx; 1333 } 1334 1335 /* Free deleted descriptors */ 1336 for (i = newsize; i < oldsize; i++) { 1337 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1338 ioat_free_ring_entry(ioat, ent); 1339 } 1340 1341 /* Fix up hardware ring. */ 1342 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1343 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1344 hw->next = next->hw_desc_bus_addr; 1345 1346 free(ioat->ring, M_IOAT); 1347 ioat->ring = newring; 1348 ioat->ring_size_order = oldorder - 1; 1349 error = 0; 1350 1351out: 1352 mtx_unlock(&ioat->cleanup_lock); 1353out_unlocked: 1354 if (error) 1355 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1356 return (error); 1357} 1358 1359static void 1360ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1361{ 1362 struct ioat_descriptor *desc; 1363 1364 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1365 IOAT_CHANERR_STR); 1366 if (chanerr == 0) 1367 return; 1368 1369 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1370 1371 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1372 dump_descriptor(desc->u.raw); 1373 1374 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1375 dump_descriptor(desc->u.raw); 1376} 1377 1378static void 1379ioat_timer_callback(void *arg) 1380{ 1381 struct ioat_descriptor **newring; 1382 struct ioat_softc *ioat; 1383 uint32_t order; 1384 1385 ioat = arg; 1386 ioat_log_message(1, "%s\n", __func__); 1387 1388 if (ioat->is_completion_pending) { 1389 ioat_process_events(ioat); 1390 return; 1391 } 1392 1393 /* Slowly scale the ring down if idle. */ 1394 mtx_lock(&ioat->submit_lock); 1395 order = ioat->ring_size_order; 1396 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1397 mtx_unlock(&ioat->submit_lock); 1398 goto out; 1399 } 1400 ioat->is_resize_pending = TRUE; 1401 mtx_unlock(&ioat->submit_lock); 1402 1403 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1404 M_NOWAIT); 1405 1406 mtx_lock(&ioat->submit_lock); 1407 KASSERT(ioat->ring_size_order == order, 1408 ("resize_pending protects order")); 1409 1410 if (newring != NULL) 1411 ring_shrink(ioat, order, newring); 1412 1413 ioat->is_resize_pending = FALSE; 1414 mtx_unlock(&ioat->submit_lock); 1415 1416out: 1417 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1418 callout_reset(&ioat->timer, 10 * hz, 1419 ioat_timer_callback, ioat); 1420} 1421 1422/* 1423 * Support Functions 1424 */ 1425static void 1426ioat_submit_single(struct ioat_softc *ioat) 1427{ 1428 1429 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1430 atomic_add_rel_int(&ioat->head, 1); 1431 atomic_add_rel_int(&ioat->hw_head, 1); 1432 1433 if (!ioat->is_completion_pending) { 1434 ioat->is_completion_pending = TRUE; 1435 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1436 ioat_timer_callback, ioat); 1437 } 1438 1439 ioat->stats.descriptors_submitted++; 1440} 1441 1442static int 1443ioat_reset_hw(struct ioat_softc *ioat) 1444{ 1445 uint64_t status; 1446 uint32_t chanerr; 1447 unsigned timeout; 1448 int error; 1449 1450 mtx_lock(IOAT_REFLK); 1451 ioat->quiescing = TRUE; 1452 ioat_drain_locked(ioat); 1453 mtx_unlock(IOAT_REFLK); 1454 1455 status = ioat_get_chansts(ioat); 1456 if (is_ioat_active(status) || is_ioat_idle(status)) 1457 ioat_suspend(ioat); 1458 1459 /* Wait at most 20 ms */ 1460 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1461 timeout < 20; timeout++) { 1462 DELAY(1000); 1463 status = ioat_get_chansts(ioat); 1464 } 1465 if (timeout == 20) { 1466 error = ETIMEDOUT; 1467 goto out; 1468 } 1469 1470 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1471 1472 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1473 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1474 1475 /* 1476 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1477 * that can cause stability issues for IOAT v3. 1478 */ 1479 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1480 4); 1481 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1482 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1483 1484 /* 1485 * BDXDE and BWD models reset MSI-X registers on device reset. 1486 * Save/restore their contents manually. 1487 */ 1488 if (ioat_model_resets_msix(ioat)) { 1489 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1490 pci_save_state(ioat->device); 1491 } 1492 1493 ioat_reset(ioat); 1494 1495 /* Wait at most 20 ms */ 1496 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1497 DELAY(1000); 1498 if (timeout == 20) { 1499 error = ETIMEDOUT; 1500 goto out; 1501 } 1502 1503 if (ioat_model_resets_msix(ioat)) { 1504 ioat_log_message(1, "device resets registers; restored\n"); 1505 pci_restore_state(ioat->device); 1506 } 1507 1508 /* Reset attempts to return the hardware to "halted." */ 1509 status = ioat_get_chansts(ioat); 1510 if (is_ioat_active(status) || is_ioat_idle(status)) { 1511 /* So this really shouldn't happen... */ 1512 ioat_log_message(0, "Device is active after a reset?\n"); 1513 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1514 error = 0; 1515 goto out; 1516 } 1517 1518 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1519 if (chanerr != 0) { 1520 mtx_lock(&ioat->cleanup_lock); 1521 ioat_halted_debug(ioat, chanerr); 1522 mtx_unlock(&ioat->cleanup_lock); 1523 error = EIO; 1524 goto out; 1525 } 1526 1527 /* 1528 * Bring device back online after reset. Writing CHAINADDR brings the 1529 * device back to active. 1530 * 1531 * The internal ring counter resets to zero, so we have to start over 1532 * at zero as well. 1533 */ 1534 ioat->tail = ioat->head = ioat->hw_head = 0; 1535 ioat->last_seen = 0; 1536 1537 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1538 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1539 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1540 error = 0; 1541 1542out: 1543 mtx_lock(IOAT_REFLK); 1544 ioat->quiescing = FALSE; 1545 mtx_unlock(IOAT_REFLK); 1546 1547 if (error == 0) 1548 error = ioat_start_channel(ioat); 1549 1550 return (error); 1551} 1552 1553static int 1554sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1555{ 1556 struct ioat_softc *ioat; 1557 struct sbuf sb; 1558 uint64_t status; 1559 int error; 1560 1561 ioat = arg1; 1562 1563 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1564 1565 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1566 switch (status) { 1567 case IOAT_CHANSTS_ACTIVE: 1568 sbuf_printf(&sb, "ACTIVE"); 1569 break; 1570 case IOAT_CHANSTS_IDLE: 1571 sbuf_printf(&sb, "IDLE"); 1572 break; 1573 case IOAT_CHANSTS_SUSPENDED: 1574 sbuf_printf(&sb, "SUSPENDED"); 1575 break; 1576 case IOAT_CHANSTS_HALTED: 1577 sbuf_printf(&sb, "HALTED"); 1578 break; 1579 case IOAT_CHANSTS_ARMED: 1580 sbuf_printf(&sb, "ARMED"); 1581 break; 1582 default: 1583 sbuf_printf(&sb, "UNKNOWN"); 1584 break; 1585 } 1586 error = sbuf_finish(&sb); 1587 sbuf_delete(&sb); 1588 1589 if (error != 0 || req->newptr == NULL) 1590 return (error); 1591 return (EINVAL); 1592} 1593 1594static int 1595sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1596{ 1597 struct ioat_softc *ioat; 1598 struct sbuf sb; 1599#define PRECISION "1" 1600 const uintmax_t factor = 10; 1601 uintmax_t rate; 1602 int error; 1603 1604 ioat = arg1; 1605 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1606 1607 if (ioat->stats.interrupts == 0) { 1608 sbuf_printf(&sb, "NaN"); 1609 goto out; 1610 } 1611 rate = ioat->stats.descriptors_processed * factor / 1612 ioat->stats.interrupts; 1613 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1614 rate % factor); 1615#undef PRECISION 1616out: 1617 error = sbuf_finish(&sb); 1618 sbuf_delete(&sb); 1619 if (error != 0 || req->newptr == NULL) 1620 return (error); 1621 return (EINVAL); 1622} 1623 1624static int 1625sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1626{ 1627 struct ioat_descriptor *desc; 1628 struct ioat_softc *ioat; 1629 int error, arg; 1630 1631 ioat = arg1; 1632 1633 arg = 0; 1634 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1635 if (error != 0 || req->newptr == NULL) 1636 return (error); 1637 1638 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1639 if (error != 0) 1640 return (error); 1641 1642 if (arg != 0) { 1643 ioat_acquire(&ioat->dmaengine); 1644 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1645 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1646 0); 1647 if (desc == NULL) 1648 error = ENOMEM; 1649 else 1650 ioat_submit_single(ioat); 1651 ioat_release(&ioat->dmaengine); 1652 } 1653 return (error); 1654} 1655 1656static int 1657sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1658{ 1659 struct ioat_softc *ioat; 1660 int error, arg; 1661 1662 ioat = arg1; 1663 1664 arg = 0; 1665 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1666 if (error != 0 || req->newptr == NULL) 1667 return (error); 1668 1669 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1670 if (error != 0) 1671 return (error); 1672 1673 if (arg != 0) 1674 error = ioat_reset_hw(ioat); 1675 1676 return (error); 1677} 1678 1679static void 1680dump_descriptor(void *hw_desc) 1681{ 1682 int i, j; 1683 1684 for (i = 0; i < 2; i++) { 1685 for (j = 0; j < 8; j++) 1686 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1687 printf("\n"); 1688 } 1689} 1690 1691static void 1692ioat_setup_sysctl(device_t device) 1693{ 1694 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1695 struct sysctl_ctx_list *ctx; 1696 struct sysctl_oid *tree, *tmp; 1697 struct ioat_softc *ioat; 1698 1699 ioat = DEVICE2SOFTC(device); 1700 ctx = device_get_sysctl_ctx(device); 1701 tree = device_get_sysctl_tree(device); 1702 par = SYSCTL_CHILDREN(tree); 1703 1704 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1705 &ioat->version, 0, "HW version (0xMM form)"); 1706 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1707 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1708 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1709 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1710 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1711 &ioat->intrdelay_max, 0, 1712 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1713 1714 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1715 "IOAT channel internal state"); 1716 state = SYSCTL_CHILDREN(tmp); 1717 1718 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1719 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1720 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1721 0, "SW descriptor head pointer index"); 1722 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1723 0, "SW descriptor tail pointer index"); 1724 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1725 &ioat->hw_head, 0, "HW DMACOUNT"); 1726 1727 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1728 ioat->comp_update, "HW addr of last completion"); 1729 1730 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1731 &ioat->is_resize_pending, 0, "resize pending"); 1732 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1733 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1734 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1735 &ioat->is_reset_pending, 0, "reset pending"); 1736 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1737 &ioat->is_channel_running, 0, "channel running"); 1738 1739 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1740 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1741 "String of the channel status"); 1742 1743 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1744 &ioat->cached_intrdelay, 0, 1745 "Current INTRDELAY on this channel (cached, microseconds)"); 1746 1747 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1748 "Big hammers (mostly for testing)"); 1749 hammer = SYSCTL_CHILDREN(tmp); 1750 1751 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1752 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1753 "Set to non-zero to reset the hardware"); 1754 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1755 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1756 "Set to non-zero to inject a recoverable hardware error"); 1757 1758 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1759 "IOAT channel statistics"); 1760 statpar = SYSCTL_CHILDREN(tmp); 1761 1762 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1763 &ioat->stats.interrupts, 1764 "Number of interrupts processed on this channel"); 1765 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1766 &ioat->stats.descriptors_processed, 1767 "Number of descriptors processed on this channel"); 1768 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1769 &ioat->stats.descriptors_submitted, 1770 "Number of descriptors submitted to this channel"); 1771 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1772 &ioat->stats.descriptors_error, 1773 "Number of descriptors failed by channel errors"); 1774 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1775 &ioat->stats.channel_halts, 0, 1776 "Number of times the channel has halted"); 1777 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1778 &ioat->stats.last_halt_chanerr, 0, 1779 "The raw CHANERR when the channel was last halted"); 1780 1781 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1782 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1783 "Descriptors per interrupt"); 1784} 1785 1786static inline struct ioat_softc * 1787ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1788{ 1789 uint32_t old; 1790 1791 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1792 1793 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1794 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1795 1796#ifdef INVARIANTS 1797 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1798 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1799#endif 1800 1801 return (ioat); 1802} 1803 1804static inline void 1805ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1806{ 1807 1808 _ioat_putn(ioat, n, kind, FALSE); 1809} 1810 1811static inline void 1812ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1813{ 1814 1815 _ioat_putn(ioat, n, kind, TRUE); 1816} 1817 1818static inline void 1819_ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1820 boolean_t locked) 1821{ 1822 uint32_t old; 1823 1824 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1825 1826 if (n == 0) 1827 return; 1828 1829#ifdef INVARIANTS 1830 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1831 KASSERT(old >= n, ("refcnt kind underflow")); 1832#endif 1833 1834 /* Skip acquiring the lock if resulting refcnt > 0. */ 1835 for (;;) { 1836 old = ioat->refcnt; 1837 if (old <= n) 1838 break; 1839 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1840 return; 1841 } 1842 1843 if (locked) 1844 mtx_assert(IOAT_REFLK, MA_OWNED); 1845 else 1846 mtx_lock(IOAT_REFLK); 1847 1848 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1849 KASSERT(old >= n, ("refcnt error")); 1850 1851 if (old == n) 1852 wakeup(IOAT_REFLK); 1853 if (!locked) 1854 mtx_unlock(IOAT_REFLK); 1855} 1856 1857static inline void 1858ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1859{ 1860 1861 ioat_putn(ioat, 1, kind); 1862} 1863 1864static void 1865ioat_drain_locked(struct ioat_softc *ioat) 1866{ 1867 1868 mtx_assert(IOAT_REFLK, MA_OWNED); 1869 while (ioat->refcnt > 0) 1870 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1871} 1872