isl12xx.c revision 323467
1/*- 2 * Copyright (c) 2017 Ian Lepore. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: stable/11/sys/dev/iicbus/isl12xx.c 323467 2017-09-11 22:21:15Z ian $"); 27 28/* 29 * Driver for ISL12xx family i2c realtime clocks: 30 * - ISL1209 = 2B sram, tamper/event timestamp 31 * - ISL1218 = 8B sram, DS13xx pin compatible (but not software compatible) 32 * - ISL1219 = 2B sram, tamper/event timestamp 33 * - ISL1220 = 8B sram, separate Fout 34 * - ISL1221 = 2B sram, separate Fout, tamper/event timestamp 35 * 36 * This driver supports only the basic RTC functionality in all these chips. 37 */ 38 39#include "opt_platform.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/clock.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/module.h> 48#include <sys/sx.h> 49 50#ifdef FDT 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53#endif 54 55#include <dev/iicbus/iiconf.h> 56#include <dev/iicbus/iicbus.h> 57 58#include "clock_if.h" 59#include "iicbus_if.h" 60 61/* 62 * All register and bit names as found in the datasheet. When a bit name ends 63 * in 'B' that stands for "bar" and it is an active-low signal; something named 64 * "EVENB" implies 1=event-disable, 0=event-enable. 65 */ 66 67#define ISL12XX_SC_REG 0x00 /* RTC Seconds */ 68 69#define ISL12XX_SR_REG 0x07 /* Status */ 70#define ISL12XX_SR_ARST (1u << 7) /* Auto-reset on status read */ 71#define ISL12XX_SR_XTOSCB (1u << 5) /* Osc disable (use ext osc) */ 72#define ISL12XX_SR_WRTC (1u << 4) /* Write RTC enable */ 73#define ISL12XX_SR_EVT (1u << 3) /* Event occurred (w0c) */ 74#define ISL12XX_SR_ALM (1u << 2) /* Alarm occurred (w0c) */ 75#define ISL12XX_SR_BAT (1u << 1) /* Running on battery (w0c) */ 76#define ISL12XX_SR_RTCF (1u << 0) /* RTC fail (power loss) */ 77#define ISL12XX_SR_W0C_BITS (ISL12XX_SR_BAT | ISL12XX_SR_ALM | ISL12XX_SR_EVT) 78 79#define ISL12XX_INT_REG 0x08 /* Interrupts */ 80#define ISL12XX_INT_IM (1u << 7) /* Alarm interrupt mode */ 81#define ISL12XX_INT_ALME (1u << 6) /* Alarm enable */ 82#define ISL12XX_INT_LPMODE (1u << 5) /* Low Power mode */ 83#define ISL12XX_INT_FOBATB (1u << 4) /* Fout/IRQ disabled on bat */ 84#define ISL12XX_INT_FO_SHIFT 0 /* Frequency output select */ 85#define ISL12XX_INT_FO_MASK 0x0f /* shift and mask. */ 86 87#define ISL12XX_EV_REG 0x09 /* Event */ 88#define ISL12XX_EV_EVIENB (1u << 7) /* Disable internal pullup */ 89#define ISL12XX_EV_EVBATB (1u << 6) /* Disable ev detect on bat */ 90#define ISL12XX_EV_RTCHLT (1u << 5) /* Halt RTC on event */ 91#define ISL12XX_EV_EVEN (1u << 4) /* Event detect enable */ 92#define ISL12XX_EV_EHYS_SHIFT 2 /* Event input hysteresis */ 93#define ISL12XX_EV_EHYS_MASK 0x03 /* selection; see datasheet */ 94#define ISL12XX_EV_ESMP_SHIFT 0 /* Event input sample rate */ 95#define ISL12XX_EV_ESMP_MASK 0x03 /* selection; see datasheet */ 96 97#define ISL12XX_ATR_REG 0x0a /* Analog trim (osc adjust) */ 98 99#define ISL12XX_DTR_REG 0x0b /* Digital trim (osc adjust) */ 100 101#define ISL12XX_SCA_REG 0x0c /* Alarm seconds */ 102 103#define ISL12XX_USR1_REG 0x12 /* User byte 1 */ 104 105#define ISL12XX_USR2_REG 0x13 /* User byte 2 */ 106 107#define ISL12XX_SCT_REG 0x14 /* Timestamp (event) seconds */ 108 109#define ISL12XX_24HR_FLAG (1u << 7) /* Hours register 24-hr mode */ 110#define ISL12XX_PM_FLAG (1u << 5) /* Hours register PM flag */ 111#define ISL12xx_12HR_MASK 0x1f /* Hours mask in AM/PM mode */ 112#define ISL12xx_24HR_MASK 0x3f /* Hours mask in 24-hr mode */ 113 114/* 115 * A struct laid out in the same order as the time registers in the chip. 116 */ 117struct time_regs { 118 uint8_t sec, min, hour, day, month, year; 119}; 120 121struct isl12xx_softc { 122 device_t dev; 123 device_t busdev; 124 struct intr_config_hook 125 init_hook; 126 bool use_ampm; 127}; 128 129#ifdef FDT 130static struct ofw_compat_data compat_data[] = { 131 {"isil,isl1209", 1}, 132 {"isil,isl1218", 1}, 133 {"isil,isl1219", 1}, 134 {"isil,isl1220", 1}, 135 {"isil,isl1221", 1}, 136 {NULL, 0}, 137}; 138#endif 139 140static inline int 141isl12xx_read1(struct isl12xx_softc *sc, uint8_t reg, uint8_t *data) 142{ 143 144 return (iicdev_readfrom(sc->dev, reg, data, 1, IIC_WAIT)); 145} 146 147static inline int 148isl12xx_write1(struct isl12xx_softc *sc, uint8_t reg, uint8_t val) 149{ 150 151 return (iicdev_writeto(sc->dev, reg, &val, 1, IIC_WAIT)); 152} 153 154static void 155isl12xx_init(void *arg) 156{ 157 struct isl12xx_softc *sc = arg; 158 uint8_t sreg; 159 160 config_intrhook_disestablish(&sc->init_hook); 161 162 /* 163 * Check the clock-stopped/power-fail bit, just so we can report it to 164 * the user at boot time. 165 */ 166 isl12xx_read1(sc, ISL12XX_SR_REG, &sreg); 167 if (sreg & ISL12XX_SR_RTCF) { 168 device_printf(sc->dev, 169 "RTC clock stopped; check battery\n"); 170 } 171 172 /* 173 * Register as a system realtime clock. 174 */ 175 clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ); 176 clock_schedule(sc->dev, 1); 177} 178 179static int 180isl12xx_probe(device_t dev) 181{ 182 183#ifdef FDT 184 if (!ofw_bus_status_okay(dev)) 185 return (ENXIO); 186 187 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 188 device_set_desc(dev, "Intersil ISL12xx RTC"); 189 return (BUS_PROBE_DEFAULT); 190 } 191#endif 192 return (ENXIO); 193} 194 195static int 196isl12xx_attach(device_t dev) 197{ 198 struct isl12xx_softc *sc = device_get_softc(dev); 199 200 sc->dev = dev; 201 sc->busdev = device_get_parent(sc->dev); 202 203 /* 204 * Chip init must wait until interrupts are enabled. Often i2c access 205 * works only when the interrupts are available. 206 */ 207 sc->init_hook.ich_func = isl12xx_init; 208 sc->init_hook.ich_arg = sc; 209 if (config_intrhook_establish(&sc->init_hook) != 0) 210 return (ENOMEM); 211 212 return (0); 213} 214 215static int 216isl12xx_detach(device_t dev) 217{ 218 219 clock_unregister(dev); 220 return (0); 221} 222 223static int 224isl12xx_gettime(device_t dev, struct timespec *ts) 225{ 226 struct isl12xx_softc *sc = device_get_softc(dev); 227 struct clocktime ct; 228 struct time_regs tregs; 229 int err; 230 uint8_t hourmask, sreg; 231 232 /* If power failed, we can't provide valid time. */ 233 if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) != 0) 234 return (err); 235 if (sreg & ISL12XX_SR_RTCF) 236 return (EINVAL); 237 238 /* Read the bcd time registers. */ 239 if ((err = iicdev_readfrom(sc->dev, ISL12XX_SC_REG, &tregs, sizeof(tregs), 240 IIC_WAIT)) != 0) 241 return (EINVAL); 242 243 /* If chip is in AM/PM mode remember that for when we set time. */ 244 if (tregs.hour & ISL12XX_24HR_FLAG) { 245 hourmask = ISL12xx_24HR_MASK; 246 } else { 247 sc->use_ampm = true; 248 hourmask = ISL12xx_12HR_MASK; 249 } 250 251 ct.nsec = 0; 252 ct.sec = FROMBCD(tregs.sec); 253 ct.min = FROMBCD(tregs.min); 254 ct.hour = FROMBCD(tregs.hour & hourmask); 255 ct.day = FROMBCD(tregs.day); 256 ct.mon = FROMBCD(tregs.month); 257 ct.year = FROMBCD(tregs.year); 258 259 if (sc->use_ampm) { 260 if (ct.hour == 12) 261 ct.hour = 0; 262 if (tregs.hour & ISL12XX_PM_FLAG) 263 ct.hour += 12; 264 } 265 266 return (clock_ct_to_ts(&ct, ts)); 267} 268 269static int 270isl12xx_settime(device_t dev, struct timespec *ts) 271{ 272 struct isl12xx_softc *sc = device_get_softc(dev); 273 struct clocktime ct; 274 struct time_regs tregs; 275 int err; 276 uint8_t ampmflags, sreg; 277 278 /* 279 * We request a timespec with no resolution-adjustment. That also 280 * disables utc adjustment, so apply that ourselves. 281 */ 282 ts->tv_sec -= utc_offset(); 283 ts->tv_nsec = 0; 284 clock_ts_to_ct(ts, &ct); 285 286 /* If the chip is in AM/PM mode, adjust hour and set flags as needed. */ 287 if (!sc->use_ampm) { 288 ampmflags = ISL12XX_24HR_FLAG; 289 } else { 290 ampmflags = 0; 291 if (ct.hour >= 12) { 292 ct.hour -= 12; 293 ampmflags |= ISL12XX_PM_FLAG; 294 } 295 if (ct.hour == 0) 296 ct.hour = 12; 297 } 298 299 tregs.sec = TOBCD(ct.sec); 300 tregs.min = TOBCD(ct.min); 301 tregs.hour = TOBCD(ct.hour) | ampmflags; 302 tregs.day = TOBCD(ct.day); 303 tregs.month = TOBCD(ct.mon); 304 tregs.year = TOBCD(ct.year % 100); 305 306 /* 307 * To set the time we have to set the WRTC enable bit in the control 308 * register, then write the time regs, then clear the WRTC bit. While 309 * doing so we have to be careful to not write a 0 to any sreg bit which 310 * is "write 0 to clear". One of those bits could get set between 311 * reading and writing the register. All those bits ignore attempts to 312 * write a 1, so just always OR-in all the W0C bits to be sure we never 313 * accidentally clear one. We hold ownership of the i2c bus for the 314 * whole read-modify-write sequence. 315 */ 316 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0) 317 return (err); 318 if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) { 319 sreg |= ISL12XX_SR_WRTC | ISL12XX_SR_W0C_BITS; 320 if ((err = isl12xx_write1(sc, ISL12XX_SR_REG, sreg)) == 0) { 321 err = iicdev_writeto(sc->dev, ISL12XX_SC_REG, &tregs, 322 sizeof(tregs), IIC_WAIT); 323 sreg &= ~ISL12XX_SR_WRTC; 324 isl12xx_write1(sc, ISL12XX_SR_REG, sreg); 325 } 326 } 327 iicbus_release_bus(sc->busdev, sc->dev); 328 329 return (err); 330} 331 332static device_method_t isl12xx_methods[] = { 333 /* device_if methods */ 334 DEVMETHOD(device_probe, isl12xx_probe), 335 DEVMETHOD(device_attach, isl12xx_attach), 336 DEVMETHOD(device_detach, isl12xx_detach), 337 338 /* clock_if methods */ 339 DEVMETHOD(clock_gettime, isl12xx_gettime), 340 DEVMETHOD(clock_settime, isl12xx_settime), 341 342 DEVMETHOD_END, 343}; 344 345static driver_t isl12xx_driver = { 346 "isl12xx", 347 isl12xx_methods, 348 sizeof(struct isl12xx_softc), 349}; 350static devclass_t isl12xx_devclass; 351 352DRIVER_MODULE(isl12xx, iicbus, isl12xx_driver, isl12xx_devclass, NULL, NULL); 353MODULE_VERSION(isl12xx, 1); 354MODULE_DEPEND(isl12xx, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 355