138774Snsouch/*- 293023Snsouch * Copyright (c) 1998, 2001 Nicolas Souchu 338774Snsouch * All rights reserved. 438774Snsouch * 538774Snsouch * Redistribution and use in source and binary forms, with or without 638774Snsouch * modification, are permitted provided that the following conditions 738774Snsouch * are met: 838774Snsouch * 1. Redistributions of source code must retain the above copyright 938774Snsouch * notice, this list of conditions and the following disclaimer. 1038774Snsouch * 2. Redistributions in binary form must reproduce the above copyright 1138774Snsouch * notice, this list of conditions and the following disclaimer in the 1238774Snsouch * documentation and/or other materials provided with the distribution. 1338774Snsouch * 1438774Snsouch * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1538774Snsouch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1638774Snsouch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1738774Snsouch * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1838774Snsouch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1938774Snsouch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2038774Snsouch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2138774Snsouch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2238774Snsouch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2338774Snsouch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2438774Snsouch * SUCH DAMAGE. 2538774Snsouch * 2650477Speter * $FreeBSD: stable/11/sys/dev/iicbus/iiconf.h 331722 2018-03-29 02:50:57Z eadler $ 2738774Snsouch */ 2838774Snsouch#ifndef __IICONF_H 2938774Snsouch#define __IICONF_H 3038774Snsouch 3138774Snsouch#include <sys/queue.h> 32268564Srpaulo#include <dev/iicbus/iic.h> 3338774Snsouch 34160372Simp 3543301Sdillon#define IICPRI (PZERO+8) /* XXX sleep/wakeup queue priority */ 3638774Snsouch 3738774Snsouch#define LSB 0x1 3838774Snsouch 3938774Snsouch/* 40331497Sian * Options affecting iicbus_request_bus() 4138774Snsouch */ 4238774Snsouch#define IIC_DONTWAIT 0 4338774Snsouch#define IIC_NOINTR 0 4438774Snsouch#define IIC_WAIT 0x1 4538774Snsouch#define IIC_INTR 0x2 46289104Sian#define IIC_INTRWAIT (IIC_INTR | IIC_WAIT) 47331497Sian#define IIC_RECURSIVE 0x4 4838774Snsouch 4938774Snsouch/* 5038774Snsouch * i2c modes 5138774Snsouch */ 5238774Snsouch#define IIC_MASTER 0x1 5338774Snsouch#define IIC_SLAVE 0x2 5438774Snsouch#define IIC_POLLED 0x4 5538774Snsouch 5638774Snsouch/* 5738774Snsouch * i2c speed 5838774Snsouch */ 5938774Snsouch#define IIC_UNKNOWN 0x0 6038774Snsouch#define IIC_SLOW 0x1 6138774Snsouch#define IIC_FAST 0x2 6238774Snsouch#define IIC_FASTEST 0x3 6338774Snsouch 6440782Snsouch#define IIC_LAST_READ 0x1 6540782Snsouch 6638774Snsouch/* 6740782Snsouch * callback index 6840782Snsouch */ 6940782Snsouch#define IIC_REQUEST_BUS 0x1 7040782Snsouch#define IIC_RELEASE_BUS 0x2 7140782Snsouch 7240782Snsouch/* 7338774Snsouch * interrupt events 7438774Snsouch */ 7538774Snsouch#define INTR_GENERAL 0x1 /* general call received */ 7638774Snsouch#define INTR_START 0x2 /* the I2C interface is addressed */ 7738774Snsouch#define INTR_STOP 0x3 /* stop condition received */ 7838774Snsouch#define INTR_RECEIVE 0x4 /* character received */ 7938774Snsouch#define INTR_TRANSMIT 0x5 /* character to transmit */ 8038774Snsouch#define INTR_ERROR 0x6 /* error */ 8138774Snsouch#define INTR_NOACK 0x7 /* no ack from master receiver */ 8238774Snsouch 8338774Snsouch/* 8438774Snsouch * adapter layer errors 8538774Snsouch */ 86298955Spfg#define IIC_NOERR 0x0 /* no error occurred */ 87289093Sian#define IIC_EBUSERR 0x1 /* bus error (hardware not in expected state) */ 8838774Snsouch#define IIC_ENOACK 0x2 /* ack not received until timeout */ 8938774Snsouch#define IIC_ETIMEOUT 0x3 /* timeout */ 90289093Sian#define IIC_EBUSBSY 0x4 /* bus busy (reserved by another client) */ 9138774Snsouch#define IIC_ESTATUS 0x5 /* status error */ 9238774Snsouch#define IIC_EUNDERFLOW 0x6 /* slave ready for more data */ 9338774Snsouch#define IIC_EOVERFLOW 0x7 /* too much data */ 9440782Snsouch#define IIC_ENOTSUPP 0x8 /* request not supported */ 9540782Snsouch#define IIC_ENOADDR 0x9 /* no address assigned to the interface */ 96289095Sian#define IIC_ERESOURCE 0xa /* resources (memory, whatever) unavailable */ 9738774Snsouch 98289097Sian/* 99289097Sian * Note that all iicbus functions return IIC_Exxxxx status values, 100289097Sian * except iic2errno() (obviously) and iicbus_started() (returns bool). 101289097Sian */ 102289095Sianextern int iic2errno(int); 10338774Snsouchextern int iicbus_request_bus(device_t, device_t, int); 10438774Snsouchextern int iicbus_release_bus(device_t, device_t); 10538774Snsouchextern device_t iicbus_alloc_bus(device_t); 10638774Snsouch 10738774Snsouchextern void iicbus_intr(device_t, int, char *); 10838774Snsouch 10940782Snsouchextern int iicbus_null_repeated_start(device_t, u_char); 11040782Snsouchextern int iicbus_null_callback(device_t, int, caddr_t); 11140782Snsouch 11240782Snsouch#define iicbus_reset(bus,speed,addr,oldaddr) \ 11340782Snsouch (IICBUS_RESET(device_get_parent(bus), speed, addr, oldaddr)) 11438774Snsouch 11542442Snsouch/* basic I2C operations */ 11642442Snsouchextern int iicbus_started(device_t); 11742442Snsouchextern int iicbus_start(device_t, u_char, int); 11842442Snsouchextern int iicbus_stop(device_t); 11943346Srogerextern int iicbus_repeated_start(device_t, u_char, int); 120164901Simpextern int iicbus_write(device_t, const char *, int, int *, int); 12142442Snsouchextern int iicbus_read(device_t, char *, int, int *, int, int); 12242442Snsouch 12343346Sroger/* single byte read/write functions, start/stop not managed */ 12443346Srogerextern int iicbus_write_byte(device_t, char, int); 12543346Srogerextern int iicbus_read_byte(device_t, char *, int); 12643346Sroger 12742442Snsouch/* Read/write operations with start/stop conditions managed */ 12838774Snsouchextern int iicbus_block_write(device_t, u_char, char *, int, int *); 12938774Snsouchextern int iicbus_block_read(device_t, u_char, char *, int, int *); 13038774Snsouch 131160372Simp/* vectors of iic operations to pass to bridge */ 132160372Simpint iicbus_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); 133289726Sianint iicbus_transfer_excl(device_t bus, struct iic_msg *msgs, uint32_t nmsgs, 134289726Sian int how); 135160372Simpint iicbus_transfer_gen(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); 136160372Simp 137323446Sian/* 138323446Sian * Simple register read/write routines, but the "register" can be any size. 139323446Sian * The transfers are done with iicbus_transfer_excl(). Reads use a repeat-start 140323446Sian * between sending the address and reading; writes use a single start/stop. 141323446Sian */ 142323446Sianint iicdev_readfrom(device_t _slavedev, uint8_t _regaddr, void *_buffer, 143323446Sian uint16_t _buflen, int _waithow); 144323446Sianint iicdev_writeto(device_t _slavedev, uint8_t _regaddr, void *_buffer, 145323446Sian uint16_t _buflen, int _waithow); 146323446Sian 14793023Snsouch#define IICBUS_MODVER 1 14893023Snsouch#define IICBUS_MINVER 1 14993023Snsouch#define IICBUS_MAXVER 1 15093023Snsouch#define IICBUS_PREFVER IICBUS_MODVER 15193023Snsouch 152116559Sjmgextern driver_t iicbb_driver; 153116559Sjmgextern devclass_t iicbb_devclass; 154116559Sjmg 15593023Snsouch#define IICBB_MODVER 1 15693023Snsouch#define IICBB_MINVER 1 15793023Snsouch#define IICBB_MAXVER 1 15893023Snsouch#define IICBB_PREFVER IICBB_MODVER 15993023Snsouch 16038774Snsouch#endif 161