ichsmb_pci.c revision 66703
166703Sarchie 266703Sarchie/* 366703Sarchie * ichsmb_pci.c 466703Sarchie * 566703Sarchie * Copyright (c) 2000 Whistle Communications, Inc. 666703Sarchie * All rights reserved. 766703Sarchie * 866703Sarchie * Subject to the following obligations and disclaimer of warranty, use and 966703Sarchie * redistribution of this software, in source or object code forms, with or 1066703Sarchie * without modifications are expressly permitted by Whistle Communications; 1166703Sarchie * provided, however, that: 1266703Sarchie * 1. Any and all reproductions of the source or object code must include the 1366703Sarchie * copyright notice above and the following disclaimer of warranties; and 1466703Sarchie * 2. No rights are granted, in any manner or form, to use Whistle 1566703Sarchie * Communications, Inc. trademarks, including the mark "WHISTLE 1666703Sarchie * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 1766703Sarchie * such appears in the above copyright notice or in the software. 1866703Sarchie * 1966703Sarchie * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 2066703Sarchie * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 2166703Sarchie * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 2266703Sarchie * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 2366703Sarchie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 2466703Sarchie * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 2566703Sarchie * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 2666703Sarchie * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 2766703Sarchie * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 2866703Sarchie * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 2966703Sarchie * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 3066703Sarchie * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 3166703Sarchie * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 3266703Sarchie * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3366703Sarchie * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3466703Sarchie * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 3566703Sarchie * OF SUCH DAMAGE. 3666703Sarchie * 3766703Sarchie * Author: Archie Cobbs <archie@freebsd.org> 3866703Sarchie * 3966703Sarchie * $FreeBSD: head/sys/dev/ichsmb/ichsmb_pci.c 66703 2000-10-06 00:09:46Z archie $ 4066703Sarchie */ 4166703Sarchie 4266703Sarchie/* 4366703Sarchie * Support for the SMBus controller logical device which is part of the 4466703Sarchie * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips. 4566703Sarchie */ 4666703Sarchie 4766703Sarchie#include <sys/param.h> 4866703Sarchie#include <sys/systm.h> 4966703Sarchie#include <sys/kernel.h> 5066703Sarchie#include <sys/errno.h> 5166703Sarchie#include <sys/syslog.h> 5266703Sarchie#include <sys/bus.h> 5366703Sarchie 5466703Sarchie#include <machine/bus.h> 5566703Sarchie#include <sys/rman.h> 5666703Sarchie#include <machine/resource.h> 5766703Sarchie 5866703Sarchie#include <pci/pcivar.h> 5966703Sarchie#include <pci/pcireg.h> 6066703Sarchie 6166703Sarchie#include <dev/smbus/smbconf.h> 6266703Sarchie 6366703Sarchie#include <dev/ichsmb/ichsmb_var.h> 6466703Sarchie#include <dev/ichsmb/ichsmb_reg.h> 6566703Sarchie 6666703Sarchie/* PCI unique identifiers */ 6766703Sarchie#define ID_81801AA 0x24138086 6866703Sarchie#define ID_81801AB 0x24238086 6966703Sarchie#define ID_82801BA 0x24438086 7066703Sarchie 7166703Sarchie#define PCIS_SERIALBUS_SMBUS_PROGIF 0x00 7266703Sarchie 7366703Sarchie/* Internal functions */ 7466703Sarchiestatic int ichsmb_pci_probe(device_t dev); 7566703Sarchiestatic int ichsmb_pci_attach(device_t dev); 7666703Sarchie 7766703Sarchie/* Device methods */ 7866703Sarchiestatic device_method_t ichsmb_pci_methods[] = { 7966703Sarchie /* Device interface */ 8066703Sarchie DEVMETHOD(device_probe, ichsmb_pci_probe), 8166703Sarchie DEVMETHOD(device_attach, ichsmb_pci_attach), 8266703Sarchie 8366703Sarchie /* Bus methods */ 8466703Sarchie DEVMETHOD(bus_print_child, bus_generic_print_child), 8566703Sarchie 8666703Sarchie /* SMBus methods */ 8766703Sarchie DEVMETHOD(smbus_callback, ichsmb_callback), 8866703Sarchie DEVMETHOD(smbus_quick, ichsmb_quick), 8966703Sarchie DEVMETHOD(smbus_sendb, ichsmb_sendb), 9066703Sarchie DEVMETHOD(smbus_recvb, ichsmb_recvb), 9166703Sarchie DEVMETHOD(smbus_writeb, ichsmb_writeb), 9266703Sarchie DEVMETHOD(smbus_writew, ichsmb_writew), 9366703Sarchie DEVMETHOD(smbus_readb, ichsmb_readb), 9466703Sarchie DEVMETHOD(smbus_readw, ichsmb_readw), 9566703Sarchie DEVMETHOD(smbus_pcall, ichsmb_pcall), 9666703Sarchie DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 9766703Sarchie DEVMETHOD(smbus_bread, ichsmb_bread), 9866703Sarchie { 0, 0 } 9966703Sarchie}; 10066703Sarchie 10166703Sarchiestatic driver_t ichsmb_pci_driver = { 10266703Sarchie "ichsmb", 10366703Sarchie ichsmb_pci_methods, 10466703Sarchie sizeof(struct ichsmb_softc) 10566703Sarchie}; 10666703Sarchie 10766703Sarchiestatic devclass_t ichsmb_pci_devclass; 10866703Sarchie 10966703SarchieDRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0); 11066703Sarchie 11166703Sarchiestatic int 11266703Sarchieichsmb_pci_probe(device_t dev) 11366703Sarchie{ 11466703Sarchie /* Check PCI identifier */ 11566703Sarchie switch (pci_get_devid(dev)) { 11666703Sarchie case ID_81801AA: 11766703Sarchie device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller"); 11866703Sarchie break; 11966703Sarchie case ID_81801AB: 12066703Sarchie device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller"); 12166703Sarchie break; 12266703Sarchie case ID_82801BA: 12366703Sarchie device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller"); 12466703Sarchie break; 12566703Sarchie default: 12666703Sarchie if (pci_get_class(dev) == PCIC_SERIALBUS 12766703Sarchie && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS 12866703Sarchie && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) { 12966703Sarchie device_set_desc(dev, "SMBus controller"); 13066703Sarchie return (-2); /* XXX */ 13166703Sarchie } 13266703Sarchie return (ENXIO); 13366703Sarchie } 13466703Sarchie 13566703Sarchie /* Done */ 13666703Sarchie return (ichsmb_probe(dev)); 13766703Sarchie} 13866703Sarchie 13966703Sarchiestatic int 14066703Sarchieichsmb_pci_attach(device_t dev) 14166703Sarchie{ 14266703Sarchie const sc_p sc = device_get_softc(dev); 14366703Sarchie u_int32_t cmd; 14466703Sarchie int error; 14566703Sarchie 14666703Sarchie /* Initialize private state */ 14766703Sarchie bzero(sc, sizeof(*sc)); 14866703Sarchie sc->ich_cmd = -1; 14966703Sarchie sc->dev = dev; 15066703Sarchie 15166703Sarchie /* Allocate an I/O range */ 15266703Sarchie sc->io_rid = ICH_SMB_BASE; 15366703Sarchie sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 15466703Sarchie &sc->io_rid, 0, ~0, 16, RF_ACTIVE); 15566703Sarchie if (sc->io_res == NULL) { 15666703Sarchie log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev)); 15766703Sarchie error = ENXIO; 15866703Sarchie goto fail; 15966703Sarchie } 16066703Sarchie sc->io_bst = rman_get_bustag(sc->io_res); 16166703Sarchie sc->io_bsh = rman_get_bushandle(sc->io_res); 16266703Sarchie 16366703Sarchie /* Allocate interrupt */ 16466703Sarchie sc->irq_rid = 0; 16566703Sarchie sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, 16666703Sarchie &sc->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 16766703Sarchie if (sc->irq_res == NULL) { 16866703Sarchie log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev)); 16966703Sarchie error = ENXIO; 17066703Sarchie goto fail; 17166703Sarchie } 17266703Sarchie 17366703Sarchie /* Set up interrupt handler */ 17466703Sarchie error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 17566703Sarchie ichsmb_device_intr, sc, &sc->irq_handle); 17666703Sarchie if (error != 0) { 17766703Sarchie log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev)); 17866703Sarchie goto fail; 17966703Sarchie } 18066703Sarchie 18166703Sarchie /* Enable I/O mapping */ 18266703Sarchie cmd = pci_read_config(dev, PCIR_COMMAND, 4); 18366703Sarchie cmd |= PCIM_CMD_PORTEN; 18466703Sarchie pci_write_config(dev, PCIR_COMMAND, cmd, 4); 18566703Sarchie cmd = pci_read_config(dev, PCIR_COMMAND, 4); 18666703Sarchie if ((cmd & PCIM_CMD_PORTEN) == 0) { 18766703Sarchie log(LOG_ERR, "%s: can't enable memory map\n", 18866703Sarchie device_get_nameunit(dev)); 18966703Sarchie error = ENXIO; 19066703Sarchie goto fail; 19166703Sarchie } 19266703Sarchie 19366703Sarchie /* Enable device */ 19466703Sarchie pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 19566703Sarchie 19666703Sarchie /* Done */ 19766703Sarchie return (ichsmb_attach(dev)); 19866703Sarchie 19966703Sarchiefail: 20066703Sarchie /* Attach failed, release resources */ 20166703Sarchie ichsmb_release_resources(sc); 20266703Sarchie return (error); 20366703Sarchie} 20466703Sarchie 205