ichsmb_pci.c revision 119418
1119418Sobrien/*- 266703Sarchie * ichsmb_pci.c 366703Sarchie * 4119418Sobrien * Author: Archie Cobbs <archie@freebsd.org> 566703Sarchie * Copyright (c) 2000 Whistle Communications, Inc. 666703Sarchie * All rights reserved. 7119418Sobrien * Author: Archie Cobbs <archie@freebsd.org> 866703Sarchie * 966703Sarchie * Subject to the following obligations and disclaimer of warranty, use and 1066703Sarchie * redistribution of this software, in source or object code forms, with or 1166703Sarchie * without modifications are expressly permitted by Whistle Communications; 1266703Sarchie * provided, however, that: 1366703Sarchie * 1. Any and all reproductions of the source or object code must include the 1466703Sarchie * copyright notice above and the following disclaimer of warranties; and 1566703Sarchie * 2. No rights are granted, in any manner or form, to use Whistle 1666703Sarchie * Communications, Inc. trademarks, including the mark "WHISTLE 1766703Sarchie * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 1866703Sarchie * such appears in the above copyright notice or in the software. 1966703Sarchie * 2066703Sarchie * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 2166703Sarchie * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 2266703Sarchie * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 2366703Sarchie * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 2466703Sarchie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 2566703Sarchie * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 2666703Sarchie * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 2766703Sarchie * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 2866703Sarchie * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 2966703Sarchie * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 3066703Sarchie * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 3166703Sarchie * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 3266703Sarchie * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 3366703Sarchie * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3466703Sarchie * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3566703Sarchie * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 3666703Sarchie * OF SUCH DAMAGE. 3766703Sarchie */ 3866703Sarchie 39119418Sobrien#include <sys/cdefs.h> 40119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/ichsmb/ichsmb_pci.c 119418 2003-08-24 17:55:58Z obrien $"); 41119418Sobrien 4266703Sarchie/* 4366703Sarchie * Support for the SMBus controller logical device which is part of the 44101742Smp * Intel 81801AA/AB/BA/CA/DC (ICH/ICH[0234]) I/O controller hub chips. 4566703Sarchie */ 4666703Sarchie 4766703Sarchie#include <sys/param.h> 4866703Sarchie#include <sys/systm.h> 4966703Sarchie#include <sys/kernel.h> 5066703Sarchie#include <sys/errno.h> 5174914Sjhb#include <sys/lock.h> 5269734Sarchie#include <sys/mutex.h> 5366703Sarchie#include <sys/syslog.h> 5466703Sarchie#include <sys/bus.h> 5566703Sarchie 5666703Sarchie#include <machine/bus.h> 5766703Sarchie#include <sys/rman.h> 5866703Sarchie#include <machine/resource.h> 5966703Sarchie 60119280Simp#include <dev/pci/pcivar.h> 61119280Simp#include <dev/pci/pcireg.h> 6266703Sarchie 6366703Sarchie#include <dev/smbus/smbconf.h> 6466703Sarchie 6566703Sarchie#include <dev/ichsmb/ichsmb_var.h> 6666703Sarchie#include <dev/ichsmb/ichsmb_reg.h> 6766703Sarchie 6866703Sarchie/* PCI unique identifiers */ 69105394Snyan#define ID_82801AA 0x24138086 70105394Snyan#define ID_82801AB 0x24238086 7166703Sarchie#define ID_82801BA 0x24438086 7296200Sjhb#define ID_82801CA 0x24838086 73101742Smp#define ID_82801DC 0x24C38086 7466703Sarchie 7566703Sarchie#define PCIS_SERIALBUS_SMBUS_PROGIF 0x00 7666703Sarchie 7766703Sarchie/* Internal functions */ 7866703Sarchiestatic int ichsmb_pci_probe(device_t dev); 7966703Sarchiestatic int ichsmb_pci_attach(device_t dev); 8066703Sarchie 8166703Sarchie/* Device methods */ 8266703Sarchiestatic device_method_t ichsmb_pci_methods[] = { 8366703Sarchie /* Device interface */ 8466703Sarchie DEVMETHOD(device_probe, ichsmb_pci_probe), 8566703Sarchie DEVMETHOD(device_attach, ichsmb_pci_attach), 8666703Sarchie 8766703Sarchie /* Bus methods */ 8866703Sarchie DEVMETHOD(bus_print_child, bus_generic_print_child), 8966703Sarchie 9066703Sarchie /* SMBus methods */ 9166703Sarchie DEVMETHOD(smbus_callback, ichsmb_callback), 9266703Sarchie DEVMETHOD(smbus_quick, ichsmb_quick), 9366703Sarchie DEVMETHOD(smbus_sendb, ichsmb_sendb), 9466703Sarchie DEVMETHOD(smbus_recvb, ichsmb_recvb), 9566703Sarchie DEVMETHOD(smbus_writeb, ichsmb_writeb), 9666703Sarchie DEVMETHOD(smbus_writew, ichsmb_writew), 9766703Sarchie DEVMETHOD(smbus_readb, ichsmb_readb), 9866703Sarchie DEVMETHOD(smbus_readw, ichsmb_readw), 9966703Sarchie DEVMETHOD(smbus_pcall, ichsmb_pcall), 10066703Sarchie DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 10166703Sarchie DEVMETHOD(smbus_bread, ichsmb_bread), 10266703Sarchie { 0, 0 } 10366703Sarchie}; 10466703Sarchie 10566703Sarchiestatic driver_t ichsmb_pci_driver = { 10666703Sarchie "ichsmb", 10766703Sarchie ichsmb_pci_methods, 10866703Sarchie sizeof(struct ichsmb_softc) 10966703Sarchie}; 11066703Sarchie 11166703Sarchiestatic devclass_t ichsmb_pci_devclass; 11266703Sarchie 11366703SarchieDRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0); 11466703Sarchie 11566703Sarchiestatic int 11666703Sarchieichsmb_pci_probe(device_t dev) 11766703Sarchie{ 11866703Sarchie /* Check PCI identifier */ 11966703Sarchie switch (pci_get_devid(dev)) { 120105394Snyan case ID_82801AA: 12166703Sarchie device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller"); 12266703Sarchie break; 123105394Snyan case ID_82801AB: 12466703Sarchie device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller"); 12566703Sarchie break; 12666703Sarchie case ID_82801BA: 12766703Sarchie device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller"); 12866703Sarchie break; 12996200Sjhb case ID_82801CA: 13096200Sjhb device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller"); 13196200Sjhb break; 132101742Smp case ID_82801DC: 133101742Smp device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller"); 134101742Smp break; 13566703Sarchie default: 13666703Sarchie if (pci_get_class(dev) == PCIC_SERIALBUS 13766703Sarchie && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS 13866703Sarchie && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) { 13966703Sarchie device_set_desc(dev, "SMBus controller"); 14066703Sarchie return (-2); /* XXX */ 14166703Sarchie } 14266703Sarchie return (ENXIO); 14366703Sarchie } 14466703Sarchie 14566703Sarchie /* Done */ 14666703Sarchie return (ichsmb_probe(dev)); 14766703Sarchie} 14866703Sarchie 14966703Sarchiestatic int 15066703Sarchieichsmb_pci_attach(device_t dev) 15166703Sarchie{ 15266703Sarchie const sc_p sc = device_get_softc(dev); 15366703Sarchie u_int32_t cmd; 15466703Sarchie int error; 15566703Sarchie 15666703Sarchie /* Initialize private state */ 15766703Sarchie bzero(sc, sizeof(*sc)); 15866703Sarchie sc->ich_cmd = -1; 15966703Sarchie sc->dev = dev; 16066703Sarchie 16166703Sarchie /* Allocate an I/O range */ 16266703Sarchie sc->io_rid = ICH_SMB_BASE; 16366703Sarchie sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 16466703Sarchie &sc->io_rid, 0, ~0, 16, RF_ACTIVE); 16566703Sarchie if (sc->io_res == NULL) { 16666703Sarchie log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev)); 16766703Sarchie error = ENXIO; 16866703Sarchie goto fail; 16966703Sarchie } 17066703Sarchie sc->io_bst = rman_get_bustag(sc->io_res); 17166703Sarchie sc->io_bsh = rman_get_bushandle(sc->io_res); 17266703Sarchie 17366703Sarchie /* Allocate interrupt */ 17466703Sarchie sc->irq_rid = 0; 17566703Sarchie sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, 17666703Sarchie &sc->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 17766703Sarchie if (sc->irq_res == NULL) { 17866703Sarchie log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev)); 17966703Sarchie error = ENXIO; 18066703Sarchie goto fail; 18166703Sarchie } 18266703Sarchie 18366703Sarchie /* Set up interrupt handler */ 18466703Sarchie error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 18566703Sarchie ichsmb_device_intr, sc, &sc->irq_handle); 18666703Sarchie if (error != 0) { 18766703Sarchie log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev)); 18866703Sarchie goto fail; 18966703Sarchie } 19066703Sarchie 19166703Sarchie /* Enable I/O mapping */ 19266703Sarchie cmd = pci_read_config(dev, PCIR_COMMAND, 4); 19366703Sarchie cmd |= PCIM_CMD_PORTEN; 19466703Sarchie pci_write_config(dev, PCIR_COMMAND, cmd, 4); 19566703Sarchie cmd = pci_read_config(dev, PCIR_COMMAND, 4); 19666703Sarchie if ((cmd & PCIM_CMD_PORTEN) == 0) { 19766703Sarchie log(LOG_ERR, "%s: can't enable memory map\n", 19866703Sarchie device_get_nameunit(dev)); 19966703Sarchie error = ENXIO; 20066703Sarchie goto fail; 20166703Sarchie } 20266703Sarchie 20366703Sarchie /* Enable device */ 20466703Sarchie pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 20566703Sarchie 20666703Sarchie /* Done */ 20766703Sarchie return (ichsmb_attach(dev)); 20866703Sarchie 20966703Sarchiefail: 21066703Sarchie /* Attach failed, release resources */ 21166703Sarchie ichsmb_release_resources(sc); 21266703Sarchie return (error); 21366703Sarchie} 21466703Sarchie 215