1139749Simp/*- 28471Sache * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 38471Sache * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 48471Sache * All rights reserved. 58471Sache * 68471Sache * Redistribution and use in source and binary forms, with or without 78471Sache * modification, are permitted provided that the following conditions 88471Sache * are met: 98471Sache * 1. Redistributions of source code must retain the above copyright 108471Sache * notice, this list of conditions and the following disclaimer. 118471Sache * 2. Redistributions in binary form must reproduce the above copyright 128471Sache * notice, this list of conditions and the following disclaimer in the 138471Sache * documentation and/or other materials provided with the distribution. 148471Sache * 158471Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 168471Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 178471Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 188471Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 198471Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 208471Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 218471Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 228471Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 238471Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 248471Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 258471Sache * SUCH DAMAGE. 2659874Speter * 2759874Speter * $FreeBSD$ 288471Sache */ 298471Sache 308471Sache/* 318471Sache * Cirrus Logic CD180 registers 328471Sache */ 338471Sache 348471Sache/* Global registers */ 358471Sache#define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */ 368471Sache#define CD180_GICR 0x41 /* Global Interrupting Channel Register */ 378471Sache#define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */ 388471Sache#define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */ 398471Sache#define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */ 408471Sache#define CD180_CAR 0x64 /* Channel Access Register */ 418471Sache#define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */ 428471Sache#define CD180_PPRH 0x70 /* Prescaler Period Register MSB */ 438471Sache#define CD180_PPRL 0x71 /* Prescaler Period Register LSB */ 448471Sache#define CD180_RDR 0x78 /* Receiver Data Register */ 458471Sache#define CD180_RCSR 0x7A /* Receiver Character Status Register */ 468471Sache#define CD180_TDR 0x7B /* Transmit Data Register */ 478471Sache#define CD180_EOIR 0x7F /* End of Interrupt Register */ 488471Sache 498471Sache/* Channel Registers */ 508471Sache#define CD180_CCR 0x01 /* Channel Command Register */ 518471Sache#define CD180_IER 0x02 /* Interrupt Enable Register */ 528471Sache#define CD180_COR1 0x03 /* Channel Option Register 1 */ 538471Sache#define CD180_COR2 0x04 /* Channel Option Register 1 */ 548471Sache#define CD180_COR3 0x05 /* Channel Option Register 1 */ 558471Sache#define CD180_CCSR 0x06 /* Channel Control STatus Register */ 568471Sache#define CD180_RDCR 0x07 /* Receive Data Count Register */ 578471Sache#define CD180_SCHR1 0x09 /* Special Character Register 1 */ 588471Sache#define CD180_SCHR2 0x0A /* Special Character Register 2 */ 598471Sache#define CD180_SCHR3 0x0B /* Special Character Register 3 */ 608471Sache#define CD180_SCHR4 0x0C /* Special Character Register 4 */ 618471Sache#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */ 628471Sache#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */ 638471Sache#define CD180_MCR 0x12 /* Modem Change Register */ 648471Sache#define CD180_RTPR 0x18 /* Receive Timeout Period Register */ 658471Sache#define CD180_MSVR 0x28 /* Modem Signal Value Register */ 668471Sache#define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register MSB */ 678471Sache#define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register LSB */ 688471Sache#define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register MSB */ 698471Sache#define CD180_TBPRL 0x3A /* Transmit Baud Rate Period Register LSB */ 708471Sache 718471Sache/** Register descritpions **/ 728471Sache 738471Sache/* Global Interrupt Vector Register */ 748471Sache#define GIVR_IT_MSCI 0x01 /* Modem Signal Change Interrupt */ 758471Sache#define GIVR_IT_TDI 0x02 /* Transmit Data Interrupt */ 768471Sache#define GIVR_IT_RGDI 0x03 /* Receive Good Data Interrupt */ 778471Sache#define GIVR_IT_REI 0x07 /* Receive Exception Interrupt */ 788471Sache 798471Sache/* Global Interrupt Channel Register */ 808471Sache#define GICR_CHAN 0x1C /* Channel Number Mask */ 818471Sache#define GICR_LSH 2 /* Channel Number Shift */ 828471Sache 838471Sache/* Channel Address Register */ 848471Sache#define CAR_CHAN 0x07 /* Channel Number Mask */ 85298955Spfg#define CAR_A7 0x08 /* Address bit 7 (unused) */ 868471Sache 878471Sache/* Receive Character Status Register */ 888471Sache#define RCSR_OE 0x01 /* Overrun Error */ 898471Sache#define RCSR_FE 0x02 /* Frame Error */ 908471Sache#define RCSR_PE 0x04 /* Parity Error */ 919232Sache#define RCSR_Break 0x08 /* Break detected */ 929232Sache#define RCSR_Timeout 0x80 /* Rx Timeout */ 939232Sache#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */ 948471Sache#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */ 958471Sache#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */ 968471Sache#define RCSR_SC3 0x30 /* Special Char 3 */ 978471Sache#define RCSR_SC4 0x40 /* Special Char 4 */ 988471Sache 998471Sache/* Channel Command Register */ 1009232Sache#define CCR_ResetChan 0x80 /* Reset Channel */ 1018471Sache#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */ 1028471Sache#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */ 1038471Sache#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */ 1048471Sache#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */ 1059232Sache#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */ 1069232Sache#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */ 1079232Sache#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */ 1089232Sache#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */ 1099232Sache#define CCR_RCVRDIS 0x11 /* Receiver Disable */ 1109232Sache#define CCR_RCVREN 0x12 /* Receiver Enable */ 1119232Sache#define CCR_XMTRDIS 0x14 /* Transmitter Disable */ 1129232Sache#define CCR_XMTREN 0x18 /* Transmitter Enable */ 1138471Sache 1148471Sache/* Interrupt Enable Register */ 1158471Sache#define IER_DSR 0x80 /* Enable interrupt on DSR change */ 1168471Sache#define IER_CD 0x40 /* Enable interrupt on CD change */ 1178471Sache#define IER_CTS 0x20 /* Enable interrupt on CTS change */ 1189232Sache#define IER_RxData 0x10 /* Enable interrupt on Receive Data */ 1199232Sache#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */ 1209232Sache#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */ 1219232Sache#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/ 1228471Sache#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */ 1238471Sache 1248471Sache/* Channel Option Register 1 */ 1258471Sache#define COR1_ODDP 0x80 /* Odd Parity */ 1269232Sache#define COR1_ParMMASK 0x60 /* Parity Mode mask */ 1278471Sache#define COR1_NOPAR 0x02 /* No Parity */ 1288471Sache#define COR1_FORCEPAR 0x20 /* Force Parity */ 1298471Sache#define COR1_NORMPAR 0x40 /* Normal Parity */ 1309232Sache#define COR1_Ignore 0x10 /* Ignore Parity on RX */ 1319232Sache#define COR1_StopMASK 0x0C /* Stop Bits mode mask */ 1328471Sache#define COR1_1SB 0x00 /* 1 Stop Bit */ 1338471Sache#define COR1_15SB 0x04 /* 1.5 Stop Bits */ 1348471Sache#define COR1_2SB 0x08 /* 2 Stop Bits */ 1358471Sache#define COR1_CHLMASK 0x03 /* Character Length mask */ 1368471Sache#define COR1_5BITS 0x00 /* 5 bits */ 1378471Sache#define COR1_6BITS 0x01 /* 6 bits */ 1388471Sache#define COR1_7BITS 0x02 /* 7 bits */ 1398471Sache#define COR1_8BITS 0x03 /* 8 bits */ 1408471Sache 1418471Sache/* Channel Option Register 2 */ 1428471Sache#define COR2_IXM 0x80 /* Implied XON mode */ 1439232Sache#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */ 1448471Sache#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */ 1458471Sache#define COR2_LLM 0x10 /* Local Loopback Mode */ 1468471Sache#define COR2_RLM 0x08 /* Remote Loopback Mode */ 1479232Sache#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */ 1489232Sache#define COR2_CtsAE 0x02 /* CTS Automatic Enable */ 1499232Sache#define COR2_DsrAE 0x01 /* DSR Automatic Enable */ 1508471Sache 1518471Sache/* Channel Option Register 3 */ 1529232Sache#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */ 1539232Sache#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */ 1548471Sache#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */ 1558471Sache#define COR3_SCDE 0x10 /* Special Character Detection Enable */ 1569232Sache#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */ 1578471Sache 1588471Sache/* Channel Control Status Register */ 1599232Sache#define CCSR_RxEn 0x80 /* Revceiver Enabled */ 1609232Sache#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */ 1619232Sache#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */ 1629232Sache#define CCSR_TxEn 0x08 /* Transmitter Enabled */ 1639232Sache#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */ 1649232Sache#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */ 1658471Sache 1668471Sache/* Modem Change Option Register 1 */ 1679232Sache#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */ 1689232Sache#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */ 1699232Sache#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */ 1709232Sache#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */ 1718471Sache 1728471Sache/* Modem Change Option Register 2 */ 1739232Sache#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */ 1749232Sache#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */ 1759232Sache#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */ 1768471Sache 1778471Sache/* Modem Change Register */ 1789232Sache#define MCR_DSRchg 0x80 /* DSR Changed */ 1799232Sache#define MCR_CDchg 0x40 /* CD Changed */ 1809232Sache#define MCR_CTSchg 0x20 /* CTS Changed */ 1818471Sache 1828471Sache/* Modem Signal Value Register */ 1838471Sache#define MSVR_DSR 0x80 /* Current state of DSR input */ 1848471Sache#define MSVR_CD 0x40 /* Current state of DSR input */ 1858471Sache#define MSVR_CTS 0x20 /* Current state of CTS input */ 1868471Sache#define MSVR_DTR 0x02 /* Current state of DTR output */ 1878471Sache#define MSVR_RTS 0x01 /* Current state of RTS output */ 1888471Sache 1898471Sache/* Escape characters */ 1908471Sache#define CD180_C_ESC 0x00 /* Escape character */ 1918471Sache#define CD180_C_SBRK 0x81 /* Start sending BREAK */ 1928471Sache#define CD180_C_DELAY 0x82 /* Delay output */ 1938471Sache#define CD180_C_EBRK 0x83 /* Stop sending BREAK */ 1948471Sache 1958471Sache/* Miscellaneous */ 1968471Sache#define CD180_NCHAN 8 /* 8 channels per chip */ 1978471Sache#define CD180_CTICKS 16 /* 16 ticks for character processing */ 1988471Sache#define CD180_NFIFO 8 /* 8 bytes in FIFO */ 199