hwpmc_intel.c revision 282658
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 282658 2015-05-08 19:40:00Z jhb $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44static int 45intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46{ 47 (void) pc; 48 49 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59} 60 61static int 62intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63{ 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74} 75 76struct pmc_mdep * 77pmc_intel_initialize(void) 78{ 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus, stepping, verov; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 error = 0; 91 verov = 0; 92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 93 stepping = cpu_id & 0xF; 94 95 switch (cpu_id & 0xF00) { 96#if defined(__i386__) 97 case 0x500: /* Pentium family processors */ 98 cputype = PMC_CPU_INTEL_P5; 99 break; 100#endif 101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 102 switch (model) { 103#if defined(__i386__) 104 case 0x1: 105 cputype = PMC_CPU_INTEL_P6; 106 break; 107 case 0x3: case 0x5: 108 cputype = PMC_CPU_INTEL_PII; 109 break; 110 case 0x6: case 0x16: 111 cputype = PMC_CPU_INTEL_CL; 112 break; 113 case 0x7: case 0x8: case 0xA: case 0xB: 114 cputype = PMC_CPU_INTEL_PIII; 115 break; 116 case 0x9: case 0xD: 117 cputype = PMC_CPU_INTEL_PM; 118 break; 119#endif 120 case 0xE: 121 cputype = PMC_CPU_INTEL_CORE; 122 break; 123 case 0xF: 124 /* Per Intel document 315338-020. */ 125 if (stepping == 0x7) { 126 cputype = PMC_CPU_INTEL_CORE; 127 verov = 1; 128 } else { 129 cputype = PMC_CPU_INTEL_CORE2; 130 nclasses = 3; 131 } 132 break; 133 case 0x17: 134 cputype = PMC_CPU_INTEL_CORE2EXTREME; 135 nclasses = 3; 136 break; 137 case 0x1C: /* Per Intel document 320047-002. */ 138 cputype = PMC_CPU_INTEL_ATOM; 139 nclasses = 3; 140 break; 141 case 0x1A: 142 case 0x1E: /* 143 * Per Intel document 253669-032 9/2009, 144 * pages A-2 and A-57 145 */ 146 case 0x1F: /* 147 * Per Intel document 253669-032 9/2009, 148 * pages A-2 and A-57 149 */ 150 cputype = PMC_CPU_INTEL_COREI7; 151 nclasses = 5; 152 break; 153 case 0x2E: 154 cputype = PMC_CPU_INTEL_NEHALEM_EX; 155 nclasses = 3; 156 break; 157 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 158 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 159 cputype = PMC_CPU_INTEL_WESTMERE; 160 nclasses = 5; 161 break; 162 case 0x2F: /* Westmere-EX, seen in wild */ 163 cputype = PMC_CPU_INTEL_WESTMERE_EX; 164 nclasses = 3; 165 break; 166 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 167 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 168 nclasses = 5; 169 break; 170 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 171 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 172 nclasses = 3; 173 break; 174 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 175 cputype = PMC_CPU_INTEL_IVYBRIDGE; 176 nclasses = 3; 177 break; 178 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 179 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 180 nclasses = 3; 181 break; 182 case 0x3D: 183 cputype = PMC_CPU_INTEL_BROADWELL; 184 nclasses = 3; 185 break; 186 case 0x3F: /* Per Intel document 325462-045US 09/2014. */ 187 case 0x46: /* Per Intel document 325462-045US 09/2014. */ 188 /* Should 46 be XEON. probably its own? */ 189 cputype = PMC_CPU_INTEL_HASWELL_XEON; 190 nclasses = 3; 191 break; 192 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 193 case 0x45: /* Per Intel document 325462-045US 09/2014. */ 194 cputype = PMC_CPU_INTEL_HASWELL; 195 nclasses = 5; 196 break; 197 case 0x4D: /* Per Intel document 330061-001 01/2014. */ 198 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT; 199 nclasses = 3; 200 break; 201 } 202 break; 203#if defined(__i386__) || defined(__amd64__) 204 case 0xF00: /* P4 */ 205 if (model >= 0 && model <= 6) /* known models */ 206 cputype = PMC_CPU_INTEL_PIV; 207 break; 208 } 209#endif 210 211 if ((int) cputype == -1) { 212 printf("pmc: Unknown Intel CPU.\n"); 213 return (NULL); 214 } 215 216 /* Allocate base class and initialize machine dependent struct */ 217 pmc_mdep = pmc_mdep_alloc(nclasses); 218 219 pmc_mdep->pmd_cputype = cputype; 220 pmc_mdep->pmd_switch_in = intel_switch_in; 221 pmc_mdep->pmd_switch_out = intel_switch_out; 222 223 ncpus = pmc_cpu_max(); 224 error = pmc_tsc_initialize(pmc_mdep, ncpus); 225 if (error) 226 goto error; 227 switch (cputype) { 228#if defined(__i386__) || defined(__amd64__) 229 /* 230 * Intel Core, Core 2 and Atom processors. 231 */ 232 case PMC_CPU_INTEL_ATOM: 233 case PMC_CPU_INTEL_ATOM_SILVERMONT: 234 case PMC_CPU_INTEL_BROADWELL: 235 case PMC_CPU_INTEL_CORE: 236 case PMC_CPU_INTEL_CORE2: 237 case PMC_CPU_INTEL_CORE2EXTREME: 238 case PMC_CPU_INTEL_COREI7: 239 case PMC_CPU_INTEL_NEHALEM_EX: 240 case PMC_CPU_INTEL_IVYBRIDGE: 241 case PMC_CPU_INTEL_SANDYBRIDGE: 242 case PMC_CPU_INTEL_WESTMERE: 243 case PMC_CPU_INTEL_WESTMERE_EX: 244 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 245 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 246 case PMC_CPU_INTEL_HASWELL: 247 case PMC_CPU_INTEL_HASWELL_XEON: 248 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 249 break; 250 251 /* 252 * Intel Pentium 4 Processors, and P4/EMT64 processors. 253 */ 254 255 case PMC_CPU_INTEL_PIV: 256 error = pmc_p4_initialize(pmc_mdep, ncpus); 257 break; 258#endif 259 260#if defined(__i386__) 261 /* 262 * P6 Family Processors 263 */ 264 265 case PMC_CPU_INTEL_P6: 266 case PMC_CPU_INTEL_CL: 267 case PMC_CPU_INTEL_PII: 268 case PMC_CPU_INTEL_PIII: 269 case PMC_CPU_INTEL_PM: 270 error = pmc_p6_initialize(pmc_mdep, ncpus); 271 break; 272 273 /* 274 * Intel Pentium PMCs. 275 */ 276 277 case PMC_CPU_INTEL_P5: 278 error = pmc_p5_initialize(pmc_mdep, ncpus); 279 break; 280#endif 281 282 default: 283 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 284 } 285 286 if (error) { 287 pmc_tsc_finalize(pmc_mdep); 288 goto error; 289 } 290 291 /* 292 * Init the uncore class. 293 */ 294#if defined(__i386__) || defined(__amd64__) 295 switch (cputype) { 296 /* 297 * Intel Corei7 and Westmere processors. 298 */ 299 case PMC_CPU_INTEL_COREI7: 300 case PMC_CPU_INTEL_HASWELL: 301 case PMC_CPU_INTEL_SANDYBRIDGE: 302 case PMC_CPU_INTEL_WESTMERE: 303 case PMC_CPU_INTEL_BROADWELL: 304 error = pmc_uncore_initialize(pmc_mdep, ncpus); 305 break; 306 default: 307 break; 308 } 309#endif 310 error: 311 if (error) { 312 pmc_mdep_free(pmc_mdep); 313 pmc_mdep = NULL; 314 } 315 316 return (pmc_mdep); 317} 318 319void 320pmc_intel_finalize(struct pmc_mdep *md) 321{ 322 pmc_tsc_finalize(md); 323 324 switch (md->pmd_cputype) { 325#if defined(__i386__) || defined(__amd64__) 326 case PMC_CPU_INTEL_ATOM: 327 case PMC_CPU_INTEL_ATOM_SILVERMONT: 328 case PMC_CPU_INTEL_BROADWELL: 329 case PMC_CPU_INTEL_CORE: 330 case PMC_CPU_INTEL_CORE2: 331 case PMC_CPU_INTEL_CORE2EXTREME: 332 case PMC_CPU_INTEL_COREI7: 333 case PMC_CPU_INTEL_NEHALEM_EX: 334 case PMC_CPU_INTEL_HASWELL: 335 case PMC_CPU_INTEL_HASWELL_XEON: 336 case PMC_CPU_INTEL_IVYBRIDGE: 337 case PMC_CPU_INTEL_SANDYBRIDGE: 338 case PMC_CPU_INTEL_WESTMERE: 339 case PMC_CPU_INTEL_WESTMERE_EX: 340 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 341 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 342 pmc_core_finalize(md); 343 break; 344 345 case PMC_CPU_INTEL_PIV: 346 pmc_p4_finalize(md); 347 break; 348#endif 349#if defined(__i386__) 350 case PMC_CPU_INTEL_P6: 351 case PMC_CPU_INTEL_CL: 352 case PMC_CPU_INTEL_PII: 353 case PMC_CPU_INTEL_PIII: 354 case PMC_CPU_INTEL_PM: 355 pmc_p6_finalize(md); 356 break; 357 case PMC_CPU_INTEL_P5: 358 pmc_p5_finalize(md); 359 break; 360#endif 361 default: 362 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 363 } 364 365 /* 366 * Uncore. 367 */ 368#if defined(__i386__) || defined(__amd64__) 369 switch (md->pmd_cputype) { 370 case PMC_CPU_INTEL_BROADWELL: 371 case PMC_CPU_INTEL_COREI7: 372 case PMC_CPU_INTEL_HASWELL: 373 case PMC_CPU_INTEL_SANDYBRIDGE: 374 case PMC_CPU_INTEL_WESTMERE: 375 pmc_uncore_finalize(md); 376 break; 377 default: 378 break; 379 } 380#endif 381} 382