hwpmc_intel.c revision 259647
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 259647 2013-12-20 14:03:56Z attilio $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44static int 45intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46{ 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59} 60 61static int 62intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63{ 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74} 75 76struct pmc_mdep * 77pmc_intel_initialize(void) 78{ 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus, stepping, verov; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 error = 0; 91 verov = 0; 92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 93 stepping = cpu_id & 0xF; 94 95 switch (cpu_id & 0xF00) { 96#if defined(__i386__) 97 case 0x500: /* Pentium family processors */ 98 cputype = PMC_CPU_INTEL_P5; 99 break; 100#endif 101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 102 switch (model) { 103#if defined(__i386__) 104 case 0x1: 105 cputype = PMC_CPU_INTEL_P6; 106 break; 107 case 0x3: case 0x5: 108 cputype = PMC_CPU_INTEL_PII; 109 break; 110 case 0x6: case 0x16: 111 cputype = PMC_CPU_INTEL_CL; 112 break; 113 case 0x7: case 0x8: case 0xA: case 0xB: 114 cputype = PMC_CPU_INTEL_PIII; 115 break; 116 case 0x9: case 0xD: 117 cputype = PMC_CPU_INTEL_PM; 118 break; 119#endif 120 case 0xE: 121 cputype = PMC_CPU_INTEL_CORE; 122 break; 123 case 0xF: 124 /* Per Intel document 315338-020. */ 125 if (stepping == 0x7) { 126 cputype = PMC_CPU_INTEL_CORE; 127 verov = 1; 128 } else { 129 cputype = PMC_CPU_INTEL_CORE2; 130 nclasses = 3; 131 } 132 break; 133 case 0x17: 134 cputype = PMC_CPU_INTEL_CORE2EXTREME; 135 nclasses = 3; 136 break; 137 case 0x1C: /* Per Intel document 320047-002. */ 138 cputype = PMC_CPU_INTEL_ATOM; 139 nclasses = 3; 140 break; 141 case 0x1A: 142 case 0x1E: /* 143 * Per Intel document 253669-032 9/2009, 144 * pages A-2 and A-57 145 */ 146 case 0x1F: /* 147 * Per Intel document 253669-032 9/2009, 148 * pages A-2 and A-57 149 */ 150 case 0x2E: 151 cputype = PMC_CPU_INTEL_COREI7; 152 nclasses = 5; 153 break; 154 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 155 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 156 cputype = PMC_CPU_INTEL_WESTMERE; 157 nclasses = 5; 158 break; 159 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 160 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 161 nclasses = 5; 162 break; 163 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 164 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 165 nclasses = 3; 166 break; 167 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 168 cputype = PMC_CPU_INTEL_IVYBRIDGE; 169 nclasses = 3; 170 break; 171 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 172 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 173 nclasses = 3; 174 break; 175 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 176 cputype = PMC_CPU_INTEL_HASWELL; 177 nclasses = 5; 178 break; 179 } 180 break; 181#if defined(__i386__) || defined(__amd64__) 182 case 0xF00: /* P4 */ 183 if (model >= 0 && model <= 6) /* known models */ 184 cputype = PMC_CPU_INTEL_PIV; 185 break; 186 } 187#endif 188 189 if ((int) cputype == -1) { 190 printf("pmc: Unknown Intel CPU.\n"); 191 return (NULL); 192 } 193 194 /* Allocate base class and initialize machine dependent struct */ 195 pmc_mdep = pmc_mdep_alloc(nclasses); 196 197 pmc_mdep->pmd_cputype = cputype; 198 pmc_mdep->pmd_switch_in = intel_switch_in; 199 pmc_mdep->pmd_switch_out = intel_switch_out; 200 201 ncpus = pmc_cpu_max(); 202 error = pmc_tsc_initialize(pmc_mdep, ncpus); 203 if (error) 204 goto error; 205 switch (cputype) { 206#if defined(__i386__) || defined(__amd64__) 207 /* 208 * Intel Core, Core 2 and Atom processors. 209 */ 210 case PMC_CPU_INTEL_ATOM: 211 case PMC_CPU_INTEL_CORE: 212 case PMC_CPU_INTEL_CORE2: 213 case PMC_CPU_INTEL_CORE2EXTREME: 214 case PMC_CPU_INTEL_COREI7: 215 case PMC_CPU_INTEL_IVYBRIDGE: 216 case PMC_CPU_INTEL_SANDYBRIDGE: 217 case PMC_CPU_INTEL_WESTMERE: 218 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 219 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 220 case PMC_CPU_INTEL_HASWELL: 221 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 222 break; 223 224 /* 225 * Intel Pentium 4 Processors, and P4/EMT64 processors. 226 */ 227 228 case PMC_CPU_INTEL_PIV: 229 error = pmc_p4_initialize(pmc_mdep, ncpus); 230 break; 231#endif 232 233#if defined(__i386__) 234 /* 235 * P6 Family Processors 236 */ 237 238 case PMC_CPU_INTEL_P6: 239 case PMC_CPU_INTEL_CL: 240 case PMC_CPU_INTEL_PII: 241 case PMC_CPU_INTEL_PIII: 242 case PMC_CPU_INTEL_PM: 243 error = pmc_p6_initialize(pmc_mdep, ncpus); 244 break; 245 246 /* 247 * Intel Pentium PMCs. 248 */ 249 250 case PMC_CPU_INTEL_P5: 251 error = pmc_p5_initialize(pmc_mdep, ncpus); 252 break; 253#endif 254 255 default: 256 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 257 } 258 259 if (error) { 260 pmc_tsc_finalize(pmc_mdep); 261 goto error; 262 } 263 264 /* 265 * Init the uncore class. 266 */ 267#if defined(__i386__) || defined(__amd64__) 268 switch (cputype) { 269 /* 270 * Intel Corei7 and Westmere processors. 271 */ 272 case PMC_CPU_INTEL_COREI7: 273 case PMC_CPU_INTEL_HASWELL: 274 case PMC_CPU_INTEL_SANDYBRIDGE: 275 case PMC_CPU_INTEL_WESTMERE: 276 error = pmc_uncore_initialize(pmc_mdep, ncpus); 277 break; 278 default: 279 break; 280 } 281#endif 282 error: 283 if (error) { 284 pmc_mdep_free(pmc_mdep); 285 pmc_mdep = NULL; 286 } 287 288 return (pmc_mdep); 289} 290 291void 292pmc_intel_finalize(struct pmc_mdep *md) 293{ 294 pmc_tsc_finalize(md); 295 296 switch (md->pmd_cputype) { 297#if defined(__i386__) || defined(__amd64__) 298 case PMC_CPU_INTEL_ATOM: 299 case PMC_CPU_INTEL_CORE: 300 case PMC_CPU_INTEL_CORE2: 301 case PMC_CPU_INTEL_CORE2EXTREME: 302 case PMC_CPU_INTEL_COREI7: 303 case PMC_CPU_INTEL_HASWELL: 304 case PMC_CPU_INTEL_IVYBRIDGE: 305 case PMC_CPU_INTEL_SANDYBRIDGE: 306 case PMC_CPU_INTEL_WESTMERE: 307 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 308 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 309 pmc_core_finalize(md); 310 break; 311 312 case PMC_CPU_INTEL_PIV: 313 pmc_p4_finalize(md); 314 break; 315#endif 316#if defined(__i386__) 317 case PMC_CPU_INTEL_P6: 318 case PMC_CPU_INTEL_CL: 319 case PMC_CPU_INTEL_PII: 320 case PMC_CPU_INTEL_PIII: 321 case PMC_CPU_INTEL_PM: 322 pmc_p6_finalize(md); 323 break; 324 case PMC_CPU_INTEL_P5: 325 pmc_p5_finalize(md); 326 break; 327#endif 328 default: 329 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 330 } 331 332 /* 333 * Uncore. 334 */ 335#if defined(__i386__) || defined(__amd64__) 336 switch (md->pmd_cputype) { 337 case PMC_CPU_INTEL_COREI7: 338 case PMC_CPU_INTEL_HASWELL: 339 case PMC_CPU_INTEL_SANDYBRIDGE: 340 case PMC_CPU_INTEL_WESTMERE: 341 pmc_uncore_finalize(md); 342 break; 343 default: 344 break; 345 } 346#endif 347} 348