1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/dev/hwpmc/hwpmc_intel.c 350353 2019-07-26 10:21:55Z kib $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44static int 45intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46{ 47 (void) pc; 48 49 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59} 60 61static int 62intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63{ 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74} 75 76struct pmc_mdep * 77pmc_intel_initialize(void) 78{ 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus, stepping, verov; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 error = 0; 91 verov = 0; 92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 93 stepping = cpu_id & 0xF; 94 95 switch (cpu_id & 0xF00) { 96#if defined(__i386__) 97 case 0x500: /* Pentium family processors */ 98 cputype = PMC_CPU_INTEL_P5; 99 break; 100#endif 101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 102 switch (model) { 103#if defined(__i386__) 104 case 0x1: 105 cputype = PMC_CPU_INTEL_P6; 106 break; 107 case 0x3: case 0x5: 108 cputype = PMC_CPU_INTEL_PII; 109 break; 110 case 0x6: case 0x16: 111 cputype = PMC_CPU_INTEL_CL; 112 break; 113 case 0x7: case 0x8: case 0xA: case 0xB: 114 cputype = PMC_CPU_INTEL_PIII; 115 break; 116 case 0x9: case 0xD: 117 cputype = PMC_CPU_INTEL_PM; 118 break; 119#endif 120 case 0xE: 121 cputype = PMC_CPU_INTEL_CORE; 122 break; 123 case 0xF: 124 /* Per Intel document 315338-020. */ 125 if (stepping == 0x7) { 126 cputype = PMC_CPU_INTEL_CORE; 127 verov = 1; 128 } else { 129 cputype = PMC_CPU_INTEL_CORE2; 130 nclasses = 3; 131 } 132 break; 133 case 0x17: 134 cputype = PMC_CPU_INTEL_CORE2EXTREME; 135 nclasses = 3; 136 break; 137 case 0x1C: /* Per Intel document 320047-002. */ 138 cputype = PMC_CPU_INTEL_ATOM; 139 nclasses = 3; 140 break; 141 case 0x1A: 142 case 0x1E: /* 143 * Per Intel document 253669-032 9/2009, 144 * pages A-2 and A-57 145 */ 146 case 0x1F: /* 147 * Per Intel document 253669-032 9/2009, 148 * pages A-2 and A-57 149 */ 150 cputype = PMC_CPU_INTEL_COREI7; 151 nclasses = 5; 152 break; 153 case 0x2E: 154 cputype = PMC_CPU_INTEL_NEHALEM_EX; 155 nclasses = 3; 156 break; 157 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 158 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 159 cputype = PMC_CPU_INTEL_WESTMERE; 160 nclasses = 5; 161 break; 162 case 0x2F: /* Westmere-EX, seen in wild */ 163 cputype = PMC_CPU_INTEL_WESTMERE_EX; 164 nclasses = 3; 165 break; 166 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 167 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 168 nclasses = 5; 169 break; 170 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 171 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 172 nclasses = 3; 173 break; 174 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 175 cputype = PMC_CPU_INTEL_IVYBRIDGE; 176 nclasses = 3; 177 break; 178 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 179 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 180 nclasses = 3; 181 break; 182 case 0x4e: 183 case 0x5e: 184 cputype = PMC_CPU_INTEL_SKYLAKE; 185 nclasses = 3; 186 break; 187 case 0x55: /* SDM rev 63 */ 188 cputype = PMC_CPU_INTEL_SKYLAKE_XEON; 189 nclasses = 3; 190 break; 191 case 0x3D: 192 case 0x47: 193 cputype = PMC_CPU_INTEL_BROADWELL; 194 nclasses = 3; 195 break; 196 case 0x4f: 197 case 0x56: 198 cputype = PMC_CPU_INTEL_BROADWELL_XEON; 199 nclasses = 3; 200 break; 201 case 0x3F: /* Per Intel document 325462-045US 09/2014. */ 202 case 0x46: /* Per Intel document 325462-045US 09/2014. */ 203 /* Should 46 be XEON. probably its own? */ 204 cputype = PMC_CPU_INTEL_HASWELL_XEON; 205 nclasses = 3; 206 break; 207 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 208 case 0x45: /* Per Intel document 325462-045US 09/2014. */ 209 cputype = PMC_CPU_INTEL_HASWELL; 210 nclasses = 5; 211 break; 212 case 0x37: 213 case 0x4A: 214 case 0x4D: /* Per Intel document 330061-001 01/2014. */ 215 case 0x5A: 216 case 0x5D: 217 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT; 218 nclasses = 3; 219 break; 220 } 221 break; 222#if defined(__i386__) || defined(__amd64__) 223 case 0xF00: /* P4 */ 224 if (model >= 0 && model <= 6) /* known models */ 225 cputype = PMC_CPU_INTEL_PIV; 226 break; 227 } 228#endif 229 230 if ((int) cputype == -1) { 231 printf("pmc: Unknown Intel CPU.\n"); 232 return (NULL); 233 } 234 235 /* Allocate base class and initialize machine dependent struct */ 236 pmc_mdep = pmc_mdep_alloc(nclasses); 237 238 pmc_mdep->pmd_cputype = cputype; 239 pmc_mdep->pmd_switch_in = intel_switch_in; 240 pmc_mdep->pmd_switch_out = intel_switch_out; 241 242 ncpus = pmc_cpu_max(); 243 error = pmc_tsc_initialize(pmc_mdep, ncpus); 244 if (error) 245 goto error; 246 switch (cputype) { 247#if defined(__i386__) || defined(__amd64__) 248 /* 249 * Intel Core, Core 2 and Atom processors. 250 */ 251 case PMC_CPU_INTEL_ATOM: 252 case PMC_CPU_INTEL_ATOM_SILVERMONT: 253 case PMC_CPU_INTEL_BROADWELL: 254 case PMC_CPU_INTEL_BROADWELL_XEON: 255 case PMC_CPU_INTEL_SKYLAKE_XEON: 256 case PMC_CPU_INTEL_SKYLAKE: 257 case PMC_CPU_INTEL_CORE: 258 case PMC_CPU_INTEL_CORE2: 259 case PMC_CPU_INTEL_CORE2EXTREME: 260 case PMC_CPU_INTEL_COREI7: 261 case PMC_CPU_INTEL_NEHALEM_EX: 262 case PMC_CPU_INTEL_IVYBRIDGE: 263 case PMC_CPU_INTEL_SANDYBRIDGE: 264 case PMC_CPU_INTEL_WESTMERE: 265 case PMC_CPU_INTEL_WESTMERE_EX: 266 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 267 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 268 case PMC_CPU_INTEL_HASWELL: 269 case PMC_CPU_INTEL_HASWELL_XEON: 270 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 271 break; 272 273 /* 274 * Intel Pentium 4 Processors, and P4/EMT64 processors. 275 */ 276 277 case PMC_CPU_INTEL_PIV: 278 error = pmc_p4_initialize(pmc_mdep, ncpus); 279 break; 280#endif 281 282#if defined(__i386__) 283 /* 284 * P6 Family Processors 285 */ 286 287 case PMC_CPU_INTEL_P6: 288 case PMC_CPU_INTEL_CL: 289 case PMC_CPU_INTEL_PII: 290 case PMC_CPU_INTEL_PIII: 291 case PMC_CPU_INTEL_PM: 292 error = pmc_p6_initialize(pmc_mdep, ncpus); 293 break; 294 295 /* 296 * Intel Pentium PMCs. 297 */ 298 299 case PMC_CPU_INTEL_P5: 300 error = pmc_p5_initialize(pmc_mdep, ncpus); 301 break; 302#endif 303 304 default: 305 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 306 } 307 308 if (error) { 309 pmc_tsc_finalize(pmc_mdep); 310 goto error; 311 } 312 313 /* 314 * Init the uncore class. 315 */ 316#if defined(__i386__) || defined(__amd64__) 317 switch (cputype) { 318 /* 319 * Intel Corei7 and Westmere processors. 320 */ 321 case PMC_CPU_INTEL_COREI7: 322 case PMC_CPU_INTEL_HASWELL: 323 case PMC_CPU_INTEL_SANDYBRIDGE: 324 case PMC_CPU_INTEL_WESTMERE: 325 case PMC_CPU_INTEL_BROADWELL: 326 error = pmc_uncore_initialize(pmc_mdep, ncpus); 327 break; 328 default: 329 break; 330 } 331#endif 332 error: 333 if (error) { 334 pmc_mdep_free(pmc_mdep); 335 pmc_mdep = NULL; 336 } 337 338 return (pmc_mdep); 339} 340 341void 342pmc_intel_finalize(struct pmc_mdep *md) 343{ 344 pmc_tsc_finalize(md); 345 346 switch (md->pmd_cputype) { 347#if defined(__i386__) || defined(__amd64__) 348 case PMC_CPU_INTEL_ATOM: 349 case PMC_CPU_INTEL_ATOM_SILVERMONT: 350 case PMC_CPU_INTEL_BROADWELL: 351 case PMC_CPU_INTEL_BROADWELL_XEON: 352 case PMC_CPU_INTEL_SKYLAKE_XEON: 353 case PMC_CPU_INTEL_SKYLAKE: 354 case PMC_CPU_INTEL_CORE: 355 case PMC_CPU_INTEL_CORE2: 356 case PMC_CPU_INTEL_CORE2EXTREME: 357 case PMC_CPU_INTEL_COREI7: 358 case PMC_CPU_INTEL_NEHALEM_EX: 359 case PMC_CPU_INTEL_HASWELL: 360 case PMC_CPU_INTEL_HASWELL_XEON: 361 case PMC_CPU_INTEL_IVYBRIDGE: 362 case PMC_CPU_INTEL_SANDYBRIDGE: 363 case PMC_CPU_INTEL_WESTMERE: 364 case PMC_CPU_INTEL_WESTMERE_EX: 365 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 366 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 367 pmc_core_finalize(md); 368 break; 369 370 case PMC_CPU_INTEL_PIV: 371 pmc_p4_finalize(md); 372 break; 373#endif 374#if defined(__i386__) 375 case PMC_CPU_INTEL_P6: 376 case PMC_CPU_INTEL_CL: 377 case PMC_CPU_INTEL_PII: 378 case PMC_CPU_INTEL_PIII: 379 case PMC_CPU_INTEL_PM: 380 pmc_p6_finalize(md); 381 break; 382 case PMC_CPU_INTEL_P5: 383 pmc_p5_finalize(md); 384 break; 385#endif 386 default: 387 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 388 } 389 390 /* 391 * Uncore. 392 */ 393#if defined(__i386__) || defined(__amd64__) 394 switch (md->pmd_cputype) { 395 case PMC_CPU_INTEL_BROADWELL: 396 case PMC_CPU_INTEL_COREI7: 397 case PMC_CPU_INTEL_HASWELL: 398 case PMC_CPU_INTEL_SANDYBRIDGE: 399 case PMC_CPU_INTEL_WESTMERE: 400 pmc_uncore_finalize(md); 401 break; 402 default: 403 break; 404 } 405#endif 406} 407