hifn7751reg.h revision 302408
1/* $FreeBSD: stable/11/sys/dev/hifn/hifn7751reg.h 167755 2007-03-21 03:42:51Z sam $ */ 2/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ 3 4/*- 5 * Invertex AEON / Hifn 7751 driver 6 * Copyright (c) 1999 Invertex Inc. All rights reserved. 7 * Copyright (c) 1999 Theo de Raadt 8 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 9 * http://www.netsec.net 10 * 11 * Please send any comments, feedback, bug-fixes, or feature requests to 12 * software@invertex.com. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 * 42 */ 43#ifndef __HIFN_H__ 44#define __HIFN_H__ 45 46#include <sys/endian.h> 47 48/* 49 * Some PCI configuration space offset defines. The names were made 50 * identical to the names used by the Linux kernel. 51 */ 52#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ 53#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ 54#define HIFN_TRDY_TIMEOUT 0x40 55#define HIFN_RETRY_TIMEOUT 0x41 56 57/* 58 * PCI vendor and device identifiers 59 * (the names are preserved from their OpenBSD source). 60 */ 61#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ 62#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ 63#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ 64#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ 65#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ 66#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ 67#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ 68 69#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ 70#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ 71 72#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ 73#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ 74 75/* 76 * The values below should multiple of 4 -- and be large enough to handle 77 * any command the driver implements. 78 * 79 * MAX_COMMAND = base command + mac command + encrypt command + 80 * mac-key + rc4-key 81 * MAX_RESULT = base result + mac result + mac + encrypt result 82 * 83 * 84 */ 85#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) 86#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) 87 88/* 89 * hifn_desc_t 90 * 91 * Holds an individual descriptor for any of the rings. 92 */ 93typedef struct hifn_desc { 94 volatile u_int32_t l; /* length and status bits */ 95 volatile u_int32_t p; 96} hifn_desc_t; 97 98/* 99 * Masks for the "length" field of struct hifn_desc. 100 */ 101#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ 102#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ 103#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ 104#define HIFN_D_OVER 0x08000000 /* overflow */ 105#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ 106#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ 107#define HIFN_D_VALID 0x80000000 /* valid bit */ 108 109 110/* 111 * Processing Unit Registers (offset from BASEREG0) 112 */ 113#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ 114#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ 115#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ 116#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ 117#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ 118#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ 119#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ 120#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ 121#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ 122#define HIFN_0_MUTE1 0x80 123#define HIFN_0_MUTE2 0x90 124#define HIFN_0_SPACESIZE 0x100 /* Register space size */ 125 126/* Processing Unit Control Register (HIFN_0_PUCTRL) */ 127#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ 128#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ 129#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ 130#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ 131#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ 132 133/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ 134#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ 135#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ 136#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 137#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 138#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ 139#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ 140#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ 141#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ 142#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ 143#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ 144 145/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ 146#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ 147#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ 148#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ 149#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ 150#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ 151#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ 152#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ 153#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ 154#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ 155#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ 156#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ 157#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ 158#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ 159#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ 160#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ 161#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ 162#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ 163#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ 164#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ 165#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ 166#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ 167#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ 168#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ 169 170/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ 171#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ 172#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ 173#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 174#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 175#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ 176#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ 177#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ 178#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ 179#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ 180#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ 181 182/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ 183#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ 184#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ 185#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 186#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 187#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ 188#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ 189#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ 190#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ 191#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ 192#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ 193#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ 194#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ 195#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ 196#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ 197#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ 198#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ 199#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ 200 201/* FIFO Status Register (HIFN_0_FIFOSTAT) */ 202#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ 203#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ 204 205/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ 206#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ 207 208/* 209 * DMA Interface Registers (offset from BASEREG1) 210 */ 211#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ 212#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ 213#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ 214#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ 215#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ 216#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ 217#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ 218#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ 219#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ 220#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ 221#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ 222#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ 223#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ 224#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ 225#define HIFN_1_REVID 0x98 /* Revision ID */ 226 227#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ 228#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ 229#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ 230#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ 231#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ 232#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ 233#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ 234#define HIFN_1_RNG_DATA 0x318 /* RNG data */ 235#define HIFN_1_PUB_MODE 0x320 /* PK mode */ 236#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ 237#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ 238#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ 239#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ 240 241/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ 242#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ 243#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ 244#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ 245#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ 246#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ 247#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ 248#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ 249#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ 250#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ 251#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ 252#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ 253#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ 254#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ 255#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 256#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ 257#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ 258#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ 259#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ 260#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ 261#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ 262#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ 263#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ 264#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 265#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ 266#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ 267#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ 268#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ 269#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ 270#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ 271#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ 272#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ 273#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ 274#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 275#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ 276#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ 277#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ 278#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ 279#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ 280 281/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ 282#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ 283#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ 284#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ 285#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ 286#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ 287#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 288#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ 289#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ 290#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ 291#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ 292#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 293#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ 294#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ 295#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ 296#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ 297#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ 298#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 299#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ 300#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ 301#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ 302#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ 303#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ 304 305/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ 306#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ 307#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ 308#define HIFN_DMACNFG_UNLOCK 0x00000800 309#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ 310#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ 311#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ 312#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ 313#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ 314 315/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ 316#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ 317#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ 318#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ 319#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ 320#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 321#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 322#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 323#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 324 325/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ 326#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ 327 328/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ 329#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ 330#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ 331#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ 332 333/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ 334#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ 335#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ 336 337/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ 338#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ 339#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ 340#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ 341#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ 342#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ 343#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ 344#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ 345#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ 346#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ 347 348/* Public key reset register (HIFN_1_PUB_RESET) */ 349#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ 350 351/* Public operation register (HIFN_1_PUB_OP) */ 352#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ 353#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ 354#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ 355#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ 356#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ 357#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ 358#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ 359#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ 360#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ 361#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ 362#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ 363#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ 364#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ 365#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ 366#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ 367#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ 368#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ 369 370/* Public operand length register (HIFN_1_PUB_OPLEN) */ 371#define HIFN_PUBOPLEN_MODLEN 0x0000007f 372#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 373#define HIFN_PUBOPLEN_REDLEN 0x003c0000 374 375/* Public status register (HIFN_1_PUB_STATUS) */ 376#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ 377#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ 378#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ 379#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ 380#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ 381#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ 382#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ 383 384/* Public interrupt enable register (HIFN_1_PUB_IEN) */ 385#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ 386 387/* Random number generator config register (HIFN_1_RNG_CONFIG) */ 388#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ 389 390/* 391 * Register offsets in register set 1 392 */ 393 394#define HIFN_UNLOCK_SECRET1 0xf4 395#define HIFN_UNLOCK_SECRET2 0xfc 396 397/* 398 * PLL config register 399 * 400 * This register is present only on 7954/7955/7956 parts. It must be 401 * programmed according to the bus interface method used by the h/w. 402 * Note that the parts require a stable clock. Since the PCI clock 403 * may vary the reference clock must usually be used. To avoid 404 * overclocking the core logic, setup must be done carefully, refer 405 * to the driver for details. The exact multiplier required varies 406 * by part and system configuration; refer to the Hifn documentation. 407 */ 408#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ 409#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ 410/* bit 2 reserved */ 411#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ 412#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ 413/* bits 5-9 reserved */ 414#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ 415#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ 416#define HIFN_PLL_ND_SHIFT 11 417#define HIFN_PLL_ND_2 0x00000000 /* 2x */ 418#define HIFN_PLL_ND_4 0x00000800 /* 4x */ 419#define HIFN_PLL_ND_6 0x00001000 /* 6x */ 420#define HIFN_PLL_ND_8 0x00001800 /* 8x */ 421#define HIFN_PLL_ND_10 0x00002000 /* 10x */ 422#define HIFN_PLL_ND_12 0x00002800 /* 12x */ 423/* bits 14-15 reserved */ 424#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ 425/* bits 17-31 reserved */ 426 427/* 428 * Board configuration specifies only these bits. 429 */ 430#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) 431 432/* 433 * Public Key Engine Mode Register 434 */ 435#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ 436#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ 437 438 439/********************************************************************* 440 * Structs for board commands 441 * 442 *********************************************************************/ 443 444/* 445 * Structure to help build up the command data structure. 446 */ 447typedef struct hifn_base_command { 448 volatile u_int16_t masks; 449 volatile u_int16_t session_num; 450 volatile u_int16_t total_source_count; 451 volatile u_int16_t total_dest_count; 452} hifn_base_command_t; 453 454#define HIFN_BASE_CMD_MAC 0x0400 455#define HIFN_BASE_CMD_CRYPT 0x0800 456#define HIFN_BASE_CMD_DECODE 0x2000 457#define HIFN_BASE_CMD_SRCLEN_M 0xc000 458#define HIFN_BASE_CMD_SRCLEN_S 14 459#define HIFN_BASE_CMD_DSTLEN_M 0x3000 460#define HIFN_BASE_CMD_DSTLEN_S 12 461#define HIFN_BASE_CMD_LENMASK_HI 0x30000 462#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff 463 464/* 465 * Structure to help build up the command data structure. 466 */ 467typedef struct hifn_crypt_command { 468 volatile u_int16_t masks; 469 volatile u_int16_t header_skip; 470 volatile u_int16_t source_count; 471 volatile u_int16_t reserved; 472} hifn_crypt_command_t; 473 474#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ 475#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ 476#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ 477#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ 478#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ 479#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ 480#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ 481#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ 482#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ 483#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ 484#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ 485#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ 486#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ 487 488#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 489#define HIFN_CRYPT_CMD_SRCLEN_S 14 490 491#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ 492#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ 493#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ 494#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ 495 496/* 497 * Structure to help build up the command data structure. 498 */ 499typedef struct hifn_mac_command { 500 volatile u_int16_t masks; 501 volatile u_int16_t header_skip; 502 volatile u_int16_t source_count; 503 volatile u_int16_t reserved; 504} hifn_mac_command_t; 505 506#define HIFN_MAC_CMD_ALG_MASK 0x0001 507#define HIFN_MAC_CMD_ALG_SHA1 0x0000 508#define HIFN_MAC_CMD_ALG_MD5 0x0001 509#define HIFN_MAC_CMD_MODE_MASK 0x000c 510#define HIFN_MAC_CMD_MODE_HMAC 0x0000 511#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 512#define HIFN_MAC_CMD_MODE_HASH 0x0008 513#define HIFN_MAC_CMD_MODE_FULL 0x0004 514#define HIFN_MAC_CMD_TRUNC 0x0010 515#define HIFN_MAC_CMD_RESULT 0x0020 516#define HIFN_MAC_CMD_APPEND 0x0040 517#define HIFN_MAC_CMD_SRCLEN_M 0xc000 518#define HIFN_MAC_CMD_SRCLEN_S 14 519 520/* 521 * MAC POS IPsec initiates authentication after encryption on encodes 522 * and before decryption on decodes. 523 */ 524#define HIFN_MAC_CMD_POS_IPSEC 0x0200 525#define HIFN_MAC_CMD_NEW_KEY 0x0800 526 527/* 528 * The poll frequency and poll scalar defines are unshifted values used 529 * to set fields in the DMA Configuration Register. 530 */ 531#ifndef HIFN_POLL_FREQUENCY 532#define HIFN_POLL_FREQUENCY 0x1 533#endif 534 535#ifndef HIFN_POLL_SCALAR 536#define HIFN_POLL_SCALAR 0x0 537#endif 538 539#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ 540#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ 541#endif /* __HIFN_H__ */ 542