hifn7751.c revision 158705
1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3139749Simp/*- 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9120915Ssam * Copyright (c) 2003 Hifn Inc. 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam */ 42104477Ssam 43119418Sobrien#include <sys/cdefs.h> 44119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/hifn/hifn7751.c 158705 2006-05-17 18:34:26Z pjd $"); 45119418Sobrien 46104477Ssam/* 47120915Ssam * Driver for various Hifn encryption processors. 48104477Ssam */ 49112124Ssam#include "opt_hifn.h" 50104477Ssam 51104477Ssam#include <sys/param.h> 52104477Ssam#include <sys/systm.h> 53104477Ssam#include <sys/proc.h> 54104477Ssam#include <sys/errno.h> 55104477Ssam#include <sys/malloc.h> 56104477Ssam#include <sys/kernel.h> 57129879Sphk#include <sys/module.h> 58104477Ssam#include <sys/mbuf.h> 59104477Ssam#include <sys/lock.h> 60104477Ssam#include <sys/mutex.h> 61104477Ssam#include <sys/sysctl.h> 62104477Ssam 63104477Ssam#include <vm/vm.h> 64104477Ssam#include <vm/pmap.h> 65104477Ssam 66104477Ssam#include <machine/bus.h> 67104477Ssam#include <machine/resource.h> 68104477Ssam#include <sys/bus.h> 69104477Ssam#include <sys/rman.h> 70104477Ssam 71104477Ssam#include <opencrypto/cryptodev.h> 72104477Ssam#include <sys/random.h> 73104477Ssam 74119280Simp#include <dev/pci/pcivar.h> 75119280Simp#include <dev/pci/pcireg.h> 76112124Ssam 77112124Ssam#ifdef HIFN_RNDTEST 78112124Ssam#include <dev/rndtest/rndtest.h> 79112124Ssam#endif 80104477Ssam#include <dev/hifn/hifn7751reg.h> 81104477Ssam#include <dev/hifn/hifn7751var.h> 82104477Ssam 83104477Ssam/* 84104477Ssam * Prototypes and count for the pci_device structure 85104477Ssam */ 86104477Ssamstatic int hifn_probe(device_t); 87104477Ssamstatic int hifn_attach(device_t); 88104477Ssamstatic int hifn_detach(device_t); 89104477Ssamstatic int hifn_suspend(device_t); 90104477Ssamstatic int hifn_resume(device_t); 91104477Ssamstatic void hifn_shutdown(device_t); 92104477Ssam 93104477Ssamstatic device_method_t hifn_methods[] = { 94104477Ssam /* Device interface */ 95104477Ssam DEVMETHOD(device_probe, hifn_probe), 96104477Ssam DEVMETHOD(device_attach, hifn_attach), 97104477Ssam DEVMETHOD(device_detach, hifn_detach), 98104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 99104477Ssam DEVMETHOD(device_resume, hifn_resume), 100104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 101104477Ssam 102104477Ssam /* bus interface */ 103104477Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 104104477Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 105104477Ssam 106104477Ssam { 0, 0 } 107104477Ssam}; 108104477Ssamstatic driver_t hifn_driver = { 109104477Ssam "hifn", 110104477Ssam hifn_methods, 111104477Ssam sizeof (struct hifn_softc) 112104477Ssam}; 113104477Ssamstatic devclass_t hifn_devclass; 114104477Ssam 115104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 116105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 117112124Ssam#ifdef HIFN_RNDTEST 118112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 119112124Ssam#endif 120104477Ssam 121104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 122104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 123104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 124104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 125104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 126104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 127104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 128104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 129104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 130104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 131104477Ssamstatic void hifn_sessions(struct hifn_softc *); 132104477Ssamstatic void hifn_intr(void *); 133104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 134104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 135104477Ssamstatic int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 136104477Ssamstatic int hifn_freesession(void *, u_int64_t); 137104477Ssamstatic int hifn_process(void *, struct cryptop *, int); 138104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 139104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 140104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 141104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 142104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 143104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 144104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 145104477Ssamstatic void hifn_rng(void *); 146104477Ssamstatic void hifn_tick(void *); 147104477Ssamstatic void hifn_abort(struct hifn_softc *); 148104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 149104477Ssam 150104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 151104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 152104477Ssam 153131575Sstefanfstatic __inline u_int32_t 154104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 155104477Ssam{ 156104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 157104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 158104477Ssam return (v); 159104477Ssam} 160104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 161104477Ssam 162131575Sstefanfstatic __inline u_int32_t 163104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 164104477Ssam{ 165104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 166104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 167104477Ssam return (v); 168104477Ssam} 169104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 170104477Ssam 171109596SsamSYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 172109596Ssam 173104477Ssam#ifdef HIFN_DEBUG 174104477Ssamstatic int hifn_debug = 0; 175109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 176109596Ssam 0, "control debugging msgs"); 177104477Ssam#endif 178104477Ssam 179104477Ssamstatic struct hifn_stats hifnstats; 180109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 181109596Ssam hifn_stats, "driver statistics"); 182112121Ssamstatic int hifn_maxbatch = 1; 183109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 184109596Ssam 0, "max ops to batch w/o interrupt"); 185104477Ssam 186104477Ssam/* 187104477Ssam * Probe for a supported device. The PCI vendor and device 188104477Ssam * IDs are used to detect devices we know how to handle. 189104477Ssam */ 190104477Ssamstatic int 191104477Ssamhifn_probe(device_t dev) 192104477Ssam{ 193104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 194104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 195143161Simp return (BUS_PROBE_DEFAULT); 196104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 197104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 198104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 199120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 200120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 201104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 202143161Simp return (BUS_PROBE_DEFAULT); 203104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 204104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 205143161Simp return (BUS_PROBE_DEFAULT); 206104477Ssam return (ENXIO); 207104477Ssam} 208104477Ssam 209104477Ssamstatic void 210104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 211104477Ssam{ 212104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 213104477Ssam *paddr = segs->ds_addr; 214104477Ssam} 215104477Ssam 216104477Ssamstatic const char* 217104477Ssamhifn_partname(struct hifn_softc *sc) 218104477Ssam{ 219104477Ssam /* XXX sprintf numbers when not decoded */ 220104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 221104477Ssam case PCI_VENDOR_HIFN: 222104477Ssam switch (pci_get_device(sc->sc_dev)) { 223104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 224104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 225104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 226104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 227120915Ssam case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 228120915Ssam case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 229104477Ssam } 230104477Ssam return "Hifn unknown-part"; 231104477Ssam case PCI_VENDOR_INVERTEX: 232104477Ssam switch (pci_get_device(sc->sc_dev)) { 233104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 234104477Ssam } 235104477Ssam return "Invertex unknown-part"; 236104477Ssam case PCI_VENDOR_NETSEC: 237104477Ssam switch (pci_get_device(sc->sc_dev)) { 238104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 239104477Ssam } 240104477Ssam return "NetSec unknown-part"; 241104477Ssam } 242104477Ssam return "Unknown-vendor unknown-part"; 243104477Ssam} 244104477Ssam 245112124Ssamstatic void 246112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 247112124Ssam{ 248112124Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 249112124Ssam} 250112124Ssam 251140480Ssamstatic u_int 252140480Ssamcheckmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max) 253140480Ssam{ 254140480Ssam if (v > max) { 255140480Ssam device_printf(dev, "Warning, %s %u out of range, " 256140480Ssam "using max %u\n", what, v, max); 257140480Ssam v = max; 258140480Ssam } else if (v < min) { 259140480Ssam device_printf(dev, "Warning, %s %u out of range, " 260140480Ssam "using min %u\n", what, v, min); 261140480Ssam v = min; 262140480Ssam } 263140480Ssam return v; 264140480Ssam} 265140480Ssam 266104477Ssam/* 267140480Ssam * Select PLL configuration for 795x parts. This is complicated in 268140480Ssam * that we cannot determine the optimal parameters without user input. 269140480Ssam * The reference clock is derived from an external clock through a 270140480Ssam * multiplier. The external clock is either the host bus (i.e. PCI) 271140480Ssam * or an external clock generator. When using the PCI bus we assume 272140480Ssam * the clock is either 33 or 66 MHz; for an external source we cannot 273140480Ssam * tell the speed. 274140480Ssam * 275140480Ssam * PLL configuration is done with a string: "pci" for PCI bus, or "ext" 276140480Ssam * for an external source, followed by the frequency. We calculate 277140480Ssam * the appropriate multiplier and PLL register contents accordingly. 278140480Ssam * When no configuration is given we default to "pci66" since that 279140480Ssam * always will allow the card to work. If a card is using the PCI 280140480Ssam * bus clock and in a 33MHz slot then it will be operating at half 281140480Ssam * speed until the correct information is provided. 282140480Ssam */ 283140480Ssamstatic void 284140480Ssamhifn_getpllconfig(device_t dev, u_int *pll) 285140480Ssam{ 286140480Ssam const char *pllspec; 287140480Ssam u_int freq, mul, fl, fh; 288140480Ssam u_int32_t pllconfig; 289140480Ssam char *nxt; 290140480Ssam 291140480Ssam if (resource_string_value("hifn", device_get_unit(dev), 292140480Ssam "pllconfig", &pllspec)) 293140480Ssam pllspec = "pci66"; 294140480Ssam fl = 33, fh = 66; 295140480Ssam pllconfig = 0; 296140480Ssam if (strncmp(pllspec, "ext", 3) == 0) { 297140480Ssam pllspec += 3; 298140480Ssam pllconfig |= HIFN_PLL_REF_SEL; 299140480Ssam switch (pci_get_device(dev)) { 300140480Ssam case PCI_PRODUCT_HIFN_7955: 301140480Ssam case PCI_PRODUCT_HIFN_7956: 302140480Ssam fl = 20, fh = 100; 303140480Ssam break; 304140480Ssam#ifdef notyet 305140480Ssam case PCI_PRODUCT_HIFN_7954: 306140480Ssam fl = 20, fh = 66; 307140480Ssam break; 308140480Ssam#endif 309140480Ssam } 310140480Ssam } else if (strncmp(pllspec, "pci", 3) == 0) 311140480Ssam pllspec += 3; 312140480Ssam freq = strtoul(pllspec, &nxt, 10); 313140480Ssam if (nxt == pllspec) 314140480Ssam freq = 66; 315140480Ssam else 316140480Ssam freq = checkmaxmin(dev, "frequency", freq, fl, fh); 317140480Ssam /* 318140480Ssam * Calculate multiplier. We target a Fck of 266 MHz, 319140480Ssam * allowing only even values, possibly rounded down. 320140480Ssam * Multipliers > 8 must set the charge pump current. 321140480Ssam */ 322140480Ssam mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); 323140480Ssam pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; 324140480Ssam if (mul > 8) 325140480Ssam pllconfig |= HIFN_PLL_IS; 326140480Ssam *pll = pllconfig; 327140480Ssam} 328140480Ssam 329140480Ssam/* 330104477Ssam * Attach an interface that successfully probed. 331104477Ssam */ 332104477Ssamstatic int 333104477Ssamhifn_attach(device_t dev) 334104477Ssam{ 335104477Ssam struct hifn_softc *sc = device_get_softc(dev); 336104477Ssam u_int32_t cmd; 337104477Ssam caddr_t kva; 338104477Ssam int rseg, rid; 339104477Ssam char rbase; 340104477Ssam u_int16_t ena, rev; 341104477Ssam 342104477Ssam KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 343104477Ssam bzero(sc, sizeof (*sc)); 344104477Ssam sc->sc_dev = dev; 345104477Ssam 346115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 347104477Ssam 348104477Ssam /* XXX handle power management */ 349104477Ssam 350104477Ssam /* 351120915Ssam * The 7951 and 795x have a random number generator and 352104477Ssam * public key support; note this. 353104477Ssam */ 354104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 355120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 356120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 357120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 358104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 359104477Ssam /* 360104477Ssam * The 7811 has a random number generator and 361104477Ssam * we also note it's identity 'cuz of some quirks. 362104477Ssam */ 363104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 364104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 365104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 366104477Ssam 367104477Ssam /* 368120915Ssam * The 795x parts support AES. 369120915Ssam */ 370120915Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 371120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 372140480Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { 373120915Ssam sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 374140480Ssam /* 375140480Ssam * Select PLL configuration. This depends on the 376140480Ssam * bus and board design and must be manually configured 377140480Ssam * if the default setting is unacceptable. 378140480Ssam */ 379140480Ssam hifn_getpllconfig(dev, &sc->sc_pllconfig); 380140480Ssam } 381120915Ssam 382120915Ssam /* 383104477Ssam * Configure support for memory-mapped access to 384104477Ssam * registers and for DMA operations. 385104477Ssam */ 386104477Ssam#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 387104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 388104477Ssam cmd |= PCIM_ENA; 389104477Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 390104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 391104477Ssam if ((cmd & PCIM_ENA) != PCIM_ENA) { 392104477Ssam device_printf(dev, "failed to enable %s\n", 393104477Ssam (cmd & PCIM_ENA) == 0 ? 394104477Ssam "memory mapping & bus mastering" : 395104477Ssam (cmd & PCIM_CMD_MEMEN) == 0 ? 396104477Ssam "memory mapping" : "bus mastering"); 397104477Ssam goto fail_pci; 398104477Ssam } 399104477Ssam#undef PCIM_ENA 400104477Ssam 401104477Ssam /* 402104477Ssam * Setup PCI resources. Note that we record the bus 403104477Ssam * tag and handle for each register mapping, this is 404104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 405104477Ssam * and WRITE_REG_1 macros throughout the driver. 406104477Ssam */ 407104477Ssam rid = HIFN_BAR0; 408127135Snjl sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 409127135Snjl RF_ACTIVE); 410104477Ssam if (sc->sc_bar0res == NULL) { 411104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 412104477Ssam goto fail_pci; 413104477Ssam } 414104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 415104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 416104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 417104477Ssam 418104477Ssam rid = HIFN_BAR1; 419127135Snjl sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 420127135Snjl RF_ACTIVE); 421104477Ssam if (sc->sc_bar1res == NULL) { 422104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 423104477Ssam goto fail_io0; 424104477Ssam } 425104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 426104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 427104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 428104477Ssam 429104477Ssam hifn_set_retry(sc); 430104477Ssam 431104477Ssam /* 432104477Ssam * Setup the area where the Hifn DMA's descriptors 433104477Ssam * and associated data structures. 434104477Ssam */ 435104477Ssam if (bus_dma_tag_create(NULL, /* parent */ 436104477Ssam 1, 0, /* alignment,boundary */ 437104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 438104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 439104477Ssam NULL, NULL, /* filter, filterarg */ 440104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 441104477Ssam MAX_SCATTER, /* nsegments */ 442104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 443104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 444117126Sscottl NULL, /* lockfunc */ 445117126Sscottl NULL, /* lockarg */ 446104477Ssam &sc->sc_dmat)) { 447104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 448104477Ssam goto fail_io1; 449104477Ssam } 450104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 451104477Ssam device_printf(dev, "cannot create dma map\n"); 452104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 453104477Ssam goto fail_io1; 454104477Ssam } 455104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 456104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 457104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 458104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 459104477Ssam goto fail_io1; 460104477Ssam } 461104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 462104477Ssam sizeof (*sc->sc_dma), 463104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 464104477Ssam BUS_DMA_NOWAIT)) { 465104477Ssam device_printf(dev, "cannot load dma map\n"); 466104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 467104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 468104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 469104477Ssam goto fail_io1; 470104477Ssam } 471104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 472104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 473104477Ssam 474123824Ssam KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 475123824Ssam KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 476123824Ssam KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 477123824Ssam KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 478104477Ssam 479104477Ssam /* 480104477Ssam * Reset the board and do the ``secret handshake'' 481104477Ssam * to enable the crypto support. Then complete the 482104477Ssam * initialization procedure by setting up the interrupt 483104477Ssam * and hooking in to the system crypto support so we'll 484104477Ssam * get used for system services like the crypto device, 485104477Ssam * IPsec, RNG device, etc. 486104477Ssam */ 487104477Ssam hifn_reset_board(sc, 0); 488104477Ssam 489104477Ssam if (hifn_enable_crypto(sc) != 0) { 490104477Ssam device_printf(dev, "crypto enabling failed\n"); 491104477Ssam goto fail_mem; 492104477Ssam } 493104477Ssam hifn_reset_puc(sc); 494104477Ssam 495104477Ssam hifn_init_dma(sc); 496104477Ssam hifn_init_pci_registers(sc); 497104477Ssam 498120915Ssam /* XXX can't dynamically determine ram type for 795x; force dram */ 499120915Ssam if (sc->sc_flags & HIFN_IS_7956) 500120915Ssam sc->sc_drammodel = 1; 501120915Ssam else if (hifn_ramtype(sc)) 502104477Ssam goto fail_mem; 503104477Ssam 504104477Ssam if (sc->sc_drammodel == 0) 505104477Ssam hifn_sramsize(sc); 506104477Ssam else 507104477Ssam hifn_dramsize(sc); 508104477Ssam 509104477Ssam /* 510104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 511104477Ssam * of the address lines were left floating 512104477Ssam */ 513104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 514104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 515104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 516104477Ssam sc->sc_ramsize >>= 1; 517104477Ssam 518104477Ssam /* 519104477Ssam * Arrange the interrupt line. 520104477Ssam */ 521104477Ssam rid = 0; 522127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 523127135Snjl RF_SHAREABLE|RF_ACTIVE); 524104477Ssam if (sc->sc_irq == NULL) { 525104477Ssam device_printf(dev, "could not map interrupt\n"); 526104477Ssam goto fail_mem; 527104477Ssam } 528104477Ssam /* 529104477Ssam * NB: Network code assumes we are blocked with splimp() 530104477Ssam * so make sure the IRQ is marked appropriately. 531104477Ssam */ 532115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 533104477Ssam hifn_intr, sc, &sc->sc_intrhand)) { 534104477Ssam device_printf(dev, "could not setup interrupt\n"); 535104477Ssam goto fail_intr2; 536104477Ssam } 537104477Ssam 538104477Ssam hifn_sessions(sc); 539104477Ssam 540104477Ssam /* 541104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 542104477Ssam * from the 7951. 543104477Ssam */ 544104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 545104477Ssam 546104477Ssam rseg = sc->sc_ramsize / 1024; 547104477Ssam rbase = 'K'; 548104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 549104477Ssam rbase = 'M'; 550104477Ssam rseg /= 1024; 551104477Ssam } 552140480Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", 553104477Ssam hifn_partname(sc), rev, 554136526Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's'); 555140480Ssam if (sc->sc_flags & HIFN_IS_7956) 556140480Ssam printf(", pll=0x%x<%s clk, %ux mult>", 557140480Ssam sc->sc_pllconfig, 558140480Ssam sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", 559140480Ssam 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); 560140480Ssam printf("\n"); 561104477Ssam 562104477Ssam sc->sc_cid = crypto_get_driverid(0); 563104477Ssam if (sc->sc_cid < 0) { 564104477Ssam device_printf(dev, "could not get crypto driver id\n"); 565104477Ssam goto fail_intr; 566104477Ssam } 567104477Ssam 568104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 569104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 570104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 571104477Ssam 572104477Ssam switch (ena) { 573104477Ssam case HIFN_PUSTAT_ENA_2: 574104477Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 575104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 576104477Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 577104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 578120915Ssam if (sc->sc_flags & HIFN_HAS_AES) 579120915Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 580120915Ssam hifn_newsession, hifn_freesession, 581120915Ssam hifn_process, sc); 582104477Ssam /*FALLTHROUGH*/ 583104477Ssam case HIFN_PUSTAT_ENA_1: 584104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 585104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 586104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 587104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 588104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 589104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 590104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 591104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 592104477Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 593104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 594104477Ssam break; 595104477Ssam } 596104477Ssam 597104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 598104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 599104477Ssam 600104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 601104477Ssam hifn_init_pubrng(sc); 602104477Ssam 603119137Ssam callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 604104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 605104477Ssam 606104477Ssam return (0); 607104477Ssam 608104477Ssamfail_intr: 609104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 610104477Ssamfail_intr2: 611104477Ssam /* XXX don't store rid */ 612104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 613104477Ssamfail_mem: 614104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 615104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 616104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 617104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 618104477Ssam 619104477Ssam /* Turn off DMA polling */ 620104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 621104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 622104477Ssamfail_io1: 623104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 624104477Ssamfail_io0: 625104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 626104477Ssamfail_pci: 627104477Ssam mtx_destroy(&sc->sc_mtx); 628104477Ssam return (ENXIO); 629104477Ssam} 630104477Ssam 631104477Ssam/* 632104477Ssam * Detach an interface that successfully probed. 633104477Ssam */ 634104477Ssamstatic int 635104477Ssamhifn_detach(device_t dev) 636104477Ssam{ 637104477Ssam struct hifn_softc *sc = device_get_softc(dev); 638104477Ssam 639104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 640104477Ssam 641115748Ssam /* disable interrupts */ 642115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 643104477Ssam 644104477Ssam /*XXX other resources */ 645104477Ssam callout_stop(&sc->sc_tickto); 646104477Ssam callout_stop(&sc->sc_rngto); 647115848Ssam#ifdef HIFN_RNDTEST 648115848Ssam if (sc->sc_rndtest) 649115862Ssam rndtest_detach(sc->sc_rndtest); 650115848Ssam#endif 651104477Ssam 652104477Ssam /* Turn off DMA polling */ 653104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 654104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 655104477Ssam 656104477Ssam crypto_unregister_all(sc->sc_cid); 657104477Ssam 658104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 659104477Ssam 660104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 661104477Ssam /* XXX don't store rid */ 662104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 663104477Ssam 664104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 665104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 666104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 667104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 668104477Ssam 669104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 670104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 671104477Ssam 672104477Ssam mtx_destroy(&sc->sc_mtx); 673104477Ssam 674104477Ssam return (0); 675104477Ssam} 676104477Ssam 677104477Ssam/* 678104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 679104477Ssam * get confused by errant DMAs when rebooting. 680104477Ssam */ 681104477Ssamstatic void 682104477Ssamhifn_shutdown(device_t dev) 683104477Ssam{ 684104477Ssam#ifdef notyet 685104477Ssam hifn_stop(device_get_softc(dev)); 686104477Ssam#endif 687104477Ssam} 688104477Ssam 689104477Ssam/* 690104477Ssam * Device suspend routine. Stop the interface and save some PCI 691104477Ssam * settings in case the BIOS doesn't restore them properly on 692104477Ssam * resume. 693104477Ssam */ 694104477Ssamstatic int 695104477Ssamhifn_suspend(device_t dev) 696104477Ssam{ 697104477Ssam struct hifn_softc *sc = device_get_softc(dev); 698104477Ssam#ifdef notyet 699104477Ssam hifn_stop(sc); 700104477Ssam#endif 701104477Ssam sc->sc_suspended = 1; 702104477Ssam 703104477Ssam return (0); 704104477Ssam} 705104477Ssam 706104477Ssam/* 707104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 708104477Ssam * doesn't, re-enable busmastering, and restart the interface if 709104477Ssam * appropriate. 710104477Ssam */ 711104477Ssamstatic int 712104477Ssamhifn_resume(device_t dev) 713104477Ssam{ 714104477Ssam struct hifn_softc *sc = device_get_softc(dev); 715104477Ssam#ifdef notyet 716104477Ssam /* reenable busmastering */ 717104477Ssam pci_enable_busmaster(dev); 718104477Ssam pci_enable_io(dev, HIFN_RES); 719104477Ssam 720104477Ssam /* reinitialize interface if necessary */ 721104477Ssam if (ifp->if_flags & IFF_UP) 722104477Ssam rl_init(sc); 723104477Ssam#endif 724104477Ssam sc->sc_suspended = 0; 725104477Ssam 726104477Ssam return (0); 727104477Ssam} 728104477Ssam 729104477Ssamstatic int 730104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 731104477Ssam{ 732104477Ssam u_int32_t r; 733104477Ssam int i; 734104477Ssam 735112124Ssam#ifdef HIFN_RNDTEST 736112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 737112124Ssam if (sc->sc_rndtest) 738112124Ssam sc->sc_harvest = rndtest_harvest; 739112124Ssam else 740112124Ssam sc->sc_harvest = default_harvest; 741112124Ssam#else 742112124Ssam sc->sc_harvest = default_harvest; 743112124Ssam#endif 744104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 745104477Ssam /* Reset 7951 public key/rng engine */ 746104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 747104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 748104477Ssam 749104477Ssam for (i = 0; i < 100; i++) { 750104477Ssam DELAY(1000); 751104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 752104477Ssam HIFN_PUBRST_RESET) == 0) 753104477Ssam break; 754104477Ssam } 755104477Ssam 756104477Ssam if (i == 100) { 757104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 758104477Ssam return (1); 759104477Ssam } 760104477Ssam } 761104477Ssam 762104477Ssam /* Enable the rng, if available */ 763104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 764104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 765104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 766104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 767104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 768104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 769104477Ssam } 770104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 771104477Ssam HIFN_7811_RNGCFG_DEFL); 772104477Ssam r |= HIFN_7811_RNGENA_ENA; 773104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 774104477Ssam } else 775104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 776104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 777104477Ssam HIFN_RNGCFG_ENA); 778104477Ssam 779104477Ssam sc->sc_rngfirst = 1; 780104477Ssam if (hz >= 100) 781104477Ssam sc->sc_rnghz = hz / 100; 782104477Ssam else 783104477Ssam sc->sc_rnghz = 1; 784119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 785104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 786104477Ssam } 787104477Ssam 788104477Ssam /* Enable public key engine, if available */ 789104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 790104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 791104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 792104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 793104477Ssam } 794104477Ssam 795104477Ssam return (0); 796104477Ssam} 797104477Ssam 798104477Ssamstatic void 799104477Ssamhifn_rng(void *vsc) 800104477Ssam{ 801104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 802104477Ssam struct hifn_softc *sc = vsc; 803104477Ssam u_int32_t sts, num[2]; 804104477Ssam int i; 805104477Ssam 806104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 807104477Ssam for (i = 0; i < 5; i++) { 808104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 809104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 810104477Ssam device_printf(sc->sc_dev, 811104477Ssam "RNG underflow: disabling\n"); 812104477Ssam return; 813104477Ssam } 814104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 815104477Ssam break; 816104477Ssam 817104477Ssam /* 818104477Ssam * There are at least two words in the RNG FIFO 819104477Ssam * at this point. 820104477Ssam */ 821104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 822104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 823104477Ssam /* NB: discard first data read */ 824104477Ssam if (sc->sc_rngfirst) 825104477Ssam sc->sc_rngfirst = 0; 826104477Ssam else 827112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 828112124Ssam num, sizeof (num)); 829104477Ssam } 830104477Ssam } else { 831104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 832104477Ssam 833104477Ssam /* NB: discard first data read */ 834104477Ssam if (sc->sc_rngfirst) 835104477Ssam sc->sc_rngfirst = 0; 836104477Ssam else 837112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 838112124Ssam num, sizeof (num[0])); 839104477Ssam } 840104477Ssam 841104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 842104477Ssam#undef RANDOM_BITS 843104477Ssam} 844104477Ssam 845104477Ssamstatic void 846104477Ssamhifn_puc_wait(struct hifn_softc *sc) 847104477Ssam{ 848104477Ssam int i; 849104477Ssam 850104477Ssam for (i = 5000; i > 0; i--) { 851104477Ssam DELAY(1); 852104477Ssam if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 853104477Ssam break; 854104477Ssam } 855104477Ssam if (!i) 856104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 857104477Ssam} 858104477Ssam 859104477Ssam/* 860104477Ssam * Reset the processing unit. 861104477Ssam */ 862104477Ssamstatic void 863104477Ssamhifn_reset_puc(struct hifn_softc *sc) 864104477Ssam{ 865104477Ssam /* Reset processing unit */ 866104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 867104477Ssam hifn_puc_wait(sc); 868104477Ssam} 869104477Ssam 870104477Ssam/* 871104477Ssam * Set the Retry and TRDY registers; note that we set them to 872104477Ssam * zero because the 7811 locks up when forced to retry (section 873104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 874104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 875104477Ssam */ 876104477Ssamstatic void 877104477Ssamhifn_set_retry(struct hifn_softc *sc) 878104477Ssam{ 879104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 880104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 881104477Ssam pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 882104477Ssam} 883104477Ssam 884104477Ssam/* 885104477Ssam * Resets the board. Values in the regesters are left as is 886104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 887104477Ssam */ 888104477Ssamstatic void 889104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 890104477Ssam{ 891104477Ssam u_int32_t reg; 892104477Ssam 893104477Ssam /* 894104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 895104477Ssam * resetting the board and zeros out the other fields. 896104477Ssam */ 897104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 898104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 899104477Ssam 900104477Ssam /* 901104477Ssam * Now that polling has been disabled, we have to wait 1 ms 902104477Ssam * before resetting the board. 903104477Ssam */ 904104477Ssam DELAY(1000); 905104477Ssam 906104477Ssam /* Reset the DMA unit */ 907104477Ssam if (full) { 908104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 909104477Ssam DELAY(1000); 910104477Ssam } else { 911104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 912104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 913104477Ssam hifn_reset_puc(sc); 914104477Ssam } 915104477Ssam 916104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 917104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 918104477Ssam 919104477Ssam /* Bring dma unit out of reset */ 920104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 921104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 922104477Ssam 923104477Ssam hifn_puc_wait(sc); 924104477Ssam hifn_set_retry(sc); 925104477Ssam 926104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 927104477Ssam for (reg = 0; reg < 1000; reg++) { 928104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 929104477Ssam HIFN_MIPSRST_CRAMINIT) 930104477Ssam break; 931104477Ssam DELAY(1000); 932104477Ssam } 933104477Ssam if (reg == 1000) 934104477Ssam printf(": cram init timeout\n"); 935104477Ssam } 936104477Ssam} 937104477Ssam 938104477Ssamstatic u_int32_t 939104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 940104477Ssam{ 941104477Ssam int i; 942104477Ssam u_int32_t v; 943104477Ssam 944104477Ssam for (i = 0; i < cnt; i++) { 945104477Ssam 946104477Ssam /* get the parity */ 947104477Ssam v = a & 0x80080125; 948104477Ssam v ^= v >> 16; 949104477Ssam v ^= v >> 8; 950104477Ssam v ^= v >> 4; 951104477Ssam v ^= v >> 2; 952104477Ssam v ^= v >> 1; 953104477Ssam 954104477Ssam a = (v & 1) ^ (a << 1); 955104477Ssam } 956104477Ssam 957104477Ssam return a; 958104477Ssam} 959104477Ssam 960104477Ssamstruct pci2id { 961104477Ssam u_short pci_vendor; 962104477Ssam u_short pci_prod; 963104477Ssam char card_id[13]; 964104477Ssam}; 965104477Ssamstatic struct pci2id pci2id[] = { 966104477Ssam { 967104477Ssam PCI_VENDOR_HIFN, 968104477Ssam PCI_PRODUCT_HIFN_7951, 969104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 970104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 971104477Ssam }, { 972120915Ssam PCI_VENDOR_HIFN, 973120915Ssam PCI_PRODUCT_HIFN_7955, 974120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 975120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 976120915Ssam }, { 977120915Ssam PCI_VENDOR_HIFN, 978120915Ssam PCI_PRODUCT_HIFN_7956, 979120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 980120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 981120915Ssam }, { 982104477Ssam PCI_VENDOR_NETSEC, 983104477Ssam PCI_PRODUCT_NETSEC_7751, 984104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 985104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 986104477Ssam }, { 987104477Ssam PCI_VENDOR_INVERTEX, 988104477Ssam PCI_PRODUCT_INVERTEX_AEON, 989104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 990104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 991104477Ssam }, { 992104477Ssam PCI_VENDOR_HIFN, 993104477Ssam PCI_PRODUCT_HIFN_7811, 994104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 995104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 996104477Ssam }, { 997104477Ssam /* 998104477Ssam * Other vendors share this PCI ID as well, such as 999104477Ssam * http://www.powercrypt.com, and obviously they also 1000104477Ssam * use the same key. 1001104477Ssam */ 1002104477Ssam PCI_VENDOR_HIFN, 1003104477Ssam PCI_PRODUCT_HIFN_7751, 1004104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1005104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1006104477Ssam }, 1007104477Ssam}; 1008104477Ssam 1009104477Ssam/* 1010104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 1011104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 1012104477Ssam * as enabling crypto twice will lock the board. 1013104477Ssam */ 1014104477Ssamstatic int 1015104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 1016104477Ssam{ 1017104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 1018104477Ssam char *offtbl = NULL; 1019104477Ssam 1020104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 1021104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 1022104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 1023104477Ssam offtbl = pci2id[i].card_id; 1024104477Ssam break; 1025104477Ssam } 1026104477Ssam } 1027104477Ssam if (offtbl == NULL) { 1028104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 1029104477Ssam return (1); 1030104477Ssam } 1031104477Ssam 1032104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1033104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 1034104477Ssam 1035104477Ssam /* 1036104477Ssam * The RAM config register's encrypt level bit needs to be set before 1037104477Ssam * every read performed on the encryption level register. 1038104477Ssam */ 1039104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1040104477Ssam 1041104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1042104477Ssam 1043104477Ssam /* 1044104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 1045104477Ssam * next reboot. 1046104477Ssam */ 1047104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 1048104477Ssam#ifdef HIFN_DEBUG 1049104477Ssam if (hifn_debug) 1050104477Ssam device_printf(sc->sc_dev, 1051104477Ssam "Strong crypto already enabled!\n"); 1052104477Ssam#endif 1053104477Ssam goto report; 1054104477Ssam } 1055104477Ssam 1056104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 1057104477Ssam#ifdef HIFN_DEBUG 1058104477Ssam if (hifn_debug) 1059104477Ssam device_printf(sc->sc_dev, 1060104477Ssam "Unknown encryption level 0x%x\n", encl); 1061104477Ssam#endif 1062104477Ssam return 1; 1063104477Ssam } 1064104477Ssam 1065104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 1066104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 1067104477Ssam DELAY(1000); 1068104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 1069104477Ssam DELAY(1000); 1070104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 1071104477Ssam DELAY(1000); 1072104477Ssam 1073104477Ssam for (i = 0; i <= 12; i++) { 1074104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1075104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1076104477Ssam 1077104477Ssam DELAY(1000); 1078104477Ssam } 1079104477Ssam 1080104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1081104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1082104477Ssam 1083104477Ssam#ifdef HIFN_DEBUG 1084104477Ssam if (hifn_debug) { 1085104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1086104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 1087104477Ssam "locked until next system reset!\n"); 1088104477Ssam else 1089104477Ssam device_printf(sc->sc_dev, "Engine enabled " 1090104477Ssam "successfully!\n"); 1091104477Ssam } 1092104477Ssam#endif 1093104477Ssam 1094104477Ssamreport: 1095104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1096104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1097104477Ssam 1098104477Ssam switch (encl) { 1099104477Ssam case HIFN_PUSTAT_ENA_1: 1100104477Ssam case HIFN_PUSTAT_ENA_2: 1101104477Ssam break; 1102104477Ssam case HIFN_PUSTAT_ENA_0: 1103104477Ssam default: 1104104477Ssam device_printf(sc->sc_dev, "disabled"); 1105104477Ssam break; 1106104477Ssam } 1107104477Ssam 1108104477Ssam return 0; 1109104477Ssam} 1110104477Ssam 1111104477Ssam/* 1112104477Ssam * Give initial values to the registers listed in the "Register Space" 1113104477Ssam * section of the HIFN Software Development reference manual. 1114104477Ssam */ 1115104477Ssamstatic void 1116104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1117104477Ssam{ 1118104477Ssam /* write fixed values needed by the Initialization registers */ 1119104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1120104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1121104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1122104477Ssam 1123104477Ssam /* write all 4 ring address registers */ 1124104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1125104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1126104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1127104477Ssam offsetof(struct hifn_dma, srcr[0])); 1128104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1129104477Ssam offsetof(struct hifn_dma, dstr[0])); 1130104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1131104477Ssam offsetof(struct hifn_dma, resr[0])); 1132104477Ssam 1133104477Ssam DELAY(2000); 1134104477Ssam 1135104477Ssam /* write status register */ 1136104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1137104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1138104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1139104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1140104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1141104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1142104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1143104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1144104477Ssam HIFN_DMACSR_S_WAIT | 1145104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1146104477Ssam HIFN_DMACSR_C_WAIT | 1147104477Ssam HIFN_DMACSR_ENGINE | 1148104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1149104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1150104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1151104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1152104477Ssam 1153104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1154104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1155104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1156104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1157104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1158104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1159104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1160104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1161104477Ssam 1162104477Ssam 1163120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1164140480Ssam u_int32_t pll; 1165140480Ssam 1166120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1167120915Ssam HIFN_PUCNFG_TCALLPHASES | 1168120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1169140480Ssam 1170140480Ssam /* turn off the clocks and insure bypass is set */ 1171140480Ssam pll = READ_REG_1(sc, HIFN_1_PLL); 1172140480Ssam pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) 1173140480Ssam | HIFN_PLL_BP; 1174140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1175140480Ssam DELAY(10*1000); /* 10ms */ 1176140480Ssam /* change configuration */ 1177140480Ssam pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; 1178140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1179140480Ssam DELAY(10*1000); /* 10ms */ 1180140480Ssam /* disable bypass */ 1181140480Ssam pll &= ~HIFN_PLL_BP; 1182140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1183140480Ssam /* enable clocks with new configuration */ 1184140480Ssam pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; 1185140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1186120915Ssam } else { 1187120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1188120915Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1189120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1190120915Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1191120915Ssam } 1192120915Ssam 1193104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1194104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1195104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1196104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1197104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1198104477Ssam} 1199104477Ssam 1200104477Ssam/* 1201104477Ssam * The maximum number of sessions supported by the card 1202104477Ssam * is dependent on the amount of context ram, which 1203104477Ssam * encryption algorithms are enabled, and how compression 1204104477Ssam * is configured. This should be configured before this 1205104477Ssam * routine is called. 1206104477Ssam */ 1207104477Ssamstatic void 1208104477Ssamhifn_sessions(struct hifn_softc *sc) 1209104477Ssam{ 1210104477Ssam u_int32_t pucnfg; 1211104477Ssam int ctxsize; 1212104477Ssam 1213104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1214104477Ssam 1215104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1216104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1217104477Ssam ctxsize = 128; 1218104477Ssam else 1219104477Ssam ctxsize = 512; 1220120915Ssam /* 1221120915Ssam * 7955/7956 has internal context memory of 32K 1222120915Ssam */ 1223120915Ssam if (sc->sc_flags & HIFN_IS_7956) 1224120915Ssam sc->sc_maxses = 32768 / ctxsize; 1225120915Ssam else 1226120915Ssam sc->sc_maxses = 1 + 1227120915Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1228104477Ssam } else 1229104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1230104477Ssam 1231104477Ssam if (sc->sc_maxses > 2048) 1232104477Ssam sc->sc_maxses = 2048; 1233104477Ssam} 1234104477Ssam 1235104477Ssam/* 1236104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1237104477Ssam * state when this is called. 1238104477Ssam */ 1239104477Ssamstatic int 1240104477Ssamhifn_ramtype(struct hifn_softc *sc) 1241104477Ssam{ 1242104477Ssam u_int8_t data[8], dataexpect[8]; 1243104477Ssam int i; 1244104477Ssam 1245104477Ssam for (i = 0; i < sizeof(data); i++) 1246104477Ssam data[i] = dataexpect[i] = 0x55; 1247104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1248104477Ssam return (-1); 1249104477Ssam if (hifn_readramaddr(sc, 0, data)) 1250104477Ssam return (-1); 1251104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1252104477Ssam sc->sc_drammodel = 1; 1253104477Ssam return (0); 1254104477Ssam } 1255104477Ssam 1256104477Ssam for (i = 0; i < sizeof(data); i++) 1257104477Ssam data[i] = dataexpect[i] = 0xaa; 1258104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1259104477Ssam return (-1); 1260104477Ssam if (hifn_readramaddr(sc, 0, data)) 1261104477Ssam return (-1); 1262104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1263104477Ssam sc->sc_drammodel = 1; 1264104477Ssam return (0); 1265104477Ssam } 1266104477Ssam 1267104477Ssam return (0); 1268104477Ssam} 1269104477Ssam 1270104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1271104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1272104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1273104477Ssam 1274104477Ssamstatic int 1275104477Ssamhifn_sramsize(struct hifn_softc *sc) 1276104477Ssam{ 1277104477Ssam u_int32_t a; 1278104477Ssam u_int8_t data[8]; 1279104477Ssam u_int8_t dataexpect[sizeof(data)]; 1280104477Ssam int32_t i; 1281104477Ssam 1282104477Ssam for (i = 0; i < sizeof(data); i++) 1283104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1284104477Ssam 1285104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1286104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1287104477Ssam bcopy(&i, data, sizeof(i)); 1288104477Ssam hifn_writeramaddr(sc, a, data); 1289104477Ssam } 1290104477Ssam 1291104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1292104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1293104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1294104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1295104477Ssam return (0); 1296104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1297104477Ssam return (0); 1298104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1299104477Ssam } 1300104477Ssam 1301104477Ssam return (0); 1302104477Ssam} 1303104477Ssam 1304104477Ssam/* 1305104477Ssam * XXX For dram boards, one should really try all of the 1306104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1307104477Ssam * is already set up correctly. 1308104477Ssam */ 1309104477Ssamstatic int 1310104477Ssamhifn_dramsize(struct hifn_softc *sc) 1311104477Ssam{ 1312104477Ssam u_int32_t cnfg; 1313104477Ssam 1314120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1315120915Ssam /* 1316120915Ssam * 7955/7956 have a fixed internal ram of only 32K. 1317120915Ssam */ 1318120915Ssam sc->sc_ramsize = 32768; 1319120915Ssam } else { 1320120915Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1321120915Ssam HIFN_PUCNFG_DRAMMASK; 1322120915Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1323120915Ssam } 1324104477Ssam return (0); 1325104477Ssam} 1326104477Ssam 1327104477Ssamstatic void 1328104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1329104477Ssam{ 1330104477Ssam struct hifn_dma *dma = sc->sc_dma; 1331104477Ssam 1332104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1333104477Ssam dma->cmdi = 0; 1334104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1335104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1336104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1337104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1338104477Ssam } 1339104477Ssam *cmdp = dma->cmdi++; 1340104477Ssam dma->cmdk = dma->cmdi; 1341104477Ssam 1342104477Ssam if (dma->srci == HIFN_D_SRC_RSIZE) { 1343104477Ssam dma->srci = 0; 1344104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1345104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1346104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1347104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1348104477Ssam } 1349104477Ssam *srcp = dma->srci++; 1350104477Ssam dma->srck = dma->srci; 1351104477Ssam 1352104477Ssam if (dma->dsti == HIFN_D_DST_RSIZE) { 1353104477Ssam dma->dsti = 0; 1354104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1355104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1356104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1357104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1358104477Ssam } 1359104477Ssam *dstp = dma->dsti++; 1360104477Ssam dma->dstk = dma->dsti; 1361104477Ssam 1362104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1363104477Ssam dma->resi = 0; 1364104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1365104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1366104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1367104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1368104477Ssam } 1369104477Ssam *resp = dma->resi++; 1370104477Ssam dma->resk = dma->resi; 1371104477Ssam} 1372104477Ssam 1373104477Ssamstatic int 1374104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1375104477Ssam{ 1376104477Ssam struct hifn_dma *dma = sc->sc_dma; 1377104477Ssam hifn_base_command_t wc; 1378104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1379104477Ssam int r, cmdi, resi, srci, dsti; 1380104477Ssam 1381104477Ssam wc.masks = htole16(3 << 13); 1382104477Ssam wc.session_num = htole16(addr >> 14); 1383104477Ssam wc.total_source_count = htole16(8); 1384104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1385104477Ssam 1386104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1387104477Ssam 1388104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1389104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1390104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1391104477Ssam 1392104477Ssam /* build write command */ 1393104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1394104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1395104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1396104477Ssam 1397104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1398104477Ssam + offsetof(struct hifn_dma, test_src)); 1399104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1400104477Ssam + offsetof(struct hifn_dma, test_dst)); 1401104477Ssam 1402104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1403104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1404104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1405104477Ssam dma->resr[resi].l = htole32(4 | masks); 1406104477Ssam 1407104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1408104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1409104477Ssam 1410104477Ssam for (r = 10000; r >= 0; r--) { 1411104477Ssam DELAY(10); 1412104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1413104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1414104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1415104477Ssam break; 1416104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1417104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1418104477Ssam } 1419104477Ssam if (r == 0) { 1420104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1421104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1422104477Ssam r = -1; 1423104477Ssam return (-1); 1424104477Ssam } else 1425104477Ssam r = 0; 1426104477Ssam 1427104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1428104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1429104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1430104477Ssam 1431104477Ssam return (r); 1432104477Ssam} 1433104477Ssam 1434104477Ssamstatic int 1435104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1436104477Ssam{ 1437104477Ssam struct hifn_dma *dma = sc->sc_dma; 1438104477Ssam hifn_base_command_t rc; 1439104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1440104477Ssam int r, cmdi, srci, dsti, resi; 1441104477Ssam 1442104477Ssam rc.masks = htole16(2 << 13); 1443104477Ssam rc.session_num = htole16(addr >> 14); 1444104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1445104477Ssam rc.total_dest_count = htole16(8); 1446104477Ssam 1447104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1448104477Ssam 1449104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1450104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1451104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1452104477Ssam 1453104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1454104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1455104477Ssam 1456104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1457104477Ssam offsetof(struct hifn_dma, test_src)); 1458104477Ssam dma->test_src = 0; 1459104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1460104477Ssam offsetof(struct hifn_dma, test_dst)); 1461104477Ssam dma->test_dst = 0; 1462104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1463104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1464104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1465104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1466104477Ssam 1467104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1468104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1469104477Ssam 1470104477Ssam for (r = 10000; r >= 0; r--) { 1471104477Ssam DELAY(10); 1472104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1473104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1474104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1475104477Ssam break; 1476104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1477104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1478104477Ssam } 1479104477Ssam if (r == 0) { 1480104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1481104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1482104477Ssam r = -1; 1483104477Ssam } else { 1484104477Ssam r = 0; 1485104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1486104477Ssam } 1487104477Ssam 1488104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1489104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1490104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1491104477Ssam 1492104477Ssam return (r); 1493104477Ssam} 1494104477Ssam 1495104477Ssam/* 1496104477Ssam * Initialize the descriptor rings. 1497104477Ssam */ 1498104477Ssamstatic void 1499104477Ssamhifn_init_dma(struct hifn_softc *sc) 1500104477Ssam{ 1501104477Ssam struct hifn_dma *dma = sc->sc_dma; 1502104477Ssam int i; 1503104477Ssam 1504104477Ssam hifn_set_retry(sc); 1505104477Ssam 1506104477Ssam /* initialize static pointer values */ 1507104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1508104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1509104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1510104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1511104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1512104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1513104477Ssam 1514104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1515104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1516104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1517104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1518104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1519104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1520104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1521104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1522104477Ssam 1523104477Ssam dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1524104477Ssam dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1525104477Ssam dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1526104477Ssam} 1527104477Ssam 1528104477Ssam/* 1529104477Ssam * Writes out the raw command buffer space. Returns the 1530104477Ssam * command buffer size. 1531104477Ssam */ 1532104477Ssamstatic u_int 1533104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1534104477Ssam{ 1535104477Ssam u_int8_t *buf_pos; 1536104477Ssam hifn_base_command_t *base_cmd; 1537104477Ssam hifn_mac_command_t *mac_cmd; 1538104477Ssam hifn_crypt_command_t *cry_cmd; 1539120915Ssam int using_mac, using_crypt, len, ivlen; 1540104477Ssam u_int32_t dlen, slen; 1541104477Ssam 1542104477Ssam buf_pos = buf; 1543104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1544104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1545104477Ssam 1546104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1547104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1548104477Ssam slen = cmd->src_mapsize; 1549104477Ssam if (cmd->sloplen) 1550104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1551104477Ssam else 1552104477Ssam dlen = cmd->dst_mapsize; 1553104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1554104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1555104477Ssam dlen >>= 16; 1556104477Ssam slen >>= 16; 1557136526Ssam base_cmd->session_num = htole16( 1558104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1559104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1560104477Ssam buf_pos += sizeof(hifn_base_command_t); 1561104477Ssam 1562104477Ssam if (using_mac) { 1563104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1564104477Ssam dlen = cmd->maccrd->crd_len; 1565104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1566104477Ssam dlen >>= 16; 1567104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1568104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1569104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1570104477Ssam mac_cmd->reserved = 0; 1571104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1572104477Ssam } 1573104477Ssam 1574104477Ssam if (using_crypt) { 1575104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1576104477Ssam dlen = cmd->enccrd->crd_len; 1577104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1578104477Ssam dlen >>= 16; 1579104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1580104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1581104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1582104477Ssam cry_cmd->reserved = 0; 1583104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1584104477Ssam } 1585104477Ssam 1586104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1587104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1588104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1589104477Ssam } 1590104477Ssam 1591104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1592104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1593104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1594104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1595104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1596104477Ssam break; 1597104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1598104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1599120915Ssam buf_pos += HIFN_DES_KEY_LENGTH; 1600104477Ssam break; 1601104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1602104477Ssam len = 256; 1603104477Ssam do { 1604104477Ssam int clen; 1605104477Ssam 1606104477Ssam clen = MIN(cmd->cklen, len); 1607104477Ssam bcopy(cmd->ck, buf_pos, clen); 1608104477Ssam len -= clen; 1609104477Ssam buf_pos += clen; 1610104477Ssam } while (len > 0); 1611104477Ssam bzero(buf_pos, 4); 1612104477Ssam buf_pos += 4; 1613104477Ssam break; 1614120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1615120915Ssam /* 1616120915Ssam * AES keys are variable 128, 192 and 1617120915Ssam * 256 bits (16, 24 and 32 bytes). 1618120915Ssam */ 1619120915Ssam bcopy(cmd->ck, buf_pos, cmd->cklen); 1620120915Ssam buf_pos += cmd->cklen; 1621120915Ssam break; 1622104477Ssam } 1623104477Ssam } 1624104477Ssam 1625104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1626120915Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1627120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1628120915Ssam ivlen = HIFN_AES_IV_LENGTH; 1629120915Ssam break; 1630120915Ssam default: 1631120915Ssam ivlen = HIFN_IV_LENGTH; 1632120915Ssam break; 1633120915Ssam } 1634120915Ssam bcopy(cmd->iv, buf_pos, ivlen); 1635120915Ssam buf_pos += ivlen; 1636104477Ssam } 1637104477Ssam 1638104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1639104477Ssam bzero(buf_pos, 8); 1640104477Ssam buf_pos += 8; 1641104477Ssam } 1642104477Ssam 1643104477Ssam return (buf_pos - buf); 1644104477Ssam} 1645104477Ssam 1646104477Ssamstatic int 1647104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1648104477Ssam{ 1649104477Ssam int i; 1650104477Ssam 1651104477Ssam for (i = 0; i < op->nsegs; i++) { 1652104477Ssam if (op->segs[i].ds_addr & 3) 1653104477Ssam return (0); 1654104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1655104477Ssam return (0); 1656104477Ssam } 1657104477Ssam return (1); 1658104477Ssam} 1659104477Ssam 1660104477Ssamstatic int 1661104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1662104477Ssam{ 1663104477Ssam struct hifn_dma *dma = sc->sc_dma; 1664104477Ssam struct hifn_operand *dst = &cmd->dst; 1665104477Ssam u_int32_t p, l; 1666104477Ssam int idx, used = 0, i; 1667104477Ssam 1668104477Ssam idx = dma->dsti; 1669104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1670104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1671104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1672104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1673104477Ssam HIFN_DSTR_SYNC(sc, idx, 1674104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1675104477Ssam used++; 1676104477Ssam 1677104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1678104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1679104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1680104477Ssam HIFN_DSTR_SYNC(sc, idx, 1681104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1682104477Ssam idx = 0; 1683104477Ssam } 1684104477Ssam } 1685104477Ssam 1686104477Ssam if (cmd->sloplen == 0) { 1687104477Ssam p = dst->segs[i].ds_addr; 1688104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1689104477Ssam dst->segs[i].ds_len; 1690104477Ssam } else { 1691104477Ssam p = sc->sc_dma_physaddr + 1692104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1693104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1694104477Ssam sizeof(u_int32_t); 1695104477Ssam 1696104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1697104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1698104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1699104477Ssam HIFN_D_MASKDONEIRQ | 1700104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1701104477Ssam HIFN_DSTR_SYNC(sc, idx, 1702104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1703104477Ssam used++; 1704104477Ssam 1705104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1706104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1707104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1708104477Ssam HIFN_DSTR_SYNC(sc, idx, 1709104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1710104477Ssam idx = 0; 1711104477Ssam } 1712104477Ssam } 1713104477Ssam } 1714104477Ssam dma->dstr[idx].p = htole32(p); 1715104477Ssam dma->dstr[idx].l = htole32(l); 1716104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1717104477Ssam used++; 1718104477Ssam 1719104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1720104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1721104477Ssam HIFN_D_MASKDONEIRQ); 1722104477Ssam HIFN_DSTR_SYNC(sc, idx, 1723104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1724104477Ssam idx = 0; 1725104477Ssam } 1726104477Ssam 1727104477Ssam dma->dsti = idx; 1728104477Ssam dma->dstu += used; 1729104477Ssam return (idx); 1730104477Ssam} 1731104477Ssam 1732104477Ssamstatic int 1733104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1734104477Ssam{ 1735104477Ssam struct hifn_dma *dma = sc->sc_dma; 1736104477Ssam struct hifn_operand *src = &cmd->src; 1737104477Ssam int idx, i; 1738104477Ssam u_int32_t last = 0; 1739104477Ssam 1740104477Ssam idx = dma->srci; 1741104477Ssam for (i = 0; i < src->nsegs; i++) { 1742104477Ssam if (i == src->nsegs - 1) 1743104477Ssam last = HIFN_D_LAST; 1744104477Ssam 1745104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1746104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1747104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1748104477Ssam HIFN_SRCR_SYNC(sc, idx, 1749104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1750104477Ssam 1751104477Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1752104477Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1753104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1754104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1755104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1756104477Ssam idx = 0; 1757104477Ssam } 1758104477Ssam } 1759104477Ssam dma->srci = idx; 1760104477Ssam dma->srcu += src->nsegs; 1761104477Ssam return (idx); 1762104477Ssam} 1763104477Ssam 1764104477Ssamstatic void 1765104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1766104477Ssam{ 1767104477Ssam struct hifn_operand *op = arg; 1768104477Ssam 1769104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1770104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1771104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1772104477Ssam op->mapsize = mapsize; 1773104477Ssam op->nsegs = nsegs; 1774104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1775104477Ssam} 1776104477Ssam 1777104477Ssamstatic int 1778104477Ssamhifn_crypto( 1779104477Ssam struct hifn_softc *sc, 1780104477Ssam struct hifn_command *cmd, 1781104477Ssam struct cryptop *crp, 1782104477Ssam int hint) 1783104477Ssam{ 1784104477Ssam struct hifn_dma *dma = sc->sc_dma; 1785104477Ssam u_int32_t cmdlen; 1786104477Ssam int cmdi, resi, err = 0; 1787104477Ssam 1788104477Ssam /* 1789104477Ssam * need 1 cmd, and 1 res 1790104477Ssam * 1791104477Ssam * NB: check this first since it's easy. 1792104477Ssam */ 1793115748Ssam HIFN_LOCK(sc); 1794104477Ssam if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1795104477Ssam (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1796104477Ssam#ifdef HIFN_DEBUG 1797104477Ssam if (hifn_debug) { 1798104477Ssam device_printf(sc->sc_dev, 1799104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1800104477Ssam dma->cmdu, dma->resu); 1801104477Ssam } 1802104477Ssam#endif 1803104477Ssam hifnstats.hst_nomem_cr++; 1804115748Ssam HIFN_UNLOCK(sc); 1805104477Ssam return (ERESTART); 1806104477Ssam } 1807104477Ssam 1808104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1809104477Ssam hifnstats.hst_nomem_map++; 1810115748Ssam HIFN_UNLOCK(sc); 1811104477Ssam return (ENOMEM); 1812104477Ssam } 1813104477Ssam 1814104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1815104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1816104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1817104477Ssam hifnstats.hst_nomem_load++; 1818104477Ssam err = ENOMEM; 1819104477Ssam goto err_srcmap1; 1820104477Ssam } 1821104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1822104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1823104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1824104477Ssam hifnstats.hst_nomem_load++; 1825104477Ssam err = ENOMEM; 1826104477Ssam goto err_srcmap1; 1827104477Ssam } 1828104477Ssam } else { 1829104477Ssam err = EINVAL; 1830104477Ssam goto err_srcmap1; 1831104477Ssam } 1832104477Ssam 1833104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1834104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1835104477Ssam cmd->dst = cmd->src; 1836104477Ssam } else { 1837104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1838104477Ssam err = EINVAL; 1839104477Ssam goto err_srcmap; 1840104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1841104477Ssam int totlen, len; 1842104477Ssam struct mbuf *m, *m0, *mlast; 1843104477Ssam 1844104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1845104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1846104477Ssam hifnstats.hst_unaligned++; 1847104477Ssam /* 1848104477Ssam * Source is not aligned on a longword boundary. 1849104477Ssam * Copy the data to insure alignment. If we fail 1850104477Ssam * to allocate mbufs or clusters while doing this 1851104477Ssam * we return ERESTART so the operation is requeued 1852104477Ssam * at the crypto later, but only if there are 1853104477Ssam * ops already posted to the hardware; otherwise we 1854104477Ssam * have no guarantee that we'll be re-entered. 1855104477Ssam */ 1856104477Ssam totlen = cmd->src_mapsize; 1857104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1858104477Ssam len = MHLEN; 1859111119Simp MGETHDR(m0, M_DONTWAIT, MT_DATA); 1860111119Simp if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1861108466Ssam m_free(m0); 1862108466Ssam m0 = NULL; 1863108466Ssam } 1864104477Ssam } else { 1865104477Ssam len = MLEN; 1866111119Simp MGET(m0, M_DONTWAIT, MT_DATA); 1867104477Ssam } 1868104477Ssam if (m0 == NULL) { 1869104477Ssam hifnstats.hst_nomem_mbuf++; 1870104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1871104477Ssam goto err_srcmap; 1872104477Ssam } 1873104477Ssam if (totlen >= MINCLSIZE) { 1874111119Simp MCLGET(m0, M_DONTWAIT); 1875104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1876104477Ssam hifnstats.hst_nomem_mcl++; 1877104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1878104477Ssam m_freem(m0); 1879104477Ssam goto err_srcmap; 1880104477Ssam } 1881104477Ssam len = MCLBYTES; 1882104477Ssam } 1883104477Ssam totlen -= len; 1884104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1885104477Ssam mlast = m0; 1886104477Ssam 1887104477Ssam while (totlen > 0) { 1888111119Simp MGET(m, M_DONTWAIT, MT_DATA); 1889104477Ssam if (m == NULL) { 1890104477Ssam hifnstats.hst_nomem_mbuf++; 1891104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1892104477Ssam m_freem(m0); 1893104477Ssam goto err_srcmap; 1894104477Ssam } 1895104477Ssam len = MLEN; 1896104477Ssam if (totlen >= MINCLSIZE) { 1897111119Simp MCLGET(m, M_DONTWAIT); 1898104477Ssam if ((m->m_flags & M_EXT) == 0) { 1899104477Ssam hifnstats.hst_nomem_mcl++; 1900104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1901104477Ssam mlast->m_next = m; 1902104477Ssam m_freem(m0); 1903104477Ssam goto err_srcmap; 1904104477Ssam } 1905104477Ssam len = MCLBYTES; 1906104477Ssam } 1907104477Ssam 1908104477Ssam m->m_len = len; 1909104477Ssam m0->m_pkthdr.len += len; 1910104477Ssam totlen -= len; 1911104477Ssam 1912104477Ssam mlast->m_next = m; 1913104477Ssam mlast = m; 1914104477Ssam } 1915104477Ssam cmd->dst_m = m0; 1916104477Ssam } 1917104477Ssam } 1918104477Ssam 1919104477Ssam if (cmd->dst_map == NULL) { 1920104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1921104477Ssam hifnstats.hst_nomem_map++; 1922104477Ssam err = ENOMEM; 1923104477Ssam goto err_srcmap; 1924104477Ssam } 1925104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1926104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1927104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1928104477Ssam hifnstats.hst_nomem_map++; 1929104477Ssam err = ENOMEM; 1930104477Ssam goto err_dstmap1; 1931104477Ssam } 1932104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1933104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1934104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1935104477Ssam hifnstats.hst_nomem_load++; 1936104477Ssam err = ENOMEM; 1937104477Ssam goto err_dstmap1; 1938104477Ssam } 1939104477Ssam } 1940104477Ssam } 1941104477Ssam 1942104477Ssam#ifdef HIFN_DEBUG 1943104477Ssam if (hifn_debug) { 1944104477Ssam device_printf(sc->sc_dev, 1945104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1946104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1947104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1948104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1949104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1950104477Ssam } 1951104477Ssam#endif 1952104477Ssam 1953104477Ssam if (cmd->src_map == cmd->dst_map) { 1954104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1955104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1956104477Ssam } else { 1957104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1958104477Ssam BUS_DMASYNC_PREWRITE); 1959104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1960104477Ssam BUS_DMASYNC_PREREAD); 1961104477Ssam } 1962104477Ssam 1963104477Ssam /* 1964104477Ssam * need N src, and N dst 1965104477Ssam */ 1966104477Ssam if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1967104477Ssam (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1968104477Ssam#ifdef HIFN_DEBUG 1969104477Ssam if (hifn_debug) { 1970104477Ssam device_printf(sc->sc_dev, 1971104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1972104477Ssam dma->srcu, cmd->src_nsegs, 1973104477Ssam dma->dstu, cmd->dst_nsegs); 1974104477Ssam } 1975104477Ssam#endif 1976104477Ssam hifnstats.hst_nomem_sd++; 1977104477Ssam err = ERESTART; 1978104477Ssam goto err_dstmap; 1979104477Ssam } 1980104477Ssam 1981104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1982104477Ssam dma->cmdi = 0; 1983104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1984104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1985104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1986104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1987104477Ssam } 1988104477Ssam cmdi = dma->cmdi++; 1989104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1990104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1991104477Ssam 1992104477Ssam /* .p for command/result already set */ 1993104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1994104477Ssam HIFN_D_MASKDONEIRQ); 1995104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 1996104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1997104477Ssam dma->cmdu++; 1998104477Ssam if (sc->sc_c_busy == 0) { 1999104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 2000104477Ssam sc->sc_c_busy = 1; 2001104477Ssam } 2002104477Ssam 2003104477Ssam /* 2004104477Ssam * We don't worry about missing an interrupt (which a "command wait" 2005104477Ssam * interrupt salvages us from), unless there is more than one command 2006104477Ssam * in the queue. 2007104477Ssam */ 2008104477Ssam if (dma->cmdu > 1) { 2009104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 2010104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2011104477Ssam } 2012104477Ssam 2013104477Ssam hifnstats.hst_ipackets++; 2014104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 2015104477Ssam 2016104477Ssam hifn_dmamap_load_src(sc, cmd); 2017104477Ssam if (sc->sc_s_busy == 0) { 2018104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 2019104477Ssam sc->sc_s_busy = 1; 2020104477Ssam } 2021104477Ssam 2022104477Ssam /* 2023104477Ssam * Unlike other descriptors, we don't mask done interrupt from 2024104477Ssam * result descriptor. 2025104477Ssam */ 2026104477Ssam#ifdef HIFN_DEBUG 2027104477Ssam if (hifn_debug) 2028104477Ssam printf("load res\n"); 2029104477Ssam#endif 2030104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 2031104477Ssam dma->resi = 0; 2032104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 2033104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2034104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 2035104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2036104477Ssam } 2037104477Ssam resi = dma->resi++; 2038104477Ssam KASSERT(dma->hifn_commands[resi] == NULL, 2039104477Ssam ("hifn_crypto: command slot %u busy", resi)); 2040104477Ssam dma->hifn_commands[resi] = cmd; 2041104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 2042104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 2043104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2044104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 2045104477Ssam sc->sc_curbatch++; 2046104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 2047104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 2048104477Ssam hifnstats.hst_totbatch++; 2049104477Ssam } else { 2050104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2051104477Ssam HIFN_D_VALID | HIFN_D_LAST); 2052104477Ssam sc->sc_curbatch = 0; 2053104477Ssam } 2054104477Ssam HIFN_RESR_SYNC(sc, resi, 2055104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2056104477Ssam dma->resu++; 2057104477Ssam if (sc->sc_r_busy == 0) { 2058104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 2059104477Ssam sc->sc_r_busy = 1; 2060104477Ssam } 2061104477Ssam 2062104477Ssam if (cmd->sloplen) 2063104477Ssam cmd->slopidx = resi; 2064104477Ssam 2065104477Ssam hifn_dmamap_load_dst(sc, cmd); 2066104477Ssam 2067104477Ssam if (sc->sc_d_busy == 0) { 2068104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 2069104477Ssam sc->sc_d_busy = 1; 2070104477Ssam } 2071104477Ssam 2072104477Ssam#ifdef HIFN_DEBUG 2073104477Ssam if (hifn_debug) { 2074104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 2075104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 2076104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 2077104477Ssam } 2078104477Ssam#endif 2079104477Ssam 2080104477Ssam sc->sc_active = 5; 2081115748Ssam HIFN_UNLOCK(sc); 2082104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 2083104477Ssam return (err); /* success */ 2084104477Ssam 2085104477Ssamerr_dstmap: 2086104477Ssam if (cmd->src_map != cmd->dst_map) 2087104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2088104477Ssamerr_dstmap1: 2089104477Ssam if (cmd->src_map != cmd->dst_map) 2090104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2091104477Ssamerr_srcmap: 2092104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2093104477Ssam if (cmd->src_m != cmd->dst_m) 2094104477Ssam m_freem(cmd->dst_m); 2095104477Ssam } 2096104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2097104477Ssamerr_srcmap1: 2098104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2099115748Ssam HIFN_UNLOCK(sc); 2100104477Ssam return (err); 2101104477Ssam} 2102104477Ssam 2103104477Ssamstatic void 2104104477Ssamhifn_tick(void* vsc) 2105104477Ssam{ 2106104477Ssam struct hifn_softc *sc = vsc; 2107104477Ssam 2108104477Ssam HIFN_LOCK(sc); 2109104477Ssam if (sc->sc_active == 0) { 2110104477Ssam struct hifn_dma *dma = sc->sc_dma; 2111104477Ssam u_int32_t r = 0; 2112104477Ssam 2113104477Ssam if (dma->cmdu == 0 && sc->sc_c_busy) { 2114104477Ssam sc->sc_c_busy = 0; 2115104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 2116104477Ssam } 2117104477Ssam if (dma->srcu == 0 && sc->sc_s_busy) { 2118104477Ssam sc->sc_s_busy = 0; 2119104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 2120104477Ssam } 2121104477Ssam if (dma->dstu == 0 && sc->sc_d_busy) { 2122104477Ssam sc->sc_d_busy = 0; 2123104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 2124104477Ssam } 2125104477Ssam if (dma->resu == 0 && sc->sc_r_busy) { 2126104477Ssam sc->sc_r_busy = 0; 2127104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 2128104477Ssam } 2129104477Ssam if (r) 2130104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2131104477Ssam } else 2132104477Ssam sc->sc_active--; 2133104477Ssam HIFN_UNLOCK(sc); 2134104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2135104477Ssam} 2136104477Ssam 2137104477Ssamstatic void 2138104477Ssamhifn_intr(void *arg) 2139104477Ssam{ 2140104477Ssam struct hifn_softc *sc = arg; 2141104477Ssam struct hifn_dma *dma; 2142104477Ssam u_int32_t dmacsr, restart; 2143104477Ssam int i, u; 2144104477Ssam 2145115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2146115748Ssam 2147115748Ssam /* Nothing in the DMA unit interrupted */ 2148115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 2149115748Ssam return; 2150115748Ssam 2151104477Ssam HIFN_LOCK(sc); 2152115748Ssam 2153104477Ssam dma = sc->sc_dma; 2154104477Ssam 2155104477Ssam#ifdef HIFN_DEBUG 2156104477Ssam if (hifn_debug) { 2157104477Ssam device_printf(sc->sc_dev, 2158104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2159104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2160104477Ssam dma->cmdi, dma->srci, dma->dsti, dma->resi, 2161104477Ssam dma->cmdk, dma->srck, dma->dstk, dma->resk, 2162104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2163104477Ssam } 2164104477Ssam#endif 2165104477Ssam 2166104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2167104477Ssam 2168104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2169104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2170104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2171104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2172104477Ssam 2173104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2174104477Ssam if (restart) 2175104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2176104477Ssam 2177104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2178104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2179104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2180104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2181104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2182104477Ssam } 2183104477Ssam 2184104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2185104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2186104477Ssam if (restart) { 2187104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2188104477Ssam hifnstats.hst_abort++; 2189104477Ssam hifn_abort(sc); 2190104477Ssam HIFN_UNLOCK(sc); 2191104477Ssam return; 2192104477Ssam } 2193104477Ssam 2194104477Ssam if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2195104477Ssam /* 2196104477Ssam * If no slots to process and we receive a "waiting on 2197104477Ssam * command" interrupt, we disable the "waiting on command" 2198104477Ssam * (by clearing it). 2199104477Ssam */ 2200104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2201104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2202104477Ssam } 2203104477Ssam 2204104477Ssam /* clear the rings */ 2205104477Ssam i = dma->resk; u = dma->resu; 2206104477Ssam while (u != 0) { 2207104477Ssam HIFN_RESR_SYNC(sc, i, 2208104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2209104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2210104477Ssam HIFN_RESR_SYNC(sc, i, 2211104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2212104477Ssam break; 2213104477Ssam } 2214104477Ssam 2215104477Ssam if (i != HIFN_D_RES_RSIZE) { 2216104477Ssam struct hifn_command *cmd; 2217104477Ssam u_int8_t *macbuf = NULL; 2218104477Ssam 2219104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2220104477Ssam cmd = dma->hifn_commands[i]; 2221104477Ssam KASSERT(cmd != NULL, 2222104477Ssam ("hifn_intr: null command slot %u", i)); 2223104477Ssam dma->hifn_commands[i] = NULL; 2224104477Ssam 2225104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2226104477Ssam macbuf = dma->result_bufs[i]; 2227104477Ssam macbuf += 12; 2228104477Ssam } 2229104477Ssam 2230104477Ssam hifn_callback(sc, cmd, macbuf); 2231104477Ssam hifnstats.hst_opackets++; 2232104477Ssam u--; 2233104477Ssam } 2234104477Ssam 2235104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2236104477Ssam i = 0; 2237104477Ssam } 2238104477Ssam dma->resk = i; dma->resu = u; 2239104477Ssam 2240104477Ssam i = dma->srck; u = dma->srcu; 2241104477Ssam while (u != 0) { 2242104477Ssam if (i == HIFN_D_SRC_RSIZE) 2243104477Ssam i = 0; 2244104477Ssam HIFN_SRCR_SYNC(sc, i, 2245104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2246104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2247104477Ssam HIFN_SRCR_SYNC(sc, i, 2248104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2249104477Ssam break; 2250104477Ssam } 2251104477Ssam i++, u--; 2252104477Ssam } 2253104477Ssam dma->srck = i; dma->srcu = u; 2254104477Ssam 2255104477Ssam i = dma->cmdk; u = dma->cmdu; 2256104477Ssam while (u != 0) { 2257104477Ssam HIFN_CMDR_SYNC(sc, i, 2258104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2259104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2260104477Ssam HIFN_CMDR_SYNC(sc, i, 2261104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2262104477Ssam break; 2263104477Ssam } 2264104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2265104477Ssam u--; 2266104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2267104477Ssam } 2268104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2269104477Ssam i = 0; 2270104477Ssam } 2271104477Ssam dma->cmdk = i; dma->cmdu = u; 2272104477Ssam 2273115748Ssam HIFN_UNLOCK(sc); 2274115748Ssam 2275104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2276104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2277104477Ssam#ifdef HIFN_DEBUG 2278104477Ssam if (hifn_debug) 2279104477Ssam device_printf(sc->sc_dev, 2280104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2281104477Ssam sc->sc_needwakeup, 2282104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2283104477Ssam#endif 2284104477Ssam sc->sc_needwakeup &= ~wakeup; 2285104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2286104477Ssam } 2287104477Ssam} 2288104477Ssam 2289104477Ssam/* 2290104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2291104477Ssam * contains our registration id, and should contain an encoded session 2292104477Ssam * id on successful allocation. 2293104477Ssam */ 2294104477Ssamstatic int 2295104477Ssamhifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2296104477Ssam{ 2297104477Ssam struct cryptoini *c; 2298104477Ssam struct hifn_softc *sc = arg; 2299136526Ssam int mac = 0, cry = 0, sesn; 2300136532Ssam struct hifn_session *ses = NULL; 2301104477Ssam 2302104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2303104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2304104477Ssam return (EINVAL); 2305104477Ssam 2306136526Ssam if (sc->sc_sessions == NULL) { 2307136526Ssam ses = sc->sc_sessions = (struct hifn_session *)malloc( 2308136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2309136526Ssam if (ses == NULL) 2310136526Ssam return (ENOMEM); 2311136526Ssam sesn = 0; 2312136526Ssam sc->sc_nsessions = 1; 2313136526Ssam } else { 2314136526Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 2315136526Ssam if (!sc->sc_sessions[sesn].hs_used) { 2316136526Ssam ses = &sc->sc_sessions[sesn]; 2317136526Ssam break; 2318136526Ssam } 2319136526Ssam } 2320104477Ssam 2321136526Ssam if (ses == NULL) { 2322136526Ssam sesn = sc->sc_nsessions; 2323136526Ssam ses = (struct hifn_session *)malloc((sesn + 1) * 2324136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2325136526Ssam if (ses == NULL) 2326136526Ssam return (ENOMEM); 2327136526Ssam bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 2328136526Ssam bzero(sc->sc_sessions, sesn * sizeof(*ses)); 2329136526Ssam free(sc->sc_sessions, M_DEVBUF); 2330136526Ssam sc->sc_sessions = ses; 2331136526Ssam ses = &sc->sc_sessions[sesn]; 2332136526Ssam sc->sc_nsessions++; 2333136526Ssam } 2334136526Ssam } 2335136526Ssam bzero(ses, sizeof(*ses)); 2336136526Ssam ses->hs_used = 1; 2337136526Ssam 2338104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2339104477Ssam switch (c->cri_alg) { 2340104477Ssam case CRYPTO_MD5: 2341104477Ssam case CRYPTO_SHA1: 2342104477Ssam case CRYPTO_MD5_HMAC: 2343104477Ssam case CRYPTO_SHA1_HMAC: 2344104477Ssam if (mac) 2345104477Ssam return (EINVAL); 2346104477Ssam mac = 1; 2347158705Spjd ses->hs_mlen = c->cri_mlen; 2348158705Spjd if (ses->hs_mlen == 0) { 2349158705Spjd switch (c->cri_alg) { 2350158705Spjd case CRYPTO_MD5: 2351158705Spjd case CRYPTO_MD5_HMAC: 2352158705Spjd ses->hs_mlen = 16; 2353158705Spjd break; 2354158705Spjd case CRYPTO_SHA1: 2355158705Spjd case CRYPTO_SHA1_HMAC: 2356158705Spjd ses->hs_mlen = 20; 2357158705Spjd break; 2358158705Spjd } 2359158705Spjd } 2360104477Ssam break; 2361104477Ssam case CRYPTO_DES_CBC: 2362104477Ssam case CRYPTO_3DES_CBC: 2363120915Ssam case CRYPTO_AES_CBC: 2364104477Ssam /* XXX this may read fewer, does it matter? */ 2365136526Ssam read_random(ses->hs_iv, 2366120915Ssam c->cri_alg == CRYPTO_AES_CBC ? 2367120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2368104477Ssam /*FALLTHROUGH*/ 2369104477Ssam case CRYPTO_ARC4: 2370104477Ssam if (cry) 2371104477Ssam return (EINVAL); 2372104477Ssam cry = 1; 2373104477Ssam break; 2374104477Ssam default: 2375104477Ssam return (EINVAL); 2376104477Ssam } 2377104477Ssam } 2378104477Ssam if (mac == 0 && cry == 0) 2379104477Ssam return (EINVAL); 2380104477Ssam 2381136526Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); 2382104477Ssam 2383104477Ssam return (0); 2384104477Ssam} 2385104477Ssam 2386104477Ssam/* 2387104477Ssam * Deallocate a session. 2388104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2389104477Ssam * XXX to blow away any keys already stored there. 2390104477Ssam */ 2391104477Ssamstatic int 2392104477Ssamhifn_freesession(void *arg, u_int64_t tid) 2393104477Ssam{ 2394104477Ssam struct hifn_softc *sc = arg; 2395104477Ssam int session; 2396116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2397104477Ssam 2398104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2399104477Ssam if (sc == NULL) 2400104477Ssam return (EINVAL); 2401104477Ssam 2402104477Ssam session = HIFN_SESSION(sid); 2403136526Ssam if (session >= sc->sc_nsessions) 2404104477Ssam return (EINVAL); 2405104477Ssam 2406104477Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2407104477Ssam return (0); 2408104477Ssam} 2409104477Ssam 2410104477Ssamstatic int 2411104477Ssamhifn_process(void *arg, struct cryptop *crp, int hint) 2412104477Ssam{ 2413104477Ssam struct hifn_softc *sc = arg; 2414104477Ssam struct hifn_command *cmd = NULL; 2415120915Ssam int session, err, ivlen; 2416104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2417104477Ssam 2418104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2419104477Ssam hifnstats.hst_invalid++; 2420104477Ssam return (EINVAL); 2421104477Ssam } 2422104477Ssam session = HIFN_SESSION(crp->crp_sid); 2423104477Ssam 2424136526Ssam if (sc == NULL || session >= sc->sc_nsessions) { 2425104477Ssam err = EINVAL; 2426104477Ssam goto errout; 2427104477Ssam } 2428104477Ssam 2429104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2430104477Ssam if (cmd == NULL) { 2431104477Ssam hifnstats.hst_nomem++; 2432104477Ssam err = ENOMEM; 2433104477Ssam goto errout; 2434104477Ssam } 2435104477Ssam 2436104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2437104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2438104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2439104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2440104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2441104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2442104477Ssam } else { 2443104477Ssam err = EINVAL; 2444104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2445104477Ssam } 2446104477Ssam 2447104477Ssam crd1 = crp->crp_desc; 2448104477Ssam if (crd1 == NULL) { 2449104477Ssam err = EINVAL; 2450104477Ssam goto errout; 2451104477Ssam } 2452104477Ssam crd2 = crd1->crd_next; 2453104477Ssam 2454104477Ssam if (crd2 == NULL) { 2455104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2456104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2457104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2458104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2459104477Ssam maccrd = crd1; 2460104477Ssam enccrd = NULL; 2461104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2462104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2463120915Ssam crd1->crd_alg == CRYPTO_AES_CBC || 2464104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2465104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2466104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2467104477Ssam maccrd = NULL; 2468104477Ssam enccrd = crd1; 2469104477Ssam } else { 2470104477Ssam err = EINVAL; 2471104477Ssam goto errout; 2472104477Ssam } 2473104477Ssam } else { 2474104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2475104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2476104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2477104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2478104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2479104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2480120915Ssam crd2->crd_alg == CRYPTO_AES_CBC || 2481104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2482104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2483104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2484104477Ssam maccrd = crd1; 2485104477Ssam enccrd = crd2; 2486104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2487104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2488120915Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2489120915Ssam crd1->crd_alg == CRYPTO_AES_CBC) && 2490104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2491104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2492104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2493104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2494104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2495104477Ssam enccrd = crd1; 2496104477Ssam maccrd = crd2; 2497104477Ssam } else { 2498104477Ssam /* 2499104477Ssam * We cannot order the 7751 as requested 2500104477Ssam */ 2501104477Ssam err = EINVAL; 2502104477Ssam goto errout; 2503104477Ssam } 2504104477Ssam } 2505104477Ssam 2506104477Ssam if (enccrd) { 2507104477Ssam cmd->enccrd = enccrd; 2508104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2509104477Ssam switch (enccrd->crd_alg) { 2510104477Ssam case CRYPTO_ARC4: 2511104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2512104477Ssam break; 2513104477Ssam case CRYPTO_DES_CBC: 2514104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2515104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2516104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2517104477Ssam break; 2518104477Ssam case CRYPTO_3DES_CBC: 2519104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2520104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2521104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2522104477Ssam break; 2523120915Ssam case CRYPTO_AES_CBC: 2524120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2525120915Ssam HIFN_CRYPT_CMD_MODE_CBC | 2526120915Ssam HIFN_CRYPT_CMD_NEW_IV; 2527120915Ssam break; 2528104477Ssam default: 2529104477Ssam err = EINVAL; 2530104477Ssam goto errout; 2531104477Ssam } 2532104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2533120915Ssam ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2534120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2535104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2536104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2537120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2538104477Ssam else 2539104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2540120915Ssam cmd->iv, ivlen); 2541104477Ssam 2542104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2543104477Ssam == 0) { 2544104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2545104477Ssam m_copyback(cmd->src_m, 2546104477Ssam enccrd->crd_inject, 2547120915Ssam ivlen, cmd->iv); 2548104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2549104477Ssam cuio_copyback(cmd->src_io, 2550104477Ssam enccrd->crd_inject, 2551120915Ssam ivlen, cmd->iv); 2552104477Ssam } 2553104477Ssam } else { 2554104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2555120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2556104477Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 2557104477Ssam m_copydata(cmd->src_m, 2558120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2559104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2560104477Ssam cuio_copydata(cmd->src_io, 2561120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2562104477Ssam } 2563104477Ssam } 2564104477Ssam 2565125330Sphk if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2566125330Sphk cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2567104477Ssam cmd->ck = enccrd->crd_key; 2568104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2569136526Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2570104477Ssam 2571120915Ssam /* 2572120915Ssam * Need to specify the size for the AES key in the masks. 2573120915Ssam */ 2574120915Ssam if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2575120915Ssam HIFN_CRYPT_CMD_ALG_AES) { 2576120915Ssam switch (cmd->cklen) { 2577120915Ssam case 16: 2578120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2579120915Ssam break; 2580120915Ssam case 24: 2581120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2582120915Ssam break; 2583120915Ssam case 32: 2584120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2585120915Ssam break; 2586120915Ssam default: 2587120915Ssam err = EINVAL; 2588120915Ssam goto errout; 2589120915Ssam } 2590120915Ssam } 2591104477Ssam } 2592104477Ssam 2593104477Ssam if (maccrd) { 2594104477Ssam cmd->maccrd = maccrd; 2595104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2596104477Ssam 2597104477Ssam switch (maccrd->crd_alg) { 2598104477Ssam case CRYPTO_MD5: 2599104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2600104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2601104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2602104477Ssam break; 2603104477Ssam case CRYPTO_MD5_HMAC: 2604104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2605104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2606104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2607104477Ssam break; 2608104477Ssam case CRYPTO_SHA1: 2609104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2610104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2611104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2612104477Ssam break; 2613104477Ssam case CRYPTO_SHA1_HMAC: 2614104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2615104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2616104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2617104477Ssam break; 2618104477Ssam } 2619104477Ssam 2620136526Ssam if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2621136526Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) { 2622104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2623104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2624104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2625104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2626104477Ssam } 2627104477Ssam } 2628104477Ssam 2629104477Ssam cmd->crp = crp; 2630104477Ssam cmd->session_num = session; 2631104477Ssam cmd->softc = sc; 2632104477Ssam 2633104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2634104477Ssam if (!err) { 2635104477Ssam return 0; 2636104477Ssam } else if (err == ERESTART) { 2637104477Ssam /* 2638104477Ssam * There weren't enough resources to dispatch the request 2639104477Ssam * to the part. Notify the caller so they'll requeue this 2640104477Ssam * request and resubmit it again soon. 2641104477Ssam */ 2642104477Ssam#ifdef HIFN_DEBUG 2643104477Ssam if (hifn_debug) 2644104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2645104477Ssam#endif 2646104477Ssam free(cmd, M_DEVBUF); 2647104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2648104477Ssam return (err); 2649104477Ssam } 2650104477Ssam 2651104477Ssamerrout: 2652104477Ssam if (cmd != NULL) 2653104477Ssam free(cmd, M_DEVBUF); 2654104477Ssam if (err == EINVAL) 2655104477Ssam hifnstats.hst_invalid++; 2656104477Ssam else 2657104477Ssam hifnstats.hst_nomem++; 2658104477Ssam crp->crp_etype = err; 2659104477Ssam crypto_done(crp); 2660104477Ssam return (err); 2661104477Ssam} 2662104477Ssam 2663104477Ssamstatic void 2664104477Ssamhifn_abort(struct hifn_softc *sc) 2665104477Ssam{ 2666104477Ssam struct hifn_dma *dma = sc->sc_dma; 2667104477Ssam struct hifn_command *cmd; 2668104477Ssam struct cryptop *crp; 2669104477Ssam int i, u; 2670104477Ssam 2671104477Ssam i = dma->resk; u = dma->resu; 2672104477Ssam while (u != 0) { 2673104477Ssam cmd = dma->hifn_commands[i]; 2674104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2675104477Ssam dma->hifn_commands[i] = NULL; 2676104477Ssam crp = cmd->crp; 2677104477Ssam 2678104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2679104477Ssam /* Salvage what we can. */ 2680104477Ssam u_int8_t *macbuf; 2681104477Ssam 2682104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2683104477Ssam macbuf = dma->result_bufs[i]; 2684104477Ssam macbuf += 12; 2685104477Ssam } else 2686104477Ssam macbuf = NULL; 2687104477Ssam hifnstats.hst_opackets++; 2688104477Ssam hifn_callback(sc, cmd, macbuf); 2689104477Ssam } else { 2690104477Ssam if (cmd->src_map == cmd->dst_map) { 2691104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2692104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2693104477Ssam } else { 2694104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2695104477Ssam BUS_DMASYNC_POSTWRITE); 2696104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2697104477Ssam BUS_DMASYNC_POSTREAD); 2698104477Ssam } 2699104477Ssam 2700104477Ssam if (cmd->src_m != cmd->dst_m) { 2701104477Ssam m_freem(cmd->src_m); 2702104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2703104477Ssam } 2704104477Ssam 2705104477Ssam /* non-shared buffers cannot be restarted */ 2706104477Ssam if (cmd->src_map != cmd->dst_map) { 2707104477Ssam /* 2708104477Ssam * XXX should be EAGAIN, delayed until 2709104477Ssam * after the reset. 2710104477Ssam */ 2711104477Ssam crp->crp_etype = ENOMEM; 2712104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2713104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2714104477Ssam } else 2715104477Ssam crp->crp_etype = ENOMEM; 2716104477Ssam 2717104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2718104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2719104477Ssam 2720104477Ssam free(cmd, M_DEVBUF); 2721104477Ssam if (crp->crp_etype != EAGAIN) 2722104477Ssam crypto_done(crp); 2723104477Ssam } 2724104477Ssam 2725104477Ssam if (++i == HIFN_D_RES_RSIZE) 2726104477Ssam i = 0; 2727104477Ssam u--; 2728104477Ssam } 2729104477Ssam dma->resk = i; dma->resu = u; 2730104477Ssam 2731104477Ssam hifn_reset_board(sc, 1); 2732104477Ssam hifn_init_dma(sc); 2733104477Ssam hifn_init_pci_registers(sc); 2734104477Ssam} 2735104477Ssam 2736104477Ssamstatic void 2737104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2738104477Ssam{ 2739104477Ssam struct hifn_dma *dma = sc->sc_dma; 2740104477Ssam struct cryptop *crp = cmd->crp; 2741104477Ssam struct cryptodesc *crd; 2742104477Ssam struct mbuf *m; 2743120915Ssam int totlen, i, u, ivlen; 2744104477Ssam 2745104477Ssam if (cmd->src_map == cmd->dst_map) { 2746104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2747104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2748104477Ssam } else { 2749104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2750104477Ssam BUS_DMASYNC_POSTWRITE); 2751104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2752104477Ssam BUS_DMASYNC_POSTREAD); 2753104477Ssam } 2754104477Ssam 2755104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2756104477Ssam if (cmd->src_m != cmd->dst_m) { 2757104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2758104477Ssam totlen = cmd->src_mapsize; 2759104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2760104477Ssam if (totlen < m->m_len) { 2761104477Ssam m->m_len = totlen; 2762104477Ssam totlen = 0; 2763104477Ssam } else 2764104477Ssam totlen -= m->m_len; 2765104477Ssam } 2766104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2767104477Ssam m_freem(cmd->src_m); 2768104477Ssam } 2769104477Ssam } 2770104477Ssam 2771104477Ssam if (cmd->sloplen != 0) { 2772104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2773104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2774104477Ssam cmd->src_mapsize - cmd->sloplen, 2775104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2776104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2777104477Ssam cuio_copyback((struct uio *)crp->crp_buf, 2778104477Ssam cmd->src_mapsize - cmd->sloplen, 2779104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2780104477Ssam } 2781104477Ssam 2782104477Ssam i = dma->dstk; u = dma->dstu; 2783104477Ssam while (u != 0) { 2784104477Ssam if (i == HIFN_D_DST_RSIZE) 2785104477Ssam i = 0; 2786104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2787104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2788104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2789104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2790104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2791104477Ssam break; 2792104477Ssam } 2793104477Ssam i++, u--; 2794104477Ssam } 2795104477Ssam dma->dstk = i; dma->dstu = u; 2796104477Ssam 2797104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2798104477Ssam 2799104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2800104477Ssam HIFN_BASE_CMD_CRYPT) { 2801104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2802104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2803120915Ssam crd->crd_alg != CRYPTO_3DES_CBC && 2804120915Ssam crd->crd_alg != CRYPTO_AES_CBC) 2805104477Ssam continue; 2806120915Ssam ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2807120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2808104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2809104477Ssam m_copydata((struct mbuf *)crp->crp_buf, 2810120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2811104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2812104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) { 2813104477Ssam cuio_copydata((struct uio *)crp->crp_buf, 2814120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2815104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2816104477Ssam } 2817104477Ssam break; 2818104477Ssam } 2819104477Ssam } 2820104477Ssam 2821104477Ssam if (macbuf != NULL) { 2822104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2823105275Ssam int len; 2824104477Ssam 2825158705Spjd if (crd->crd_alg != CRYPTO_MD5 && 2826158705Spjd crd->crd_alg != CRYPTO_SHA1 && 2827158705Spjd crd->crd_alg != CRYPTO_MD5_HMAC && 2828158705Spjd crd->crd_alg != CRYPTO_SHA1_HMAC) { 2829104477Ssam continue; 2830158705Spjd } 2831158705Spjd len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; 2832104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2833104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2834104477Ssam crd->crd_inject, len, macbuf); 2835104477Ssam else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2836104477Ssam bcopy((caddr_t)macbuf, crp->crp_mac, len); 2837104477Ssam break; 2838104477Ssam } 2839104477Ssam } 2840104477Ssam 2841104477Ssam if (cmd->src_map != cmd->dst_map) { 2842104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2843104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2844104477Ssam } 2845104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2846104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2847104477Ssam free(cmd, M_DEVBUF); 2848104477Ssam crypto_done(crp); 2849104477Ssam} 2850104477Ssam 2851104477Ssam/* 2852104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2853104477Ssam * and Group 1 registers; avoid conditions that could create 2854104477Ssam * burst writes by doing a read in between the writes. 2855104477Ssam * 2856104477Ssam * NB: The read we interpose is always to the same register; 2857104477Ssam * we do this because reading from an arbitrary (e.g. last) 2858104477Ssam * register may not always work. 2859104477Ssam */ 2860104477Ssamstatic void 2861104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2862104477Ssam{ 2863104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2864104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2865104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2866104477Ssam sc->sc_bar0_lastreg = reg; 2867104477Ssam } 2868104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2869104477Ssam} 2870104477Ssam 2871104477Ssamstatic void 2872104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2873104477Ssam{ 2874104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2875104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2876104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2877104477Ssam sc->sc_bar1_lastreg = reg; 2878104477Ssam } 2879104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2880104477Ssam} 2881