hifn7751.c revision 140480
1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3139749Simp/*- 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9120915Ssam * Copyright (c) 2003 Hifn Inc. 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam */ 42104477Ssam 43119418Sobrien#include <sys/cdefs.h> 44119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/hifn/hifn7751.c 140480 2005-01-19 17:03:35Z sam $"); 45119418Sobrien 46104477Ssam/* 47120915Ssam * Driver for various Hifn encryption processors. 48104477Ssam */ 49112124Ssam#include "opt_hifn.h" 50104477Ssam 51104477Ssam#include <sys/param.h> 52104477Ssam#include <sys/systm.h> 53104477Ssam#include <sys/proc.h> 54104477Ssam#include <sys/errno.h> 55104477Ssam#include <sys/malloc.h> 56104477Ssam#include <sys/kernel.h> 57129879Sphk#include <sys/module.h> 58104477Ssam#include <sys/mbuf.h> 59104477Ssam#include <sys/lock.h> 60104477Ssam#include <sys/mutex.h> 61104477Ssam#include <sys/sysctl.h> 62104477Ssam 63104477Ssam#include <vm/vm.h> 64104477Ssam#include <vm/pmap.h> 65104477Ssam 66104477Ssam#include <machine/clock.h> 67104477Ssam#include <machine/bus.h> 68104477Ssam#include <machine/resource.h> 69104477Ssam#include <sys/bus.h> 70104477Ssam#include <sys/rman.h> 71104477Ssam 72104477Ssam#include <opencrypto/cryptodev.h> 73104477Ssam#include <sys/random.h> 74104477Ssam 75119280Simp#include <dev/pci/pcivar.h> 76119280Simp#include <dev/pci/pcireg.h> 77112124Ssam 78112124Ssam#ifdef HIFN_RNDTEST 79112124Ssam#include <dev/rndtest/rndtest.h> 80112124Ssam#endif 81104477Ssam#include <dev/hifn/hifn7751reg.h> 82104477Ssam#include <dev/hifn/hifn7751var.h> 83104477Ssam 84104477Ssam/* 85104477Ssam * Prototypes and count for the pci_device structure 86104477Ssam */ 87104477Ssamstatic int hifn_probe(device_t); 88104477Ssamstatic int hifn_attach(device_t); 89104477Ssamstatic int hifn_detach(device_t); 90104477Ssamstatic int hifn_suspend(device_t); 91104477Ssamstatic int hifn_resume(device_t); 92104477Ssamstatic void hifn_shutdown(device_t); 93104477Ssam 94104477Ssamstatic device_method_t hifn_methods[] = { 95104477Ssam /* Device interface */ 96104477Ssam DEVMETHOD(device_probe, hifn_probe), 97104477Ssam DEVMETHOD(device_attach, hifn_attach), 98104477Ssam DEVMETHOD(device_detach, hifn_detach), 99104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 100104477Ssam DEVMETHOD(device_resume, hifn_resume), 101104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 102104477Ssam 103104477Ssam /* bus interface */ 104104477Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 105104477Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 106104477Ssam 107104477Ssam { 0, 0 } 108104477Ssam}; 109104477Ssamstatic driver_t hifn_driver = { 110104477Ssam "hifn", 111104477Ssam hifn_methods, 112104477Ssam sizeof (struct hifn_softc) 113104477Ssam}; 114104477Ssamstatic devclass_t hifn_devclass; 115104477Ssam 116104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 117105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 118112124Ssam#ifdef HIFN_RNDTEST 119112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 120112124Ssam#endif 121104477Ssam 122104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 123104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 124104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 125104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 126104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 127104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 128104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 129104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 130104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 131104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 132104477Ssamstatic void hifn_sessions(struct hifn_softc *); 133104477Ssamstatic void hifn_intr(void *); 134104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 135104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 136104477Ssamstatic int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 137104477Ssamstatic int hifn_freesession(void *, u_int64_t); 138104477Ssamstatic int hifn_process(void *, struct cryptop *, int); 139104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 140104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 141104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 142104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 143104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 144104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 145104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 146104477Ssamstatic void hifn_rng(void *); 147104477Ssamstatic void hifn_tick(void *); 148104477Ssamstatic void hifn_abort(struct hifn_softc *); 149104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 150104477Ssam 151104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 152104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 153104477Ssam 154131575Sstefanfstatic __inline u_int32_t 155104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 156104477Ssam{ 157104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 158104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 159104477Ssam return (v); 160104477Ssam} 161104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 162104477Ssam 163131575Sstefanfstatic __inline u_int32_t 164104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 165104477Ssam{ 166104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 167104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 168104477Ssam return (v); 169104477Ssam} 170104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 171104477Ssam 172109596SsamSYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 173109596Ssam 174104477Ssam#ifdef HIFN_DEBUG 175104477Ssamstatic int hifn_debug = 0; 176109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 177109596Ssam 0, "control debugging msgs"); 178104477Ssam#endif 179104477Ssam 180104477Ssamstatic struct hifn_stats hifnstats; 181109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 182109596Ssam hifn_stats, "driver statistics"); 183112121Ssamstatic int hifn_maxbatch = 1; 184109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 185109596Ssam 0, "max ops to batch w/o interrupt"); 186104477Ssam 187104477Ssam/* 188104477Ssam * Probe for a supported device. The PCI vendor and device 189104477Ssam * IDs are used to detect devices we know how to handle. 190104477Ssam */ 191104477Ssamstatic int 192104477Ssamhifn_probe(device_t dev) 193104477Ssam{ 194104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 195104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 196104477Ssam return (0); 197104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 198104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 199104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 200120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 201120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 202104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 203104477Ssam return (0); 204104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 205104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 206104477Ssam return (0); 207104477Ssam return (ENXIO); 208104477Ssam} 209104477Ssam 210104477Ssamstatic void 211104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 212104477Ssam{ 213104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 214104477Ssam *paddr = segs->ds_addr; 215104477Ssam} 216104477Ssam 217104477Ssamstatic const char* 218104477Ssamhifn_partname(struct hifn_softc *sc) 219104477Ssam{ 220104477Ssam /* XXX sprintf numbers when not decoded */ 221104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 222104477Ssam case PCI_VENDOR_HIFN: 223104477Ssam switch (pci_get_device(sc->sc_dev)) { 224104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 225104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 226104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 227104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 228120915Ssam case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 229120915Ssam case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 230104477Ssam } 231104477Ssam return "Hifn unknown-part"; 232104477Ssam case PCI_VENDOR_INVERTEX: 233104477Ssam switch (pci_get_device(sc->sc_dev)) { 234104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 235104477Ssam } 236104477Ssam return "Invertex unknown-part"; 237104477Ssam case PCI_VENDOR_NETSEC: 238104477Ssam switch (pci_get_device(sc->sc_dev)) { 239104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 240104477Ssam } 241104477Ssam return "NetSec unknown-part"; 242104477Ssam } 243104477Ssam return "Unknown-vendor unknown-part"; 244104477Ssam} 245104477Ssam 246112124Ssamstatic void 247112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 248112124Ssam{ 249112124Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 250112124Ssam} 251112124Ssam 252140480Ssamstatic u_int 253140480Ssamcheckmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max) 254140480Ssam{ 255140480Ssam if (v > max) { 256140480Ssam device_printf(dev, "Warning, %s %u out of range, " 257140480Ssam "using max %u\n", what, v, max); 258140480Ssam v = max; 259140480Ssam } else if (v < min) { 260140480Ssam device_printf(dev, "Warning, %s %u out of range, " 261140480Ssam "using min %u\n", what, v, min); 262140480Ssam v = min; 263140480Ssam } 264140480Ssam return v; 265140480Ssam} 266140480Ssam 267104477Ssam/* 268140480Ssam * Select PLL configuration for 795x parts. This is complicated in 269140480Ssam * that we cannot determine the optimal parameters without user input. 270140480Ssam * The reference clock is derived from an external clock through a 271140480Ssam * multiplier. The external clock is either the host bus (i.e. PCI) 272140480Ssam * or an external clock generator. When using the PCI bus we assume 273140480Ssam * the clock is either 33 or 66 MHz; for an external source we cannot 274140480Ssam * tell the speed. 275140480Ssam * 276140480Ssam * PLL configuration is done with a string: "pci" for PCI bus, or "ext" 277140480Ssam * for an external source, followed by the frequency. We calculate 278140480Ssam * the appropriate multiplier and PLL register contents accordingly. 279140480Ssam * When no configuration is given we default to "pci66" since that 280140480Ssam * always will allow the card to work. If a card is using the PCI 281140480Ssam * bus clock and in a 33MHz slot then it will be operating at half 282140480Ssam * speed until the correct information is provided. 283140480Ssam */ 284140480Ssamstatic void 285140480Ssamhifn_getpllconfig(device_t dev, u_int *pll) 286140480Ssam{ 287140480Ssam const char *pllspec; 288140480Ssam u_int freq, mul, fl, fh; 289140480Ssam u_int32_t pllconfig; 290140480Ssam char *nxt; 291140480Ssam 292140480Ssam if (resource_string_value("hifn", device_get_unit(dev), 293140480Ssam "pllconfig", &pllspec)) 294140480Ssam pllspec = "pci66"; 295140480Ssam fl = 33, fh = 66; 296140480Ssam pllconfig = 0; 297140480Ssam if (strncmp(pllspec, "ext", 3) == 0) { 298140480Ssam pllspec += 3; 299140480Ssam pllconfig |= HIFN_PLL_REF_SEL; 300140480Ssam switch (pci_get_device(dev)) { 301140480Ssam case PCI_PRODUCT_HIFN_7955: 302140480Ssam case PCI_PRODUCT_HIFN_7956: 303140480Ssam fl = 20, fh = 100; 304140480Ssam break; 305140480Ssam#ifdef notyet 306140480Ssam case PCI_PRODUCT_HIFN_7954: 307140480Ssam fl = 20, fh = 66; 308140480Ssam break; 309140480Ssam#endif 310140480Ssam } 311140480Ssam } else if (strncmp(pllspec, "pci", 3) == 0) 312140480Ssam pllspec += 3; 313140480Ssam freq = strtoul(pllspec, &nxt, 10); 314140480Ssam if (nxt == pllspec) 315140480Ssam freq = 66; 316140480Ssam else 317140480Ssam freq = checkmaxmin(dev, "frequency", freq, fl, fh); 318140480Ssam /* 319140480Ssam * Calculate multiplier. We target a Fck of 266 MHz, 320140480Ssam * allowing only even values, possibly rounded down. 321140480Ssam * Multipliers > 8 must set the charge pump current. 322140480Ssam */ 323140480Ssam mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); 324140480Ssam pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; 325140480Ssam if (mul > 8) 326140480Ssam pllconfig |= HIFN_PLL_IS; 327140480Ssam *pll = pllconfig; 328140480Ssam} 329140480Ssam 330140480Ssam/* 331104477Ssam * Attach an interface that successfully probed. 332104477Ssam */ 333104477Ssamstatic int 334104477Ssamhifn_attach(device_t dev) 335104477Ssam{ 336104477Ssam struct hifn_softc *sc = device_get_softc(dev); 337104477Ssam u_int32_t cmd; 338104477Ssam caddr_t kva; 339104477Ssam int rseg, rid; 340104477Ssam char rbase; 341104477Ssam u_int16_t ena, rev; 342104477Ssam 343104477Ssam KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 344104477Ssam bzero(sc, sizeof (*sc)); 345104477Ssam sc->sc_dev = dev; 346104477Ssam 347115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 348104477Ssam 349104477Ssam /* XXX handle power management */ 350104477Ssam 351104477Ssam /* 352120915Ssam * The 7951 and 795x have a random number generator and 353104477Ssam * public key support; note this. 354104477Ssam */ 355104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 356120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 357120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 358120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 359104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 360104477Ssam /* 361104477Ssam * The 7811 has a random number generator and 362104477Ssam * we also note it's identity 'cuz of some quirks. 363104477Ssam */ 364104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 365104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 366104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 367104477Ssam 368104477Ssam /* 369120915Ssam * The 795x parts support AES. 370120915Ssam */ 371120915Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 372120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 373140480Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { 374120915Ssam sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 375140480Ssam /* 376140480Ssam * Select PLL configuration. This depends on the 377140480Ssam * bus and board design and must be manually configured 378140480Ssam * if the default setting is unacceptable. 379140480Ssam */ 380140480Ssam hifn_getpllconfig(dev, &sc->sc_pllconfig); 381140480Ssam } 382120915Ssam 383120915Ssam /* 384104477Ssam * Configure support for memory-mapped access to 385104477Ssam * registers and for DMA operations. 386104477Ssam */ 387104477Ssam#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 388104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 389104477Ssam cmd |= PCIM_ENA; 390104477Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 391104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 392104477Ssam if ((cmd & PCIM_ENA) != PCIM_ENA) { 393104477Ssam device_printf(dev, "failed to enable %s\n", 394104477Ssam (cmd & PCIM_ENA) == 0 ? 395104477Ssam "memory mapping & bus mastering" : 396104477Ssam (cmd & PCIM_CMD_MEMEN) == 0 ? 397104477Ssam "memory mapping" : "bus mastering"); 398104477Ssam goto fail_pci; 399104477Ssam } 400104477Ssam#undef PCIM_ENA 401104477Ssam 402104477Ssam /* 403104477Ssam * Setup PCI resources. Note that we record the bus 404104477Ssam * tag and handle for each register mapping, this is 405104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 406104477Ssam * and WRITE_REG_1 macros throughout the driver. 407104477Ssam */ 408104477Ssam rid = HIFN_BAR0; 409127135Snjl sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 410127135Snjl RF_ACTIVE); 411104477Ssam if (sc->sc_bar0res == NULL) { 412104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 413104477Ssam goto fail_pci; 414104477Ssam } 415104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 416104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 417104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 418104477Ssam 419104477Ssam rid = HIFN_BAR1; 420127135Snjl sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 421127135Snjl RF_ACTIVE); 422104477Ssam if (sc->sc_bar1res == NULL) { 423104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 424104477Ssam goto fail_io0; 425104477Ssam } 426104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 427104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 428104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 429104477Ssam 430104477Ssam hifn_set_retry(sc); 431104477Ssam 432104477Ssam /* 433104477Ssam * Setup the area where the Hifn DMA's descriptors 434104477Ssam * and associated data structures. 435104477Ssam */ 436104477Ssam if (bus_dma_tag_create(NULL, /* parent */ 437104477Ssam 1, 0, /* alignment,boundary */ 438104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 439104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 440104477Ssam NULL, NULL, /* filter, filterarg */ 441104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 442104477Ssam MAX_SCATTER, /* nsegments */ 443104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 444104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 445117126Sscottl NULL, /* lockfunc */ 446117126Sscottl NULL, /* lockarg */ 447104477Ssam &sc->sc_dmat)) { 448104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 449104477Ssam goto fail_io1; 450104477Ssam } 451104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 452104477Ssam device_printf(dev, "cannot create dma map\n"); 453104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 454104477Ssam goto fail_io1; 455104477Ssam } 456104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 457104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 458104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 459104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 460104477Ssam goto fail_io1; 461104477Ssam } 462104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 463104477Ssam sizeof (*sc->sc_dma), 464104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 465104477Ssam BUS_DMA_NOWAIT)) { 466104477Ssam device_printf(dev, "cannot load dma map\n"); 467104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 468104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 469104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 470104477Ssam goto fail_io1; 471104477Ssam } 472104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 473104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 474104477Ssam 475123824Ssam KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 476123824Ssam KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 477123824Ssam KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 478123824Ssam KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 479104477Ssam 480104477Ssam /* 481104477Ssam * Reset the board and do the ``secret handshake'' 482104477Ssam * to enable the crypto support. Then complete the 483104477Ssam * initialization procedure by setting up the interrupt 484104477Ssam * and hooking in to the system crypto support so we'll 485104477Ssam * get used for system services like the crypto device, 486104477Ssam * IPsec, RNG device, etc. 487104477Ssam */ 488104477Ssam hifn_reset_board(sc, 0); 489104477Ssam 490104477Ssam if (hifn_enable_crypto(sc) != 0) { 491104477Ssam device_printf(dev, "crypto enabling failed\n"); 492104477Ssam goto fail_mem; 493104477Ssam } 494104477Ssam hifn_reset_puc(sc); 495104477Ssam 496104477Ssam hifn_init_dma(sc); 497104477Ssam hifn_init_pci_registers(sc); 498104477Ssam 499120915Ssam /* XXX can't dynamically determine ram type for 795x; force dram */ 500120915Ssam if (sc->sc_flags & HIFN_IS_7956) 501120915Ssam sc->sc_drammodel = 1; 502120915Ssam else if (hifn_ramtype(sc)) 503104477Ssam goto fail_mem; 504104477Ssam 505104477Ssam if (sc->sc_drammodel == 0) 506104477Ssam hifn_sramsize(sc); 507104477Ssam else 508104477Ssam hifn_dramsize(sc); 509104477Ssam 510104477Ssam /* 511104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 512104477Ssam * of the address lines were left floating 513104477Ssam */ 514104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 515104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 516104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 517104477Ssam sc->sc_ramsize >>= 1; 518104477Ssam 519104477Ssam /* 520104477Ssam * Arrange the interrupt line. 521104477Ssam */ 522104477Ssam rid = 0; 523127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 524127135Snjl RF_SHAREABLE|RF_ACTIVE); 525104477Ssam if (sc->sc_irq == NULL) { 526104477Ssam device_printf(dev, "could not map interrupt\n"); 527104477Ssam goto fail_mem; 528104477Ssam } 529104477Ssam /* 530104477Ssam * NB: Network code assumes we are blocked with splimp() 531104477Ssam * so make sure the IRQ is marked appropriately. 532104477Ssam */ 533115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 534104477Ssam hifn_intr, sc, &sc->sc_intrhand)) { 535104477Ssam device_printf(dev, "could not setup interrupt\n"); 536104477Ssam goto fail_intr2; 537104477Ssam } 538104477Ssam 539104477Ssam hifn_sessions(sc); 540104477Ssam 541104477Ssam /* 542104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 543104477Ssam * from the 7951. 544104477Ssam */ 545104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 546104477Ssam 547104477Ssam rseg = sc->sc_ramsize / 1024; 548104477Ssam rbase = 'K'; 549104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 550104477Ssam rbase = 'M'; 551104477Ssam rseg /= 1024; 552104477Ssam } 553140480Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", 554104477Ssam hifn_partname(sc), rev, 555136526Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's'); 556140480Ssam if (sc->sc_flags & HIFN_IS_7956) 557140480Ssam printf(", pll=0x%x<%s clk, %ux mult>", 558140480Ssam sc->sc_pllconfig, 559140480Ssam sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", 560140480Ssam 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); 561140480Ssam printf("\n"); 562104477Ssam 563104477Ssam sc->sc_cid = crypto_get_driverid(0); 564104477Ssam if (sc->sc_cid < 0) { 565104477Ssam device_printf(dev, "could not get crypto driver id\n"); 566104477Ssam goto fail_intr; 567104477Ssam } 568104477Ssam 569104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 570104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 571104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 572104477Ssam 573104477Ssam switch (ena) { 574104477Ssam case HIFN_PUSTAT_ENA_2: 575104477Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 576104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 577104477Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 578104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 579120915Ssam if (sc->sc_flags & HIFN_HAS_AES) 580120915Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 581120915Ssam hifn_newsession, hifn_freesession, 582120915Ssam hifn_process, sc); 583104477Ssam /*FALLTHROUGH*/ 584104477Ssam case HIFN_PUSTAT_ENA_1: 585104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 586104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 587104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 588104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 589104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 590104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 591104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 592104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 593104477Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 594104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 595104477Ssam break; 596104477Ssam } 597104477Ssam 598104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 599104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 600104477Ssam 601104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 602104477Ssam hifn_init_pubrng(sc); 603104477Ssam 604119137Ssam callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 605104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 606104477Ssam 607104477Ssam return (0); 608104477Ssam 609104477Ssamfail_intr: 610104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 611104477Ssamfail_intr2: 612104477Ssam /* XXX don't store rid */ 613104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 614104477Ssamfail_mem: 615104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 616104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 617104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 618104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 619104477Ssam 620104477Ssam /* Turn off DMA polling */ 621104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 622104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 623104477Ssamfail_io1: 624104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 625104477Ssamfail_io0: 626104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 627104477Ssamfail_pci: 628104477Ssam mtx_destroy(&sc->sc_mtx); 629104477Ssam return (ENXIO); 630104477Ssam} 631104477Ssam 632104477Ssam/* 633104477Ssam * Detach an interface that successfully probed. 634104477Ssam */ 635104477Ssamstatic int 636104477Ssamhifn_detach(device_t dev) 637104477Ssam{ 638104477Ssam struct hifn_softc *sc = device_get_softc(dev); 639104477Ssam 640104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 641104477Ssam 642115748Ssam /* disable interrupts */ 643115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 644104477Ssam 645104477Ssam /*XXX other resources */ 646104477Ssam callout_stop(&sc->sc_tickto); 647104477Ssam callout_stop(&sc->sc_rngto); 648115848Ssam#ifdef HIFN_RNDTEST 649115848Ssam if (sc->sc_rndtest) 650115862Ssam rndtest_detach(sc->sc_rndtest); 651115848Ssam#endif 652104477Ssam 653104477Ssam /* Turn off DMA polling */ 654104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 655104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 656104477Ssam 657104477Ssam crypto_unregister_all(sc->sc_cid); 658104477Ssam 659104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 660104477Ssam 661104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 662104477Ssam /* XXX don't store rid */ 663104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 664104477Ssam 665104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 666104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 667104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 668104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 669104477Ssam 670104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 671104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 672104477Ssam 673104477Ssam mtx_destroy(&sc->sc_mtx); 674104477Ssam 675104477Ssam return (0); 676104477Ssam} 677104477Ssam 678104477Ssam/* 679104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 680104477Ssam * get confused by errant DMAs when rebooting. 681104477Ssam */ 682104477Ssamstatic void 683104477Ssamhifn_shutdown(device_t dev) 684104477Ssam{ 685104477Ssam#ifdef notyet 686104477Ssam hifn_stop(device_get_softc(dev)); 687104477Ssam#endif 688104477Ssam} 689104477Ssam 690104477Ssam/* 691104477Ssam * Device suspend routine. Stop the interface and save some PCI 692104477Ssam * settings in case the BIOS doesn't restore them properly on 693104477Ssam * resume. 694104477Ssam */ 695104477Ssamstatic int 696104477Ssamhifn_suspend(device_t dev) 697104477Ssam{ 698104477Ssam struct hifn_softc *sc = device_get_softc(dev); 699104477Ssam#ifdef notyet 700104477Ssam int i; 701104477Ssam 702104477Ssam hifn_stop(sc); 703104477Ssam for (i = 0; i < 5; i++) 704119690Sjhb sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 705104477Ssam sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 706104477Ssam sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 707104477Ssam sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 708104477Ssam sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 709104477Ssam#endif 710104477Ssam sc->sc_suspended = 1; 711104477Ssam 712104477Ssam return (0); 713104477Ssam} 714104477Ssam 715104477Ssam/* 716104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 717104477Ssam * doesn't, re-enable busmastering, and restart the interface if 718104477Ssam * appropriate. 719104477Ssam */ 720104477Ssamstatic int 721104477Ssamhifn_resume(device_t dev) 722104477Ssam{ 723104477Ssam struct hifn_softc *sc = device_get_softc(dev); 724104477Ssam#ifdef notyet 725104477Ssam int i; 726104477Ssam 727104477Ssam /* better way to do this? */ 728104477Ssam for (i = 0; i < 5; i++) 729119690Sjhb pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 730104477Ssam pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 731104477Ssam pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 732104477Ssam pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 733104477Ssam pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 734104477Ssam 735104477Ssam /* reenable busmastering */ 736104477Ssam pci_enable_busmaster(dev); 737104477Ssam pci_enable_io(dev, HIFN_RES); 738104477Ssam 739104477Ssam /* reinitialize interface if necessary */ 740104477Ssam if (ifp->if_flags & IFF_UP) 741104477Ssam rl_init(sc); 742104477Ssam#endif 743104477Ssam sc->sc_suspended = 0; 744104477Ssam 745104477Ssam return (0); 746104477Ssam} 747104477Ssam 748104477Ssamstatic int 749104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 750104477Ssam{ 751104477Ssam u_int32_t r; 752104477Ssam int i; 753104477Ssam 754112124Ssam#ifdef HIFN_RNDTEST 755112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 756112124Ssam if (sc->sc_rndtest) 757112124Ssam sc->sc_harvest = rndtest_harvest; 758112124Ssam else 759112124Ssam sc->sc_harvest = default_harvest; 760112124Ssam#else 761112124Ssam sc->sc_harvest = default_harvest; 762112124Ssam#endif 763104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 764104477Ssam /* Reset 7951 public key/rng engine */ 765104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 766104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 767104477Ssam 768104477Ssam for (i = 0; i < 100; i++) { 769104477Ssam DELAY(1000); 770104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 771104477Ssam HIFN_PUBRST_RESET) == 0) 772104477Ssam break; 773104477Ssam } 774104477Ssam 775104477Ssam if (i == 100) { 776104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 777104477Ssam return (1); 778104477Ssam } 779104477Ssam } 780104477Ssam 781104477Ssam /* Enable the rng, if available */ 782104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 783104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 784104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 785104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 786104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 787104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 788104477Ssam } 789104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 790104477Ssam HIFN_7811_RNGCFG_DEFL); 791104477Ssam r |= HIFN_7811_RNGENA_ENA; 792104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 793104477Ssam } else 794104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 795104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 796104477Ssam HIFN_RNGCFG_ENA); 797104477Ssam 798104477Ssam sc->sc_rngfirst = 1; 799104477Ssam if (hz >= 100) 800104477Ssam sc->sc_rnghz = hz / 100; 801104477Ssam else 802104477Ssam sc->sc_rnghz = 1; 803119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 804104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 805104477Ssam } 806104477Ssam 807104477Ssam /* Enable public key engine, if available */ 808104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 809104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 810104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 811104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 812104477Ssam } 813104477Ssam 814104477Ssam return (0); 815104477Ssam} 816104477Ssam 817104477Ssamstatic void 818104477Ssamhifn_rng(void *vsc) 819104477Ssam{ 820104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 821104477Ssam struct hifn_softc *sc = vsc; 822104477Ssam u_int32_t sts, num[2]; 823104477Ssam int i; 824104477Ssam 825104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 826104477Ssam for (i = 0; i < 5; i++) { 827104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 828104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 829104477Ssam device_printf(sc->sc_dev, 830104477Ssam "RNG underflow: disabling\n"); 831104477Ssam return; 832104477Ssam } 833104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 834104477Ssam break; 835104477Ssam 836104477Ssam /* 837104477Ssam * There are at least two words in the RNG FIFO 838104477Ssam * at this point. 839104477Ssam */ 840104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 841104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 842104477Ssam /* NB: discard first data read */ 843104477Ssam if (sc->sc_rngfirst) 844104477Ssam sc->sc_rngfirst = 0; 845104477Ssam else 846112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 847112124Ssam num, sizeof (num)); 848104477Ssam } 849104477Ssam } else { 850104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 851104477Ssam 852104477Ssam /* NB: discard first data read */ 853104477Ssam if (sc->sc_rngfirst) 854104477Ssam sc->sc_rngfirst = 0; 855104477Ssam else 856112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 857112124Ssam num, sizeof (num[0])); 858104477Ssam } 859104477Ssam 860104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 861104477Ssam#undef RANDOM_BITS 862104477Ssam} 863104477Ssam 864104477Ssamstatic void 865104477Ssamhifn_puc_wait(struct hifn_softc *sc) 866104477Ssam{ 867104477Ssam int i; 868104477Ssam 869104477Ssam for (i = 5000; i > 0; i--) { 870104477Ssam DELAY(1); 871104477Ssam if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 872104477Ssam break; 873104477Ssam } 874104477Ssam if (!i) 875104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 876104477Ssam} 877104477Ssam 878104477Ssam/* 879104477Ssam * Reset the processing unit. 880104477Ssam */ 881104477Ssamstatic void 882104477Ssamhifn_reset_puc(struct hifn_softc *sc) 883104477Ssam{ 884104477Ssam /* Reset processing unit */ 885104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 886104477Ssam hifn_puc_wait(sc); 887104477Ssam} 888104477Ssam 889104477Ssam/* 890104477Ssam * Set the Retry and TRDY registers; note that we set them to 891104477Ssam * zero because the 7811 locks up when forced to retry (section 892104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 893104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 894104477Ssam */ 895104477Ssamstatic void 896104477Ssamhifn_set_retry(struct hifn_softc *sc) 897104477Ssam{ 898104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 899104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 900104477Ssam pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 901104477Ssam} 902104477Ssam 903104477Ssam/* 904104477Ssam * Resets the board. Values in the regesters are left as is 905104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 906104477Ssam */ 907104477Ssamstatic void 908104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 909104477Ssam{ 910104477Ssam u_int32_t reg; 911104477Ssam 912104477Ssam /* 913104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 914104477Ssam * resetting the board and zeros out the other fields. 915104477Ssam */ 916104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 917104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 918104477Ssam 919104477Ssam /* 920104477Ssam * Now that polling has been disabled, we have to wait 1 ms 921104477Ssam * before resetting the board. 922104477Ssam */ 923104477Ssam DELAY(1000); 924104477Ssam 925104477Ssam /* Reset the DMA unit */ 926104477Ssam if (full) { 927104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 928104477Ssam DELAY(1000); 929104477Ssam } else { 930104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 931104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 932104477Ssam hifn_reset_puc(sc); 933104477Ssam } 934104477Ssam 935104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 936104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 937104477Ssam 938104477Ssam /* Bring dma unit out of reset */ 939104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 940104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 941104477Ssam 942104477Ssam hifn_puc_wait(sc); 943104477Ssam hifn_set_retry(sc); 944104477Ssam 945104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 946104477Ssam for (reg = 0; reg < 1000; reg++) { 947104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 948104477Ssam HIFN_MIPSRST_CRAMINIT) 949104477Ssam break; 950104477Ssam DELAY(1000); 951104477Ssam } 952104477Ssam if (reg == 1000) 953104477Ssam printf(": cram init timeout\n"); 954104477Ssam } 955104477Ssam} 956104477Ssam 957104477Ssamstatic u_int32_t 958104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 959104477Ssam{ 960104477Ssam int i; 961104477Ssam u_int32_t v; 962104477Ssam 963104477Ssam for (i = 0; i < cnt; i++) { 964104477Ssam 965104477Ssam /* get the parity */ 966104477Ssam v = a & 0x80080125; 967104477Ssam v ^= v >> 16; 968104477Ssam v ^= v >> 8; 969104477Ssam v ^= v >> 4; 970104477Ssam v ^= v >> 2; 971104477Ssam v ^= v >> 1; 972104477Ssam 973104477Ssam a = (v & 1) ^ (a << 1); 974104477Ssam } 975104477Ssam 976104477Ssam return a; 977104477Ssam} 978104477Ssam 979104477Ssamstruct pci2id { 980104477Ssam u_short pci_vendor; 981104477Ssam u_short pci_prod; 982104477Ssam char card_id[13]; 983104477Ssam}; 984104477Ssamstatic struct pci2id pci2id[] = { 985104477Ssam { 986104477Ssam PCI_VENDOR_HIFN, 987104477Ssam PCI_PRODUCT_HIFN_7951, 988104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 989104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 990104477Ssam }, { 991120915Ssam PCI_VENDOR_HIFN, 992120915Ssam PCI_PRODUCT_HIFN_7955, 993120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 994120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 995120915Ssam }, { 996120915Ssam PCI_VENDOR_HIFN, 997120915Ssam PCI_PRODUCT_HIFN_7956, 998120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 999120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1000120915Ssam }, { 1001104477Ssam PCI_VENDOR_NETSEC, 1002104477Ssam PCI_PRODUCT_NETSEC_7751, 1003104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1004104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1005104477Ssam }, { 1006104477Ssam PCI_VENDOR_INVERTEX, 1007104477Ssam PCI_PRODUCT_INVERTEX_AEON, 1008104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1009104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1010104477Ssam }, { 1011104477Ssam PCI_VENDOR_HIFN, 1012104477Ssam PCI_PRODUCT_HIFN_7811, 1013104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1014104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1015104477Ssam }, { 1016104477Ssam /* 1017104477Ssam * Other vendors share this PCI ID as well, such as 1018104477Ssam * http://www.powercrypt.com, and obviously they also 1019104477Ssam * use the same key. 1020104477Ssam */ 1021104477Ssam PCI_VENDOR_HIFN, 1022104477Ssam PCI_PRODUCT_HIFN_7751, 1023104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1024104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1025104477Ssam }, 1026104477Ssam}; 1027104477Ssam 1028104477Ssam/* 1029104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 1030104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 1031104477Ssam * as enabling crypto twice will lock the board. 1032104477Ssam */ 1033104477Ssamstatic int 1034104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 1035104477Ssam{ 1036104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 1037104477Ssam char *offtbl = NULL; 1038104477Ssam 1039104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 1040104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 1041104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 1042104477Ssam offtbl = pci2id[i].card_id; 1043104477Ssam break; 1044104477Ssam } 1045104477Ssam } 1046104477Ssam if (offtbl == NULL) { 1047104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 1048104477Ssam return (1); 1049104477Ssam } 1050104477Ssam 1051104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1052104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 1053104477Ssam 1054104477Ssam /* 1055104477Ssam * The RAM config register's encrypt level bit needs to be set before 1056104477Ssam * every read performed on the encryption level register. 1057104477Ssam */ 1058104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1059104477Ssam 1060104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1061104477Ssam 1062104477Ssam /* 1063104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 1064104477Ssam * next reboot. 1065104477Ssam */ 1066104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 1067104477Ssam#ifdef HIFN_DEBUG 1068104477Ssam if (hifn_debug) 1069104477Ssam device_printf(sc->sc_dev, 1070104477Ssam "Strong crypto already enabled!\n"); 1071104477Ssam#endif 1072104477Ssam goto report; 1073104477Ssam } 1074104477Ssam 1075104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 1076104477Ssam#ifdef HIFN_DEBUG 1077104477Ssam if (hifn_debug) 1078104477Ssam device_printf(sc->sc_dev, 1079104477Ssam "Unknown encryption level 0x%x\n", encl); 1080104477Ssam#endif 1081104477Ssam return 1; 1082104477Ssam } 1083104477Ssam 1084104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 1085104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 1086104477Ssam DELAY(1000); 1087104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 1088104477Ssam DELAY(1000); 1089104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 1090104477Ssam DELAY(1000); 1091104477Ssam 1092104477Ssam for (i = 0; i <= 12; i++) { 1093104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1094104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1095104477Ssam 1096104477Ssam DELAY(1000); 1097104477Ssam } 1098104477Ssam 1099104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1100104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1101104477Ssam 1102104477Ssam#ifdef HIFN_DEBUG 1103104477Ssam if (hifn_debug) { 1104104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1105104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 1106104477Ssam "locked until next system reset!\n"); 1107104477Ssam else 1108104477Ssam device_printf(sc->sc_dev, "Engine enabled " 1109104477Ssam "successfully!\n"); 1110104477Ssam } 1111104477Ssam#endif 1112104477Ssam 1113104477Ssamreport: 1114104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1115104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1116104477Ssam 1117104477Ssam switch (encl) { 1118104477Ssam case HIFN_PUSTAT_ENA_1: 1119104477Ssam case HIFN_PUSTAT_ENA_2: 1120104477Ssam break; 1121104477Ssam case HIFN_PUSTAT_ENA_0: 1122104477Ssam default: 1123104477Ssam device_printf(sc->sc_dev, "disabled"); 1124104477Ssam break; 1125104477Ssam } 1126104477Ssam 1127104477Ssam return 0; 1128104477Ssam} 1129104477Ssam 1130104477Ssam/* 1131104477Ssam * Give initial values to the registers listed in the "Register Space" 1132104477Ssam * section of the HIFN Software Development reference manual. 1133104477Ssam */ 1134104477Ssamstatic void 1135104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1136104477Ssam{ 1137104477Ssam /* write fixed values needed by the Initialization registers */ 1138104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1139104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1140104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1141104477Ssam 1142104477Ssam /* write all 4 ring address registers */ 1143104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1144104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1145104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1146104477Ssam offsetof(struct hifn_dma, srcr[0])); 1147104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1148104477Ssam offsetof(struct hifn_dma, dstr[0])); 1149104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1150104477Ssam offsetof(struct hifn_dma, resr[0])); 1151104477Ssam 1152104477Ssam DELAY(2000); 1153104477Ssam 1154104477Ssam /* write status register */ 1155104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1156104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1157104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1158104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1159104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1160104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1161104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1162104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1163104477Ssam HIFN_DMACSR_S_WAIT | 1164104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1165104477Ssam HIFN_DMACSR_C_WAIT | 1166104477Ssam HIFN_DMACSR_ENGINE | 1167104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1168104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1169104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1170104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1171104477Ssam 1172104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1173104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1174104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1175104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1176104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1177104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1178104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1179104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1180104477Ssam 1181104477Ssam 1182120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1183140480Ssam u_int32_t pll; 1184140480Ssam 1185120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1186120915Ssam HIFN_PUCNFG_TCALLPHASES | 1187120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1188140480Ssam 1189140480Ssam /* turn off the clocks and insure bypass is set */ 1190140480Ssam pll = READ_REG_1(sc, HIFN_1_PLL); 1191140480Ssam pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) 1192140480Ssam | HIFN_PLL_BP; 1193140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1194140480Ssam DELAY(10*1000); /* 10ms */ 1195140480Ssam /* change configuration */ 1196140480Ssam pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; 1197140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1198140480Ssam DELAY(10*1000); /* 10ms */ 1199140480Ssam /* disable bypass */ 1200140480Ssam pll &= ~HIFN_PLL_BP; 1201140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1202140480Ssam /* enable clocks with new configuration */ 1203140480Ssam pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; 1204140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1205120915Ssam } else { 1206120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1207120915Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1208120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1209120915Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1210120915Ssam } 1211120915Ssam 1212104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1213104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1214104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1215104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1216104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1217104477Ssam} 1218104477Ssam 1219104477Ssam/* 1220104477Ssam * The maximum number of sessions supported by the card 1221104477Ssam * is dependent on the amount of context ram, which 1222104477Ssam * encryption algorithms are enabled, and how compression 1223104477Ssam * is configured. This should be configured before this 1224104477Ssam * routine is called. 1225104477Ssam */ 1226104477Ssamstatic void 1227104477Ssamhifn_sessions(struct hifn_softc *sc) 1228104477Ssam{ 1229104477Ssam u_int32_t pucnfg; 1230104477Ssam int ctxsize; 1231104477Ssam 1232104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1233104477Ssam 1234104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1235104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1236104477Ssam ctxsize = 128; 1237104477Ssam else 1238104477Ssam ctxsize = 512; 1239120915Ssam /* 1240120915Ssam * 7955/7956 has internal context memory of 32K 1241120915Ssam */ 1242120915Ssam if (sc->sc_flags & HIFN_IS_7956) 1243120915Ssam sc->sc_maxses = 32768 / ctxsize; 1244120915Ssam else 1245120915Ssam sc->sc_maxses = 1 + 1246120915Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1247104477Ssam } else 1248104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1249104477Ssam 1250104477Ssam if (sc->sc_maxses > 2048) 1251104477Ssam sc->sc_maxses = 2048; 1252104477Ssam} 1253104477Ssam 1254104477Ssam/* 1255104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1256104477Ssam * state when this is called. 1257104477Ssam */ 1258104477Ssamstatic int 1259104477Ssamhifn_ramtype(struct hifn_softc *sc) 1260104477Ssam{ 1261104477Ssam u_int8_t data[8], dataexpect[8]; 1262104477Ssam int i; 1263104477Ssam 1264104477Ssam for (i = 0; i < sizeof(data); i++) 1265104477Ssam data[i] = dataexpect[i] = 0x55; 1266104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1267104477Ssam return (-1); 1268104477Ssam if (hifn_readramaddr(sc, 0, data)) 1269104477Ssam return (-1); 1270104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1271104477Ssam sc->sc_drammodel = 1; 1272104477Ssam return (0); 1273104477Ssam } 1274104477Ssam 1275104477Ssam for (i = 0; i < sizeof(data); i++) 1276104477Ssam data[i] = dataexpect[i] = 0xaa; 1277104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1278104477Ssam return (-1); 1279104477Ssam if (hifn_readramaddr(sc, 0, data)) 1280104477Ssam return (-1); 1281104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1282104477Ssam sc->sc_drammodel = 1; 1283104477Ssam return (0); 1284104477Ssam } 1285104477Ssam 1286104477Ssam return (0); 1287104477Ssam} 1288104477Ssam 1289104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1290104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1291104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1292104477Ssam 1293104477Ssamstatic int 1294104477Ssamhifn_sramsize(struct hifn_softc *sc) 1295104477Ssam{ 1296104477Ssam u_int32_t a; 1297104477Ssam u_int8_t data[8]; 1298104477Ssam u_int8_t dataexpect[sizeof(data)]; 1299104477Ssam int32_t i; 1300104477Ssam 1301104477Ssam for (i = 0; i < sizeof(data); i++) 1302104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1303104477Ssam 1304104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1305104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1306104477Ssam bcopy(&i, data, sizeof(i)); 1307104477Ssam hifn_writeramaddr(sc, a, data); 1308104477Ssam } 1309104477Ssam 1310104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1311104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1312104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1313104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1314104477Ssam return (0); 1315104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1316104477Ssam return (0); 1317104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1318104477Ssam } 1319104477Ssam 1320104477Ssam return (0); 1321104477Ssam} 1322104477Ssam 1323104477Ssam/* 1324104477Ssam * XXX For dram boards, one should really try all of the 1325104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1326104477Ssam * is already set up correctly. 1327104477Ssam */ 1328104477Ssamstatic int 1329104477Ssamhifn_dramsize(struct hifn_softc *sc) 1330104477Ssam{ 1331104477Ssam u_int32_t cnfg; 1332104477Ssam 1333120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1334120915Ssam /* 1335120915Ssam * 7955/7956 have a fixed internal ram of only 32K. 1336120915Ssam */ 1337120915Ssam sc->sc_ramsize = 32768; 1338120915Ssam } else { 1339120915Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1340120915Ssam HIFN_PUCNFG_DRAMMASK; 1341120915Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1342120915Ssam } 1343104477Ssam return (0); 1344104477Ssam} 1345104477Ssam 1346104477Ssamstatic void 1347104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1348104477Ssam{ 1349104477Ssam struct hifn_dma *dma = sc->sc_dma; 1350104477Ssam 1351104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1352104477Ssam dma->cmdi = 0; 1353104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1354104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1355104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1356104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1357104477Ssam } 1358104477Ssam *cmdp = dma->cmdi++; 1359104477Ssam dma->cmdk = dma->cmdi; 1360104477Ssam 1361104477Ssam if (dma->srci == HIFN_D_SRC_RSIZE) { 1362104477Ssam dma->srci = 0; 1363104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1364104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1365104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1366104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1367104477Ssam } 1368104477Ssam *srcp = dma->srci++; 1369104477Ssam dma->srck = dma->srci; 1370104477Ssam 1371104477Ssam if (dma->dsti == HIFN_D_DST_RSIZE) { 1372104477Ssam dma->dsti = 0; 1373104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1374104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1375104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1376104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1377104477Ssam } 1378104477Ssam *dstp = dma->dsti++; 1379104477Ssam dma->dstk = dma->dsti; 1380104477Ssam 1381104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1382104477Ssam dma->resi = 0; 1383104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1384104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1385104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1386104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1387104477Ssam } 1388104477Ssam *resp = dma->resi++; 1389104477Ssam dma->resk = dma->resi; 1390104477Ssam} 1391104477Ssam 1392104477Ssamstatic int 1393104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1394104477Ssam{ 1395104477Ssam struct hifn_dma *dma = sc->sc_dma; 1396104477Ssam hifn_base_command_t wc; 1397104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1398104477Ssam int r, cmdi, resi, srci, dsti; 1399104477Ssam 1400104477Ssam wc.masks = htole16(3 << 13); 1401104477Ssam wc.session_num = htole16(addr >> 14); 1402104477Ssam wc.total_source_count = htole16(8); 1403104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1404104477Ssam 1405104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1406104477Ssam 1407104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1408104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1409104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1410104477Ssam 1411104477Ssam /* build write command */ 1412104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1413104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1414104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1415104477Ssam 1416104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1417104477Ssam + offsetof(struct hifn_dma, test_src)); 1418104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1419104477Ssam + offsetof(struct hifn_dma, test_dst)); 1420104477Ssam 1421104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1422104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1423104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1424104477Ssam dma->resr[resi].l = htole32(4 | masks); 1425104477Ssam 1426104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1427104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1428104477Ssam 1429104477Ssam for (r = 10000; r >= 0; r--) { 1430104477Ssam DELAY(10); 1431104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1432104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1433104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1434104477Ssam break; 1435104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1436104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1437104477Ssam } 1438104477Ssam if (r == 0) { 1439104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1440104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1441104477Ssam r = -1; 1442104477Ssam return (-1); 1443104477Ssam } else 1444104477Ssam r = 0; 1445104477Ssam 1446104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1447104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1448104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1449104477Ssam 1450104477Ssam return (r); 1451104477Ssam} 1452104477Ssam 1453104477Ssamstatic int 1454104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1455104477Ssam{ 1456104477Ssam struct hifn_dma *dma = sc->sc_dma; 1457104477Ssam hifn_base_command_t rc; 1458104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1459104477Ssam int r, cmdi, srci, dsti, resi; 1460104477Ssam 1461104477Ssam rc.masks = htole16(2 << 13); 1462104477Ssam rc.session_num = htole16(addr >> 14); 1463104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1464104477Ssam rc.total_dest_count = htole16(8); 1465104477Ssam 1466104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1467104477Ssam 1468104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1469104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1470104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1471104477Ssam 1472104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1473104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1474104477Ssam 1475104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1476104477Ssam offsetof(struct hifn_dma, test_src)); 1477104477Ssam dma->test_src = 0; 1478104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1479104477Ssam offsetof(struct hifn_dma, test_dst)); 1480104477Ssam dma->test_dst = 0; 1481104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1482104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1483104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1484104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1485104477Ssam 1486104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1487104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1488104477Ssam 1489104477Ssam for (r = 10000; r >= 0; r--) { 1490104477Ssam DELAY(10); 1491104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1492104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1493104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1494104477Ssam break; 1495104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1496104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1497104477Ssam } 1498104477Ssam if (r == 0) { 1499104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1500104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1501104477Ssam r = -1; 1502104477Ssam } else { 1503104477Ssam r = 0; 1504104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1505104477Ssam } 1506104477Ssam 1507104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1508104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1509104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1510104477Ssam 1511104477Ssam return (r); 1512104477Ssam} 1513104477Ssam 1514104477Ssam/* 1515104477Ssam * Initialize the descriptor rings. 1516104477Ssam */ 1517104477Ssamstatic void 1518104477Ssamhifn_init_dma(struct hifn_softc *sc) 1519104477Ssam{ 1520104477Ssam struct hifn_dma *dma = sc->sc_dma; 1521104477Ssam int i; 1522104477Ssam 1523104477Ssam hifn_set_retry(sc); 1524104477Ssam 1525104477Ssam /* initialize static pointer values */ 1526104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1527104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1528104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1529104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1530104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1531104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1532104477Ssam 1533104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1534104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1535104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1536104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1537104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1538104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1539104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1540104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1541104477Ssam 1542104477Ssam dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1543104477Ssam dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1544104477Ssam dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1545104477Ssam} 1546104477Ssam 1547104477Ssam/* 1548104477Ssam * Writes out the raw command buffer space. Returns the 1549104477Ssam * command buffer size. 1550104477Ssam */ 1551104477Ssamstatic u_int 1552104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1553104477Ssam{ 1554104477Ssam u_int8_t *buf_pos; 1555104477Ssam hifn_base_command_t *base_cmd; 1556104477Ssam hifn_mac_command_t *mac_cmd; 1557104477Ssam hifn_crypt_command_t *cry_cmd; 1558120915Ssam int using_mac, using_crypt, len, ivlen; 1559104477Ssam u_int32_t dlen, slen; 1560104477Ssam 1561104477Ssam buf_pos = buf; 1562104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1563104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1564104477Ssam 1565104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1566104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1567104477Ssam slen = cmd->src_mapsize; 1568104477Ssam if (cmd->sloplen) 1569104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1570104477Ssam else 1571104477Ssam dlen = cmd->dst_mapsize; 1572104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1573104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1574104477Ssam dlen >>= 16; 1575104477Ssam slen >>= 16; 1576136526Ssam base_cmd->session_num = htole16( 1577104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1578104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1579104477Ssam buf_pos += sizeof(hifn_base_command_t); 1580104477Ssam 1581104477Ssam if (using_mac) { 1582104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1583104477Ssam dlen = cmd->maccrd->crd_len; 1584104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1585104477Ssam dlen >>= 16; 1586104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1587104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1588104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1589104477Ssam mac_cmd->reserved = 0; 1590104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1591104477Ssam } 1592104477Ssam 1593104477Ssam if (using_crypt) { 1594104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1595104477Ssam dlen = cmd->enccrd->crd_len; 1596104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1597104477Ssam dlen >>= 16; 1598104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1599104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1600104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1601104477Ssam cry_cmd->reserved = 0; 1602104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1603104477Ssam } 1604104477Ssam 1605104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1606104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1607104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1608104477Ssam } 1609104477Ssam 1610104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1611104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1612104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1613104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1614104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1615104477Ssam break; 1616104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1617104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1618120915Ssam buf_pos += HIFN_DES_KEY_LENGTH; 1619104477Ssam break; 1620104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1621104477Ssam len = 256; 1622104477Ssam do { 1623104477Ssam int clen; 1624104477Ssam 1625104477Ssam clen = MIN(cmd->cklen, len); 1626104477Ssam bcopy(cmd->ck, buf_pos, clen); 1627104477Ssam len -= clen; 1628104477Ssam buf_pos += clen; 1629104477Ssam } while (len > 0); 1630104477Ssam bzero(buf_pos, 4); 1631104477Ssam buf_pos += 4; 1632104477Ssam break; 1633120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1634120915Ssam /* 1635120915Ssam * AES keys are variable 128, 192 and 1636120915Ssam * 256 bits (16, 24 and 32 bytes). 1637120915Ssam */ 1638120915Ssam bcopy(cmd->ck, buf_pos, cmd->cklen); 1639120915Ssam buf_pos += cmd->cklen; 1640120915Ssam break; 1641104477Ssam } 1642104477Ssam } 1643104477Ssam 1644104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1645120915Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1646120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1647120915Ssam ivlen = HIFN_AES_IV_LENGTH; 1648120915Ssam break; 1649120915Ssam default: 1650120915Ssam ivlen = HIFN_IV_LENGTH; 1651120915Ssam break; 1652120915Ssam } 1653120915Ssam bcopy(cmd->iv, buf_pos, ivlen); 1654120915Ssam buf_pos += ivlen; 1655104477Ssam } 1656104477Ssam 1657104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1658104477Ssam bzero(buf_pos, 8); 1659104477Ssam buf_pos += 8; 1660104477Ssam } 1661104477Ssam 1662104477Ssam return (buf_pos - buf); 1663104477Ssam} 1664104477Ssam 1665104477Ssamstatic int 1666104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1667104477Ssam{ 1668104477Ssam int i; 1669104477Ssam 1670104477Ssam for (i = 0; i < op->nsegs; i++) { 1671104477Ssam if (op->segs[i].ds_addr & 3) 1672104477Ssam return (0); 1673104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1674104477Ssam return (0); 1675104477Ssam } 1676104477Ssam return (1); 1677104477Ssam} 1678104477Ssam 1679104477Ssamstatic int 1680104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1681104477Ssam{ 1682104477Ssam struct hifn_dma *dma = sc->sc_dma; 1683104477Ssam struct hifn_operand *dst = &cmd->dst; 1684104477Ssam u_int32_t p, l; 1685104477Ssam int idx, used = 0, i; 1686104477Ssam 1687104477Ssam idx = dma->dsti; 1688104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1689104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1690104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1691104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1692104477Ssam HIFN_DSTR_SYNC(sc, idx, 1693104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1694104477Ssam used++; 1695104477Ssam 1696104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1697104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1698104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1699104477Ssam HIFN_DSTR_SYNC(sc, idx, 1700104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1701104477Ssam idx = 0; 1702104477Ssam } 1703104477Ssam } 1704104477Ssam 1705104477Ssam if (cmd->sloplen == 0) { 1706104477Ssam p = dst->segs[i].ds_addr; 1707104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1708104477Ssam dst->segs[i].ds_len; 1709104477Ssam } else { 1710104477Ssam p = sc->sc_dma_physaddr + 1711104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1712104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1713104477Ssam sizeof(u_int32_t); 1714104477Ssam 1715104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1716104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1717104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1718104477Ssam HIFN_D_MASKDONEIRQ | 1719104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1720104477Ssam HIFN_DSTR_SYNC(sc, idx, 1721104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1722104477Ssam used++; 1723104477Ssam 1724104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1725104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1726104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1727104477Ssam HIFN_DSTR_SYNC(sc, idx, 1728104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1729104477Ssam idx = 0; 1730104477Ssam } 1731104477Ssam } 1732104477Ssam } 1733104477Ssam dma->dstr[idx].p = htole32(p); 1734104477Ssam dma->dstr[idx].l = htole32(l); 1735104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1736104477Ssam used++; 1737104477Ssam 1738104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1739104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1740104477Ssam HIFN_D_MASKDONEIRQ); 1741104477Ssam HIFN_DSTR_SYNC(sc, idx, 1742104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1743104477Ssam idx = 0; 1744104477Ssam } 1745104477Ssam 1746104477Ssam dma->dsti = idx; 1747104477Ssam dma->dstu += used; 1748104477Ssam return (idx); 1749104477Ssam} 1750104477Ssam 1751104477Ssamstatic int 1752104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1753104477Ssam{ 1754104477Ssam struct hifn_dma *dma = sc->sc_dma; 1755104477Ssam struct hifn_operand *src = &cmd->src; 1756104477Ssam int idx, i; 1757104477Ssam u_int32_t last = 0; 1758104477Ssam 1759104477Ssam idx = dma->srci; 1760104477Ssam for (i = 0; i < src->nsegs; i++) { 1761104477Ssam if (i == src->nsegs - 1) 1762104477Ssam last = HIFN_D_LAST; 1763104477Ssam 1764104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1765104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1766104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1767104477Ssam HIFN_SRCR_SYNC(sc, idx, 1768104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1769104477Ssam 1770104477Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1771104477Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1772104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1773104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1774104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1775104477Ssam idx = 0; 1776104477Ssam } 1777104477Ssam } 1778104477Ssam dma->srci = idx; 1779104477Ssam dma->srcu += src->nsegs; 1780104477Ssam return (idx); 1781104477Ssam} 1782104477Ssam 1783104477Ssamstatic void 1784104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1785104477Ssam{ 1786104477Ssam struct hifn_operand *op = arg; 1787104477Ssam 1788104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1789104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1790104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1791104477Ssam op->mapsize = mapsize; 1792104477Ssam op->nsegs = nsegs; 1793104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1794104477Ssam} 1795104477Ssam 1796104477Ssamstatic int 1797104477Ssamhifn_crypto( 1798104477Ssam struct hifn_softc *sc, 1799104477Ssam struct hifn_command *cmd, 1800104477Ssam struct cryptop *crp, 1801104477Ssam int hint) 1802104477Ssam{ 1803104477Ssam struct hifn_dma *dma = sc->sc_dma; 1804104477Ssam u_int32_t cmdlen; 1805104477Ssam int cmdi, resi, err = 0; 1806104477Ssam 1807104477Ssam /* 1808104477Ssam * need 1 cmd, and 1 res 1809104477Ssam * 1810104477Ssam * NB: check this first since it's easy. 1811104477Ssam */ 1812115748Ssam HIFN_LOCK(sc); 1813104477Ssam if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1814104477Ssam (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1815104477Ssam#ifdef HIFN_DEBUG 1816104477Ssam if (hifn_debug) { 1817104477Ssam device_printf(sc->sc_dev, 1818104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1819104477Ssam dma->cmdu, dma->resu); 1820104477Ssam } 1821104477Ssam#endif 1822104477Ssam hifnstats.hst_nomem_cr++; 1823115748Ssam HIFN_UNLOCK(sc); 1824104477Ssam return (ERESTART); 1825104477Ssam } 1826104477Ssam 1827104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1828104477Ssam hifnstats.hst_nomem_map++; 1829115748Ssam HIFN_UNLOCK(sc); 1830104477Ssam return (ENOMEM); 1831104477Ssam } 1832104477Ssam 1833104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1834104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1835104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1836104477Ssam hifnstats.hst_nomem_load++; 1837104477Ssam err = ENOMEM; 1838104477Ssam goto err_srcmap1; 1839104477Ssam } 1840104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1841104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1842104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1843104477Ssam hifnstats.hst_nomem_load++; 1844104477Ssam err = ENOMEM; 1845104477Ssam goto err_srcmap1; 1846104477Ssam } 1847104477Ssam } else { 1848104477Ssam err = EINVAL; 1849104477Ssam goto err_srcmap1; 1850104477Ssam } 1851104477Ssam 1852104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1853104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1854104477Ssam cmd->dst = cmd->src; 1855104477Ssam } else { 1856104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1857104477Ssam err = EINVAL; 1858104477Ssam goto err_srcmap; 1859104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1860104477Ssam int totlen, len; 1861104477Ssam struct mbuf *m, *m0, *mlast; 1862104477Ssam 1863104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1864104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1865104477Ssam hifnstats.hst_unaligned++; 1866104477Ssam /* 1867104477Ssam * Source is not aligned on a longword boundary. 1868104477Ssam * Copy the data to insure alignment. If we fail 1869104477Ssam * to allocate mbufs or clusters while doing this 1870104477Ssam * we return ERESTART so the operation is requeued 1871104477Ssam * at the crypto later, but only if there are 1872104477Ssam * ops already posted to the hardware; otherwise we 1873104477Ssam * have no guarantee that we'll be re-entered. 1874104477Ssam */ 1875104477Ssam totlen = cmd->src_mapsize; 1876104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1877104477Ssam len = MHLEN; 1878111119Simp MGETHDR(m0, M_DONTWAIT, MT_DATA); 1879111119Simp if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1880108466Ssam m_free(m0); 1881108466Ssam m0 = NULL; 1882108466Ssam } 1883104477Ssam } else { 1884104477Ssam len = MLEN; 1885111119Simp MGET(m0, M_DONTWAIT, MT_DATA); 1886104477Ssam } 1887104477Ssam if (m0 == NULL) { 1888104477Ssam hifnstats.hst_nomem_mbuf++; 1889104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1890104477Ssam goto err_srcmap; 1891104477Ssam } 1892104477Ssam if (totlen >= MINCLSIZE) { 1893111119Simp MCLGET(m0, M_DONTWAIT); 1894104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1895104477Ssam hifnstats.hst_nomem_mcl++; 1896104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1897104477Ssam m_freem(m0); 1898104477Ssam goto err_srcmap; 1899104477Ssam } 1900104477Ssam len = MCLBYTES; 1901104477Ssam } 1902104477Ssam totlen -= len; 1903104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1904104477Ssam mlast = m0; 1905104477Ssam 1906104477Ssam while (totlen > 0) { 1907111119Simp MGET(m, M_DONTWAIT, MT_DATA); 1908104477Ssam if (m == NULL) { 1909104477Ssam hifnstats.hst_nomem_mbuf++; 1910104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1911104477Ssam m_freem(m0); 1912104477Ssam goto err_srcmap; 1913104477Ssam } 1914104477Ssam len = MLEN; 1915104477Ssam if (totlen >= MINCLSIZE) { 1916111119Simp MCLGET(m, M_DONTWAIT); 1917104477Ssam if ((m->m_flags & M_EXT) == 0) { 1918104477Ssam hifnstats.hst_nomem_mcl++; 1919104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1920104477Ssam mlast->m_next = m; 1921104477Ssam m_freem(m0); 1922104477Ssam goto err_srcmap; 1923104477Ssam } 1924104477Ssam len = MCLBYTES; 1925104477Ssam } 1926104477Ssam 1927104477Ssam m->m_len = len; 1928104477Ssam m0->m_pkthdr.len += len; 1929104477Ssam totlen -= len; 1930104477Ssam 1931104477Ssam mlast->m_next = m; 1932104477Ssam mlast = m; 1933104477Ssam } 1934104477Ssam cmd->dst_m = m0; 1935104477Ssam } 1936104477Ssam } 1937104477Ssam 1938104477Ssam if (cmd->dst_map == NULL) { 1939104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1940104477Ssam hifnstats.hst_nomem_map++; 1941104477Ssam err = ENOMEM; 1942104477Ssam goto err_srcmap; 1943104477Ssam } 1944104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1945104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1946104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1947104477Ssam hifnstats.hst_nomem_map++; 1948104477Ssam err = ENOMEM; 1949104477Ssam goto err_dstmap1; 1950104477Ssam } 1951104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1952104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1953104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1954104477Ssam hifnstats.hst_nomem_load++; 1955104477Ssam err = ENOMEM; 1956104477Ssam goto err_dstmap1; 1957104477Ssam } 1958104477Ssam } 1959104477Ssam } 1960104477Ssam 1961104477Ssam#ifdef HIFN_DEBUG 1962104477Ssam if (hifn_debug) { 1963104477Ssam device_printf(sc->sc_dev, 1964104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1965104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1966104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1967104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1968104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1969104477Ssam } 1970104477Ssam#endif 1971104477Ssam 1972104477Ssam if (cmd->src_map == cmd->dst_map) { 1973104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1974104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1975104477Ssam } else { 1976104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1977104477Ssam BUS_DMASYNC_PREWRITE); 1978104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1979104477Ssam BUS_DMASYNC_PREREAD); 1980104477Ssam } 1981104477Ssam 1982104477Ssam /* 1983104477Ssam * need N src, and N dst 1984104477Ssam */ 1985104477Ssam if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1986104477Ssam (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1987104477Ssam#ifdef HIFN_DEBUG 1988104477Ssam if (hifn_debug) { 1989104477Ssam device_printf(sc->sc_dev, 1990104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1991104477Ssam dma->srcu, cmd->src_nsegs, 1992104477Ssam dma->dstu, cmd->dst_nsegs); 1993104477Ssam } 1994104477Ssam#endif 1995104477Ssam hifnstats.hst_nomem_sd++; 1996104477Ssam err = ERESTART; 1997104477Ssam goto err_dstmap; 1998104477Ssam } 1999104477Ssam 2000104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 2001104477Ssam dma->cmdi = 0; 2002104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 2003104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2004104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 2005104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2006104477Ssam } 2007104477Ssam cmdi = dma->cmdi++; 2008104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 2009104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 2010104477Ssam 2011104477Ssam /* .p for command/result already set */ 2012104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 2013104477Ssam HIFN_D_MASKDONEIRQ); 2014104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 2015104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2016104477Ssam dma->cmdu++; 2017104477Ssam if (sc->sc_c_busy == 0) { 2018104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 2019104477Ssam sc->sc_c_busy = 1; 2020104477Ssam } 2021104477Ssam 2022104477Ssam /* 2023104477Ssam * We don't worry about missing an interrupt (which a "command wait" 2024104477Ssam * interrupt salvages us from), unless there is more than one command 2025104477Ssam * in the queue. 2026104477Ssam */ 2027104477Ssam if (dma->cmdu > 1) { 2028104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 2029104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2030104477Ssam } 2031104477Ssam 2032104477Ssam hifnstats.hst_ipackets++; 2033104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 2034104477Ssam 2035104477Ssam hifn_dmamap_load_src(sc, cmd); 2036104477Ssam if (sc->sc_s_busy == 0) { 2037104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 2038104477Ssam sc->sc_s_busy = 1; 2039104477Ssam } 2040104477Ssam 2041104477Ssam /* 2042104477Ssam * Unlike other descriptors, we don't mask done interrupt from 2043104477Ssam * result descriptor. 2044104477Ssam */ 2045104477Ssam#ifdef HIFN_DEBUG 2046104477Ssam if (hifn_debug) 2047104477Ssam printf("load res\n"); 2048104477Ssam#endif 2049104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 2050104477Ssam dma->resi = 0; 2051104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 2052104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2053104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 2054104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2055104477Ssam } 2056104477Ssam resi = dma->resi++; 2057104477Ssam KASSERT(dma->hifn_commands[resi] == NULL, 2058104477Ssam ("hifn_crypto: command slot %u busy", resi)); 2059104477Ssam dma->hifn_commands[resi] = cmd; 2060104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 2061104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 2062104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2063104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 2064104477Ssam sc->sc_curbatch++; 2065104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 2066104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 2067104477Ssam hifnstats.hst_totbatch++; 2068104477Ssam } else { 2069104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2070104477Ssam HIFN_D_VALID | HIFN_D_LAST); 2071104477Ssam sc->sc_curbatch = 0; 2072104477Ssam } 2073104477Ssam HIFN_RESR_SYNC(sc, resi, 2074104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2075104477Ssam dma->resu++; 2076104477Ssam if (sc->sc_r_busy == 0) { 2077104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 2078104477Ssam sc->sc_r_busy = 1; 2079104477Ssam } 2080104477Ssam 2081104477Ssam if (cmd->sloplen) 2082104477Ssam cmd->slopidx = resi; 2083104477Ssam 2084104477Ssam hifn_dmamap_load_dst(sc, cmd); 2085104477Ssam 2086104477Ssam if (sc->sc_d_busy == 0) { 2087104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 2088104477Ssam sc->sc_d_busy = 1; 2089104477Ssam } 2090104477Ssam 2091104477Ssam#ifdef HIFN_DEBUG 2092104477Ssam if (hifn_debug) { 2093104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 2094104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 2095104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 2096104477Ssam } 2097104477Ssam#endif 2098104477Ssam 2099104477Ssam sc->sc_active = 5; 2100115748Ssam HIFN_UNLOCK(sc); 2101104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 2102104477Ssam return (err); /* success */ 2103104477Ssam 2104104477Ssamerr_dstmap: 2105104477Ssam if (cmd->src_map != cmd->dst_map) 2106104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2107104477Ssamerr_dstmap1: 2108104477Ssam if (cmd->src_map != cmd->dst_map) 2109104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2110104477Ssamerr_srcmap: 2111104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2112104477Ssam if (cmd->src_m != cmd->dst_m) 2113104477Ssam m_freem(cmd->dst_m); 2114104477Ssam } 2115104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2116104477Ssamerr_srcmap1: 2117104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2118115748Ssam HIFN_UNLOCK(sc); 2119104477Ssam return (err); 2120104477Ssam} 2121104477Ssam 2122104477Ssamstatic void 2123104477Ssamhifn_tick(void* vsc) 2124104477Ssam{ 2125104477Ssam struct hifn_softc *sc = vsc; 2126104477Ssam 2127104477Ssam HIFN_LOCK(sc); 2128104477Ssam if (sc->sc_active == 0) { 2129104477Ssam struct hifn_dma *dma = sc->sc_dma; 2130104477Ssam u_int32_t r = 0; 2131104477Ssam 2132104477Ssam if (dma->cmdu == 0 && sc->sc_c_busy) { 2133104477Ssam sc->sc_c_busy = 0; 2134104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 2135104477Ssam } 2136104477Ssam if (dma->srcu == 0 && sc->sc_s_busy) { 2137104477Ssam sc->sc_s_busy = 0; 2138104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 2139104477Ssam } 2140104477Ssam if (dma->dstu == 0 && sc->sc_d_busy) { 2141104477Ssam sc->sc_d_busy = 0; 2142104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 2143104477Ssam } 2144104477Ssam if (dma->resu == 0 && sc->sc_r_busy) { 2145104477Ssam sc->sc_r_busy = 0; 2146104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 2147104477Ssam } 2148104477Ssam if (r) 2149104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2150104477Ssam } else 2151104477Ssam sc->sc_active--; 2152104477Ssam HIFN_UNLOCK(sc); 2153104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2154104477Ssam} 2155104477Ssam 2156104477Ssamstatic void 2157104477Ssamhifn_intr(void *arg) 2158104477Ssam{ 2159104477Ssam struct hifn_softc *sc = arg; 2160104477Ssam struct hifn_dma *dma; 2161104477Ssam u_int32_t dmacsr, restart; 2162104477Ssam int i, u; 2163104477Ssam 2164115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2165115748Ssam 2166115748Ssam /* Nothing in the DMA unit interrupted */ 2167115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 2168115748Ssam return; 2169115748Ssam 2170104477Ssam HIFN_LOCK(sc); 2171115748Ssam 2172104477Ssam dma = sc->sc_dma; 2173104477Ssam 2174104477Ssam#ifdef HIFN_DEBUG 2175104477Ssam if (hifn_debug) { 2176104477Ssam device_printf(sc->sc_dev, 2177104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2178104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2179104477Ssam dma->cmdi, dma->srci, dma->dsti, dma->resi, 2180104477Ssam dma->cmdk, dma->srck, dma->dstk, dma->resk, 2181104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2182104477Ssam } 2183104477Ssam#endif 2184104477Ssam 2185104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2186104477Ssam 2187104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2188104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2189104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2190104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2191104477Ssam 2192104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2193104477Ssam if (restart) 2194104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2195104477Ssam 2196104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2197104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2198104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2199104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2200104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2201104477Ssam } 2202104477Ssam 2203104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2204104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2205104477Ssam if (restart) { 2206104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2207104477Ssam hifnstats.hst_abort++; 2208104477Ssam hifn_abort(sc); 2209104477Ssam HIFN_UNLOCK(sc); 2210104477Ssam return; 2211104477Ssam } 2212104477Ssam 2213104477Ssam if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2214104477Ssam /* 2215104477Ssam * If no slots to process and we receive a "waiting on 2216104477Ssam * command" interrupt, we disable the "waiting on command" 2217104477Ssam * (by clearing it). 2218104477Ssam */ 2219104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2220104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2221104477Ssam } 2222104477Ssam 2223104477Ssam /* clear the rings */ 2224104477Ssam i = dma->resk; u = dma->resu; 2225104477Ssam while (u != 0) { 2226104477Ssam HIFN_RESR_SYNC(sc, i, 2227104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2228104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2229104477Ssam HIFN_RESR_SYNC(sc, i, 2230104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2231104477Ssam break; 2232104477Ssam } 2233104477Ssam 2234104477Ssam if (i != HIFN_D_RES_RSIZE) { 2235104477Ssam struct hifn_command *cmd; 2236104477Ssam u_int8_t *macbuf = NULL; 2237104477Ssam 2238104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2239104477Ssam cmd = dma->hifn_commands[i]; 2240104477Ssam KASSERT(cmd != NULL, 2241104477Ssam ("hifn_intr: null command slot %u", i)); 2242104477Ssam dma->hifn_commands[i] = NULL; 2243104477Ssam 2244104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2245104477Ssam macbuf = dma->result_bufs[i]; 2246104477Ssam macbuf += 12; 2247104477Ssam } 2248104477Ssam 2249104477Ssam hifn_callback(sc, cmd, macbuf); 2250104477Ssam hifnstats.hst_opackets++; 2251104477Ssam u--; 2252104477Ssam } 2253104477Ssam 2254104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2255104477Ssam i = 0; 2256104477Ssam } 2257104477Ssam dma->resk = i; dma->resu = u; 2258104477Ssam 2259104477Ssam i = dma->srck; u = dma->srcu; 2260104477Ssam while (u != 0) { 2261104477Ssam if (i == HIFN_D_SRC_RSIZE) 2262104477Ssam i = 0; 2263104477Ssam HIFN_SRCR_SYNC(sc, i, 2264104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2265104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2266104477Ssam HIFN_SRCR_SYNC(sc, i, 2267104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2268104477Ssam break; 2269104477Ssam } 2270104477Ssam i++, u--; 2271104477Ssam } 2272104477Ssam dma->srck = i; dma->srcu = u; 2273104477Ssam 2274104477Ssam i = dma->cmdk; u = dma->cmdu; 2275104477Ssam while (u != 0) { 2276104477Ssam HIFN_CMDR_SYNC(sc, i, 2277104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2278104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2279104477Ssam HIFN_CMDR_SYNC(sc, i, 2280104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2281104477Ssam break; 2282104477Ssam } 2283104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2284104477Ssam u--; 2285104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2286104477Ssam } 2287104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2288104477Ssam i = 0; 2289104477Ssam } 2290104477Ssam dma->cmdk = i; dma->cmdu = u; 2291104477Ssam 2292115748Ssam HIFN_UNLOCK(sc); 2293115748Ssam 2294104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2295104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2296104477Ssam#ifdef HIFN_DEBUG 2297104477Ssam if (hifn_debug) 2298104477Ssam device_printf(sc->sc_dev, 2299104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2300104477Ssam sc->sc_needwakeup, 2301104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2302104477Ssam#endif 2303104477Ssam sc->sc_needwakeup &= ~wakeup; 2304104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2305104477Ssam } 2306104477Ssam} 2307104477Ssam 2308104477Ssam/* 2309104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2310104477Ssam * contains our registration id, and should contain an encoded session 2311104477Ssam * id on successful allocation. 2312104477Ssam */ 2313104477Ssamstatic int 2314104477Ssamhifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2315104477Ssam{ 2316104477Ssam struct cryptoini *c; 2317104477Ssam struct hifn_softc *sc = arg; 2318136526Ssam int mac = 0, cry = 0, sesn; 2319136532Ssam struct hifn_session *ses = NULL; 2320104477Ssam 2321104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2322104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2323104477Ssam return (EINVAL); 2324104477Ssam 2325136526Ssam if (sc->sc_sessions == NULL) { 2326136526Ssam ses = sc->sc_sessions = (struct hifn_session *)malloc( 2327136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2328136526Ssam if (ses == NULL) 2329136526Ssam return (ENOMEM); 2330136526Ssam sesn = 0; 2331136526Ssam sc->sc_nsessions = 1; 2332136526Ssam } else { 2333136526Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 2334136526Ssam if (!sc->sc_sessions[sesn].hs_used) { 2335136526Ssam ses = &sc->sc_sessions[sesn]; 2336136526Ssam break; 2337136526Ssam } 2338136526Ssam } 2339104477Ssam 2340136526Ssam if (ses == NULL) { 2341136526Ssam sesn = sc->sc_nsessions; 2342136526Ssam ses = (struct hifn_session *)malloc((sesn + 1) * 2343136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2344136526Ssam if (ses == NULL) 2345136526Ssam return (ENOMEM); 2346136526Ssam bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 2347136526Ssam bzero(sc->sc_sessions, sesn * sizeof(*ses)); 2348136526Ssam free(sc->sc_sessions, M_DEVBUF); 2349136526Ssam sc->sc_sessions = ses; 2350136526Ssam ses = &sc->sc_sessions[sesn]; 2351136526Ssam sc->sc_nsessions++; 2352136526Ssam } 2353136526Ssam } 2354136526Ssam bzero(ses, sizeof(*ses)); 2355136526Ssam ses->hs_used = 1; 2356136526Ssam 2357104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2358104477Ssam switch (c->cri_alg) { 2359104477Ssam case CRYPTO_MD5: 2360104477Ssam case CRYPTO_SHA1: 2361104477Ssam case CRYPTO_MD5_HMAC: 2362104477Ssam case CRYPTO_SHA1_HMAC: 2363104477Ssam if (mac) 2364104477Ssam return (EINVAL); 2365104477Ssam mac = 1; 2366104477Ssam break; 2367104477Ssam case CRYPTO_DES_CBC: 2368104477Ssam case CRYPTO_3DES_CBC: 2369120915Ssam case CRYPTO_AES_CBC: 2370104477Ssam /* XXX this may read fewer, does it matter? */ 2371136526Ssam read_random(ses->hs_iv, 2372120915Ssam c->cri_alg == CRYPTO_AES_CBC ? 2373120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2374104477Ssam /*FALLTHROUGH*/ 2375104477Ssam case CRYPTO_ARC4: 2376104477Ssam if (cry) 2377104477Ssam return (EINVAL); 2378104477Ssam cry = 1; 2379104477Ssam break; 2380104477Ssam default: 2381104477Ssam return (EINVAL); 2382104477Ssam } 2383104477Ssam } 2384104477Ssam if (mac == 0 && cry == 0) 2385104477Ssam return (EINVAL); 2386104477Ssam 2387136526Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); 2388104477Ssam 2389104477Ssam return (0); 2390104477Ssam} 2391104477Ssam 2392104477Ssam/* 2393104477Ssam * Deallocate a session. 2394104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2395104477Ssam * XXX to blow away any keys already stored there. 2396104477Ssam */ 2397104477Ssamstatic int 2398104477Ssamhifn_freesession(void *arg, u_int64_t tid) 2399104477Ssam{ 2400104477Ssam struct hifn_softc *sc = arg; 2401104477Ssam int session; 2402116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2403104477Ssam 2404104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2405104477Ssam if (sc == NULL) 2406104477Ssam return (EINVAL); 2407104477Ssam 2408104477Ssam session = HIFN_SESSION(sid); 2409136526Ssam if (session >= sc->sc_nsessions) 2410104477Ssam return (EINVAL); 2411104477Ssam 2412104477Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2413104477Ssam return (0); 2414104477Ssam} 2415104477Ssam 2416104477Ssamstatic int 2417104477Ssamhifn_process(void *arg, struct cryptop *crp, int hint) 2418104477Ssam{ 2419104477Ssam struct hifn_softc *sc = arg; 2420104477Ssam struct hifn_command *cmd = NULL; 2421120915Ssam int session, err, ivlen; 2422104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2423104477Ssam 2424104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2425104477Ssam hifnstats.hst_invalid++; 2426104477Ssam return (EINVAL); 2427104477Ssam } 2428104477Ssam session = HIFN_SESSION(crp->crp_sid); 2429104477Ssam 2430136526Ssam if (sc == NULL || session >= sc->sc_nsessions) { 2431104477Ssam err = EINVAL; 2432104477Ssam goto errout; 2433104477Ssam } 2434104477Ssam 2435104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2436104477Ssam if (cmd == NULL) { 2437104477Ssam hifnstats.hst_nomem++; 2438104477Ssam err = ENOMEM; 2439104477Ssam goto errout; 2440104477Ssam } 2441104477Ssam 2442104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2443104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2444104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2445104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2446104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2447104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2448104477Ssam } else { 2449104477Ssam err = EINVAL; 2450104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2451104477Ssam } 2452104477Ssam 2453104477Ssam crd1 = crp->crp_desc; 2454104477Ssam if (crd1 == NULL) { 2455104477Ssam err = EINVAL; 2456104477Ssam goto errout; 2457104477Ssam } 2458104477Ssam crd2 = crd1->crd_next; 2459104477Ssam 2460104477Ssam if (crd2 == NULL) { 2461104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2462104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2463104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2464104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2465104477Ssam maccrd = crd1; 2466104477Ssam enccrd = NULL; 2467104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2468104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2469120915Ssam crd1->crd_alg == CRYPTO_AES_CBC || 2470104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2471104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2472104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2473104477Ssam maccrd = NULL; 2474104477Ssam enccrd = crd1; 2475104477Ssam } else { 2476104477Ssam err = EINVAL; 2477104477Ssam goto errout; 2478104477Ssam } 2479104477Ssam } else { 2480104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2481104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2482104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2483104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2484104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2485104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2486120915Ssam crd2->crd_alg == CRYPTO_AES_CBC || 2487104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2488104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2489104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2490104477Ssam maccrd = crd1; 2491104477Ssam enccrd = crd2; 2492104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2493104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2494120915Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2495120915Ssam crd1->crd_alg == CRYPTO_AES_CBC) && 2496104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2497104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2498104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2499104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2500104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2501104477Ssam enccrd = crd1; 2502104477Ssam maccrd = crd2; 2503104477Ssam } else { 2504104477Ssam /* 2505104477Ssam * We cannot order the 7751 as requested 2506104477Ssam */ 2507104477Ssam err = EINVAL; 2508104477Ssam goto errout; 2509104477Ssam } 2510104477Ssam } 2511104477Ssam 2512104477Ssam if (enccrd) { 2513104477Ssam cmd->enccrd = enccrd; 2514104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2515104477Ssam switch (enccrd->crd_alg) { 2516104477Ssam case CRYPTO_ARC4: 2517104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2518104477Ssam break; 2519104477Ssam case CRYPTO_DES_CBC: 2520104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2521104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2522104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2523104477Ssam break; 2524104477Ssam case CRYPTO_3DES_CBC: 2525104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2526104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2527104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2528104477Ssam break; 2529120915Ssam case CRYPTO_AES_CBC: 2530120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2531120915Ssam HIFN_CRYPT_CMD_MODE_CBC | 2532120915Ssam HIFN_CRYPT_CMD_NEW_IV; 2533120915Ssam break; 2534104477Ssam default: 2535104477Ssam err = EINVAL; 2536104477Ssam goto errout; 2537104477Ssam } 2538104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2539120915Ssam ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2540120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2541104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2542104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2543120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2544104477Ssam else 2545104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2546120915Ssam cmd->iv, ivlen); 2547104477Ssam 2548104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2549104477Ssam == 0) { 2550104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2551104477Ssam m_copyback(cmd->src_m, 2552104477Ssam enccrd->crd_inject, 2553120915Ssam ivlen, cmd->iv); 2554104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2555104477Ssam cuio_copyback(cmd->src_io, 2556104477Ssam enccrd->crd_inject, 2557120915Ssam ivlen, cmd->iv); 2558104477Ssam } 2559104477Ssam } else { 2560104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2561120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2562104477Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 2563104477Ssam m_copydata(cmd->src_m, 2564120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2565104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2566104477Ssam cuio_copydata(cmd->src_io, 2567120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2568104477Ssam } 2569104477Ssam } 2570104477Ssam 2571125330Sphk if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2572125330Sphk cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2573104477Ssam cmd->ck = enccrd->crd_key; 2574104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2575136526Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2576104477Ssam 2577120915Ssam /* 2578120915Ssam * Need to specify the size for the AES key in the masks. 2579120915Ssam */ 2580120915Ssam if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2581120915Ssam HIFN_CRYPT_CMD_ALG_AES) { 2582120915Ssam switch (cmd->cklen) { 2583120915Ssam case 16: 2584120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2585120915Ssam break; 2586120915Ssam case 24: 2587120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2588120915Ssam break; 2589120915Ssam case 32: 2590120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2591120915Ssam break; 2592120915Ssam default: 2593120915Ssam err = EINVAL; 2594120915Ssam goto errout; 2595120915Ssam } 2596120915Ssam } 2597104477Ssam } 2598104477Ssam 2599104477Ssam if (maccrd) { 2600104477Ssam cmd->maccrd = maccrd; 2601104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2602104477Ssam 2603104477Ssam switch (maccrd->crd_alg) { 2604104477Ssam case CRYPTO_MD5: 2605104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2606104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2607104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2608104477Ssam break; 2609104477Ssam case CRYPTO_MD5_HMAC: 2610104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2611104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2612104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2613104477Ssam break; 2614104477Ssam case CRYPTO_SHA1: 2615104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2616104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2617104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2618104477Ssam break; 2619104477Ssam case CRYPTO_SHA1_HMAC: 2620104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2621104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2622104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2623104477Ssam break; 2624104477Ssam } 2625104477Ssam 2626136526Ssam if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2627136526Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) { 2628104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2629104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2630104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2631104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2632104477Ssam } 2633104477Ssam } 2634104477Ssam 2635104477Ssam cmd->crp = crp; 2636104477Ssam cmd->session_num = session; 2637104477Ssam cmd->softc = sc; 2638104477Ssam 2639104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2640104477Ssam if (!err) { 2641104477Ssam return 0; 2642104477Ssam } else if (err == ERESTART) { 2643104477Ssam /* 2644104477Ssam * There weren't enough resources to dispatch the request 2645104477Ssam * to the part. Notify the caller so they'll requeue this 2646104477Ssam * request and resubmit it again soon. 2647104477Ssam */ 2648104477Ssam#ifdef HIFN_DEBUG 2649104477Ssam if (hifn_debug) 2650104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2651104477Ssam#endif 2652104477Ssam free(cmd, M_DEVBUF); 2653104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2654104477Ssam return (err); 2655104477Ssam } 2656104477Ssam 2657104477Ssamerrout: 2658104477Ssam if (cmd != NULL) 2659104477Ssam free(cmd, M_DEVBUF); 2660104477Ssam if (err == EINVAL) 2661104477Ssam hifnstats.hst_invalid++; 2662104477Ssam else 2663104477Ssam hifnstats.hst_nomem++; 2664104477Ssam crp->crp_etype = err; 2665104477Ssam crypto_done(crp); 2666104477Ssam return (err); 2667104477Ssam} 2668104477Ssam 2669104477Ssamstatic void 2670104477Ssamhifn_abort(struct hifn_softc *sc) 2671104477Ssam{ 2672104477Ssam struct hifn_dma *dma = sc->sc_dma; 2673104477Ssam struct hifn_command *cmd; 2674104477Ssam struct cryptop *crp; 2675104477Ssam int i, u; 2676104477Ssam 2677104477Ssam i = dma->resk; u = dma->resu; 2678104477Ssam while (u != 0) { 2679104477Ssam cmd = dma->hifn_commands[i]; 2680104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2681104477Ssam dma->hifn_commands[i] = NULL; 2682104477Ssam crp = cmd->crp; 2683104477Ssam 2684104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2685104477Ssam /* Salvage what we can. */ 2686104477Ssam u_int8_t *macbuf; 2687104477Ssam 2688104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2689104477Ssam macbuf = dma->result_bufs[i]; 2690104477Ssam macbuf += 12; 2691104477Ssam } else 2692104477Ssam macbuf = NULL; 2693104477Ssam hifnstats.hst_opackets++; 2694104477Ssam hifn_callback(sc, cmd, macbuf); 2695104477Ssam } else { 2696104477Ssam if (cmd->src_map == cmd->dst_map) { 2697104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2698104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2699104477Ssam } else { 2700104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2701104477Ssam BUS_DMASYNC_POSTWRITE); 2702104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2703104477Ssam BUS_DMASYNC_POSTREAD); 2704104477Ssam } 2705104477Ssam 2706104477Ssam if (cmd->src_m != cmd->dst_m) { 2707104477Ssam m_freem(cmd->src_m); 2708104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2709104477Ssam } 2710104477Ssam 2711104477Ssam /* non-shared buffers cannot be restarted */ 2712104477Ssam if (cmd->src_map != cmd->dst_map) { 2713104477Ssam /* 2714104477Ssam * XXX should be EAGAIN, delayed until 2715104477Ssam * after the reset. 2716104477Ssam */ 2717104477Ssam crp->crp_etype = ENOMEM; 2718104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2719104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2720104477Ssam } else 2721104477Ssam crp->crp_etype = ENOMEM; 2722104477Ssam 2723104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2724104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2725104477Ssam 2726104477Ssam free(cmd, M_DEVBUF); 2727104477Ssam if (crp->crp_etype != EAGAIN) 2728104477Ssam crypto_done(crp); 2729104477Ssam } 2730104477Ssam 2731104477Ssam if (++i == HIFN_D_RES_RSIZE) 2732104477Ssam i = 0; 2733104477Ssam u--; 2734104477Ssam } 2735104477Ssam dma->resk = i; dma->resu = u; 2736104477Ssam 2737104477Ssam hifn_reset_board(sc, 1); 2738104477Ssam hifn_init_dma(sc); 2739104477Ssam hifn_init_pci_registers(sc); 2740104477Ssam} 2741104477Ssam 2742104477Ssamstatic void 2743104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2744104477Ssam{ 2745104477Ssam struct hifn_dma *dma = sc->sc_dma; 2746104477Ssam struct cryptop *crp = cmd->crp; 2747104477Ssam struct cryptodesc *crd; 2748104477Ssam struct mbuf *m; 2749120915Ssam int totlen, i, u, ivlen; 2750104477Ssam 2751104477Ssam if (cmd->src_map == cmd->dst_map) { 2752104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2753104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2754104477Ssam } else { 2755104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2756104477Ssam BUS_DMASYNC_POSTWRITE); 2757104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2758104477Ssam BUS_DMASYNC_POSTREAD); 2759104477Ssam } 2760104477Ssam 2761104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2762104477Ssam if (cmd->src_m != cmd->dst_m) { 2763104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2764104477Ssam totlen = cmd->src_mapsize; 2765104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2766104477Ssam if (totlen < m->m_len) { 2767104477Ssam m->m_len = totlen; 2768104477Ssam totlen = 0; 2769104477Ssam } else 2770104477Ssam totlen -= m->m_len; 2771104477Ssam } 2772104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2773104477Ssam m_freem(cmd->src_m); 2774104477Ssam } 2775104477Ssam } 2776104477Ssam 2777104477Ssam if (cmd->sloplen != 0) { 2778104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2779104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2780104477Ssam cmd->src_mapsize - cmd->sloplen, 2781104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2782104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2783104477Ssam cuio_copyback((struct uio *)crp->crp_buf, 2784104477Ssam cmd->src_mapsize - cmd->sloplen, 2785104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2786104477Ssam } 2787104477Ssam 2788104477Ssam i = dma->dstk; u = dma->dstu; 2789104477Ssam while (u != 0) { 2790104477Ssam if (i == HIFN_D_DST_RSIZE) 2791104477Ssam i = 0; 2792104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2793104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2794104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2795104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2796104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2797104477Ssam break; 2798104477Ssam } 2799104477Ssam i++, u--; 2800104477Ssam } 2801104477Ssam dma->dstk = i; dma->dstu = u; 2802104477Ssam 2803104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2804104477Ssam 2805104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2806104477Ssam HIFN_BASE_CMD_CRYPT) { 2807104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2808104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2809120915Ssam crd->crd_alg != CRYPTO_3DES_CBC && 2810120915Ssam crd->crd_alg != CRYPTO_AES_CBC) 2811104477Ssam continue; 2812120915Ssam ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2813120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2814104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2815104477Ssam m_copydata((struct mbuf *)crp->crp_buf, 2816120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2817104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2818104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) { 2819104477Ssam cuio_copydata((struct uio *)crp->crp_buf, 2820120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2821104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2822104477Ssam } 2823104477Ssam break; 2824104477Ssam } 2825104477Ssam } 2826104477Ssam 2827104477Ssam if (macbuf != NULL) { 2828104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2829105275Ssam int len; 2830104477Ssam 2831105275Ssam if (crd->crd_alg == CRYPTO_MD5) 2832105275Ssam len = 16; 2833105275Ssam else if (crd->crd_alg == CRYPTO_SHA1) 2834105275Ssam len = 20; 2835105275Ssam else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2836105275Ssam crd->crd_alg == CRYPTO_SHA1_HMAC) 2837105275Ssam len = 12; 2838105275Ssam else 2839104477Ssam continue; 2840104477Ssam 2841104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2842104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2843104477Ssam crd->crd_inject, len, macbuf); 2844104477Ssam else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2845104477Ssam bcopy((caddr_t)macbuf, crp->crp_mac, len); 2846104477Ssam break; 2847104477Ssam } 2848104477Ssam } 2849104477Ssam 2850104477Ssam if (cmd->src_map != cmd->dst_map) { 2851104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2852104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2853104477Ssam } 2854104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2855104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2856104477Ssam free(cmd, M_DEVBUF); 2857104477Ssam crypto_done(crp); 2858104477Ssam} 2859104477Ssam 2860104477Ssam/* 2861104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2862104477Ssam * and Group 1 registers; avoid conditions that could create 2863104477Ssam * burst writes by doing a read in between the writes. 2864104477Ssam * 2865104477Ssam * NB: The read we interpose is always to the same register; 2866104477Ssam * we do this because reading from an arbitrary (e.g. last) 2867104477Ssam * register may not always work. 2868104477Ssam */ 2869104477Ssamstatic void 2870104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2871104477Ssam{ 2872104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2873104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2874104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2875104477Ssam sc->sc_bar0_lastreg = reg; 2876104477Ssam } 2877104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2878104477Ssam} 2879104477Ssam 2880104477Ssamstatic void 2881104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2882104477Ssam{ 2883104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2884104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2885104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2886104477Ssam sc->sc_bar1_lastreg = reg; 2887104477Ssam } 2888104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2889104477Ssam} 2890