hifn7751.c revision 131575
1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3104477Ssam/* 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9120915Ssam * Copyright (c) 2003 Hifn Inc. 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam */ 42104477Ssam 43119418Sobrien#include <sys/cdefs.h> 44119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/hifn/hifn7751.c 131575 2004-07-04 16:11:03Z stefanf $"); 45119418Sobrien 46104477Ssam/* 47120915Ssam * Driver for various Hifn encryption processors. 48104477Ssam */ 49112124Ssam#include "opt_hifn.h" 50104477Ssam 51104477Ssam#include <sys/param.h> 52104477Ssam#include <sys/systm.h> 53104477Ssam#include <sys/proc.h> 54104477Ssam#include <sys/errno.h> 55104477Ssam#include <sys/malloc.h> 56104477Ssam#include <sys/kernel.h> 57129879Sphk#include <sys/module.h> 58104477Ssam#include <sys/mbuf.h> 59104477Ssam#include <sys/lock.h> 60104477Ssam#include <sys/mutex.h> 61104477Ssam#include <sys/sysctl.h> 62104477Ssam 63104477Ssam#include <vm/vm.h> 64104477Ssam#include <vm/pmap.h> 65104477Ssam 66104477Ssam#include <machine/clock.h> 67104477Ssam#include <machine/bus.h> 68104477Ssam#include <machine/resource.h> 69104477Ssam#include <sys/bus.h> 70104477Ssam#include <sys/rman.h> 71104477Ssam 72104477Ssam#include <opencrypto/cryptodev.h> 73104477Ssam#include <sys/random.h> 74104477Ssam 75119280Simp#include <dev/pci/pcivar.h> 76119280Simp#include <dev/pci/pcireg.h> 77112124Ssam 78112124Ssam#ifdef HIFN_RNDTEST 79112124Ssam#include <dev/rndtest/rndtest.h> 80112124Ssam#endif 81104477Ssam#include <dev/hifn/hifn7751reg.h> 82104477Ssam#include <dev/hifn/hifn7751var.h> 83104477Ssam 84104477Ssam/* 85104477Ssam * Prototypes and count for the pci_device structure 86104477Ssam */ 87104477Ssamstatic int hifn_probe(device_t); 88104477Ssamstatic int hifn_attach(device_t); 89104477Ssamstatic int hifn_detach(device_t); 90104477Ssamstatic int hifn_suspend(device_t); 91104477Ssamstatic int hifn_resume(device_t); 92104477Ssamstatic void hifn_shutdown(device_t); 93104477Ssam 94104477Ssamstatic device_method_t hifn_methods[] = { 95104477Ssam /* Device interface */ 96104477Ssam DEVMETHOD(device_probe, hifn_probe), 97104477Ssam DEVMETHOD(device_attach, hifn_attach), 98104477Ssam DEVMETHOD(device_detach, hifn_detach), 99104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 100104477Ssam DEVMETHOD(device_resume, hifn_resume), 101104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 102104477Ssam 103104477Ssam /* bus interface */ 104104477Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 105104477Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 106104477Ssam 107104477Ssam { 0, 0 } 108104477Ssam}; 109104477Ssamstatic driver_t hifn_driver = { 110104477Ssam "hifn", 111104477Ssam hifn_methods, 112104477Ssam sizeof (struct hifn_softc) 113104477Ssam}; 114104477Ssamstatic devclass_t hifn_devclass; 115104477Ssam 116104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 117105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 118112124Ssam#ifdef HIFN_RNDTEST 119112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 120112124Ssam#endif 121104477Ssam 122104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 123104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 124104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 125104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 126104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 127104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 128104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 129104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 130104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 131104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 132104477Ssamstatic void hifn_sessions(struct hifn_softc *); 133104477Ssamstatic void hifn_intr(void *); 134104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 135104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 136104477Ssamstatic int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 137104477Ssamstatic int hifn_freesession(void *, u_int64_t); 138104477Ssamstatic int hifn_process(void *, struct cryptop *, int); 139104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 140104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 141104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 142104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 143104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 144104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 145104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 146104477Ssamstatic void hifn_rng(void *); 147104477Ssamstatic void hifn_tick(void *); 148104477Ssamstatic void hifn_abort(struct hifn_softc *); 149104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 150104477Ssam 151104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 152104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 153104477Ssam 154131575Sstefanfstatic __inline u_int32_t 155104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 156104477Ssam{ 157104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 158104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 159104477Ssam return (v); 160104477Ssam} 161104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 162104477Ssam 163131575Sstefanfstatic __inline u_int32_t 164104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 165104477Ssam{ 166104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 167104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 168104477Ssam return (v); 169104477Ssam} 170104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 171104477Ssam 172109596SsamSYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 173109596Ssam 174104477Ssam#ifdef HIFN_DEBUG 175104477Ssamstatic int hifn_debug = 0; 176109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 177109596Ssam 0, "control debugging msgs"); 178104477Ssam#endif 179104477Ssam 180104477Ssamstatic struct hifn_stats hifnstats; 181109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 182109596Ssam hifn_stats, "driver statistics"); 183112121Ssamstatic int hifn_maxbatch = 1; 184109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 185109596Ssam 0, "max ops to batch w/o interrupt"); 186104477Ssam 187104477Ssam/* 188104477Ssam * Probe for a supported device. The PCI vendor and device 189104477Ssam * IDs are used to detect devices we know how to handle. 190104477Ssam */ 191104477Ssamstatic int 192104477Ssamhifn_probe(device_t dev) 193104477Ssam{ 194104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 195104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 196104477Ssam return (0); 197104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 198104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 199104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 200120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 201120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 202104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 203104477Ssam return (0); 204104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 205104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 206104477Ssam return (0); 207104477Ssam return (ENXIO); 208104477Ssam} 209104477Ssam 210104477Ssamstatic void 211104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 212104477Ssam{ 213104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 214104477Ssam *paddr = segs->ds_addr; 215104477Ssam} 216104477Ssam 217104477Ssamstatic const char* 218104477Ssamhifn_partname(struct hifn_softc *sc) 219104477Ssam{ 220104477Ssam /* XXX sprintf numbers when not decoded */ 221104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 222104477Ssam case PCI_VENDOR_HIFN: 223104477Ssam switch (pci_get_device(sc->sc_dev)) { 224104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 225104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 226104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 227104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 228120915Ssam case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 229120915Ssam case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 230104477Ssam } 231104477Ssam return "Hifn unknown-part"; 232104477Ssam case PCI_VENDOR_INVERTEX: 233104477Ssam switch (pci_get_device(sc->sc_dev)) { 234104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 235104477Ssam } 236104477Ssam return "Invertex unknown-part"; 237104477Ssam case PCI_VENDOR_NETSEC: 238104477Ssam switch (pci_get_device(sc->sc_dev)) { 239104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 240104477Ssam } 241104477Ssam return "NetSec unknown-part"; 242104477Ssam } 243104477Ssam return "Unknown-vendor unknown-part"; 244104477Ssam} 245104477Ssam 246112124Ssamstatic void 247112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 248112124Ssam{ 249112124Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 250112124Ssam} 251112124Ssam 252104477Ssam/* 253104477Ssam * Attach an interface that successfully probed. 254104477Ssam */ 255104477Ssamstatic int 256104477Ssamhifn_attach(device_t dev) 257104477Ssam{ 258104477Ssam struct hifn_softc *sc = device_get_softc(dev); 259104477Ssam u_int32_t cmd; 260104477Ssam caddr_t kva; 261104477Ssam int rseg, rid; 262104477Ssam char rbase; 263104477Ssam u_int16_t ena, rev; 264104477Ssam 265104477Ssam KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 266104477Ssam bzero(sc, sizeof (*sc)); 267104477Ssam sc->sc_dev = dev; 268104477Ssam 269115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 270104477Ssam 271104477Ssam /* XXX handle power management */ 272104477Ssam 273104477Ssam /* 274120915Ssam * The 7951 and 795x have a random number generator and 275104477Ssam * public key support; note this. 276104477Ssam */ 277104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 278120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 279120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 280120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 281104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 282104477Ssam /* 283104477Ssam * The 7811 has a random number generator and 284104477Ssam * we also note it's identity 'cuz of some quirks. 285104477Ssam */ 286104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 287104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 288104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 289104477Ssam 290104477Ssam /* 291120915Ssam * The 795x parts support AES. 292120915Ssam */ 293120915Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 294120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 295120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 296120915Ssam sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 297120915Ssam 298120915Ssam /* 299104477Ssam * Configure support for memory-mapped access to 300104477Ssam * registers and for DMA operations. 301104477Ssam */ 302104477Ssam#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 303104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 304104477Ssam cmd |= PCIM_ENA; 305104477Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 306104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 307104477Ssam if ((cmd & PCIM_ENA) != PCIM_ENA) { 308104477Ssam device_printf(dev, "failed to enable %s\n", 309104477Ssam (cmd & PCIM_ENA) == 0 ? 310104477Ssam "memory mapping & bus mastering" : 311104477Ssam (cmd & PCIM_CMD_MEMEN) == 0 ? 312104477Ssam "memory mapping" : "bus mastering"); 313104477Ssam goto fail_pci; 314104477Ssam } 315104477Ssam#undef PCIM_ENA 316104477Ssam 317104477Ssam /* 318104477Ssam * Setup PCI resources. Note that we record the bus 319104477Ssam * tag and handle for each register mapping, this is 320104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 321104477Ssam * and WRITE_REG_1 macros throughout the driver. 322104477Ssam */ 323104477Ssam rid = HIFN_BAR0; 324127135Snjl sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 325127135Snjl RF_ACTIVE); 326104477Ssam if (sc->sc_bar0res == NULL) { 327104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 328104477Ssam goto fail_pci; 329104477Ssam } 330104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 331104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 332104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 333104477Ssam 334104477Ssam rid = HIFN_BAR1; 335127135Snjl sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 336127135Snjl RF_ACTIVE); 337104477Ssam if (sc->sc_bar1res == NULL) { 338104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 339104477Ssam goto fail_io0; 340104477Ssam } 341104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 342104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 343104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 344104477Ssam 345104477Ssam hifn_set_retry(sc); 346104477Ssam 347104477Ssam /* 348104477Ssam * Setup the area where the Hifn DMA's descriptors 349104477Ssam * and associated data structures. 350104477Ssam */ 351104477Ssam if (bus_dma_tag_create(NULL, /* parent */ 352104477Ssam 1, 0, /* alignment,boundary */ 353104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 354104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 355104477Ssam NULL, NULL, /* filter, filterarg */ 356104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 357104477Ssam MAX_SCATTER, /* nsegments */ 358104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 359104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 360117126Sscottl NULL, /* lockfunc */ 361117126Sscottl NULL, /* lockarg */ 362104477Ssam &sc->sc_dmat)) { 363104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 364104477Ssam goto fail_io1; 365104477Ssam } 366104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 367104477Ssam device_printf(dev, "cannot create dma map\n"); 368104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 369104477Ssam goto fail_io1; 370104477Ssam } 371104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 372104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 373104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 374104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 375104477Ssam goto fail_io1; 376104477Ssam } 377104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 378104477Ssam sizeof (*sc->sc_dma), 379104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 380104477Ssam BUS_DMA_NOWAIT)) { 381104477Ssam device_printf(dev, "cannot load dma map\n"); 382104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 383104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 384104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 385104477Ssam goto fail_io1; 386104477Ssam } 387104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 388104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 389104477Ssam 390123824Ssam KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 391123824Ssam KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 392123824Ssam KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 393123824Ssam KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 394104477Ssam 395104477Ssam /* 396104477Ssam * Reset the board and do the ``secret handshake'' 397104477Ssam * to enable the crypto support. Then complete the 398104477Ssam * initialization procedure by setting up the interrupt 399104477Ssam * and hooking in to the system crypto support so we'll 400104477Ssam * get used for system services like the crypto device, 401104477Ssam * IPsec, RNG device, etc. 402104477Ssam */ 403104477Ssam hifn_reset_board(sc, 0); 404104477Ssam 405104477Ssam if (hifn_enable_crypto(sc) != 0) { 406104477Ssam device_printf(dev, "crypto enabling failed\n"); 407104477Ssam goto fail_mem; 408104477Ssam } 409104477Ssam hifn_reset_puc(sc); 410104477Ssam 411104477Ssam hifn_init_dma(sc); 412104477Ssam hifn_init_pci_registers(sc); 413104477Ssam 414120915Ssam /* XXX can't dynamically determine ram type for 795x; force dram */ 415120915Ssam if (sc->sc_flags & HIFN_IS_7956) 416120915Ssam sc->sc_drammodel = 1; 417120915Ssam else if (hifn_ramtype(sc)) 418104477Ssam goto fail_mem; 419104477Ssam 420104477Ssam if (sc->sc_drammodel == 0) 421104477Ssam hifn_sramsize(sc); 422104477Ssam else 423104477Ssam hifn_dramsize(sc); 424104477Ssam 425104477Ssam /* 426104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 427104477Ssam * of the address lines were left floating 428104477Ssam */ 429104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 430104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 431104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 432104477Ssam sc->sc_ramsize >>= 1; 433104477Ssam 434104477Ssam /* 435104477Ssam * Arrange the interrupt line. 436104477Ssam */ 437104477Ssam rid = 0; 438127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 439127135Snjl RF_SHAREABLE|RF_ACTIVE); 440104477Ssam if (sc->sc_irq == NULL) { 441104477Ssam device_printf(dev, "could not map interrupt\n"); 442104477Ssam goto fail_mem; 443104477Ssam } 444104477Ssam /* 445104477Ssam * NB: Network code assumes we are blocked with splimp() 446104477Ssam * so make sure the IRQ is marked appropriately. 447104477Ssam */ 448115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 449104477Ssam hifn_intr, sc, &sc->sc_intrhand)) { 450104477Ssam device_printf(dev, "could not setup interrupt\n"); 451104477Ssam goto fail_intr2; 452104477Ssam } 453104477Ssam 454104477Ssam hifn_sessions(sc); 455104477Ssam 456104477Ssam /* 457104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 458104477Ssam * from the 7951. 459104477Ssam */ 460104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 461104477Ssam 462104477Ssam rseg = sc->sc_ramsize / 1024; 463104477Ssam rbase = 'K'; 464104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 465104477Ssam rbase = 'M'; 466104477Ssam rseg /= 1024; 467104477Ssam } 468104477Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 469104477Ssam hifn_partname(sc), rev, 470104477Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's', 471104477Ssam sc->sc_maxses); 472104477Ssam 473104477Ssam sc->sc_cid = crypto_get_driverid(0); 474104477Ssam if (sc->sc_cid < 0) { 475104477Ssam device_printf(dev, "could not get crypto driver id\n"); 476104477Ssam goto fail_intr; 477104477Ssam } 478104477Ssam 479104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 480104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 481104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 482104477Ssam 483104477Ssam switch (ena) { 484104477Ssam case HIFN_PUSTAT_ENA_2: 485104477Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 486104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 487104477Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 488104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 489120915Ssam if (sc->sc_flags & HIFN_HAS_AES) 490120915Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 491120915Ssam hifn_newsession, hifn_freesession, 492120915Ssam hifn_process, sc); 493104477Ssam /*FALLTHROUGH*/ 494104477Ssam case HIFN_PUSTAT_ENA_1: 495104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 496104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 497104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 498104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 499104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 500104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 501104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 502104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 503104477Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 504104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 505104477Ssam break; 506104477Ssam } 507104477Ssam 508104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 509104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 510104477Ssam 511104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 512104477Ssam hifn_init_pubrng(sc); 513104477Ssam 514119137Ssam callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 515104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 516104477Ssam 517104477Ssam return (0); 518104477Ssam 519104477Ssamfail_intr: 520104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 521104477Ssamfail_intr2: 522104477Ssam /* XXX don't store rid */ 523104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 524104477Ssamfail_mem: 525104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 526104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 527104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 528104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 529104477Ssam 530104477Ssam /* Turn off DMA polling */ 531104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 532104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 533104477Ssamfail_io1: 534104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 535104477Ssamfail_io0: 536104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 537104477Ssamfail_pci: 538104477Ssam mtx_destroy(&sc->sc_mtx); 539104477Ssam return (ENXIO); 540104477Ssam} 541104477Ssam 542104477Ssam/* 543104477Ssam * Detach an interface that successfully probed. 544104477Ssam */ 545104477Ssamstatic int 546104477Ssamhifn_detach(device_t dev) 547104477Ssam{ 548104477Ssam struct hifn_softc *sc = device_get_softc(dev); 549104477Ssam 550104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 551104477Ssam 552115748Ssam /* disable interrupts */ 553115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 554104477Ssam 555104477Ssam /*XXX other resources */ 556104477Ssam callout_stop(&sc->sc_tickto); 557104477Ssam callout_stop(&sc->sc_rngto); 558115848Ssam#ifdef HIFN_RNDTEST 559115848Ssam if (sc->sc_rndtest) 560115862Ssam rndtest_detach(sc->sc_rndtest); 561115848Ssam#endif 562104477Ssam 563104477Ssam /* Turn off DMA polling */ 564104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 565104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 566104477Ssam 567104477Ssam crypto_unregister_all(sc->sc_cid); 568104477Ssam 569104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 570104477Ssam 571104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 572104477Ssam /* XXX don't store rid */ 573104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 574104477Ssam 575104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 576104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 577104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 578104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 579104477Ssam 580104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 581104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 582104477Ssam 583104477Ssam mtx_destroy(&sc->sc_mtx); 584104477Ssam 585104477Ssam return (0); 586104477Ssam} 587104477Ssam 588104477Ssam/* 589104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 590104477Ssam * get confused by errant DMAs when rebooting. 591104477Ssam */ 592104477Ssamstatic void 593104477Ssamhifn_shutdown(device_t dev) 594104477Ssam{ 595104477Ssam#ifdef notyet 596104477Ssam hifn_stop(device_get_softc(dev)); 597104477Ssam#endif 598104477Ssam} 599104477Ssam 600104477Ssam/* 601104477Ssam * Device suspend routine. Stop the interface and save some PCI 602104477Ssam * settings in case the BIOS doesn't restore them properly on 603104477Ssam * resume. 604104477Ssam */ 605104477Ssamstatic int 606104477Ssamhifn_suspend(device_t dev) 607104477Ssam{ 608104477Ssam struct hifn_softc *sc = device_get_softc(dev); 609104477Ssam#ifdef notyet 610104477Ssam int i; 611104477Ssam 612104477Ssam hifn_stop(sc); 613104477Ssam for (i = 0; i < 5; i++) 614119690Sjhb sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 615104477Ssam sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 616104477Ssam sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 617104477Ssam sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 618104477Ssam sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 619104477Ssam#endif 620104477Ssam sc->sc_suspended = 1; 621104477Ssam 622104477Ssam return (0); 623104477Ssam} 624104477Ssam 625104477Ssam/* 626104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 627104477Ssam * doesn't, re-enable busmastering, and restart the interface if 628104477Ssam * appropriate. 629104477Ssam */ 630104477Ssamstatic int 631104477Ssamhifn_resume(device_t dev) 632104477Ssam{ 633104477Ssam struct hifn_softc *sc = device_get_softc(dev); 634104477Ssam#ifdef notyet 635104477Ssam int i; 636104477Ssam 637104477Ssam /* better way to do this? */ 638104477Ssam for (i = 0; i < 5; i++) 639119690Sjhb pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 640104477Ssam pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 641104477Ssam pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 642104477Ssam pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 643104477Ssam pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 644104477Ssam 645104477Ssam /* reenable busmastering */ 646104477Ssam pci_enable_busmaster(dev); 647104477Ssam pci_enable_io(dev, HIFN_RES); 648104477Ssam 649104477Ssam /* reinitialize interface if necessary */ 650104477Ssam if (ifp->if_flags & IFF_UP) 651104477Ssam rl_init(sc); 652104477Ssam#endif 653104477Ssam sc->sc_suspended = 0; 654104477Ssam 655104477Ssam return (0); 656104477Ssam} 657104477Ssam 658104477Ssamstatic int 659104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 660104477Ssam{ 661104477Ssam u_int32_t r; 662104477Ssam int i; 663104477Ssam 664112124Ssam#ifdef HIFN_RNDTEST 665112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 666112124Ssam if (sc->sc_rndtest) 667112124Ssam sc->sc_harvest = rndtest_harvest; 668112124Ssam else 669112124Ssam sc->sc_harvest = default_harvest; 670112124Ssam#else 671112124Ssam sc->sc_harvest = default_harvest; 672112124Ssam#endif 673104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 674104477Ssam /* Reset 7951 public key/rng engine */ 675104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 676104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 677104477Ssam 678104477Ssam for (i = 0; i < 100; i++) { 679104477Ssam DELAY(1000); 680104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 681104477Ssam HIFN_PUBRST_RESET) == 0) 682104477Ssam break; 683104477Ssam } 684104477Ssam 685104477Ssam if (i == 100) { 686104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 687104477Ssam return (1); 688104477Ssam } 689104477Ssam } 690104477Ssam 691104477Ssam /* Enable the rng, if available */ 692104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 693104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 694104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 695104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 696104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 697104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 698104477Ssam } 699104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 700104477Ssam HIFN_7811_RNGCFG_DEFL); 701104477Ssam r |= HIFN_7811_RNGENA_ENA; 702104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 703104477Ssam } else 704104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 705104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 706104477Ssam HIFN_RNGCFG_ENA); 707104477Ssam 708104477Ssam sc->sc_rngfirst = 1; 709104477Ssam if (hz >= 100) 710104477Ssam sc->sc_rnghz = hz / 100; 711104477Ssam else 712104477Ssam sc->sc_rnghz = 1; 713119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 714104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 715104477Ssam } 716104477Ssam 717104477Ssam /* Enable public key engine, if available */ 718104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 719104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 720104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 721104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 722104477Ssam } 723104477Ssam 724104477Ssam return (0); 725104477Ssam} 726104477Ssam 727104477Ssamstatic void 728104477Ssamhifn_rng(void *vsc) 729104477Ssam{ 730104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 731104477Ssam struct hifn_softc *sc = vsc; 732104477Ssam u_int32_t sts, num[2]; 733104477Ssam int i; 734104477Ssam 735104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 736104477Ssam for (i = 0; i < 5; i++) { 737104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 738104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 739104477Ssam device_printf(sc->sc_dev, 740104477Ssam "RNG underflow: disabling\n"); 741104477Ssam return; 742104477Ssam } 743104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 744104477Ssam break; 745104477Ssam 746104477Ssam /* 747104477Ssam * There are at least two words in the RNG FIFO 748104477Ssam * at this point. 749104477Ssam */ 750104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 751104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 752104477Ssam /* NB: discard first data read */ 753104477Ssam if (sc->sc_rngfirst) 754104477Ssam sc->sc_rngfirst = 0; 755104477Ssam else 756112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 757112124Ssam num, sizeof (num)); 758104477Ssam } 759104477Ssam } else { 760104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 761104477Ssam 762104477Ssam /* NB: discard first data read */ 763104477Ssam if (sc->sc_rngfirst) 764104477Ssam sc->sc_rngfirst = 0; 765104477Ssam else 766112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 767112124Ssam num, sizeof (num[0])); 768104477Ssam } 769104477Ssam 770104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 771104477Ssam#undef RANDOM_BITS 772104477Ssam} 773104477Ssam 774104477Ssamstatic void 775104477Ssamhifn_puc_wait(struct hifn_softc *sc) 776104477Ssam{ 777104477Ssam int i; 778104477Ssam 779104477Ssam for (i = 5000; i > 0; i--) { 780104477Ssam DELAY(1); 781104477Ssam if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 782104477Ssam break; 783104477Ssam } 784104477Ssam if (!i) 785104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 786104477Ssam} 787104477Ssam 788104477Ssam/* 789104477Ssam * Reset the processing unit. 790104477Ssam */ 791104477Ssamstatic void 792104477Ssamhifn_reset_puc(struct hifn_softc *sc) 793104477Ssam{ 794104477Ssam /* Reset processing unit */ 795104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 796104477Ssam hifn_puc_wait(sc); 797104477Ssam} 798104477Ssam 799104477Ssam/* 800104477Ssam * Set the Retry and TRDY registers; note that we set them to 801104477Ssam * zero because the 7811 locks up when forced to retry (section 802104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 803104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 804104477Ssam */ 805104477Ssamstatic void 806104477Ssamhifn_set_retry(struct hifn_softc *sc) 807104477Ssam{ 808104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 809104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 810104477Ssam pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 811104477Ssam} 812104477Ssam 813104477Ssam/* 814104477Ssam * Resets the board. Values in the regesters are left as is 815104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 816104477Ssam */ 817104477Ssamstatic void 818104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 819104477Ssam{ 820104477Ssam u_int32_t reg; 821104477Ssam 822104477Ssam /* 823104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 824104477Ssam * resetting the board and zeros out the other fields. 825104477Ssam */ 826104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 827104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 828104477Ssam 829104477Ssam /* 830104477Ssam * Now that polling has been disabled, we have to wait 1 ms 831104477Ssam * before resetting the board. 832104477Ssam */ 833104477Ssam DELAY(1000); 834104477Ssam 835104477Ssam /* Reset the DMA unit */ 836104477Ssam if (full) { 837104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 838104477Ssam DELAY(1000); 839104477Ssam } else { 840104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 841104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 842104477Ssam hifn_reset_puc(sc); 843104477Ssam } 844104477Ssam 845104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 846104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 847104477Ssam 848104477Ssam /* Bring dma unit out of reset */ 849104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 850104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 851104477Ssam 852104477Ssam hifn_puc_wait(sc); 853104477Ssam hifn_set_retry(sc); 854104477Ssam 855104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 856104477Ssam for (reg = 0; reg < 1000; reg++) { 857104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 858104477Ssam HIFN_MIPSRST_CRAMINIT) 859104477Ssam break; 860104477Ssam DELAY(1000); 861104477Ssam } 862104477Ssam if (reg == 1000) 863104477Ssam printf(": cram init timeout\n"); 864104477Ssam } 865104477Ssam} 866104477Ssam 867104477Ssamstatic u_int32_t 868104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 869104477Ssam{ 870104477Ssam int i; 871104477Ssam u_int32_t v; 872104477Ssam 873104477Ssam for (i = 0; i < cnt; i++) { 874104477Ssam 875104477Ssam /* get the parity */ 876104477Ssam v = a & 0x80080125; 877104477Ssam v ^= v >> 16; 878104477Ssam v ^= v >> 8; 879104477Ssam v ^= v >> 4; 880104477Ssam v ^= v >> 2; 881104477Ssam v ^= v >> 1; 882104477Ssam 883104477Ssam a = (v & 1) ^ (a << 1); 884104477Ssam } 885104477Ssam 886104477Ssam return a; 887104477Ssam} 888104477Ssam 889104477Ssamstruct pci2id { 890104477Ssam u_short pci_vendor; 891104477Ssam u_short pci_prod; 892104477Ssam char card_id[13]; 893104477Ssam}; 894104477Ssamstatic struct pci2id pci2id[] = { 895104477Ssam { 896104477Ssam PCI_VENDOR_HIFN, 897104477Ssam PCI_PRODUCT_HIFN_7951, 898104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 899104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 900104477Ssam }, { 901120915Ssam PCI_VENDOR_HIFN, 902120915Ssam PCI_PRODUCT_HIFN_7955, 903120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 904120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 905120915Ssam }, { 906120915Ssam PCI_VENDOR_HIFN, 907120915Ssam PCI_PRODUCT_HIFN_7956, 908120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 909120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 910120915Ssam }, { 911104477Ssam PCI_VENDOR_NETSEC, 912104477Ssam PCI_PRODUCT_NETSEC_7751, 913104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 914104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 915104477Ssam }, { 916104477Ssam PCI_VENDOR_INVERTEX, 917104477Ssam PCI_PRODUCT_INVERTEX_AEON, 918104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 919104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 920104477Ssam }, { 921104477Ssam PCI_VENDOR_HIFN, 922104477Ssam PCI_PRODUCT_HIFN_7811, 923104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 924104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 925104477Ssam }, { 926104477Ssam /* 927104477Ssam * Other vendors share this PCI ID as well, such as 928104477Ssam * http://www.powercrypt.com, and obviously they also 929104477Ssam * use the same key. 930104477Ssam */ 931104477Ssam PCI_VENDOR_HIFN, 932104477Ssam PCI_PRODUCT_HIFN_7751, 933104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 934104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 935104477Ssam }, 936104477Ssam}; 937104477Ssam 938104477Ssam/* 939104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 940104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 941104477Ssam * as enabling crypto twice will lock the board. 942104477Ssam */ 943104477Ssamstatic int 944104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 945104477Ssam{ 946104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 947104477Ssam char *offtbl = NULL; 948104477Ssam 949104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 950104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 951104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 952104477Ssam offtbl = pci2id[i].card_id; 953104477Ssam break; 954104477Ssam } 955104477Ssam } 956104477Ssam if (offtbl == NULL) { 957104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 958104477Ssam return (1); 959104477Ssam } 960104477Ssam 961104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 962104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 963104477Ssam 964104477Ssam /* 965104477Ssam * The RAM config register's encrypt level bit needs to be set before 966104477Ssam * every read performed on the encryption level register. 967104477Ssam */ 968104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 969104477Ssam 970104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 971104477Ssam 972104477Ssam /* 973104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 974104477Ssam * next reboot. 975104477Ssam */ 976104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 977104477Ssam#ifdef HIFN_DEBUG 978104477Ssam if (hifn_debug) 979104477Ssam device_printf(sc->sc_dev, 980104477Ssam "Strong crypto already enabled!\n"); 981104477Ssam#endif 982104477Ssam goto report; 983104477Ssam } 984104477Ssam 985104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 986104477Ssam#ifdef HIFN_DEBUG 987104477Ssam if (hifn_debug) 988104477Ssam device_printf(sc->sc_dev, 989104477Ssam "Unknown encryption level 0x%x\n", encl); 990104477Ssam#endif 991104477Ssam return 1; 992104477Ssam } 993104477Ssam 994104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 995104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 996104477Ssam DELAY(1000); 997104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 998104477Ssam DELAY(1000); 999104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 1000104477Ssam DELAY(1000); 1001104477Ssam 1002104477Ssam for (i = 0; i <= 12; i++) { 1003104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1004104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1005104477Ssam 1006104477Ssam DELAY(1000); 1007104477Ssam } 1008104477Ssam 1009104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1010104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1011104477Ssam 1012104477Ssam#ifdef HIFN_DEBUG 1013104477Ssam if (hifn_debug) { 1014104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1015104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 1016104477Ssam "locked until next system reset!\n"); 1017104477Ssam else 1018104477Ssam device_printf(sc->sc_dev, "Engine enabled " 1019104477Ssam "successfully!\n"); 1020104477Ssam } 1021104477Ssam#endif 1022104477Ssam 1023104477Ssamreport: 1024104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1025104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1026104477Ssam 1027104477Ssam switch (encl) { 1028104477Ssam case HIFN_PUSTAT_ENA_1: 1029104477Ssam case HIFN_PUSTAT_ENA_2: 1030104477Ssam break; 1031104477Ssam case HIFN_PUSTAT_ENA_0: 1032104477Ssam default: 1033104477Ssam device_printf(sc->sc_dev, "disabled"); 1034104477Ssam break; 1035104477Ssam } 1036104477Ssam 1037104477Ssam return 0; 1038104477Ssam} 1039104477Ssam 1040104477Ssam/* 1041104477Ssam * Give initial values to the registers listed in the "Register Space" 1042104477Ssam * section of the HIFN Software Development reference manual. 1043104477Ssam */ 1044104477Ssamstatic void 1045104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1046104477Ssam{ 1047104477Ssam /* write fixed values needed by the Initialization registers */ 1048104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1049104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1050104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1051104477Ssam 1052104477Ssam /* write all 4 ring address registers */ 1053104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1054104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1055104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1056104477Ssam offsetof(struct hifn_dma, srcr[0])); 1057104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1058104477Ssam offsetof(struct hifn_dma, dstr[0])); 1059104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1060104477Ssam offsetof(struct hifn_dma, resr[0])); 1061104477Ssam 1062104477Ssam DELAY(2000); 1063104477Ssam 1064104477Ssam /* write status register */ 1065104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1066104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1067104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1068104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1069104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1070104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1071104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1072104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1073104477Ssam HIFN_DMACSR_S_WAIT | 1074104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1075104477Ssam HIFN_DMACSR_C_WAIT | 1076104477Ssam HIFN_DMACSR_ENGINE | 1077104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1078104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1079104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1080104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1081104477Ssam 1082104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1083104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1084104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1085104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1086104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1087104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1088104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1089104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1090104477Ssam 1091104477Ssam 1092120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1093120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1094120915Ssam HIFN_PUCNFG_TCALLPHASES | 1095120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1096120915Ssam WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956); 1097120915Ssam } else { 1098120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1099120915Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1100120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1101120915Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1102120915Ssam } 1103120915Ssam 1104104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1105104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1106104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1107104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1108104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1109104477Ssam} 1110104477Ssam 1111104477Ssam/* 1112104477Ssam * The maximum number of sessions supported by the card 1113104477Ssam * is dependent on the amount of context ram, which 1114104477Ssam * encryption algorithms are enabled, and how compression 1115104477Ssam * is configured. This should be configured before this 1116104477Ssam * routine is called. 1117104477Ssam */ 1118104477Ssamstatic void 1119104477Ssamhifn_sessions(struct hifn_softc *sc) 1120104477Ssam{ 1121104477Ssam u_int32_t pucnfg; 1122104477Ssam int ctxsize; 1123104477Ssam 1124104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1125104477Ssam 1126104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1127104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1128104477Ssam ctxsize = 128; 1129104477Ssam else 1130104477Ssam ctxsize = 512; 1131120915Ssam /* 1132120915Ssam * 7955/7956 has internal context memory of 32K 1133120915Ssam */ 1134120915Ssam if (sc->sc_flags & HIFN_IS_7956) 1135120915Ssam sc->sc_maxses = 32768 / ctxsize; 1136120915Ssam else 1137120915Ssam sc->sc_maxses = 1 + 1138120915Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1139104477Ssam } else 1140104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1141104477Ssam 1142104477Ssam if (sc->sc_maxses > 2048) 1143104477Ssam sc->sc_maxses = 2048; 1144104477Ssam} 1145104477Ssam 1146104477Ssam/* 1147104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1148104477Ssam * state when this is called. 1149104477Ssam */ 1150104477Ssamstatic int 1151104477Ssamhifn_ramtype(struct hifn_softc *sc) 1152104477Ssam{ 1153104477Ssam u_int8_t data[8], dataexpect[8]; 1154104477Ssam int i; 1155104477Ssam 1156104477Ssam for (i = 0; i < sizeof(data); i++) 1157104477Ssam data[i] = dataexpect[i] = 0x55; 1158104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1159104477Ssam return (-1); 1160104477Ssam if (hifn_readramaddr(sc, 0, data)) 1161104477Ssam return (-1); 1162104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1163104477Ssam sc->sc_drammodel = 1; 1164104477Ssam return (0); 1165104477Ssam } 1166104477Ssam 1167104477Ssam for (i = 0; i < sizeof(data); i++) 1168104477Ssam data[i] = dataexpect[i] = 0xaa; 1169104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1170104477Ssam return (-1); 1171104477Ssam if (hifn_readramaddr(sc, 0, data)) 1172104477Ssam return (-1); 1173104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1174104477Ssam sc->sc_drammodel = 1; 1175104477Ssam return (0); 1176104477Ssam } 1177104477Ssam 1178104477Ssam return (0); 1179104477Ssam} 1180104477Ssam 1181104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1182104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1183104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1184104477Ssam 1185104477Ssamstatic int 1186104477Ssamhifn_sramsize(struct hifn_softc *sc) 1187104477Ssam{ 1188104477Ssam u_int32_t a; 1189104477Ssam u_int8_t data[8]; 1190104477Ssam u_int8_t dataexpect[sizeof(data)]; 1191104477Ssam int32_t i; 1192104477Ssam 1193104477Ssam for (i = 0; i < sizeof(data); i++) 1194104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1195104477Ssam 1196104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1197104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1198104477Ssam bcopy(&i, data, sizeof(i)); 1199104477Ssam hifn_writeramaddr(sc, a, data); 1200104477Ssam } 1201104477Ssam 1202104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1203104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1204104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1205104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1206104477Ssam return (0); 1207104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1208104477Ssam return (0); 1209104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1210104477Ssam } 1211104477Ssam 1212104477Ssam return (0); 1213104477Ssam} 1214104477Ssam 1215104477Ssam/* 1216104477Ssam * XXX For dram boards, one should really try all of the 1217104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1218104477Ssam * is already set up correctly. 1219104477Ssam */ 1220104477Ssamstatic int 1221104477Ssamhifn_dramsize(struct hifn_softc *sc) 1222104477Ssam{ 1223104477Ssam u_int32_t cnfg; 1224104477Ssam 1225120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1226120915Ssam /* 1227120915Ssam * 7955/7956 have a fixed internal ram of only 32K. 1228120915Ssam */ 1229120915Ssam sc->sc_ramsize = 32768; 1230120915Ssam } else { 1231120915Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1232120915Ssam HIFN_PUCNFG_DRAMMASK; 1233120915Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1234120915Ssam } 1235104477Ssam return (0); 1236104477Ssam} 1237104477Ssam 1238104477Ssamstatic void 1239104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1240104477Ssam{ 1241104477Ssam struct hifn_dma *dma = sc->sc_dma; 1242104477Ssam 1243104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1244104477Ssam dma->cmdi = 0; 1245104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1246104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1247104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1248104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1249104477Ssam } 1250104477Ssam *cmdp = dma->cmdi++; 1251104477Ssam dma->cmdk = dma->cmdi; 1252104477Ssam 1253104477Ssam if (dma->srci == HIFN_D_SRC_RSIZE) { 1254104477Ssam dma->srci = 0; 1255104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1256104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1257104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1258104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1259104477Ssam } 1260104477Ssam *srcp = dma->srci++; 1261104477Ssam dma->srck = dma->srci; 1262104477Ssam 1263104477Ssam if (dma->dsti == HIFN_D_DST_RSIZE) { 1264104477Ssam dma->dsti = 0; 1265104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1266104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1267104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1268104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269104477Ssam } 1270104477Ssam *dstp = dma->dsti++; 1271104477Ssam dma->dstk = dma->dsti; 1272104477Ssam 1273104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1274104477Ssam dma->resi = 0; 1275104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1276104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1277104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1278104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1279104477Ssam } 1280104477Ssam *resp = dma->resi++; 1281104477Ssam dma->resk = dma->resi; 1282104477Ssam} 1283104477Ssam 1284104477Ssamstatic int 1285104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1286104477Ssam{ 1287104477Ssam struct hifn_dma *dma = sc->sc_dma; 1288104477Ssam hifn_base_command_t wc; 1289104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1290104477Ssam int r, cmdi, resi, srci, dsti; 1291104477Ssam 1292104477Ssam wc.masks = htole16(3 << 13); 1293104477Ssam wc.session_num = htole16(addr >> 14); 1294104477Ssam wc.total_source_count = htole16(8); 1295104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1296104477Ssam 1297104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1298104477Ssam 1299104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1300104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1301104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1302104477Ssam 1303104477Ssam /* build write command */ 1304104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1305104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1306104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1307104477Ssam 1308104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1309104477Ssam + offsetof(struct hifn_dma, test_src)); 1310104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1311104477Ssam + offsetof(struct hifn_dma, test_dst)); 1312104477Ssam 1313104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1314104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1315104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1316104477Ssam dma->resr[resi].l = htole32(4 | masks); 1317104477Ssam 1318104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1319104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1320104477Ssam 1321104477Ssam for (r = 10000; r >= 0; r--) { 1322104477Ssam DELAY(10); 1323104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1324104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1325104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1326104477Ssam break; 1327104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1328104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1329104477Ssam } 1330104477Ssam if (r == 0) { 1331104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1332104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1333104477Ssam r = -1; 1334104477Ssam return (-1); 1335104477Ssam } else 1336104477Ssam r = 0; 1337104477Ssam 1338104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1339104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1340104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1341104477Ssam 1342104477Ssam return (r); 1343104477Ssam} 1344104477Ssam 1345104477Ssamstatic int 1346104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1347104477Ssam{ 1348104477Ssam struct hifn_dma *dma = sc->sc_dma; 1349104477Ssam hifn_base_command_t rc; 1350104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1351104477Ssam int r, cmdi, srci, dsti, resi; 1352104477Ssam 1353104477Ssam rc.masks = htole16(2 << 13); 1354104477Ssam rc.session_num = htole16(addr >> 14); 1355104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1356104477Ssam rc.total_dest_count = htole16(8); 1357104477Ssam 1358104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1359104477Ssam 1360104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1361104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1362104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1363104477Ssam 1364104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1365104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1366104477Ssam 1367104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1368104477Ssam offsetof(struct hifn_dma, test_src)); 1369104477Ssam dma->test_src = 0; 1370104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1371104477Ssam offsetof(struct hifn_dma, test_dst)); 1372104477Ssam dma->test_dst = 0; 1373104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1374104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1375104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1376104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1377104477Ssam 1378104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1379104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1380104477Ssam 1381104477Ssam for (r = 10000; r >= 0; r--) { 1382104477Ssam DELAY(10); 1383104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1384104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1385104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1386104477Ssam break; 1387104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1388104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1389104477Ssam } 1390104477Ssam if (r == 0) { 1391104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1392104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1393104477Ssam r = -1; 1394104477Ssam } else { 1395104477Ssam r = 0; 1396104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1397104477Ssam } 1398104477Ssam 1399104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1400104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1401104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1402104477Ssam 1403104477Ssam return (r); 1404104477Ssam} 1405104477Ssam 1406104477Ssam/* 1407104477Ssam * Initialize the descriptor rings. 1408104477Ssam */ 1409104477Ssamstatic void 1410104477Ssamhifn_init_dma(struct hifn_softc *sc) 1411104477Ssam{ 1412104477Ssam struct hifn_dma *dma = sc->sc_dma; 1413104477Ssam int i; 1414104477Ssam 1415104477Ssam hifn_set_retry(sc); 1416104477Ssam 1417104477Ssam /* initialize static pointer values */ 1418104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1419104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1420104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1421104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1422104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1423104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1424104477Ssam 1425104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1426104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1427104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1428104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1429104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1430104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1431104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1432104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1433104477Ssam 1434104477Ssam dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1435104477Ssam dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1436104477Ssam dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1437104477Ssam} 1438104477Ssam 1439104477Ssam/* 1440104477Ssam * Writes out the raw command buffer space. Returns the 1441104477Ssam * command buffer size. 1442104477Ssam */ 1443104477Ssamstatic u_int 1444104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1445104477Ssam{ 1446104477Ssam u_int8_t *buf_pos; 1447104477Ssam hifn_base_command_t *base_cmd; 1448104477Ssam hifn_mac_command_t *mac_cmd; 1449104477Ssam hifn_crypt_command_t *cry_cmd; 1450120915Ssam int using_mac, using_crypt, len, ivlen; 1451104477Ssam u_int32_t dlen, slen; 1452104477Ssam 1453104477Ssam buf_pos = buf; 1454104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1455104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1456104477Ssam 1457104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1458104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1459104477Ssam slen = cmd->src_mapsize; 1460104477Ssam if (cmd->sloplen) 1461104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1462104477Ssam else 1463104477Ssam dlen = cmd->dst_mapsize; 1464104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1465104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1466104477Ssam dlen >>= 16; 1467104477Ssam slen >>= 16; 1468104477Ssam base_cmd->session_num = htole16(cmd->session_num | 1469104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1470104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1471104477Ssam buf_pos += sizeof(hifn_base_command_t); 1472104477Ssam 1473104477Ssam if (using_mac) { 1474104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1475104477Ssam dlen = cmd->maccrd->crd_len; 1476104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1477104477Ssam dlen >>= 16; 1478104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1479104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1480104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1481104477Ssam mac_cmd->reserved = 0; 1482104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1483104477Ssam } 1484104477Ssam 1485104477Ssam if (using_crypt) { 1486104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1487104477Ssam dlen = cmd->enccrd->crd_len; 1488104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1489104477Ssam dlen >>= 16; 1490104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1491104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1492104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1493104477Ssam cry_cmd->reserved = 0; 1494104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1495104477Ssam } 1496104477Ssam 1497104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1498104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1499104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1500104477Ssam } 1501104477Ssam 1502104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1503104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1504104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1505104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1506104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1507104477Ssam break; 1508104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1509104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1510120915Ssam buf_pos += HIFN_DES_KEY_LENGTH; 1511104477Ssam break; 1512104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1513104477Ssam len = 256; 1514104477Ssam do { 1515104477Ssam int clen; 1516104477Ssam 1517104477Ssam clen = MIN(cmd->cklen, len); 1518104477Ssam bcopy(cmd->ck, buf_pos, clen); 1519104477Ssam len -= clen; 1520104477Ssam buf_pos += clen; 1521104477Ssam } while (len > 0); 1522104477Ssam bzero(buf_pos, 4); 1523104477Ssam buf_pos += 4; 1524104477Ssam break; 1525120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1526120915Ssam /* 1527120915Ssam * AES keys are variable 128, 192 and 1528120915Ssam * 256 bits (16, 24 and 32 bytes). 1529120915Ssam */ 1530120915Ssam bcopy(cmd->ck, buf_pos, cmd->cklen); 1531120915Ssam buf_pos += cmd->cklen; 1532120915Ssam break; 1533104477Ssam } 1534104477Ssam } 1535104477Ssam 1536104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1537120915Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1538120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1539120915Ssam ivlen = HIFN_AES_IV_LENGTH; 1540120915Ssam break; 1541120915Ssam default: 1542120915Ssam ivlen = HIFN_IV_LENGTH; 1543120915Ssam break; 1544120915Ssam } 1545120915Ssam bcopy(cmd->iv, buf_pos, ivlen); 1546120915Ssam buf_pos += ivlen; 1547104477Ssam } 1548104477Ssam 1549104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1550104477Ssam bzero(buf_pos, 8); 1551104477Ssam buf_pos += 8; 1552104477Ssam } 1553104477Ssam 1554104477Ssam return (buf_pos - buf); 1555104477Ssam} 1556104477Ssam 1557104477Ssamstatic int 1558104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1559104477Ssam{ 1560104477Ssam int i; 1561104477Ssam 1562104477Ssam for (i = 0; i < op->nsegs; i++) { 1563104477Ssam if (op->segs[i].ds_addr & 3) 1564104477Ssam return (0); 1565104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1566104477Ssam return (0); 1567104477Ssam } 1568104477Ssam return (1); 1569104477Ssam} 1570104477Ssam 1571104477Ssamstatic int 1572104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1573104477Ssam{ 1574104477Ssam struct hifn_dma *dma = sc->sc_dma; 1575104477Ssam struct hifn_operand *dst = &cmd->dst; 1576104477Ssam u_int32_t p, l; 1577104477Ssam int idx, used = 0, i; 1578104477Ssam 1579104477Ssam idx = dma->dsti; 1580104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1581104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1582104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1583104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1584104477Ssam HIFN_DSTR_SYNC(sc, idx, 1585104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1586104477Ssam used++; 1587104477Ssam 1588104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1589104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1590104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1591104477Ssam HIFN_DSTR_SYNC(sc, idx, 1592104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1593104477Ssam idx = 0; 1594104477Ssam } 1595104477Ssam } 1596104477Ssam 1597104477Ssam if (cmd->sloplen == 0) { 1598104477Ssam p = dst->segs[i].ds_addr; 1599104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1600104477Ssam dst->segs[i].ds_len; 1601104477Ssam } else { 1602104477Ssam p = sc->sc_dma_physaddr + 1603104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1604104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1605104477Ssam sizeof(u_int32_t); 1606104477Ssam 1607104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1608104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1609104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1610104477Ssam HIFN_D_MASKDONEIRQ | 1611104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1612104477Ssam HIFN_DSTR_SYNC(sc, idx, 1613104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1614104477Ssam used++; 1615104477Ssam 1616104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1617104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1618104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1619104477Ssam HIFN_DSTR_SYNC(sc, idx, 1620104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1621104477Ssam idx = 0; 1622104477Ssam } 1623104477Ssam } 1624104477Ssam } 1625104477Ssam dma->dstr[idx].p = htole32(p); 1626104477Ssam dma->dstr[idx].l = htole32(l); 1627104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1628104477Ssam used++; 1629104477Ssam 1630104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1631104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1632104477Ssam HIFN_D_MASKDONEIRQ); 1633104477Ssam HIFN_DSTR_SYNC(sc, idx, 1634104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1635104477Ssam idx = 0; 1636104477Ssam } 1637104477Ssam 1638104477Ssam dma->dsti = idx; 1639104477Ssam dma->dstu += used; 1640104477Ssam return (idx); 1641104477Ssam} 1642104477Ssam 1643104477Ssamstatic int 1644104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1645104477Ssam{ 1646104477Ssam struct hifn_dma *dma = sc->sc_dma; 1647104477Ssam struct hifn_operand *src = &cmd->src; 1648104477Ssam int idx, i; 1649104477Ssam u_int32_t last = 0; 1650104477Ssam 1651104477Ssam idx = dma->srci; 1652104477Ssam for (i = 0; i < src->nsegs; i++) { 1653104477Ssam if (i == src->nsegs - 1) 1654104477Ssam last = HIFN_D_LAST; 1655104477Ssam 1656104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1657104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1658104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1659104477Ssam HIFN_SRCR_SYNC(sc, idx, 1660104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1661104477Ssam 1662104477Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1663104477Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1664104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1665104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1666104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1667104477Ssam idx = 0; 1668104477Ssam } 1669104477Ssam } 1670104477Ssam dma->srci = idx; 1671104477Ssam dma->srcu += src->nsegs; 1672104477Ssam return (idx); 1673104477Ssam} 1674104477Ssam 1675104477Ssamstatic void 1676104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1677104477Ssam{ 1678104477Ssam struct hifn_operand *op = arg; 1679104477Ssam 1680104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1681104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1682104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1683104477Ssam op->mapsize = mapsize; 1684104477Ssam op->nsegs = nsegs; 1685104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1686104477Ssam} 1687104477Ssam 1688104477Ssamstatic int 1689104477Ssamhifn_crypto( 1690104477Ssam struct hifn_softc *sc, 1691104477Ssam struct hifn_command *cmd, 1692104477Ssam struct cryptop *crp, 1693104477Ssam int hint) 1694104477Ssam{ 1695104477Ssam struct hifn_dma *dma = sc->sc_dma; 1696104477Ssam u_int32_t cmdlen; 1697104477Ssam int cmdi, resi, err = 0; 1698104477Ssam 1699104477Ssam /* 1700104477Ssam * need 1 cmd, and 1 res 1701104477Ssam * 1702104477Ssam * NB: check this first since it's easy. 1703104477Ssam */ 1704115748Ssam HIFN_LOCK(sc); 1705104477Ssam if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1706104477Ssam (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1707104477Ssam#ifdef HIFN_DEBUG 1708104477Ssam if (hifn_debug) { 1709104477Ssam device_printf(sc->sc_dev, 1710104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1711104477Ssam dma->cmdu, dma->resu); 1712104477Ssam } 1713104477Ssam#endif 1714104477Ssam hifnstats.hst_nomem_cr++; 1715115748Ssam HIFN_UNLOCK(sc); 1716104477Ssam return (ERESTART); 1717104477Ssam } 1718104477Ssam 1719104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1720104477Ssam hifnstats.hst_nomem_map++; 1721115748Ssam HIFN_UNLOCK(sc); 1722104477Ssam return (ENOMEM); 1723104477Ssam } 1724104477Ssam 1725104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1726104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1727104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1728104477Ssam hifnstats.hst_nomem_load++; 1729104477Ssam err = ENOMEM; 1730104477Ssam goto err_srcmap1; 1731104477Ssam } 1732104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1733104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1734104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1735104477Ssam hifnstats.hst_nomem_load++; 1736104477Ssam err = ENOMEM; 1737104477Ssam goto err_srcmap1; 1738104477Ssam } 1739104477Ssam } else { 1740104477Ssam err = EINVAL; 1741104477Ssam goto err_srcmap1; 1742104477Ssam } 1743104477Ssam 1744104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1745104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1746104477Ssam cmd->dst = cmd->src; 1747104477Ssam } else { 1748104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1749104477Ssam err = EINVAL; 1750104477Ssam goto err_srcmap; 1751104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1752104477Ssam int totlen, len; 1753104477Ssam struct mbuf *m, *m0, *mlast; 1754104477Ssam 1755104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1756104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1757104477Ssam hifnstats.hst_unaligned++; 1758104477Ssam /* 1759104477Ssam * Source is not aligned on a longword boundary. 1760104477Ssam * Copy the data to insure alignment. If we fail 1761104477Ssam * to allocate mbufs or clusters while doing this 1762104477Ssam * we return ERESTART so the operation is requeued 1763104477Ssam * at the crypto later, but only if there are 1764104477Ssam * ops already posted to the hardware; otherwise we 1765104477Ssam * have no guarantee that we'll be re-entered. 1766104477Ssam */ 1767104477Ssam totlen = cmd->src_mapsize; 1768104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1769104477Ssam len = MHLEN; 1770111119Simp MGETHDR(m0, M_DONTWAIT, MT_DATA); 1771111119Simp if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1772108466Ssam m_free(m0); 1773108466Ssam m0 = NULL; 1774108466Ssam } 1775104477Ssam } else { 1776104477Ssam len = MLEN; 1777111119Simp MGET(m0, M_DONTWAIT, MT_DATA); 1778104477Ssam } 1779104477Ssam if (m0 == NULL) { 1780104477Ssam hifnstats.hst_nomem_mbuf++; 1781104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1782104477Ssam goto err_srcmap; 1783104477Ssam } 1784104477Ssam if (totlen >= MINCLSIZE) { 1785111119Simp MCLGET(m0, M_DONTWAIT); 1786104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1787104477Ssam hifnstats.hst_nomem_mcl++; 1788104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1789104477Ssam m_freem(m0); 1790104477Ssam goto err_srcmap; 1791104477Ssam } 1792104477Ssam len = MCLBYTES; 1793104477Ssam } 1794104477Ssam totlen -= len; 1795104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1796104477Ssam mlast = m0; 1797104477Ssam 1798104477Ssam while (totlen > 0) { 1799111119Simp MGET(m, M_DONTWAIT, MT_DATA); 1800104477Ssam if (m == NULL) { 1801104477Ssam hifnstats.hst_nomem_mbuf++; 1802104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1803104477Ssam m_freem(m0); 1804104477Ssam goto err_srcmap; 1805104477Ssam } 1806104477Ssam len = MLEN; 1807104477Ssam if (totlen >= MINCLSIZE) { 1808111119Simp MCLGET(m, M_DONTWAIT); 1809104477Ssam if ((m->m_flags & M_EXT) == 0) { 1810104477Ssam hifnstats.hst_nomem_mcl++; 1811104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1812104477Ssam mlast->m_next = m; 1813104477Ssam m_freem(m0); 1814104477Ssam goto err_srcmap; 1815104477Ssam } 1816104477Ssam len = MCLBYTES; 1817104477Ssam } 1818104477Ssam 1819104477Ssam m->m_len = len; 1820104477Ssam m0->m_pkthdr.len += len; 1821104477Ssam totlen -= len; 1822104477Ssam 1823104477Ssam mlast->m_next = m; 1824104477Ssam mlast = m; 1825104477Ssam } 1826104477Ssam cmd->dst_m = m0; 1827104477Ssam } 1828104477Ssam } 1829104477Ssam 1830104477Ssam if (cmd->dst_map == NULL) { 1831104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1832104477Ssam hifnstats.hst_nomem_map++; 1833104477Ssam err = ENOMEM; 1834104477Ssam goto err_srcmap; 1835104477Ssam } 1836104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1837104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1838104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1839104477Ssam hifnstats.hst_nomem_map++; 1840104477Ssam err = ENOMEM; 1841104477Ssam goto err_dstmap1; 1842104477Ssam } 1843104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1844104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1845104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1846104477Ssam hifnstats.hst_nomem_load++; 1847104477Ssam err = ENOMEM; 1848104477Ssam goto err_dstmap1; 1849104477Ssam } 1850104477Ssam } 1851104477Ssam } 1852104477Ssam 1853104477Ssam#ifdef HIFN_DEBUG 1854104477Ssam if (hifn_debug) { 1855104477Ssam device_printf(sc->sc_dev, 1856104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1857104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1858104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1859104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1860104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1861104477Ssam } 1862104477Ssam#endif 1863104477Ssam 1864104477Ssam if (cmd->src_map == cmd->dst_map) { 1865104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1866104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1867104477Ssam } else { 1868104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1869104477Ssam BUS_DMASYNC_PREWRITE); 1870104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1871104477Ssam BUS_DMASYNC_PREREAD); 1872104477Ssam } 1873104477Ssam 1874104477Ssam /* 1875104477Ssam * need N src, and N dst 1876104477Ssam */ 1877104477Ssam if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1878104477Ssam (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1879104477Ssam#ifdef HIFN_DEBUG 1880104477Ssam if (hifn_debug) { 1881104477Ssam device_printf(sc->sc_dev, 1882104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1883104477Ssam dma->srcu, cmd->src_nsegs, 1884104477Ssam dma->dstu, cmd->dst_nsegs); 1885104477Ssam } 1886104477Ssam#endif 1887104477Ssam hifnstats.hst_nomem_sd++; 1888104477Ssam err = ERESTART; 1889104477Ssam goto err_dstmap; 1890104477Ssam } 1891104477Ssam 1892104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1893104477Ssam dma->cmdi = 0; 1894104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1895104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1896104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1897104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1898104477Ssam } 1899104477Ssam cmdi = dma->cmdi++; 1900104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1901104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1902104477Ssam 1903104477Ssam /* .p for command/result already set */ 1904104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1905104477Ssam HIFN_D_MASKDONEIRQ); 1906104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 1907104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1908104477Ssam dma->cmdu++; 1909104477Ssam if (sc->sc_c_busy == 0) { 1910104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1911104477Ssam sc->sc_c_busy = 1; 1912104477Ssam } 1913104477Ssam 1914104477Ssam /* 1915104477Ssam * We don't worry about missing an interrupt (which a "command wait" 1916104477Ssam * interrupt salvages us from), unless there is more than one command 1917104477Ssam * in the queue. 1918104477Ssam */ 1919104477Ssam if (dma->cmdu > 1) { 1920104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1921104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1922104477Ssam } 1923104477Ssam 1924104477Ssam hifnstats.hst_ipackets++; 1925104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 1926104477Ssam 1927104477Ssam hifn_dmamap_load_src(sc, cmd); 1928104477Ssam if (sc->sc_s_busy == 0) { 1929104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1930104477Ssam sc->sc_s_busy = 1; 1931104477Ssam } 1932104477Ssam 1933104477Ssam /* 1934104477Ssam * Unlike other descriptors, we don't mask done interrupt from 1935104477Ssam * result descriptor. 1936104477Ssam */ 1937104477Ssam#ifdef HIFN_DEBUG 1938104477Ssam if (hifn_debug) 1939104477Ssam printf("load res\n"); 1940104477Ssam#endif 1941104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1942104477Ssam dma->resi = 0; 1943104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1944104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1945104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1946104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1947104477Ssam } 1948104477Ssam resi = dma->resi++; 1949104477Ssam KASSERT(dma->hifn_commands[resi] == NULL, 1950104477Ssam ("hifn_crypto: command slot %u busy", resi)); 1951104477Ssam dma->hifn_commands[resi] = cmd; 1952104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1953104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1954104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1955104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1956104477Ssam sc->sc_curbatch++; 1957104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1958104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 1959104477Ssam hifnstats.hst_totbatch++; 1960104477Ssam } else { 1961104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1962104477Ssam HIFN_D_VALID | HIFN_D_LAST); 1963104477Ssam sc->sc_curbatch = 0; 1964104477Ssam } 1965104477Ssam HIFN_RESR_SYNC(sc, resi, 1966104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1967104477Ssam dma->resu++; 1968104477Ssam if (sc->sc_r_busy == 0) { 1969104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1970104477Ssam sc->sc_r_busy = 1; 1971104477Ssam } 1972104477Ssam 1973104477Ssam if (cmd->sloplen) 1974104477Ssam cmd->slopidx = resi; 1975104477Ssam 1976104477Ssam hifn_dmamap_load_dst(sc, cmd); 1977104477Ssam 1978104477Ssam if (sc->sc_d_busy == 0) { 1979104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1980104477Ssam sc->sc_d_busy = 1; 1981104477Ssam } 1982104477Ssam 1983104477Ssam#ifdef HIFN_DEBUG 1984104477Ssam if (hifn_debug) { 1985104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1986104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1987104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 1988104477Ssam } 1989104477Ssam#endif 1990104477Ssam 1991104477Ssam sc->sc_active = 5; 1992115748Ssam HIFN_UNLOCK(sc); 1993104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1994104477Ssam return (err); /* success */ 1995104477Ssam 1996104477Ssamerr_dstmap: 1997104477Ssam if (cmd->src_map != cmd->dst_map) 1998104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1999104477Ssamerr_dstmap1: 2000104477Ssam if (cmd->src_map != cmd->dst_map) 2001104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2002104477Ssamerr_srcmap: 2003104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2004104477Ssam if (cmd->src_m != cmd->dst_m) 2005104477Ssam m_freem(cmd->dst_m); 2006104477Ssam } 2007104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2008104477Ssamerr_srcmap1: 2009104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2010115748Ssam HIFN_UNLOCK(sc); 2011104477Ssam return (err); 2012104477Ssam} 2013104477Ssam 2014104477Ssamstatic void 2015104477Ssamhifn_tick(void* vsc) 2016104477Ssam{ 2017104477Ssam struct hifn_softc *sc = vsc; 2018104477Ssam 2019104477Ssam HIFN_LOCK(sc); 2020104477Ssam if (sc->sc_active == 0) { 2021104477Ssam struct hifn_dma *dma = sc->sc_dma; 2022104477Ssam u_int32_t r = 0; 2023104477Ssam 2024104477Ssam if (dma->cmdu == 0 && sc->sc_c_busy) { 2025104477Ssam sc->sc_c_busy = 0; 2026104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 2027104477Ssam } 2028104477Ssam if (dma->srcu == 0 && sc->sc_s_busy) { 2029104477Ssam sc->sc_s_busy = 0; 2030104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 2031104477Ssam } 2032104477Ssam if (dma->dstu == 0 && sc->sc_d_busy) { 2033104477Ssam sc->sc_d_busy = 0; 2034104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 2035104477Ssam } 2036104477Ssam if (dma->resu == 0 && sc->sc_r_busy) { 2037104477Ssam sc->sc_r_busy = 0; 2038104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 2039104477Ssam } 2040104477Ssam if (r) 2041104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2042104477Ssam } else 2043104477Ssam sc->sc_active--; 2044104477Ssam HIFN_UNLOCK(sc); 2045104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2046104477Ssam} 2047104477Ssam 2048104477Ssamstatic void 2049104477Ssamhifn_intr(void *arg) 2050104477Ssam{ 2051104477Ssam struct hifn_softc *sc = arg; 2052104477Ssam struct hifn_dma *dma; 2053104477Ssam u_int32_t dmacsr, restart; 2054104477Ssam int i, u; 2055104477Ssam 2056115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2057115748Ssam 2058115748Ssam /* Nothing in the DMA unit interrupted */ 2059115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 2060115748Ssam return; 2061115748Ssam 2062104477Ssam HIFN_LOCK(sc); 2063115748Ssam 2064104477Ssam dma = sc->sc_dma; 2065104477Ssam 2066104477Ssam#ifdef HIFN_DEBUG 2067104477Ssam if (hifn_debug) { 2068104477Ssam device_printf(sc->sc_dev, 2069104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2070104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2071104477Ssam dma->cmdi, dma->srci, dma->dsti, dma->resi, 2072104477Ssam dma->cmdk, dma->srck, dma->dstk, dma->resk, 2073104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2074104477Ssam } 2075104477Ssam#endif 2076104477Ssam 2077104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2078104477Ssam 2079104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2080104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2081104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2082104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2083104477Ssam 2084104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2085104477Ssam if (restart) 2086104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2087104477Ssam 2088104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2089104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2090104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2091104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2092104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2093104477Ssam } 2094104477Ssam 2095104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2096104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2097104477Ssam if (restart) { 2098104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2099104477Ssam hifnstats.hst_abort++; 2100104477Ssam hifn_abort(sc); 2101104477Ssam HIFN_UNLOCK(sc); 2102104477Ssam return; 2103104477Ssam } 2104104477Ssam 2105104477Ssam if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2106104477Ssam /* 2107104477Ssam * If no slots to process and we receive a "waiting on 2108104477Ssam * command" interrupt, we disable the "waiting on command" 2109104477Ssam * (by clearing it). 2110104477Ssam */ 2111104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2112104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2113104477Ssam } 2114104477Ssam 2115104477Ssam /* clear the rings */ 2116104477Ssam i = dma->resk; u = dma->resu; 2117104477Ssam while (u != 0) { 2118104477Ssam HIFN_RESR_SYNC(sc, i, 2119104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2120104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2121104477Ssam HIFN_RESR_SYNC(sc, i, 2122104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2123104477Ssam break; 2124104477Ssam } 2125104477Ssam 2126104477Ssam if (i != HIFN_D_RES_RSIZE) { 2127104477Ssam struct hifn_command *cmd; 2128104477Ssam u_int8_t *macbuf = NULL; 2129104477Ssam 2130104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2131104477Ssam cmd = dma->hifn_commands[i]; 2132104477Ssam KASSERT(cmd != NULL, 2133104477Ssam ("hifn_intr: null command slot %u", i)); 2134104477Ssam dma->hifn_commands[i] = NULL; 2135104477Ssam 2136104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2137104477Ssam macbuf = dma->result_bufs[i]; 2138104477Ssam macbuf += 12; 2139104477Ssam } 2140104477Ssam 2141104477Ssam hifn_callback(sc, cmd, macbuf); 2142104477Ssam hifnstats.hst_opackets++; 2143104477Ssam u--; 2144104477Ssam } 2145104477Ssam 2146104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2147104477Ssam i = 0; 2148104477Ssam } 2149104477Ssam dma->resk = i; dma->resu = u; 2150104477Ssam 2151104477Ssam i = dma->srck; u = dma->srcu; 2152104477Ssam while (u != 0) { 2153104477Ssam if (i == HIFN_D_SRC_RSIZE) 2154104477Ssam i = 0; 2155104477Ssam HIFN_SRCR_SYNC(sc, i, 2156104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2157104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2158104477Ssam HIFN_SRCR_SYNC(sc, i, 2159104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2160104477Ssam break; 2161104477Ssam } 2162104477Ssam i++, u--; 2163104477Ssam } 2164104477Ssam dma->srck = i; dma->srcu = u; 2165104477Ssam 2166104477Ssam i = dma->cmdk; u = dma->cmdu; 2167104477Ssam while (u != 0) { 2168104477Ssam HIFN_CMDR_SYNC(sc, i, 2169104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2170104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2171104477Ssam HIFN_CMDR_SYNC(sc, i, 2172104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2173104477Ssam break; 2174104477Ssam } 2175104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2176104477Ssam u--; 2177104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2178104477Ssam } 2179104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2180104477Ssam i = 0; 2181104477Ssam } 2182104477Ssam dma->cmdk = i; dma->cmdu = u; 2183104477Ssam 2184115748Ssam HIFN_UNLOCK(sc); 2185115748Ssam 2186104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2187104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2188104477Ssam#ifdef HIFN_DEBUG 2189104477Ssam if (hifn_debug) 2190104477Ssam device_printf(sc->sc_dev, 2191104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2192104477Ssam sc->sc_needwakeup, 2193104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2194104477Ssam#endif 2195104477Ssam sc->sc_needwakeup &= ~wakeup; 2196104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2197104477Ssam } 2198104477Ssam} 2199104477Ssam 2200104477Ssam/* 2201104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2202104477Ssam * contains our registration id, and should contain an encoded session 2203104477Ssam * id on successful allocation. 2204104477Ssam */ 2205104477Ssamstatic int 2206104477Ssamhifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2207104477Ssam{ 2208104477Ssam struct cryptoini *c; 2209104477Ssam struct hifn_softc *sc = arg; 2210104477Ssam int i, mac = 0, cry = 0; 2211104477Ssam 2212104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2213104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2214104477Ssam return (EINVAL); 2215104477Ssam 2216104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2217104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2218104477Ssam break; 2219104477Ssam if (i == sc->sc_maxses) 2220104477Ssam return (ENOMEM); 2221104477Ssam 2222104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2223104477Ssam switch (c->cri_alg) { 2224104477Ssam case CRYPTO_MD5: 2225104477Ssam case CRYPTO_SHA1: 2226104477Ssam case CRYPTO_MD5_HMAC: 2227104477Ssam case CRYPTO_SHA1_HMAC: 2228104477Ssam if (mac) 2229104477Ssam return (EINVAL); 2230104477Ssam mac = 1; 2231104477Ssam break; 2232104477Ssam case CRYPTO_DES_CBC: 2233104477Ssam case CRYPTO_3DES_CBC: 2234120915Ssam case CRYPTO_AES_CBC: 2235104477Ssam /* XXX this may read fewer, does it matter? */ 2236120915Ssam read_random(sc->sc_sessions[i].hs_iv, 2237120915Ssam c->cri_alg == CRYPTO_AES_CBC ? 2238120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2239104477Ssam /*FALLTHROUGH*/ 2240104477Ssam case CRYPTO_ARC4: 2241104477Ssam if (cry) 2242104477Ssam return (EINVAL); 2243104477Ssam cry = 1; 2244104477Ssam break; 2245104477Ssam default: 2246104477Ssam return (EINVAL); 2247104477Ssam } 2248104477Ssam } 2249104477Ssam if (mac == 0 && cry == 0) 2250104477Ssam return (EINVAL); 2251104477Ssam 2252104477Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2253104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2254104477Ssam 2255104477Ssam return (0); 2256104477Ssam} 2257104477Ssam 2258104477Ssam/* 2259104477Ssam * Deallocate a session. 2260104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2261104477Ssam * XXX to blow away any keys already stored there. 2262104477Ssam */ 2263104477Ssamstatic int 2264104477Ssamhifn_freesession(void *arg, u_int64_t tid) 2265104477Ssam{ 2266104477Ssam struct hifn_softc *sc = arg; 2267104477Ssam int session; 2268116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2269104477Ssam 2270104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2271104477Ssam if (sc == NULL) 2272104477Ssam return (EINVAL); 2273104477Ssam 2274104477Ssam session = HIFN_SESSION(sid); 2275104477Ssam if (session >= sc->sc_maxses) 2276104477Ssam return (EINVAL); 2277104477Ssam 2278104477Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2279104477Ssam return (0); 2280104477Ssam} 2281104477Ssam 2282104477Ssamstatic int 2283104477Ssamhifn_process(void *arg, struct cryptop *crp, int hint) 2284104477Ssam{ 2285104477Ssam struct hifn_softc *sc = arg; 2286104477Ssam struct hifn_command *cmd = NULL; 2287120915Ssam int session, err, ivlen; 2288104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2289104477Ssam 2290104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2291104477Ssam hifnstats.hst_invalid++; 2292104477Ssam return (EINVAL); 2293104477Ssam } 2294104477Ssam session = HIFN_SESSION(crp->crp_sid); 2295104477Ssam 2296104477Ssam if (sc == NULL || session >= sc->sc_maxses) { 2297104477Ssam err = EINVAL; 2298104477Ssam goto errout; 2299104477Ssam } 2300104477Ssam 2301104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2302104477Ssam if (cmd == NULL) { 2303104477Ssam hifnstats.hst_nomem++; 2304104477Ssam err = ENOMEM; 2305104477Ssam goto errout; 2306104477Ssam } 2307104477Ssam 2308104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2309104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2310104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2311104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2312104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2313104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2314104477Ssam } else { 2315104477Ssam err = EINVAL; 2316104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2317104477Ssam } 2318104477Ssam 2319104477Ssam crd1 = crp->crp_desc; 2320104477Ssam if (crd1 == NULL) { 2321104477Ssam err = EINVAL; 2322104477Ssam goto errout; 2323104477Ssam } 2324104477Ssam crd2 = crd1->crd_next; 2325104477Ssam 2326104477Ssam if (crd2 == NULL) { 2327104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2328104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2329104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2330104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2331104477Ssam maccrd = crd1; 2332104477Ssam enccrd = NULL; 2333104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2334104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2335120915Ssam crd1->crd_alg == CRYPTO_AES_CBC || 2336104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2337104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2338104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2339104477Ssam maccrd = NULL; 2340104477Ssam enccrd = crd1; 2341104477Ssam } else { 2342104477Ssam err = EINVAL; 2343104477Ssam goto errout; 2344104477Ssam } 2345104477Ssam } else { 2346104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2347104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2348104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2349104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2350104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2351104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2352120915Ssam crd2->crd_alg == CRYPTO_AES_CBC || 2353104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2354104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2355104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2356104477Ssam maccrd = crd1; 2357104477Ssam enccrd = crd2; 2358104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2359104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2360120915Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2361120915Ssam crd1->crd_alg == CRYPTO_AES_CBC) && 2362104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2363104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2364104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2365104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2366104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2367104477Ssam enccrd = crd1; 2368104477Ssam maccrd = crd2; 2369104477Ssam } else { 2370104477Ssam /* 2371104477Ssam * We cannot order the 7751 as requested 2372104477Ssam */ 2373104477Ssam err = EINVAL; 2374104477Ssam goto errout; 2375104477Ssam } 2376104477Ssam } 2377104477Ssam 2378104477Ssam if (enccrd) { 2379104477Ssam cmd->enccrd = enccrd; 2380104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2381104477Ssam switch (enccrd->crd_alg) { 2382104477Ssam case CRYPTO_ARC4: 2383104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2384104477Ssam if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2385104477Ssam != sc->sc_sessions[session].hs_prev_op) 2386104477Ssam sc->sc_sessions[session].hs_state = 2387104477Ssam HS_STATE_USED; 2388104477Ssam break; 2389104477Ssam case CRYPTO_DES_CBC: 2390104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2391104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2392104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2393104477Ssam break; 2394104477Ssam case CRYPTO_3DES_CBC: 2395104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2396104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2397104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2398104477Ssam break; 2399120915Ssam case CRYPTO_AES_CBC: 2400120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2401120915Ssam HIFN_CRYPT_CMD_MODE_CBC | 2402120915Ssam HIFN_CRYPT_CMD_NEW_IV; 2403120915Ssam break; 2404104477Ssam default: 2405104477Ssam err = EINVAL; 2406104477Ssam goto errout; 2407104477Ssam } 2408104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2409120915Ssam ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2410120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2411104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2412104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2413120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2414104477Ssam else 2415104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2416120915Ssam cmd->iv, ivlen); 2417104477Ssam 2418104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2419104477Ssam == 0) { 2420104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2421104477Ssam m_copyback(cmd->src_m, 2422104477Ssam enccrd->crd_inject, 2423120915Ssam ivlen, cmd->iv); 2424104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2425104477Ssam cuio_copyback(cmd->src_io, 2426104477Ssam enccrd->crd_inject, 2427120915Ssam ivlen, cmd->iv); 2428104477Ssam } 2429104477Ssam } else { 2430104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2431120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2432104477Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 2433104477Ssam m_copydata(cmd->src_m, 2434120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2435104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2436104477Ssam cuio_copydata(cmd->src_io, 2437120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2438104477Ssam } 2439104477Ssam } 2440104477Ssam 2441125330Sphk if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2442125330Sphk cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2443104477Ssam cmd->ck = enccrd->crd_key; 2444104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2445104477Ssam 2446120915Ssam /* 2447120915Ssam * Need to specify the size for the AES key in the masks. 2448120915Ssam */ 2449120915Ssam if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2450120915Ssam HIFN_CRYPT_CMD_ALG_AES) { 2451120915Ssam switch (cmd->cklen) { 2452120915Ssam case 16: 2453120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2454120915Ssam break; 2455120915Ssam case 24: 2456120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2457120915Ssam break; 2458120915Ssam case 32: 2459120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2460120915Ssam break; 2461120915Ssam default: 2462120915Ssam err = EINVAL; 2463120915Ssam goto errout; 2464120915Ssam } 2465120915Ssam } 2466120915Ssam 2467104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2468104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2469104477Ssam } 2470104477Ssam 2471104477Ssam if (maccrd) { 2472104477Ssam cmd->maccrd = maccrd; 2473104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2474104477Ssam 2475104477Ssam switch (maccrd->crd_alg) { 2476104477Ssam case CRYPTO_MD5: 2477104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2478104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2479104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2480104477Ssam break; 2481104477Ssam case CRYPTO_MD5_HMAC: 2482104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2483104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2484104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2485104477Ssam break; 2486104477Ssam case CRYPTO_SHA1: 2487104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2488104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2489104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2490104477Ssam break; 2491104477Ssam case CRYPTO_SHA1_HMAC: 2492104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2493104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2494104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2495104477Ssam break; 2496104477Ssam } 2497104477Ssam 2498104477Ssam if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2499104477Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2500104477Ssam sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2501104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2502104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2503104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2504104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2505104477Ssam } 2506104477Ssam } 2507104477Ssam 2508104477Ssam cmd->crp = crp; 2509104477Ssam cmd->session_num = session; 2510104477Ssam cmd->softc = sc; 2511104477Ssam 2512104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2513104477Ssam if (!err) { 2514104477Ssam if (enccrd) 2515104477Ssam sc->sc_sessions[session].hs_prev_op = 2516104477Ssam enccrd->crd_flags & CRD_F_ENCRYPT; 2517104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2518104477Ssam sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2519104477Ssam return 0; 2520104477Ssam } else if (err == ERESTART) { 2521104477Ssam /* 2522104477Ssam * There weren't enough resources to dispatch the request 2523104477Ssam * to the part. Notify the caller so they'll requeue this 2524104477Ssam * request and resubmit it again soon. 2525104477Ssam */ 2526104477Ssam#ifdef HIFN_DEBUG 2527104477Ssam if (hifn_debug) 2528104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2529104477Ssam#endif 2530104477Ssam free(cmd, M_DEVBUF); 2531104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2532104477Ssam return (err); 2533104477Ssam } 2534104477Ssam 2535104477Ssamerrout: 2536104477Ssam if (cmd != NULL) 2537104477Ssam free(cmd, M_DEVBUF); 2538104477Ssam if (err == EINVAL) 2539104477Ssam hifnstats.hst_invalid++; 2540104477Ssam else 2541104477Ssam hifnstats.hst_nomem++; 2542104477Ssam crp->crp_etype = err; 2543104477Ssam crypto_done(crp); 2544104477Ssam return (err); 2545104477Ssam} 2546104477Ssam 2547104477Ssamstatic void 2548104477Ssamhifn_abort(struct hifn_softc *sc) 2549104477Ssam{ 2550104477Ssam struct hifn_dma *dma = sc->sc_dma; 2551104477Ssam struct hifn_command *cmd; 2552104477Ssam struct cryptop *crp; 2553104477Ssam int i, u; 2554104477Ssam 2555104477Ssam i = dma->resk; u = dma->resu; 2556104477Ssam while (u != 0) { 2557104477Ssam cmd = dma->hifn_commands[i]; 2558104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2559104477Ssam dma->hifn_commands[i] = NULL; 2560104477Ssam crp = cmd->crp; 2561104477Ssam 2562104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2563104477Ssam /* Salvage what we can. */ 2564104477Ssam u_int8_t *macbuf; 2565104477Ssam 2566104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2567104477Ssam macbuf = dma->result_bufs[i]; 2568104477Ssam macbuf += 12; 2569104477Ssam } else 2570104477Ssam macbuf = NULL; 2571104477Ssam hifnstats.hst_opackets++; 2572104477Ssam hifn_callback(sc, cmd, macbuf); 2573104477Ssam } else { 2574104477Ssam if (cmd->src_map == cmd->dst_map) { 2575104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2576104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2577104477Ssam } else { 2578104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2579104477Ssam BUS_DMASYNC_POSTWRITE); 2580104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2581104477Ssam BUS_DMASYNC_POSTREAD); 2582104477Ssam } 2583104477Ssam 2584104477Ssam if (cmd->src_m != cmd->dst_m) { 2585104477Ssam m_freem(cmd->src_m); 2586104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2587104477Ssam } 2588104477Ssam 2589104477Ssam /* non-shared buffers cannot be restarted */ 2590104477Ssam if (cmd->src_map != cmd->dst_map) { 2591104477Ssam /* 2592104477Ssam * XXX should be EAGAIN, delayed until 2593104477Ssam * after the reset. 2594104477Ssam */ 2595104477Ssam crp->crp_etype = ENOMEM; 2596104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2597104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2598104477Ssam } else 2599104477Ssam crp->crp_etype = ENOMEM; 2600104477Ssam 2601104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2602104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2603104477Ssam 2604104477Ssam free(cmd, M_DEVBUF); 2605104477Ssam if (crp->crp_etype != EAGAIN) 2606104477Ssam crypto_done(crp); 2607104477Ssam } 2608104477Ssam 2609104477Ssam if (++i == HIFN_D_RES_RSIZE) 2610104477Ssam i = 0; 2611104477Ssam u--; 2612104477Ssam } 2613104477Ssam dma->resk = i; dma->resu = u; 2614104477Ssam 2615104477Ssam /* Force upload of key next time */ 2616104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2617104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2618104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2619104477Ssam 2620104477Ssam hifn_reset_board(sc, 1); 2621104477Ssam hifn_init_dma(sc); 2622104477Ssam hifn_init_pci_registers(sc); 2623104477Ssam} 2624104477Ssam 2625104477Ssamstatic void 2626104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2627104477Ssam{ 2628104477Ssam struct hifn_dma *dma = sc->sc_dma; 2629104477Ssam struct cryptop *crp = cmd->crp; 2630104477Ssam struct cryptodesc *crd; 2631104477Ssam struct mbuf *m; 2632120915Ssam int totlen, i, u, ivlen; 2633104477Ssam 2634104477Ssam if (cmd->src_map == cmd->dst_map) { 2635104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2636104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2637104477Ssam } else { 2638104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2639104477Ssam BUS_DMASYNC_POSTWRITE); 2640104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2641104477Ssam BUS_DMASYNC_POSTREAD); 2642104477Ssam } 2643104477Ssam 2644104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2645104477Ssam if (cmd->src_m != cmd->dst_m) { 2646104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2647104477Ssam totlen = cmd->src_mapsize; 2648104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2649104477Ssam if (totlen < m->m_len) { 2650104477Ssam m->m_len = totlen; 2651104477Ssam totlen = 0; 2652104477Ssam } else 2653104477Ssam totlen -= m->m_len; 2654104477Ssam } 2655104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2656104477Ssam m_freem(cmd->src_m); 2657104477Ssam } 2658104477Ssam } 2659104477Ssam 2660104477Ssam if (cmd->sloplen != 0) { 2661104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2662104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2663104477Ssam cmd->src_mapsize - cmd->sloplen, 2664104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2665104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2666104477Ssam cuio_copyback((struct uio *)crp->crp_buf, 2667104477Ssam cmd->src_mapsize - cmd->sloplen, 2668104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2669104477Ssam } 2670104477Ssam 2671104477Ssam i = dma->dstk; u = dma->dstu; 2672104477Ssam while (u != 0) { 2673104477Ssam if (i == HIFN_D_DST_RSIZE) 2674104477Ssam i = 0; 2675104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2676104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2677104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2678104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2679104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2680104477Ssam break; 2681104477Ssam } 2682104477Ssam i++, u--; 2683104477Ssam } 2684104477Ssam dma->dstk = i; dma->dstu = u; 2685104477Ssam 2686104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2687104477Ssam 2688104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2689104477Ssam HIFN_BASE_CMD_CRYPT) { 2690104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2691104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2692120915Ssam crd->crd_alg != CRYPTO_3DES_CBC && 2693120915Ssam crd->crd_alg != CRYPTO_AES_CBC) 2694104477Ssam continue; 2695120915Ssam ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2696120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2697104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2698104477Ssam m_copydata((struct mbuf *)crp->crp_buf, 2699120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2700104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2701104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) { 2702104477Ssam cuio_copydata((struct uio *)crp->crp_buf, 2703120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2704104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2705104477Ssam } 2706104477Ssam break; 2707104477Ssam } 2708104477Ssam } 2709104477Ssam 2710104477Ssam if (macbuf != NULL) { 2711104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2712105275Ssam int len; 2713104477Ssam 2714105275Ssam if (crd->crd_alg == CRYPTO_MD5) 2715105275Ssam len = 16; 2716105275Ssam else if (crd->crd_alg == CRYPTO_SHA1) 2717105275Ssam len = 20; 2718105275Ssam else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2719105275Ssam crd->crd_alg == CRYPTO_SHA1_HMAC) 2720105275Ssam len = 12; 2721105275Ssam else 2722104477Ssam continue; 2723104477Ssam 2724104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2725104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2726104477Ssam crd->crd_inject, len, macbuf); 2727104477Ssam else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2728104477Ssam bcopy((caddr_t)macbuf, crp->crp_mac, len); 2729104477Ssam break; 2730104477Ssam } 2731104477Ssam } 2732104477Ssam 2733104477Ssam if (cmd->src_map != cmd->dst_map) { 2734104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2735104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2736104477Ssam } 2737104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2738104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2739104477Ssam free(cmd, M_DEVBUF); 2740104477Ssam crypto_done(crp); 2741104477Ssam} 2742104477Ssam 2743104477Ssam/* 2744104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2745104477Ssam * and Group 1 registers; avoid conditions that could create 2746104477Ssam * burst writes by doing a read in between the writes. 2747104477Ssam * 2748104477Ssam * NB: The read we interpose is always to the same register; 2749104477Ssam * we do this because reading from an arbitrary (e.g. last) 2750104477Ssam * register may not always work. 2751104477Ssam */ 2752104477Ssamstatic void 2753104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2754104477Ssam{ 2755104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2756104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2757104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2758104477Ssam sc->sc_bar0_lastreg = reg; 2759104477Ssam } 2760104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2761104477Ssam} 2762104477Ssam 2763104477Ssamstatic void 2764104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2765104477Ssam{ 2766104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2767104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2768104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2769104477Ssam sc->sc_bar1_lastreg = reg; 2770104477Ssam } 2771104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2772104477Ssam} 2773