hifn7751.c revision 125330
1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3104477Ssam/* 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9120915Ssam * Copyright (c) 2003 Hifn Inc. 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam */ 42104477Ssam 43119418Sobrien#include <sys/cdefs.h> 44119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/hifn/hifn7751.c 125330 2004-02-02 17:06:34Z phk $"); 45119418Sobrien 46104477Ssam/* 47120915Ssam * Driver for various Hifn encryption processors. 48104477Ssam */ 49112124Ssam#include "opt_hifn.h" 50104477Ssam 51104477Ssam#include <sys/param.h> 52104477Ssam#include <sys/systm.h> 53104477Ssam#include <sys/proc.h> 54104477Ssam#include <sys/errno.h> 55104477Ssam#include <sys/malloc.h> 56104477Ssam#include <sys/kernel.h> 57104477Ssam#include <sys/mbuf.h> 58104477Ssam#include <sys/lock.h> 59104477Ssam#include <sys/mutex.h> 60104477Ssam#include <sys/sysctl.h> 61104477Ssam 62104477Ssam#include <vm/vm.h> 63104477Ssam#include <vm/pmap.h> 64104477Ssam 65104477Ssam#include <machine/clock.h> 66104477Ssam#include <machine/bus.h> 67104477Ssam#include <machine/resource.h> 68104477Ssam#include <sys/bus.h> 69104477Ssam#include <sys/rman.h> 70104477Ssam 71104477Ssam#include <opencrypto/cryptodev.h> 72104477Ssam#include <sys/random.h> 73104477Ssam 74119280Simp#include <dev/pci/pcivar.h> 75119280Simp#include <dev/pci/pcireg.h> 76112124Ssam 77112124Ssam#ifdef HIFN_RNDTEST 78112124Ssam#include <dev/rndtest/rndtest.h> 79112124Ssam#endif 80104477Ssam#include <dev/hifn/hifn7751reg.h> 81104477Ssam#include <dev/hifn/hifn7751var.h> 82104477Ssam 83104477Ssam/* 84104477Ssam * Prototypes and count for the pci_device structure 85104477Ssam */ 86104477Ssamstatic int hifn_probe(device_t); 87104477Ssamstatic int hifn_attach(device_t); 88104477Ssamstatic int hifn_detach(device_t); 89104477Ssamstatic int hifn_suspend(device_t); 90104477Ssamstatic int hifn_resume(device_t); 91104477Ssamstatic void hifn_shutdown(device_t); 92104477Ssam 93104477Ssamstatic device_method_t hifn_methods[] = { 94104477Ssam /* Device interface */ 95104477Ssam DEVMETHOD(device_probe, hifn_probe), 96104477Ssam DEVMETHOD(device_attach, hifn_attach), 97104477Ssam DEVMETHOD(device_detach, hifn_detach), 98104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 99104477Ssam DEVMETHOD(device_resume, hifn_resume), 100104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 101104477Ssam 102104477Ssam /* bus interface */ 103104477Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 104104477Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 105104477Ssam 106104477Ssam { 0, 0 } 107104477Ssam}; 108104477Ssamstatic driver_t hifn_driver = { 109104477Ssam "hifn", 110104477Ssam hifn_methods, 111104477Ssam sizeof (struct hifn_softc) 112104477Ssam}; 113104477Ssamstatic devclass_t hifn_devclass; 114104477Ssam 115104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 116105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 117112124Ssam#ifdef HIFN_RNDTEST 118112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 119112124Ssam#endif 120104477Ssam 121104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 122104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 123104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 124104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 125104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 126104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 127104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 128104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 129104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 130104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 131104477Ssamstatic void hifn_sessions(struct hifn_softc *); 132104477Ssamstatic void hifn_intr(void *); 133104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 134104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 135104477Ssamstatic int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 136104477Ssamstatic int hifn_freesession(void *, u_int64_t); 137104477Ssamstatic int hifn_process(void *, struct cryptop *, int); 138104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 139104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 140104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 141104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 142104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 143104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 144104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 145104477Ssamstatic void hifn_rng(void *); 146104477Ssamstatic void hifn_tick(void *); 147104477Ssamstatic void hifn_abort(struct hifn_softc *); 148104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 149104477Ssam 150104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 151104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 152104477Ssam 153104477Ssamstatic __inline__ u_int32_t 154104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 155104477Ssam{ 156104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 157104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 158104477Ssam return (v); 159104477Ssam} 160104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 161104477Ssam 162104477Ssamstatic __inline__ u_int32_t 163104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 164104477Ssam{ 165104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 166104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 167104477Ssam return (v); 168104477Ssam} 169104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 170104477Ssam 171109596SsamSYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 172109596Ssam 173104477Ssam#ifdef HIFN_DEBUG 174104477Ssamstatic int hifn_debug = 0; 175109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 176109596Ssam 0, "control debugging msgs"); 177104477Ssam#endif 178104477Ssam 179104477Ssamstatic struct hifn_stats hifnstats; 180109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 181109596Ssam hifn_stats, "driver statistics"); 182112121Ssamstatic int hifn_maxbatch = 1; 183109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 184109596Ssam 0, "max ops to batch w/o interrupt"); 185104477Ssam 186104477Ssam/* 187104477Ssam * Probe for a supported device. The PCI vendor and device 188104477Ssam * IDs are used to detect devices we know how to handle. 189104477Ssam */ 190104477Ssamstatic int 191104477Ssamhifn_probe(device_t dev) 192104477Ssam{ 193104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 194104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 195104477Ssam return (0); 196104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 197104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 198104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 199120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 200120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 201104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 202104477Ssam return (0); 203104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 204104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 205104477Ssam return (0); 206104477Ssam return (ENXIO); 207104477Ssam} 208104477Ssam 209104477Ssamstatic void 210104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 211104477Ssam{ 212104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 213104477Ssam *paddr = segs->ds_addr; 214104477Ssam} 215104477Ssam 216104477Ssamstatic const char* 217104477Ssamhifn_partname(struct hifn_softc *sc) 218104477Ssam{ 219104477Ssam /* XXX sprintf numbers when not decoded */ 220104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 221104477Ssam case PCI_VENDOR_HIFN: 222104477Ssam switch (pci_get_device(sc->sc_dev)) { 223104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 224104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 225104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 226104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 227120915Ssam case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 228120915Ssam case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 229104477Ssam } 230104477Ssam return "Hifn unknown-part"; 231104477Ssam case PCI_VENDOR_INVERTEX: 232104477Ssam switch (pci_get_device(sc->sc_dev)) { 233104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 234104477Ssam } 235104477Ssam return "Invertex unknown-part"; 236104477Ssam case PCI_VENDOR_NETSEC: 237104477Ssam switch (pci_get_device(sc->sc_dev)) { 238104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 239104477Ssam } 240104477Ssam return "NetSec unknown-part"; 241104477Ssam } 242104477Ssam return "Unknown-vendor unknown-part"; 243104477Ssam} 244104477Ssam 245112124Ssamstatic void 246112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 247112124Ssam{ 248112124Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 249112124Ssam} 250112124Ssam 251104477Ssam/* 252104477Ssam * Attach an interface that successfully probed. 253104477Ssam */ 254104477Ssamstatic int 255104477Ssamhifn_attach(device_t dev) 256104477Ssam{ 257104477Ssam struct hifn_softc *sc = device_get_softc(dev); 258104477Ssam u_int32_t cmd; 259104477Ssam caddr_t kva; 260104477Ssam int rseg, rid; 261104477Ssam char rbase; 262104477Ssam u_int16_t ena, rev; 263104477Ssam 264104477Ssam KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 265104477Ssam bzero(sc, sizeof (*sc)); 266104477Ssam sc->sc_dev = dev; 267104477Ssam 268115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 269104477Ssam 270104477Ssam /* XXX handle power management */ 271104477Ssam 272104477Ssam /* 273120915Ssam * The 7951 and 795x have a random number generator and 274104477Ssam * public key support; note this. 275104477Ssam */ 276104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 277120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 278120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 279120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 280104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 281104477Ssam /* 282104477Ssam * The 7811 has a random number generator and 283104477Ssam * we also note it's identity 'cuz of some quirks. 284104477Ssam */ 285104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 286104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 287104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 288104477Ssam 289104477Ssam /* 290120915Ssam * The 795x parts support AES. 291120915Ssam */ 292120915Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 293120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 294120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 295120915Ssam sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 296120915Ssam 297120915Ssam /* 298104477Ssam * Configure support for memory-mapped access to 299104477Ssam * registers and for DMA operations. 300104477Ssam */ 301104477Ssam#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 302104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 303104477Ssam cmd |= PCIM_ENA; 304104477Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 305104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 306104477Ssam if ((cmd & PCIM_ENA) != PCIM_ENA) { 307104477Ssam device_printf(dev, "failed to enable %s\n", 308104477Ssam (cmd & PCIM_ENA) == 0 ? 309104477Ssam "memory mapping & bus mastering" : 310104477Ssam (cmd & PCIM_CMD_MEMEN) == 0 ? 311104477Ssam "memory mapping" : "bus mastering"); 312104477Ssam goto fail_pci; 313104477Ssam } 314104477Ssam#undef PCIM_ENA 315104477Ssam 316104477Ssam /* 317104477Ssam * Setup PCI resources. Note that we record the bus 318104477Ssam * tag and handle for each register mapping, this is 319104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 320104477Ssam * and WRITE_REG_1 macros throughout the driver. 321104477Ssam */ 322104477Ssam rid = HIFN_BAR0; 323104477Ssam sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 324104477Ssam 0, ~0, 1, RF_ACTIVE); 325104477Ssam if (sc->sc_bar0res == NULL) { 326104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 327104477Ssam goto fail_pci; 328104477Ssam } 329104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 330104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 331104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 332104477Ssam 333104477Ssam rid = HIFN_BAR1; 334104477Ssam sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 335104477Ssam 0, ~0, 1, RF_ACTIVE); 336104477Ssam if (sc->sc_bar1res == NULL) { 337104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 338104477Ssam goto fail_io0; 339104477Ssam } 340104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 341104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 342104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 343104477Ssam 344104477Ssam hifn_set_retry(sc); 345104477Ssam 346104477Ssam /* 347104477Ssam * Setup the area where the Hifn DMA's descriptors 348104477Ssam * and associated data structures. 349104477Ssam */ 350104477Ssam if (bus_dma_tag_create(NULL, /* parent */ 351104477Ssam 1, 0, /* alignment,boundary */ 352104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 353104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 354104477Ssam NULL, NULL, /* filter, filterarg */ 355104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 356104477Ssam MAX_SCATTER, /* nsegments */ 357104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 358104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 359117126Sscottl NULL, /* lockfunc */ 360117126Sscottl NULL, /* lockarg */ 361104477Ssam &sc->sc_dmat)) { 362104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 363104477Ssam goto fail_io1; 364104477Ssam } 365104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 366104477Ssam device_printf(dev, "cannot create dma map\n"); 367104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 368104477Ssam goto fail_io1; 369104477Ssam } 370104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 371104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 372104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 373104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 374104477Ssam goto fail_io1; 375104477Ssam } 376104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 377104477Ssam sizeof (*sc->sc_dma), 378104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 379104477Ssam BUS_DMA_NOWAIT)) { 380104477Ssam device_printf(dev, "cannot load dma map\n"); 381104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 382104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 383104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 384104477Ssam goto fail_io1; 385104477Ssam } 386104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 387104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 388104477Ssam 389123824Ssam KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 390123824Ssam KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 391123824Ssam KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 392123824Ssam KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 393104477Ssam 394104477Ssam /* 395104477Ssam * Reset the board and do the ``secret handshake'' 396104477Ssam * to enable the crypto support. Then complete the 397104477Ssam * initialization procedure by setting up the interrupt 398104477Ssam * and hooking in to the system crypto support so we'll 399104477Ssam * get used for system services like the crypto device, 400104477Ssam * IPsec, RNG device, etc. 401104477Ssam */ 402104477Ssam hifn_reset_board(sc, 0); 403104477Ssam 404104477Ssam if (hifn_enable_crypto(sc) != 0) { 405104477Ssam device_printf(dev, "crypto enabling failed\n"); 406104477Ssam goto fail_mem; 407104477Ssam } 408104477Ssam hifn_reset_puc(sc); 409104477Ssam 410104477Ssam hifn_init_dma(sc); 411104477Ssam hifn_init_pci_registers(sc); 412104477Ssam 413120915Ssam /* XXX can't dynamically determine ram type for 795x; force dram */ 414120915Ssam if (sc->sc_flags & HIFN_IS_7956) 415120915Ssam sc->sc_drammodel = 1; 416120915Ssam else if (hifn_ramtype(sc)) 417104477Ssam goto fail_mem; 418104477Ssam 419104477Ssam if (sc->sc_drammodel == 0) 420104477Ssam hifn_sramsize(sc); 421104477Ssam else 422104477Ssam hifn_dramsize(sc); 423104477Ssam 424104477Ssam /* 425104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 426104477Ssam * of the address lines were left floating 427104477Ssam */ 428104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 429104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 430104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 431104477Ssam sc->sc_ramsize >>= 1; 432104477Ssam 433104477Ssam /* 434104477Ssam * Arrange the interrupt line. 435104477Ssam */ 436104477Ssam rid = 0; 437104477Ssam sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 438104477Ssam 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 439104477Ssam if (sc->sc_irq == NULL) { 440104477Ssam device_printf(dev, "could not map interrupt\n"); 441104477Ssam goto fail_mem; 442104477Ssam } 443104477Ssam /* 444104477Ssam * NB: Network code assumes we are blocked with splimp() 445104477Ssam * so make sure the IRQ is marked appropriately. 446104477Ssam */ 447115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 448104477Ssam hifn_intr, sc, &sc->sc_intrhand)) { 449104477Ssam device_printf(dev, "could not setup interrupt\n"); 450104477Ssam goto fail_intr2; 451104477Ssam } 452104477Ssam 453104477Ssam hifn_sessions(sc); 454104477Ssam 455104477Ssam /* 456104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 457104477Ssam * from the 7951. 458104477Ssam */ 459104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 460104477Ssam 461104477Ssam rseg = sc->sc_ramsize / 1024; 462104477Ssam rbase = 'K'; 463104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 464104477Ssam rbase = 'M'; 465104477Ssam rseg /= 1024; 466104477Ssam } 467104477Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 468104477Ssam hifn_partname(sc), rev, 469104477Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's', 470104477Ssam sc->sc_maxses); 471104477Ssam 472104477Ssam sc->sc_cid = crypto_get_driverid(0); 473104477Ssam if (sc->sc_cid < 0) { 474104477Ssam device_printf(dev, "could not get crypto driver id\n"); 475104477Ssam goto fail_intr; 476104477Ssam } 477104477Ssam 478104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 479104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 480104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 481104477Ssam 482104477Ssam switch (ena) { 483104477Ssam case HIFN_PUSTAT_ENA_2: 484104477Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 485104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 486104477Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 487104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 488120915Ssam if (sc->sc_flags & HIFN_HAS_AES) 489120915Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 490120915Ssam hifn_newsession, hifn_freesession, 491120915Ssam hifn_process, sc); 492104477Ssam /*FALLTHROUGH*/ 493104477Ssam case HIFN_PUSTAT_ENA_1: 494104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 495104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 496104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 497104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 498104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 499104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 500104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 501104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 502104477Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 503104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 504104477Ssam break; 505104477Ssam } 506104477Ssam 507104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 508104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 509104477Ssam 510104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 511104477Ssam hifn_init_pubrng(sc); 512104477Ssam 513119137Ssam callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 514104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 515104477Ssam 516104477Ssam return (0); 517104477Ssam 518104477Ssamfail_intr: 519104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 520104477Ssamfail_intr2: 521104477Ssam /* XXX don't store rid */ 522104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 523104477Ssamfail_mem: 524104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 525104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 526104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 527104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 528104477Ssam 529104477Ssam /* Turn off DMA polling */ 530104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 531104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 532104477Ssamfail_io1: 533104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 534104477Ssamfail_io0: 535104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 536104477Ssamfail_pci: 537104477Ssam mtx_destroy(&sc->sc_mtx); 538104477Ssam return (ENXIO); 539104477Ssam} 540104477Ssam 541104477Ssam/* 542104477Ssam * Detach an interface that successfully probed. 543104477Ssam */ 544104477Ssamstatic int 545104477Ssamhifn_detach(device_t dev) 546104477Ssam{ 547104477Ssam struct hifn_softc *sc = device_get_softc(dev); 548104477Ssam 549104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 550104477Ssam 551115748Ssam /* disable interrupts */ 552115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 553104477Ssam 554104477Ssam /*XXX other resources */ 555104477Ssam callout_stop(&sc->sc_tickto); 556104477Ssam callout_stop(&sc->sc_rngto); 557115848Ssam#ifdef HIFN_RNDTEST 558115848Ssam if (sc->sc_rndtest) 559115862Ssam rndtest_detach(sc->sc_rndtest); 560115848Ssam#endif 561104477Ssam 562104477Ssam /* Turn off DMA polling */ 563104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 564104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 565104477Ssam 566104477Ssam crypto_unregister_all(sc->sc_cid); 567104477Ssam 568104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 569104477Ssam 570104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 571104477Ssam /* XXX don't store rid */ 572104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 573104477Ssam 574104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 575104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 576104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 577104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 578104477Ssam 579104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 580104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 581104477Ssam 582104477Ssam mtx_destroy(&sc->sc_mtx); 583104477Ssam 584104477Ssam return (0); 585104477Ssam} 586104477Ssam 587104477Ssam/* 588104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 589104477Ssam * get confused by errant DMAs when rebooting. 590104477Ssam */ 591104477Ssamstatic void 592104477Ssamhifn_shutdown(device_t dev) 593104477Ssam{ 594104477Ssam#ifdef notyet 595104477Ssam hifn_stop(device_get_softc(dev)); 596104477Ssam#endif 597104477Ssam} 598104477Ssam 599104477Ssam/* 600104477Ssam * Device suspend routine. Stop the interface and save some PCI 601104477Ssam * settings in case the BIOS doesn't restore them properly on 602104477Ssam * resume. 603104477Ssam */ 604104477Ssamstatic int 605104477Ssamhifn_suspend(device_t dev) 606104477Ssam{ 607104477Ssam struct hifn_softc *sc = device_get_softc(dev); 608104477Ssam#ifdef notyet 609104477Ssam int i; 610104477Ssam 611104477Ssam hifn_stop(sc); 612104477Ssam for (i = 0; i < 5; i++) 613119690Sjhb sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 614104477Ssam sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 615104477Ssam sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 616104477Ssam sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 617104477Ssam sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 618104477Ssam#endif 619104477Ssam sc->sc_suspended = 1; 620104477Ssam 621104477Ssam return (0); 622104477Ssam} 623104477Ssam 624104477Ssam/* 625104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 626104477Ssam * doesn't, re-enable busmastering, and restart the interface if 627104477Ssam * appropriate. 628104477Ssam */ 629104477Ssamstatic int 630104477Ssamhifn_resume(device_t dev) 631104477Ssam{ 632104477Ssam struct hifn_softc *sc = device_get_softc(dev); 633104477Ssam#ifdef notyet 634104477Ssam int i; 635104477Ssam 636104477Ssam /* better way to do this? */ 637104477Ssam for (i = 0; i < 5; i++) 638119690Sjhb pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 639104477Ssam pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 640104477Ssam pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 641104477Ssam pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 642104477Ssam pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 643104477Ssam 644104477Ssam /* reenable busmastering */ 645104477Ssam pci_enable_busmaster(dev); 646104477Ssam pci_enable_io(dev, HIFN_RES); 647104477Ssam 648104477Ssam /* reinitialize interface if necessary */ 649104477Ssam if (ifp->if_flags & IFF_UP) 650104477Ssam rl_init(sc); 651104477Ssam#endif 652104477Ssam sc->sc_suspended = 0; 653104477Ssam 654104477Ssam return (0); 655104477Ssam} 656104477Ssam 657104477Ssamstatic int 658104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 659104477Ssam{ 660104477Ssam u_int32_t r; 661104477Ssam int i; 662104477Ssam 663112124Ssam#ifdef HIFN_RNDTEST 664112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 665112124Ssam if (sc->sc_rndtest) 666112124Ssam sc->sc_harvest = rndtest_harvest; 667112124Ssam else 668112124Ssam sc->sc_harvest = default_harvest; 669112124Ssam#else 670112124Ssam sc->sc_harvest = default_harvest; 671112124Ssam#endif 672104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 673104477Ssam /* Reset 7951 public key/rng engine */ 674104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 675104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 676104477Ssam 677104477Ssam for (i = 0; i < 100; i++) { 678104477Ssam DELAY(1000); 679104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 680104477Ssam HIFN_PUBRST_RESET) == 0) 681104477Ssam break; 682104477Ssam } 683104477Ssam 684104477Ssam if (i == 100) { 685104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 686104477Ssam return (1); 687104477Ssam } 688104477Ssam } 689104477Ssam 690104477Ssam /* Enable the rng, if available */ 691104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 692104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 693104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 694104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 695104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 696104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 697104477Ssam } 698104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 699104477Ssam HIFN_7811_RNGCFG_DEFL); 700104477Ssam r |= HIFN_7811_RNGENA_ENA; 701104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 702104477Ssam } else 703104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 704104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 705104477Ssam HIFN_RNGCFG_ENA); 706104477Ssam 707104477Ssam sc->sc_rngfirst = 1; 708104477Ssam if (hz >= 100) 709104477Ssam sc->sc_rnghz = hz / 100; 710104477Ssam else 711104477Ssam sc->sc_rnghz = 1; 712119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 713104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 714104477Ssam } 715104477Ssam 716104477Ssam /* Enable public key engine, if available */ 717104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 718104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 719104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 720104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 721104477Ssam } 722104477Ssam 723104477Ssam return (0); 724104477Ssam} 725104477Ssam 726104477Ssamstatic void 727104477Ssamhifn_rng(void *vsc) 728104477Ssam{ 729104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 730104477Ssam struct hifn_softc *sc = vsc; 731104477Ssam u_int32_t sts, num[2]; 732104477Ssam int i; 733104477Ssam 734104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 735104477Ssam for (i = 0; i < 5; i++) { 736104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 737104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 738104477Ssam device_printf(sc->sc_dev, 739104477Ssam "RNG underflow: disabling\n"); 740104477Ssam return; 741104477Ssam } 742104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 743104477Ssam break; 744104477Ssam 745104477Ssam /* 746104477Ssam * There are at least two words in the RNG FIFO 747104477Ssam * at this point. 748104477Ssam */ 749104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 750104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 751104477Ssam /* NB: discard first data read */ 752104477Ssam if (sc->sc_rngfirst) 753104477Ssam sc->sc_rngfirst = 0; 754104477Ssam else 755112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 756112124Ssam num, sizeof (num)); 757104477Ssam } 758104477Ssam } else { 759104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 760104477Ssam 761104477Ssam /* NB: discard first data read */ 762104477Ssam if (sc->sc_rngfirst) 763104477Ssam sc->sc_rngfirst = 0; 764104477Ssam else 765112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 766112124Ssam num, sizeof (num[0])); 767104477Ssam } 768104477Ssam 769104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 770104477Ssam#undef RANDOM_BITS 771104477Ssam} 772104477Ssam 773104477Ssamstatic void 774104477Ssamhifn_puc_wait(struct hifn_softc *sc) 775104477Ssam{ 776104477Ssam int i; 777104477Ssam 778104477Ssam for (i = 5000; i > 0; i--) { 779104477Ssam DELAY(1); 780104477Ssam if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 781104477Ssam break; 782104477Ssam } 783104477Ssam if (!i) 784104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 785104477Ssam} 786104477Ssam 787104477Ssam/* 788104477Ssam * Reset the processing unit. 789104477Ssam */ 790104477Ssamstatic void 791104477Ssamhifn_reset_puc(struct hifn_softc *sc) 792104477Ssam{ 793104477Ssam /* Reset processing unit */ 794104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 795104477Ssam hifn_puc_wait(sc); 796104477Ssam} 797104477Ssam 798104477Ssam/* 799104477Ssam * Set the Retry and TRDY registers; note that we set them to 800104477Ssam * zero because the 7811 locks up when forced to retry (section 801104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 802104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 803104477Ssam */ 804104477Ssamstatic void 805104477Ssamhifn_set_retry(struct hifn_softc *sc) 806104477Ssam{ 807104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 808104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 809104477Ssam pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 810104477Ssam} 811104477Ssam 812104477Ssam/* 813104477Ssam * Resets the board. Values in the regesters are left as is 814104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 815104477Ssam */ 816104477Ssamstatic void 817104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 818104477Ssam{ 819104477Ssam u_int32_t reg; 820104477Ssam 821104477Ssam /* 822104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 823104477Ssam * resetting the board and zeros out the other fields. 824104477Ssam */ 825104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 826104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 827104477Ssam 828104477Ssam /* 829104477Ssam * Now that polling has been disabled, we have to wait 1 ms 830104477Ssam * before resetting the board. 831104477Ssam */ 832104477Ssam DELAY(1000); 833104477Ssam 834104477Ssam /* Reset the DMA unit */ 835104477Ssam if (full) { 836104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 837104477Ssam DELAY(1000); 838104477Ssam } else { 839104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 840104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 841104477Ssam hifn_reset_puc(sc); 842104477Ssam } 843104477Ssam 844104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 845104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 846104477Ssam 847104477Ssam /* Bring dma unit out of reset */ 848104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 849104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 850104477Ssam 851104477Ssam hifn_puc_wait(sc); 852104477Ssam hifn_set_retry(sc); 853104477Ssam 854104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 855104477Ssam for (reg = 0; reg < 1000; reg++) { 856104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 857104477Ssam HIFN_MIPSRST_CRAMINIT) 858104477Ssam break; 859104477Ssam DELAY(1000); 860104477Ssam } 861104477Ssam if (reg == 1000) 862104477Ssam printf(": cram init timeout\n"); 863104477Ssam } 864104477Ssam} 865104477Ssam 866104477Ssamstatic u_int32_t 867104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 868104477Ssam{ 869104477Ssam int i; 870104477Ssam u_int32_t v; 871104477Ssam 872104477Ssam for (i = 0; i < cnt; i++) { 873104477Ssam 874104477Ssam /* get the parity */ 875104477Ssam v = a & 0x80080125; 876104477Ssam v ^= v >> 16; 877104477Ssam v ^= v >> 8; 878104477Ssam v ^= v >> 4; 879104477Ssam v ^= v >> 2; 880104477Ssam v ^= v >> 1; 881104477Ssam 882104477Ssam a = (v & 1) ^ (a << 1); 883104477Ssam } 884104477Ssam 885104477Ssam return a; 886104477Ssam} 887104477Ssam 888104477Ssamstruct pci2id { 889104477Ssam u_short pci_vendor; 890104477Ssam u_short pci_prod; 891104477Ssam char card_id[13]; 892104477Ssam}; 893104477Ssamstatic struct pci2id pci2id[] = { 894104477Ssam { 895104477Ssam PCI_VENDOR_HIFN, 896104477Ssam PCI_PRODUCT_HIFN_7951, 897104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 898104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 899104477Ssam }, { 900120915Ssam PCI_VENDOR_HIFN, 901120915Ssam PCI_PRODUCT_HIFN_7955, 902120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 903120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 904120915Ssam }, { 905120915Ssam PCI_VENDOR_HIFN, 906120915Ssam PCI_PRODUCT_HIFN_7956, 907120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 908120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 909120915Ssam }, { 910104477Ssam PCI_VENDOR_NETSEC, 911104477Ssam PCI_PRODUCT_NETSEC_7751, 912104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 913104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 914104477Ssam }, { 915104477Ssam PCI_VENDOR_INVERTEX, 916104477Ssam PCI_PRODUCT_INVERTEX_AEON, 917104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 918104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 919104477Ssam }, { 920104477Ssam PCI_VENDOR_HIFN, 921104477Ssam PCI_PRODUCT_HIFN_7811, 922104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 923104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 924104477Ssam }, { 925104477Ssam /* 926104477Ssam * Other vendors share this PCI ID as well, such as 927104477Ssam * http://www.powercrypt.com, and obviously they also 928104477Ssam * use the same key. 929104477Ssam */ 930104477Ssam PCI_VENDOR_HIFN, 931104477Ssam PCI_PRODUCT_HIFN_7751, 932104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 933104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 934104477Ssam }, 935104477Ssam}; 936104477Ssam 937104477Ssam/* 938104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 939104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 940104477Ssam * as enabling crypto twice will lock the board. 941104477Ssam */ 942104477Ssamstatic int 943104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 944104477Ssam{ 945104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 946104477Ssam char *offtbl = NULL; 947104477Ssam 948104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 949104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 950104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 951104477Ssam offtbl = pci2id[i].card_id; 952104477Ssam break; 953104477Ssam } 954104477Ssam } 955104477Ssam if (offtbl == NULL) { 956104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 957104477Ssam return (1); 958104477Ssam } 959104477Ssam 960104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 961104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 962104477Ssam 963104477Ssam /* 964104477Ssam * The RAM config register's encrypt level bit needs to be set before 965104477Ssam * every read performed on the encryption level register. 966104477Ssam */ 967104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 968104477Ssam 969104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 970104477Ssam 971104477Ssam /* 972104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 973104477Ssam * next reboot. 974104477Ssam */ 975104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 976104477Ssam#ifdef HIFN_DEBUG 977104477Ssam if (hifn_debug) 978104477Ssam device_printf(sc->sc_dev, 979104477Ssam "Strong crypto already enabled!\n"); 980104477Ssam#endif 981104477Ssam goto report; 982104477Ssam } 983104477Ssam 984104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 985104477Ssam#ifdef HIFN_DEBUG 986104477Ssam if (hifn_debug) 987104477Ssam device_printf(sc->sc_dev, 988104477Ssam "Unknown encryption level 0x%x\n", encl); 989104477Ssam#endif 990104477Ssam return 1; 991104477Ssam } 992104477Ssam 993104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 994104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 995104477Ssam DELAY(1000); 996104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 997104477Ssam DELAY(1000); 998104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 999104477Ssam DELAY(1000); 1000104477Ssam 1001104477Ssam for (i = 0; i <= 12; i++) { 1002104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1003104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1004104477Ssam 1005104477Ssam DELAY(1000); 1006104477Ssam } 1007104477Ssam 1008104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1009104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1010104477Ssam 1011104477Ssam#ifdef HIFN_DEBUG 1012104477Ssam if (hifn_debug) { 1013104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1014104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 1015104477Ssam "locked until next system reset!\n"); 1016104477Ssam else 1017104477Ssam device_printf(sc->sc_dev, "Engine enabled " 1018104477Ssam "successfully!\n"); 1019104477Ssam } 1020104477Ssam#endif 1021104477Ssam 1022104477Ssamreport: 1023104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1024104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1025104477Ssam 1026104477Ssam switch (encl) { 1027104477Ssam case HIFN_PUSTAT_ENA_1: 1028104477Ssam case HIFN_PUSTAT_ENA_2: 1029104477Ssam break; 1030104477Ssam case HIFN_PUSTAT_ENA_0: 1031104477Ssam default: 1032104477Ssam device_printf(sc->sc_dev, "disabled"); 1033104477Ssam break; 1034104477Ssam } 1035104477Ssam 1036104477Ssam return 0; 1037104477Ssam} 1038104477Ssam 1039104477Ssam/* 1040104477Ssam * Give initial values to the registers listed in the "Register Space" 1041104477Ssam * section of the HIFN Software Development reference manual. 1042104477Ssam */ 1043104477Ssamstatic void 1044104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1045104477Ssam{ 1046104477Ssam /* write fixed values needed by the Initialization registers */ 1047104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1048104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1049104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1050104477Ssam 1051104477Ssam /* write all 4 ring address registers */ 1052104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1053104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1054104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1055104477Ssam offsetof(struct hifn_dma, srcr[0])); 1056104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1057104477Ssam offsetof(struct hifn_dma, dstr[0])); 1058104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1059104477Ssam offsetof(struct hifn_dma, resr[0])); 1060104477Ssam 1061104477Ssam DELAY(2000); 1062104477Ssam 1063104477Ssam /* write status register */ 1064104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1065104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1066104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1067104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1068104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1069104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1070104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1071104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1072104477Ssam HIFN_DMACSR_S_WAIT | 1073104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1074104477Ssam HIFN_DMACSR_C_WAIT | 1075104477Ssam HIFN_DMACSR_ENGINE | 1076104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1077104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1078104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1079104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1080104477Ssam 1081104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1082104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1083104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1084104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1085104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1086104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1087104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1088104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1089104477Ssam 1090104477Ssam 1091120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1092120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1093120915Ssam HIFN_PUCNFG_TCALLPHASES | 1094120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1095120915Ssam WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956); 1096120915Ssam } else { 1097120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1098120915Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1099120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1100120915Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1101120915Ssam } 1102120915Ssam 1103104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1104104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1105104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1106104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1107104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1108104477Ssam} 1109104477Ssam 1110104477Ssam/* 1111104477Ssam * The maximum number of sessions supported by the card 1112104477Ssam * is dependent on the amount of context ram, which 1113104477Ssam * encryption algorithms are enabled, and how compression 1114104477Ssam * is configured. This should be configured before this 1115104477Ssam * routine is called. 1116104477Ssam */ 1117104477Ssamstatic void 1118104477Ssamhifn_sessions(struct hifn_softc *sc) 1119104477Ssam{ 1120104477Ssam u_int32_t pucnfg; 1121104477Ssam int ctxsize; 1122104477Ssam 1123104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1124104477Ssam 1125104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1126104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1127104477Ssam ctxsize = 128; 1128104477Ssam else 1129104477Ssam ctxsize = 512; 1130120915Ssam /* 1131120915Ssam * 7955/7956 has internal context memory of 32K 1132120915Ssam */ 1133120915Ssam if (sc->sc_flags & HIFN_IS_7956) 1134120915Ssam sc->sc_maxses = 32768 / ctxsize; 1135120915Ssam else 1136120915Ssam sc->sc_maxses = 1 + 1137120915Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1138104477Ssam } else 1139104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1140104477Ssam 1141104477Ssam if (sc->sc_maxses > 2048) 1142104477Ssam sc->sc_maxses = 2048; 1143104477Ssam} 1144104477Ssam 1145104477Ssam/* 1146104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1147104477Ssam * state when this is called. 1148104477Ssam */ 1149104477Ssamstatic int 1150104477Ssamhifn_ramtype(struct hifn_softc *sc) 1151104477Ssam{ 1152104477Ssam u_int8_t data[8], dataexpect[8]; 1153104477Ssam int i; 1154104477Ssam 1155104477Ssam for (i = 0; i < sizeof(data); i++) 1156104477Ssam data[i] = dataexpect[i] = 0x55; 1157104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1158104477Ssam return (-1); 1159104477Ssam if (hifn_readramaddr(sc, 0, data)) 1160104477Ssam return (-1); 1161104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1162104477Ssam sc->sc_drammodel = 1; 1163104477Ssam return (0); 1164104477Ssam } 1165104477Ssam 1166104477Ssam for (i = 0; i < sizeof(data); i++) 1167104477Ssam data[i] = dataexpect[i] = 0xaa; 1168104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1169104477Ssam return (-1); 1170104477Ssam if (hifn_readramaddr(sc, 0, data)) 1171104477Ssam return (-1); 1172104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1173104477Ssam sc->sc_drammodel = 1; 1174104477Ssam return (0); 1175104477Ssam } 1176104477Ssam 1177104477Ssam return (0); 1178104477Ssam} 1179104477Ssam 1180104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1181104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1182104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1183104477Ssam 1184104477Ssamstatic int 1185104477Ssamhifn_sramsize(struct hifn_softc *sc) 1186104477Ssam{ 1187104477Ssam u_int32_t a; 1188104477Ssam u_int8_t data[8]; 1189104477Ssam u_int8_t dataexpect[sizeof(data)]; 1190104477Ssam int32_t i; 1191104477Ssam 1192104477Ssam for (i = 0; i < sizeof(data); i++) 1193104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1194104477Ssam 1195104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1196104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1197104477Ssam bcopy(&i, data, sizeof(i)); 1198104477Ssam hifn_writeramaddr(sc, a, data); 1199104477Ssam } 1200104477Ssam 1201104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1202104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1203104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1204104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1205104477Ssam return (0); 1206104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1207104477Ssam return (0); 1208104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1209104477Ssam } 1210104477Ssam 1211104477Ssam return (0); 1212104477Ssam} 1213104477Ssam 1214104477Ssam/* 1215104477Ssam * XXX For dram boards, one should really try all of the 1216104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1217104477Ssam * is already set up correctly. 1218104477Ssam */ 1219104477Ssamstatic int 1220104477Ssamhifn_dramsize(struct hifn_softc *sc) 1221104477Ssam{ 1222104477Ssam u_int32_t cnfg; 1223104477Ssam 1224120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1225120915Ssam /* 1226120915Ssam * 7955/7956 have a fixed internal ram of only 32K. 1227120915Ssam */ 1228120915Ssam sc->sc_ramsize = 32768; 1229120915Ssam } else { 1230120915Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1231120915Ssam HIFN_PUCNFG_DRAMMASK; 1232120915Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1233120915Ssam } 1234104477Ssam return (0); 1235104477Ssam} 1236104477Ssam 1237104477Ssamstatic void 1238104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1239104477Ssam{ 1240104477Ssam struct hifn_dma *dma = sc->sc_dma; 1241104477Ssam 1242104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1243104477Ssam dma->cmdi = 0; 1244104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1245104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1246104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1247104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1248104477Ssam } 1249104477Ssam *cmdp = dma->cmdi++; 1250104477Ssam dma->cmdk = dma->cmdi; 1251104477Ssam 1252104477Ssam if (dma->srci == HIFN_D_SRC_RSIZE) { 1253104477Ssam dma->srci = 0; 1254104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1255104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1256104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1257104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1258104477Ssam } 1259104477Ssam *srcp = dma->srci++; 1260104477Ssam dma->srck = dma->srci; 1261104477Ssam 1262104477Ssam if (dma->dsti == HIFN_D_DST_RSIZE) { 1263104477Ssam dma->dsti = 0; 1264104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1265104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1266104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1267104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1268104477Ssam } 1269104477Ssam *dstp = dma->dsti++; 1270104477Ssam dma->dstk = dma->dsti; 1271104477Ssam 1272104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1273104477Ssam dma->resi = 0; 1274104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1275104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1276104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1277104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1278104477Ssam } 1279104477Ssam *resp = dma->resi++; 1280104477Ssam dma->resk = dma->resi; 1281104477Ssam} 1282104477Ssam 1283104477Ssamstatic int 1284104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1285104477Ssam{ 1286104477Ssam struct hifn_dma *dma = sc->sc_dma; 1287104477Ssam hifn_base_command_t wc; 1288104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1289104477Ssam int r, cmdi, resi, srci, dsti; 1290104477Ssam 1291104477Ssam wc.masks = htole16(3 << 13); 1292104477Ssam wc.session_num = htole16(addr >> 14); 1293104477Ssam wc.total_source_count = htole16(8); 1294104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1295104477Ssam 1296104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1297104477Ssam 1298104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1299104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1300104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1301104477Ssam 1302104477Ssam /* build write command */ 1303104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1304104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1305104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1306104477Ssam 1307104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1308104477Ssam + offsetof(struct hifn_dma, test_src)); 1309104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1310104477Ssam + offsetof(struct hifn_dma, test_dst)); 1311104477Ssam 1312104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1313104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1314104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1315104477Ssam dma->resr[resi].l = htole32(4 | masks); 1316104477Ssam 1317104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1318104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1319104477Ssam 1320104477Ssam for (r = 10000; r >= 0; r--) { 1321104477Ssam DELAY(10); 1322104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1323104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1324104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1325104477Ssam break; 1326104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1327104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1328104477Ssam } 1329104477Ssam if (r == 0) { 1330104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1331104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1332104477Ssam r = -1; 1333104477Ssam return (-1); 1334104477Ssam } else 1335104477Ssam r = 0; 1336104477Ssam 1337104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1338104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1339104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1340104477Ssam 1341104477Ssam return (r); 1342104477Ssam} 1343104477Ssam 1344104477Ssamstatic int 1345104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1346104477Ssam{ 1347104477Ssam struct hifn_dma *dma = sc->sc_dma; 1348104477Ssam hifn_base_command_t rc; 1349104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1350104477Ssam int r, cmdi, srci, dsti, resi; 1351104477Ssam 1352104477Ssam rc.masks = htole16(2 << 13); 1353104477Ssam rc.session_num = htole16(addr >> 14); 1354104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1355104477Ssam rc.total_dest_count = htole16(8); 1356104477Ssam 1357104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1358104477Ssam 1359104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1360104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1361104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1362104477Ssam 1363104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1364104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1365104477Ssam 1366104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1367104477Ssam offsetof(struct hifn_dma, test_src)); 1368104477Ssam dma->test_src = 0; 1369104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1370104477Ssam offsetof(struct hifn_dma, test_dst)); 1371104477Ssam dma->test_dst = 0; 1372104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1373104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1374104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1375104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1376104477Ssam 1377104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1378104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1379104477Ssam 1380104477Ssam for (r = 10000; r >= 0; r--) { 1381104477Ssam DELAY(10); 1382104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1383104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1384104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1385104477Ssam break; 1386104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1387104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1388104477Ssam } 1389104477Ssam if (r == 0) { 1390104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1391104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1392104477Ssam r = -1; 1393104477Ssam } else { 1394104477Ssam r = 0; 1395104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1396104477Ssam } 1397104477Ssam 1398104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1399104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1400104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1401104477Ssam 1402104477Ssam return (r); 1403104477Ssam} 1404104477Ssam 1405104477Ssam/* 1406104477Ssam * Initialize the descriptor rings. 1407104477Ssam */ 1408104477Ssamstatic void 1409104477Ssamhifn_init_dma(struct hifn_softc *sc) 1410104477Ssam{ 1411104477Ssam struct hifn_dma *dma = sc->sc_dma; 1412104477Ssam int i; 1413104477Ssam 1414104477Ssam hifn_set_retry(sc); 1415104477Ssam 1416104477Ssam /* initialize static pointer values */ 1417104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1418104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1419104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1420104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1421104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1422104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1423104477Ssam 1424104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1425104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1426104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1427104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1428104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1429104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1430104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1431104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1432104477Ssam 1433104477Ssam dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1434104477Ssam dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1435104477Ssam dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1436104477Ssam} 1437104477Ssam 1438104477Ssam/* 1439104477Ssam * Writes out the raw command buffer space. Returns the 1440104477Ssam * command buffer size. 1441104477Ssam */ 1442104477Ssamstatic u_int 1443104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1444104477Ssam{ 1445104477Ssam u_int8_t *buf_pos; 1446104477Ssam hifn_base_command_t *base_cmd; 1447104477Ssam hifn_mac_command_t *mac_cmd; 1448104477Ssam hifn_crypt_command_t *cry_cmd; 1449120915Ssam int using_mac, using_crypt, len, ivlen; 1450104477Ssam u_int32_t dlen, slen; 1451104477Ssam 1452104477Ssam buf_pos = buf; 1453104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1454104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1455104477Ssam 1456104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1457104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1458104477Ssam slen = cmd->src_mapsize; 1459104477Ssam if (cmd->sloplen) 1460104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1461104477Ssam else 1462104477Ssam dlen = cmd->dst_mapsize; 1463104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1464104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1465104477Ssam dlen >>= 16; 1466104477Ssam slen >>= 16; 1467104477Ssam base_cmd->session_num = htole16(cmd->session_num | 1468104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1469104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1470104477Ssam buf_pos += sizeof(hifn_base_command_t); 1471104477Ssam 1472104477Ssam if (using_mac) { 1473104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1474104477Ssam dlen = cmd->maccrd->crd_len; 1475104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1476104477Ssam dlen >>= 16; 1477104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1478104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1479104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1480104477Ssam mac_cmd->reserved = 0; 1481104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1482104477Ssam } 1483104477Ssam 1484104477Ssam if (using_crypt) { 1485104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1486104477Ssam dlen = cmd->enccrd->crd_len; 1487104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1488104477Ssam dlen >>= 16; 1489104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1490104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1491104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1492104477Ssam cry_cmd->reserved = 0; 1493104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1494104477Ssam } 1495104477Ssam 1496104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1497104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1498104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1499104477Ssam } 1500104477Ssam 1501104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1502104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1503104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1504104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1505104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1506104477Ssam break; 1507104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1508104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1509120915Ssam buf_pos += HIFN_DES_KEY_LENGTH; 1510104477Ssam break; 1511104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1512104477Ssam len = 256; 1513104477Ssam do { 1514104477Ssam int clen; 1515104477Ssam 1516104477Ssam clen = MIN(cmd->cklen, len); 1517104477Ssam bcopy(cmd->ck, buf_pos, clen); 1518104477Ssam len -= clen; 1519104477Ssam buf_pos += clen; 1520104477Ssam } while (len > 0); 1521104477Ssam bzero(buf_pos, 4); 1522104477Ssam buf_pos += 4; 1523104477Ssam break; 1524120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1525120915Ssam /* 1526120915Ssam * AES keys are variable 128, 192 and 1527120915Ssam * 256 bits (16, 24 and 32 bytes). 1528120915Ssam */ 1529120915Ssam bcopy(cmd->ck, buf_pos, cmd->cklen); 1530120915Ssam buf_pos += cmd->cklen; 1531120915Ssam break; 1532104477Ssam } 1533104477Ssam } 1534104477Ssam 1535104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1536120915Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1537120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1538120915Ssam ivlen = HIFN_AES_IV_LENGTH; 1539120915Ssam break; 1540120915Ssam default: 1541120915Ssam ivlen = HIFN_IV_LENGTH; 1542120915Ssam break; 1543120915Ssam } 1544120915Ssam bcopy(cmd->iv, buf_pos, ivlen); 1545120915Ssam buf_pos += ivlen; 1546104477Ssam } 1547104477Ssam 1548104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1549104477Ssam bzero(buf_pos, 8); 1550104477Ssam buf_pos += 8; 1551104477Ssam } 1552104477Ssam 1553104477Ssam return (buf_pos - buf); 1554104477Ssam} 1555104477Ssam 1556104477Ssamstatic int 1557104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1558104477Ssam{ 1559104477Ssam int i; 1560104477Ssam 1561104477Ssam for (i = 0; i < op->nsegs; i++) { 1562104477Ssam if (op->segs[i].ds_addr & 3) 1563104477Ssam return (0); 1564104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1565104477Ssam return (0); 1566104477Ssam } 1567104477Ssam return (1); 1568104477Ssam} 1569104477Ssam 1570104477Ssamstatic int 1571104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1572104477Ssam{ 1573104477Ssam struct hifn_dma *dma = sc->sc_dma; 1574104477Ssam struct hifn_operand *dst = &cmd->dst; 1575104477Ssam u_int32_t p, l; 1576104477Ssam int idx, used = 0, i; 1577104477Ssam 1578104477Ssam idx = dma->dsti; 1579104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1580104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1581104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1582104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1583104477Ssam HIFN_DSTR_SYNC(sc, idx, 1584104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1585104477Ssam used++; 1586104477Ssam 1587104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1588104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1589104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1590104477Ssam HIFN_DSTR_SYNC(sc, idx, 1591104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1592104477Ssam idx = 0; 1593104477Ssam } 1594104477Ssam } 1595104477Ssam 1596104477Ssam if (cmd->sloplen == 0) { 1597104477Ssam p = dst->segs[i].ds_addr; 1598104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1599104477Ssam dst->segs[i].ds_len; 1600104477Ssam } else { 1601104477Ssam p = sc->sc_dma_physaddr + 1602104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1603104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1604104477Ssam sizeof(u_int32_t); 1605104477Ssam 1606104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1607104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1608104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1609104477Ssam HIFN_D_MASKDONEIRQ | 1610104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1611104477Ssam HIFN_DSTR_SYNC(sc, idx, 1612104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1613104477Ssam used++; 1614104477Ssam 1615104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1616104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1617104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1618104477Ssam HIFN_DSTR_SYNC(sc, idx, 1619104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1620104477Ssam idx = 0; 1621104477Ssam } 1622104477Ssam } 1623104477Ssam } 1624104477Ssam dma->dstr[idx].p = htole32(p); 1625104477Ssam dma->dstr[idx].l = htole32(l); 1626104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1627104477Ssam used++; 1628104477Ssam 1629104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1630104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1631104477Ssam HIFN_D_MASKDONEIRQ); 1632104477Ssam HIFN_DSTR_SYNC(sc, idx, 1633104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1634104477Ssam idx = 0; 1635104477Ssam } 1636104477Ssam 1637104477Ssam dma->dsti = idx; 1638104477Ssam dma->dstu += used; 1639104477Ssam return (idx); 1640104477Ssam} 1641104477Ssam 1642104477Ssamstatic int 1643104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1644104477Ssam{ 1645104477Ssam struct hifn_dma *dma = sc->sc_dma; 1646104477Ssam struct hifn_operand *src = &cmd->src; 1647104477Ssam int idx, i; 1648104477Ssam u_int32_t last = 0; 1649104477Ssam 1650104477Ssam idx = dma->srci; 1651104477Ssam for (i = 0; i < src->nsegs; i++) { 1652104477Ssam if (i == src->nsegs - 1) 1653104477Ssam last = HIFN_D_LAST; 1654104477Ssam 1655104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1656104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1657104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1658104477Ssam HIFN_SRCR_SYNC(sc, idx, 1659104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1660104477Ssam 1661104477Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1662104477Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1663104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1664104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1665104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1666104477Ssam idx = 0; 1667104477Ssam } 1668104477Ssam } 1669104477Ssam dma->srci = idx; 1670104477Ssam dma->srcu += src->nsegs; 1671104477Ssam return (idx); 1672104477Ssam} 1673104477Ssam 1674104477Ssamstatic void 1675104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1676104477Ssam{ 1677104477Ssam struct hifn_operand *op = arg; 1678104477Ssam 1679104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1680104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1681104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1682104477Ssam op->mapsize = mapsize; 1683104477Ssam op->nsegs = nsegs; 1684104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1685104477Ssam} 1686104477Ssam 1687104477Ssamstatic int 1688104477Ssamhifn_crypto( 1689104477Ssam struct hifn_softc *sc, 1690104477Ssam struct hifn_command *cmd, 1691104477Ssam struct cryptop *crp, 1692104477Ssam int hint) 1693104477Ssam{ 1694104477Ssam struct hifn_dma *dma = sc->sc_dma; 1695104477Ssam u_int32_t cmdlen; 1696104477Ssam int cmdi, resi, err = 0; 1697104477Ssam 1698104477Ssam /* 1699104477Ssam * need 1 cmd, and 1 res 1700104477Ssam * 1701104477Ssam * NB: check this first since it's easy. 1702104477Ssam */ 1703115748Ssam HIFN_LOCK(sc); 1704104477Ssam if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1705104477Ssam (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1706104477Ssam#ifdef HIFN_DEBUG 1707104477Ssam if (hifn_debug) { 1708104477Ssam device_printf(sc->sc_dev, 1709104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1710104477Ssam dma->cmdu, dma->resu); 1711104477Ssam } 1712104477Ssam#endif 1713104477Ssam hifnstats.hst_nomem_cr++; 1714115748Ssam HIFN_UNLOCK(sc); 1715104477Ssam return (ERESTART); 1716104477Ssam } 1717104477Ssam 1718104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1719104477Ssam hifnstats.hst_nomem_map++; 1720115748Ssam HIFN_UNLOCK(sc); 1721104477Ssam return (ENOMEM); 1722104477Ssam } 1723104477Ssam 1724104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1725104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1726104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1727104477Ssam hifnstats.hst_nomem_load++; 1728104477Ssam err = ENOMEM; 1729104477Ssam goto err_srcmap1; 1730104477Ssam } 1731104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1732104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1733104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1734104477Ssam hifnstats.hst_nomem_load++; 1735104477Ssam err = ENOMEM; 1736104477Ssam goto err_srcmap1; 1737104477Ssam } 1738104477Ssam } else { 1739104477Ssam err = EINVAL; 1740104477Ssam goto err_srcmap1; 1741104477Ssam } 1742104477Ssam 1743104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1744104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1745104477Ssam cmd->dst = cmd->src; 1746104477Ssam } else { 1747104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1748104477Ssam err = EINVAL; 1749104477Ssam goto err_srcmap; 1750104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1751104477Ssam int totlen, len; 1752104477Ssam struct mbuf *m, *m0, *mlast; 1753104477Ssam 1754104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1755104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1756104477Ssam hifnstats.hst_unaligned++; 1757104477Ssam /* 1758104477Ssam * Source is not aligned on a longword boundary. 1759104477Ssam * Copy the data to insure alignment. If we fail 1760104477Ssam * to allocate mbufs or clusters while doing this 1761104477Ssam * we return ERESTART so the operation is requeued 1762104477Ssam * at the crypto later, but only if there are 1763104477Ssam * ops already posted to the hardware; otherwise we 1764104477Ssam * have no guarantee that we'll be re-entered. 1765104477Ssam */ 1766104477Ssam totlen = cmd->src_mapsize; 1767104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1768104477Ssam len = MHLEN; 1769111119Simp MGETHDR(m0, M_DONTWAIT, MT_DATA); 1770111119Simp if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1771108466Ssam m_free(m0); 1772108466Ssam m0 = NULL; 1773108466Ssam } 1774104477Ssam } else { 1775104477Ssam len = MLEN; 1776111119Simp MGET(m0, M_DONTWAIT, MT_DATA); 1777104477Ssam } 1778104477Ssam if (m0 == NULL) { 1779104477Ssam hifnstats.hst_nomem_mbuf++; 1780104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1781104477Ssam goto err_srcmap; 1782104477Ssam } 1783104477Ssam if (totlen >= MINCLSIZE) { 1784111119Simp MCLGET(m0, M_DONTWAIT); 1785104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1786104477Ssam hifnstats.hst_nomem_mcl++; 1787104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1788104477Ssam m_freem(m0); 1789104477Ssam goto err_srcmap; 1790104477Ssam } 1791104477Ssam len = MCLBYTES; 1792104477Ssam } 1793104477Ssam totlen -= len; 1794104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1795104477Ssam mlast = m0; 1796104477Ssam 1797104477Ssam while (totlen > 0) { 1798111119Simp MGET(m, M_DONTWAIT, MT_DATA); 1799104477Ssam if (m == NULL) { 1800104477Ssam hifnstats.hst_nomem_mbuf++; 1801104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1802104477Ssam m_freem(m0); 1803104477Ssam goto err_srcmap; 1804104477Ssam } 1805104477Ssam len = MLEN; 1806104477Ssam if (totlen >= MINCLSIZE) { 1807111119Simp MCLGET(m, M_DONTWAIT); 1808104477Ssam if ((m->m_flags & M_EXT) == 0) { 1809104477Ssam hifnstats.hst_nomem_mcl++; 1810104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1811104477Ssam mlast->m_next = m; 1812104477Ssam m_freem(m0); 1813104477Ssam goto err_srcmap; 1814104477Ssam } 1815104477Ssam len = MCLBYTES; 1816104477Ssam } 1817104477Ssam 1818104477Ssam m->m_len = len; 1819104477Ssam m0->m_pkthdr.len += len; 1820104477Ssam totlen -= len; 1821104477Ssam 1822104477Ssam mlast->m_next = m; 1823104477Ssam mlast = m; 1824104477Ssam } 1825104477Ssam cmd->dst_m = m0; 1826104477Ssam } 1827104477Ssam } 1828104477Ssam 1829104477Ssam if (cmd->dst_map == NULL) { 1830104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1831104477Ssam hifnstats.hst_nomem_map++; 1832104477Ssam err = ENOMEM; 1833104477Ssam goto err_srcmap; 1834104477Ssam } 1835104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1836104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1837104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1838104477Ssam hifnstats.hst_nomem_map++; 1839104477Ssam err = ENOMEM; 1840104477Ssam goto err_dstmap1; 1841104477Ssam } 1842104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1843104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1844104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1845104477Ssam hifnstats.hst_nomem_load++; 1846104477Ssam err = ENOMEM; 1847104477Ssam goto err_dstmap1; 1848104477Ssam } 1849104477Ssam } 1850104477Ssam } 1851104477Ssam 1852104477Ssam#ifdef HIFN_DEBUG 1853104477Ssam if (hifn_debug) { 1854104477Ssam device_printf(sc->sc_dev, 1855104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1856104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1857104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1858104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1859104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1860104477Ssam } 1861104477Ssam#endif 1862104477Ssam 1863104477Ssam if (cmd->src_map == cmd->dst_map) { 1864104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1865104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1866104477Ssam } else { 1867104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1868104477Ssam BUS_DMASYNC_PREWRITE); 1869104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1870104477Ssam BUS_DMASYNC_PREREAD); 1871104477Ssam } 1872104477Ssam 1873104477Ssam /* 1874104477Ssam * need N src, and N dst 1875104477Ssam */ 1876104477Ssam if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1877104477Ssam (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1878104477Ssam#ifdef HIFN_DEBUG 1879104477Ssam if (hifn_debug) { 1880104477Ssam device_printf(sc->sc_dev, 1881104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1882104477Ssam dma->srcu, cmd->src_nsegs, 1883104477Ssam dma->dstu, cmd->dst_nsegs); 1884104477Ssam } 1885104477Ssam#endif 1886104477Ssam hifnstats.hst_nomem_sd++; 1887104477Ssam err = ERESTART; 1888104477Ssam goto err_dstmap; 1889104477Ssam } 1890104477Ssam 1891104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1892104477Ssam dma->cmdi = 0; 1893104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1894104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1895104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1896104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1897104477Ssam } 1898104477Ssam cmdi = dma->cmdi++; 1899104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1900104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1901104477Ssam 1902104477Ssam /* .p for command/result already set */ 1903104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1904104477Ssam HIFN_D_MASKDONEIRQ); 1905104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 1906104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1907104477Ssam dma->cmdu++; 1908104477Ssam if (sc->sc_c_busy == 0) { 1909104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1910104477Ssam sc->sc_c_busy = 1; 1911104477Ssam } 1912104477Ssam 1913104477Ssam /* 1914104477Ssam * We don't worry about missing an interrupt (which a "command wait" 1915104477Ssam * interrupt salvages us from), unless there is more than one command 1916104477Ssam * in the queue. 1917104477Ssam */ 1918104477Ssam if (dma->cmdu > 1) { 1919104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1920104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1921104477Ssam } 1922104477Ssam 1923104477Ssam hifnstats.hst_ipackets++; 1924104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 1925104477Ssam 1926104477Ssam hifn_dmamap_load_src(sc, cmd); 1927104477Ssam if (sc->sc_s_busy == 0) { 1928104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1929104477Ssam sc->sc_s_busy = 1; 1930104477Ssam } 1931104477Ssam 1932104477Ssam /* 1933104477Ssam * Unlike other descriptors, we don't mask done interrupt from 1934104477Ssam * result descriptor. 1935104477Ssam */ 1936104477Ssam#ifdef HIFN_DEBUG 1937104477Ssam if (hifn_debug) 1938104477Ssam printf("load res\n"); 1939104477Ssam#endif 1940104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1941104477Ssam dma->resi = 0; 1942104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1943104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1944104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1945104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946104477Ssam } 1947104477Ssam resi = dma->resi++; 1948104477Ssam KASSERT(dma->hifn_commands[resi] == NULL, 1949104477Ssam ("hifn_crypto: command slot %u busy", resi)); 1950104477Ssam dma->hifn_commands[resi] = cmd; 1951104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1952104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1953104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1954104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1955104477Ssam sc->sc_curbatch++; 1956104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1957104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 1958104477Ssam hifnstats.hst_totbatch++; 1959104477Ssam } else { 1960104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1961104477Ssam HIFN_D_VALID | HIFN_D_LAST); 1962104477Ssam sc->sc_curbatch = 0; 1963104477Ssam } 1964104477Ssam HIFN_RESR_SYNC(sc, resi, 1965104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1966104477Ssam dma->resu++; 1967104477Ssam if (sc->sc_r_busy == 0) { 1968104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1969104477Ssam sc->sc_r_busy = 1; 1970104477Ssam } 1971104477Ssam 1972104477Ssam if (cmd->sloplen) 1973104477Ssam cmd->slopidx = resi; 1974104477Ssam 1975104477Ssam hifn_dmamap_load_dst(sc, cmd); 1976104477Ssam 1977104477Ssam if (sc->sc_d_busy == 0) { 1978104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1979104477Ssam sc->sc_d_busy = 1; 1980104477Ssam } 1981104477Ssam 1982104477Ssam#ifdef HIFN_DEBUG 1983104477Ssam if (hifn_debug) { 1984104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1985104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1986104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 1987104477Ssam } 1988104477Ssam#endif 1989104477Ssam 1990104477Ssam sc->sc_active = 5; 1991115748Ssam HIFN_UNLOCK(sc); 1992104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1993104477Ssam return (err); /* success */ 1994104477Ssam 1995104477Ssamerr_dstmap: 1996104477Ssam if (cmd->src_map != cmd->dst_map) 1997104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1998104477Ssamerr_dstmap1: 1999104477Ssam if (cmd->src_map != cmd->dst_map) 2000104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2001104477Ssamerr_srcmap: 2002104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2003104477Ssam if (cmd->src_m != cmd->dst_m) 2004104477Ssam m_freem(cmd->dst_m); 2005104477Ssam } 2006104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2007104477Ssamerr_srcmap1: 2008104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2009115748Ssam HIFN_UNLOCK(sc); 2010104477Ssam return (err); 2011104477Ssam} 2012104477Ssam 2013104477Ssamstatic void 2014104477Ssamhifn_tick(void* vsc) 2015104477Ssam{ 2016104477Ssam struct hifn_softc *sc = vsc; 2017104477Ssam 2018104477Ssam HIFN_LOCK(sc); 2019104477Ssam if (sc->sc_active == 0) { 2020104477Ssam struct hifn_dma *dma = sc->sc_dma; 2021104477Ssam u_int32_t r = 0; 2022104477Ssam 2023104477Ssam if (dma->cmdu == 0 && sc->sc_c_busy) { 2024104477Ssam sc->sc_c_busy = 0; 2025104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 2026104477Ssam } 2027104477Ssam if (dma->srcu == 0 && sc->sc_s_busy) { 2028104477Ssam sc->sc_s_busy = 0; 2029104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 2030104477Ssam } 2031104477Ssam if (dma->dstu == 0 && sc->sc_d_busy) { 2032104477Ssam sc->sc_d_busy = 0; 2033104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 2034104477Ssam } 2035104477Ssam if (dma->resu == 0 && sc->sc_r_busy) { 2036104477Ssam sc->sc_r_busy = 0; 2037104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 2038104477Ssam } 2039104477Ssam if (r) 2040104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2041104477Ssam } else 2042104477Ssam sc->sc_active--; 2043104477Ssam HIFN_UNLOCK(sc); 2044104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2045104477Ssam} 2046104477Ssam 2047104477Ssamstatic void 2048104477Ssamhifn_intr(void *arg) 2049104477Ssam{ 2050104477Ssam struct hifn_softc *sc = arg; 2051104477Ssam struct hifn_dma *dma; 2052104477Ssam u_int32_t dmacsr, restart; 2053104477Ssam int i, u; 2054104477Ssam 2055115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2056115748Ssam 2057115748Ssam /* Nothing in the DMA unit interrupted */ 2058115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 2059115748Ssam return; 2060115748Ssam 2061104477Ssam HIFN_LOCK(sc); 2062115748Ssam 2063104477Ssam dma = sc->sc_dma; 2064104477Ssam 2065104477Ssam#ifdef HIFN_DEBUG 2066104477Ssam if (hifn_debug) { 2067104477Ssam device_printf(sc->sc_dev, 2068104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2069104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2070104477Ssam dma->cmdi, dma->srci, dma->dsti, dma->resi, 2071104477Ssam dma->cmdk, dma->srck, dma->dstk, dma->resk, 2072104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2073104477Ssam } 2074104477Ssam#endif 2075104477Ssam 2076104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2077104477Ssam 2078104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2079104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2080104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2081104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2082104477Ssam 2083104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2084104477Ssam if (restart) 2085104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2086104477Ssam 2087104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2088104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2089104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2090104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2091104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2092104477Ssam } 2093104477Ssam 2094104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2095104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2096104477Ssam if (restart) { 2097104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2098104477Ssam hifnstats.hst_abort++; 2099104477Ssam hifn_abort(sc); 2100104477Ssam HIFN_UNLOCK(sc); 2101104477Ssam return; 2102104477Ssam } 2103104477Ssam 2104104477Ssam if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2105104477Ssam /* 2106104477Ssam * If no slots to process and we receive a "waiting on 2107104477Ssam * command" interrupt, we disable the "waiting on command" 2108104477Ssam * (by clearing it). 2109104477Ssam */ 2110104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2111104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2112104477Ssam } 2113104477Ssam 2114104477Ssam /* clear the rings */ 2115104477Ssam i = dma->resk; u = dma->resu; 2116104477Ssam while (u != 0) { 2117104477Ssam HIFN_RESR_SYNC(sc, i, 2118104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2119104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2120104477Ssam HIFN_RESR_SYNC(sc, i, 2121104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2122104477Ssam break; 2123104477Ssam } 2124104477Ssam 2125104477Ssam if (i != HIFN_D_RES_RSIZE) { 2126104477Ssam struct hifn_command *cmd; 2127104477Ssam u_int8_t *macbuf = NULL; 2128104477Ssam 2129104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2130104477Ssam cmd = dma->hifn_commands[i]; 2131104477Ssam KASSERT(cmd != NULL, 2132104477Ssam ("hifn_intr: null command slot %u", i)); 2133104477Ssam dma->hifn_commands[i] = NULL; 2134104477Ssam 2135104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2136104477Ssam macbuf = dma->result_bufs[i]; 2137104477Ssam macbuf += 12; 2138104477Ssam } 2139104477Ssam 2140104477Ssam hifn_callback(sc, cmd, macbuf); 2141104477Ssam hifnstats.hst_opackets++; 2142104477Ssam u--; 2143104477Ssam } 2144104477Ssam 2145104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2146104477Ssam i = 0; 2147104477Ssam } 2148104477Ssam dma->resk = i; dma->resu = u; 2149104477Ssam 2150104477Ssam i = dma->srck; u = dma->srcu; 2151104477Ssam while (u != 0) { 2152104477Ssam if (i == HIFN_D_SRC_RSIZE) 2153104477Ssam i = 0; 2154104477Ssam HIFN_SRCR_SYNC(sc, i, 2155104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2156104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2157104477Ssam HIFN_SRCR_SYNC(sc, i, 2158104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2159104477Ssam break; 2160104477Ssam } 2161104477Ssam i++, u--; 2162104477Ssam } 2163104477Ssam dma->srck = i; dma->srcu = u; 2164104477Ssam 2165104477Ssam i = dma->cmdk; u = dma->cmdu; 2166104477Ssam while (u != 0) { 2167104477Ssam HIFN_CMDR_SYNC(sc, i, 2168104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2169104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2170104477Ssam HIFN_CMDR_SYNC(sc, i, 2171104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2172104477Ssam break; 2173104477Ssam } 2174104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2175104477Ssam u--; 2176104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2177104477Ssam } 2178104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2179104477Ssam i = 0; 2180104477Ssam } 2181104477Ssam dma->cmdk = i; dma->cmdu = u; 2182104477Ssam 2183115748Ssam HIFN_UNLOCK(sc); 2184115748Ssam 2185104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2186104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2187104477Ssam#ifdef HIFN_DEBUG 2188104477Ssam if (hifn_debug) 2189104477Ssam device_printf(sc->sc_dev, 2190104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2191104477Ssam sc->sc_needwakeup, 2192104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2193104477Ssam#endif 2194104477Ssam sc->sc_needwakeup &= ~wakeup; 2195104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2196104477Ssam } 2197104477Ssam} 2198104477Ssam 2199104477Ssam/* 2200104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2201104477Ssam * contains our registration id, and should contain an encoded session 2202104477Ssam * id on successful allocation. 2203104477Ssam */ 2204104477Ssamstatic int 2205104477Ssamhifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2206104477Ssam{ 2207104477Ssam struct cryptoini *c; 2208104477Ssam struct hifn_softc *sc = arg; 2209104477Ssam int i, mac = 0, cry = 0; 2210104477Ssam 2211104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2212104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2213104477Ssam return (EINVAL); 2214104477Ssam 2215104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2216104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2217104477Ssam break; 2218104477Ssam if (i == sc->sc_maxses) 2219104477Ssam return (ENOMEM); 2220104477Ssam 2221104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2222104477Ssam switch (c->cri_alg) { 2223104477Ssam case CRYPTO_MD5: 2224104477Ssam case CRYPTO_SHA1: 2225104477Ssam case CRYPTO_MD5_HMAC: 2226104477Ssam case CRYPTO_SHA1_HMAC: 2227104477Ssam if (mac) 2228104477Ssam return (EINVAL); 2229104477Ssam mac = 1; 2230104477Ssam break; 2231104477Ssam case CRYPTO_DES_CBC: 2232104477Ssam case CRYPTO_3DES_CBC: 2233120915Ssam case CRYPTO_AES_CBC: 2234104477Ssam /* XXX this may read fewer, does it matter? */ 2235120915Ssam read_random(sc->sc_sessions[i].hs_iv, 2236120915Ssam c->cri_alg == CRYPTO_AES_CBC ? 2237120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2238104477Ssam /*FALLTHROUGH*/ 2239104477Ssam case CRYPTO_ARC4: 2240104477Ssam if (cry) 2241104477Ssam return (EINVAL); 2242104477Ssam cry = 1; 2243104477Ssam break; 2244104477Ssam default: 2245104477Ssam return (EINVAL); 2246104477Ssam } 2247104477Ssam } 2248104477Ssam if (mac == 0 && cry == 0) 2249104477Ssam return (EINVAL); 2250104477Ssam 2251104477Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2252104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2253104477Ssam 2254104477Ssam return (0); 2255104477Ssam} 2256104477Ssam 2257104477Ssam/* 2258104477Ssam * Deallocate a session. 2259104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2260104477Ssam * XXX to blow away any keys already stored there. 2261104477Ssam */ 2262104477Ssamstatic int 2263104477Ssamhifn_freesession(void *arg, u_int64_t tid) 2264104477Ssam{ 2265104477Ssam struct hifn_softc *sc = arg; 2266104477Ssam int session; 2267116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2268104477Ssam 2269104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2270104477Ssam if (sc == NULL) 2271104477Ssam return (EINVAL); 2272104477Ssam 2273104477Ssam session = HIFN_SESSION(sid); 2274104477Ssam if (session >= sc->sc_maxses) 2275104477Ssam return (EINVAL); 2276104477Ssam 2277104477Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2278104477Ssam return (0); 2279104477Ssam} 2280104477Ssam 2281104477Ssamstatic int 2282104477Ssamhifn_process(void *arg, struct cryptop *crp, int hint) 2283104477Ssam{ 2284104477Ssam struct hifn_softc *sc = arg; 2285104477Ssam struct hifn_command *cmd = NULL; 2286120915Ssam int session, err, ivlen; 2287104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2288104477Ssam 2289104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2290104477Ssam hifnstats.hst_invalid++; 2291104477Ssam return (EINVAL); 2292104477Ssam } 2293104477Ssam session = HIFN_SESSION(crp->crp_sid); 2294104477Ssam 2295104477Ssam if (sc == NULL || session >= sc->sc_maxses) { 2296104477Ssam err = EINVAL; 2297104477Ssam goto errout; 2298104477Ssam } 2299104477Ssam 2300104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2301104477Ssam if (cmd == NULL) { 2302104477Ssam hifnstats.hst_nomem++; 2303104477Ssam err = ENOMEM; 2304104477Ssam goto errout; 2305104477Ssam } 2306104477Ssam 2307104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2308104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2309104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2310104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2311104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2312104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2313104477Ssam } else { 2314104477Ssam err = EINVAL; 2315104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2316104477Ssam } 2317104477Ssam 2318104477Ssam crd1 = crp->crp_desc; 2319104477Ssam if (crd1 == NULL) { 2320104477Ssam err = EINVAL; 2321104477Ssam goto errout; 2322104477Ssam } 2323104477Ssam crd2 = crd1->crd_next; 2324104477Ssam 2325104477Ssam if (crd2 == NULL) { 2326104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2327104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2328104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2329104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2330104477Ssam maccrd = crd1; 2331104477Ssam enccrd = NULL; 2332104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2333104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2334120915Ssam crd1->crd_alg == CRYPTO_AES_CBC || 2335104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2336104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2337104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2338104477Ssam maccrd = NULL; 2339104477Ssam enccrd = crd1; 2340104477Ssam } else { 2341104477Ssam err = EINVAL; 2342104477Ssam goto errout; 2343104477Ssam } 2344104477Ssam } else { 2345104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2346104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2347104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2348104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2349104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2350104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2351120915Ssam crd2->crd_alg == CRYPTO_AES_CBC || 2352104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2353104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2354104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2355104477Ssam maccrd = crd1; 2356104477Ssam enccrd = crd2; 2357104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2358104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2359120915Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2360120915Ssam crd1->crd_alg == CRYPTO_AES_CBC) && 2361104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2362104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2363104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2364104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2365104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2366104477Ssam enccrd = crd1; 2367104477Ssam maccrd = crd2; 2368104477Ssam } else { 2369104477Ssam /* 2370104477Ssam * We cannot order the 7751 as requested 2371104477Ssam */ 2372104477Ssam err = EINVAL; 2373104477Ssam goto errout; 2374104477Ssam } 2375104477Ssam } 2376104477Ssam 2377104477Ssam if (enccrd) { 2378104477Ssam cmd->enccrd = enccrd; 2379104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2380104477Ssam switch (enccrd->crd_alg) { 2381104477Ssam case CRYPTO_ARC4: 2382104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2383104477Ssam if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2384104477Ssam != sc->sc_sessions[session].hs_prev_op) 2385104477Ssam sc->sc_sessions[session].hs_state = 2386104477Ssam HS_STATE_USED; 2387104477Ssam break; 2388104477Ssam case CRYPTO_DES_CBC: 2389104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2390104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2391104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2392104477Ssam break; 2393104477Ssam case CRYPTO_3DES_CBC: 2394104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2395104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2396104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2397104477Ssam break; 2398120915Ssam case CRYPTO_AES_CBC: 2399120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2400120915Ssam HIFN_CRYPT_CMD_MODE_CBC | 2401120915Ssam HIFN_CRYPT_CMD_NEW_IV; 2402120915Ssam break; 2403104477Ssam default: 2404104477Ssam err = EINVAL; 2405104477Ssam goto errout; 2406104477Ssam } 2407104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2408120915Ssam ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2409120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2410104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2411104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2412120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2413104477Ssam else 2414104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2415120915Ssam cmd->iv, ivlen); 2416104477Ssam 2417104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2418104477Ssam == 0) { 2419104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2420104477Ssam m_copyback(cmd->src_m, 2421104477Ssam enccrd->crd_inject, 2422120915Ssam ivlen, cmd->iv); 2423104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2424104477Ssam cuio_copyback(cmd->src_io, 2425104477Ssam enccrd->crd_inject, 2426120915Ssam ivlen, cmd->iv); 2427104477Ssam } 2428104477Ssam } else { 2429104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2430120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2431104477Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 2432104477Ssam m_copydata(cmd->src_m, 2433120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2434104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2435104477Ssam cuio_copydata(cmd->src_io, 2436120915Ssam enccrd->crd_inject, ivlen, cmd->iv); 2437104477Ssam } 2438104477Ssam } 2439104477Ssam 2440125330Sphk if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2441125330Sphk cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2442104477Ssam cmd->ck = enccrd->crd_key; 2443104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2444104477Ssam 2445120915Ssam /* 2446120915Ssam * Need to specify the size for the AES key in the masks. 2447120915Ssam */ 2448120915Ssam if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2449120915Ssam HIFN_CRYPT_CMD_ALG_AES) { 2450120915Ssam switch (cmd->cklen) { 2451120915Ssam case 16: 2452120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2453120915Ssam break; 2454120915Ssam case 24: 2455120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2456120915Ssam break; 2457120915Ssam case 32: 2458120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2459120915Ssam break; 2460120915Ssam default: 2461120915Ssam err = EINVAL; 2462120915Ssam goto errout; 2463120915Ssam } 2464120915Ssam } 2465120915Ssam 2466104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2467104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2468104477Ssam } 2469104477Ssam 2470104477Ssam if (maccrd) { 2471104477Ssam cmd->maccrd = maccrd; 2472104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2473104477Ssam 2474104477Ssam switch (maccrd->crd_alg) { 2475104477Ssam case CRYPTO_MD5: 2476104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2477104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2478104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2479104477Ssam break; 2480104477Ssam case CRYPTO_MD5_HMAC: 2481104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2482104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2483104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2484104477Ssam break; 2485104477Ssam case CRYPTO_SHA1: 2486104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2487104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2488104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2489104477Ssam break; 2490104477Ssam case CRYPTO_SHA1_HMAC: 2491104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2492104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2493104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2494104477Ssam break; 2495104477Ssam } 2496104477Ssam 2497104477Ssam if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2498104477Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2499104477Ssam sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2500104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2501104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2502104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2503104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2504104477Ssam } 2505104477Ssam } 2506104477Ssam 2507104477Ssam cmd->crp = crp; 2508104477Ssam cmd->session_num = session; 2509104477Ssam cmd->softc = sc; 2510104477Ssam 2511104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2512104477Ssam if (!err) { 2513104477Ssam if (enccrd) 2514104477Ssam sc->sc_sessions[session].hs_prev_op = 2515104477Ssam enccrd->crd_flags & CRD_F_ENCRYPT; 2516104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2517104477Ssam sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2518104477Ssam return 0; 2519104477Ssam } else if (err == ERESTART) { 2520104477Ssam /* 2521104477Ssam * There weren't enough resources to dispatch the request 2522104477Ssam * to the part. Notify the caller so they'll requeue this 2523104477Ssam * request and resubmit it again soon. 2524104477Ssam */ 2525104477Ssam#ifdef HIFN_DEBUG 2526104477Ssam if (hifn_debug) 2527104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2528104477Ssam#endif 2529104477Ssam free(cmd, M_DEVBUF); 2530104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2531104477Ssam return (err); 2532104477Ssam } 2533104477Ssam 2534104477Ssamerrout: 2535104477Ssam if (cmd != NULL) 2536104477Ssam free(cmd, M_DEVBUF); 2537104477Ssam if (err == EINVAL) 2538104477Ssam hifnstats.hst_invalid++; 2539104477Ssam else 2540104477Ssam hifnstats.hst_nomem++; 2541104477Ssam crp->crp_etype = err; 2542104477Ssam crypto_done(crp); 2543104477Ssam return (err); 2544104477Ssam} 2545104477Ssam 2546104477Ssamstatic void 2547104477Ssamhifn_abort(struct hifn_softc *sc) 2548104477Ssam{ 2549104477Ssam struct hifn_dma *dma = sc->sc_dma; 2550104477Ssam struct hifn_command *cmd; 2551104477Ssam struct cryptop *crp; 2552104477Ssam int i, u; 2553104477Ssam 2554104477Ssam i = dma->resk; u = dma->resu; 2555104477Ssam while (u != 0) { 2556104477Ssam cmd = dma->hifn_commands[i]; 2557104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2558104477Ssam dma->hifn_commands[i] = NULL; 2559104477Ssam crp = cmd->crp; 2560104477Ssam 2561104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2562104477Ssam /* Salvage what we can. */ 2563104477Ssam u_int8_t *macbuf; 2564104477Ssam 2565104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2566104477Ssam macbuf = dma->result_bufs[i]; 2567104477Ssam macbuf += 12; 2568104477Ssam } else 2569104477Ssam macbuf = NULL; 2570104477Ssam hifnstats.hst_opackets++; 2571104477Ssam hifn_callback(sc, cmd, macbuf); 2572104477Ssam } else { 2573104477Ssam if (cmd->src_map == cmd->dst_map) { 2574104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2575104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2576104477Ssam } else { 2577104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2578104477Ssam BUS_DMASYNC_POSTWRITE); 2579104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2580104477Ssam BUS_DMASYNC_POSTREAD); 2581104477Ssam } 2582104477Ssam 2583104477Ssam if (cmd->src_m != cmd->dst_m) { 2584104477Ssam m_freem(cmd->src_m); 2585104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2586104477Ssam } 2587104477Ssam 2588104477Ssam /* non-shared buffers cannot be restarted */ 2589104477Ssam if (cmd->src_map != cmd->dst_map) { 2590104477Ssam /* 2591104477Ssam * XXX should be EAGAIN, delayed until 2592104477Ssam * after the reset. 2593104477Ssam */ 2594104477Ssam crp->crp_etype = ENOMEM; 2595104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2596104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2597104477Ssam } else 2598104477Ssam crp->crp_etype = ENOMEM; 2599104477Ssam 2600104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2601104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2602104477Ssam 2603104477Ssam free(cmd, M_DEVBUF); 2604104477Ssam if (crp->crp_etype != EAGAIN) 2605104477Ssam crypto_done(crp); 2606104477Ssam } 2607104477Ssam 2608104477Ssam if (++i == HIFN_D_RES_RSIZE) 2609104477Ssam i = 0; 2610104477Ssam u--; 2611104477Ssam } 2612104477Ssam dma->resk = i; dma->resu = u; 2613104477Ssam 2614104477Ssam /* Force upload of key next time */ 2615104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2616104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2617104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2618104477Ssam 2619104477Ssam hifn_reset_board(sc, 1); 2620104477Ssam hifn_init_dma(sc); 2621104477Ssam hifn_init_pci_registers(sc); 2622104477Ssam} 2623104477Ssam 2624104477Ssamstatic void 2625104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2626104477Ssam{ 2627104477Ssam struct hifn_dma *dma = sc->sc_dma; 2628104477Ssam struct cryptop *crp = cmd->crp; 2629104477Ssam struct cryptodesc *crd; 2630104477Ssam struct mbuf *m; 2631120915Ssam int totlen, i, u, ivlen; 2632104477Ssam 2633104477Ssam if (cmd->src_map == cmd->dst_map) { 2634104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2635104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2636104477Ssam } else { 2637104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2638104477Ssam BUS_DMASYNC_POSTWRITE); 2639104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2640104477Ssam BUS_DMASYNC_POSTREAD); 2641104477Ssam } 2642104477Ssam 2643104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2644104477Ssam if (cmd->src_m != cmd->dst_m) { 2645104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2646104477Ssam totlen = cmd->src_mapsize; 2647104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2648104477Ssam if (totlen < m->m_len) { 2649104477Ssam m->m_len = totlen; 2650104477Ssam totlen = 0; 2651104477Ssam } else 2652104477Ssam totlen -= m->m_len; 2653104477Ssam } 2654104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2655104477Ssam m_freem(cmd->src_m); 2656104477Ssam } 2657104477Ssam } 2658104477Ssam 2659104477Ssam if (cmd->sloplen != 0) { 2660104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2661104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2662104477Ssam cmd->src_mapsize - cmd->sloplen, 2663104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2664104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2665104477Ssam cuio_copyback((struct uio *)crp->crp_buf, 2666104477Ssam cmd->src_mapsize - cmd->sloplen, 2667104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2668104477Ssam } 2669104477Ssam 2670104477Ssam i = dma->dstk; u = dma->dstu; 2671104477Ssam while (u != 0) { 2672104477Ssam if (i == HIFN_D_DST_RSIZE) 2673104477Ssam i = 0; 2674104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2675104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2676104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2677104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2678104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2679104477Ssam break; 2680104477Ssam } 2681104477Ssam i++, u--; 2682104477Ssam } 2683104477Ssam dma->dstk = i; dma->dstu = u; 2684104477Ssam 2685104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2686104477Ssam 2687104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2688104477Ssam HIFN_BASE_CMD_CRYPT) { 2689104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2690104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2691120915Ssam crd->crd_alg != CRYPTO_3DES_CBC && 2692120915Ssam crd->crd_alg != CRYPTO_AES_CBC) 2693104477Ssam continue; 2694120915Ssam ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2695120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2696104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2697104477Ssam m_copydata((struct mbuf *)crp->crp_buf, 2698120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2699104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2700104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) { 2701104477Ssam cuio_copydata((struct uio *)crp->crp_buf, 2702120915Ssam crd->crd_skip + crd->crd_len - ivlen, ivlen, 2703104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2704104477Ssam } 2705104477Ssam break; 2706104477Ssam } 2707104477Ssam } 2708104477Ssam 2709104477Ssam if (macbuf != NULL) { 2710104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2711105275Ssam int len; 2712104477Ssam 2713105275Ssam if (crd->crd_alg == CRYPTO_MD5) 2714105275Ssam len = 16; 2715105275Ssam else if (crd->crd_alg == CRYPTO_SHA1) 2716105275Ssam len = 20; 2717105275Ssam else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2718105275Ssam crd->crd_alg == CRYPTO_SHA1_HMAC) 2719105275Ssam len = 12; 2720105275Ssam else 2721104477Ssam continue; 2722104477Ssam 2723104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2724104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2725104477Ssam crd->crd_inject, len, macbuf); 2726104477Ssam else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2727104477Ssam bcopy((caddr_t)macbuf, crp->crp_mac, len); 2728104477Ssam break; 2729104477Ssam } 2730104477Ssam } 2731104477Ssam 2732104477Ssam if (cmd->src_map != cmd->dst_map) { 2733104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2734104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2735104477Ssam } 2736104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2737104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2738104477Ssam free(cmd, M_DEVBUF); 2739104477Ssam crypto_done(crp); 2740104477Ssam} 2741104477Ssam 2742104477Ssam/* 2743104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2744104477Ssam * and Group 1 registers; avoid conditions that could create 2745104477Ssam * burst writes by doing a read in between the writes. 2746104477Ssam * 2747104477Ssam * NB: The read we interpose is always to the same register; 2748104477Ssam * we do this because reading from an arbitrary (e.g. last) 2749104477Ssam * register may not always work. 2750104477Ssam */ 2751104477Ssamstatic void 2752104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2753104477Ssam{ 2754104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2755104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2756104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2757104477Ssam sc->sc_bar0_lastreg = reg; 2758104477Ssam } 2759104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2760104477Ssam} 2761104477Ssam 2762104477Ssamstatic void 2763104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2764104477Ssam{ 2765104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2766104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2767104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2768104477Ssam sc->sc_bar1_lastreg = reg; 2769104477Ssam } 2770104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2771104477Ssam} 2772