hifn7751.c revision 109596
1/* $FreeBSD: head/sys/dev/hifn/hifn7751.c 109596 2003-01-20 21:11:56Z sam $ */ 2/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 3 4/* 5 * Invertex AEON / Hifn 7751 driver 6 * Copyright (c) 1999 Invertex Inc. All rights reserved. 7 * Copyright (c) 1999 Theo de Raadt 8 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 9 * http://www.netsec.net 10 * 11 * This driver is based on a previous driver by Invertex, for which they 12 * requested: Please send any comments, feedback, bug-fixes, or feature 13 * requests to software@invertex.com. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 * 42 */ 43 44#define HIFN_DEBUG 45 46/* 47 * Driver for the Hifn 7751 encryption processor. 48 */ 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/mbuf.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/sysctl.h> 60 61#include <vm/vm.h> 62#include <vm/pmap.h> 63 64#include <machine/clock.h> 65#include <machine/bus.h> 66#include <machine/resource.h> 67#include <sys/bus.h> 68#include <sys/rman.h> 69 70#include <opencrypto/cryptodev.h> 71#include <sys/random.h> 72 73#include <pci/pcivar.h> 74#include <pci/pcireg.h> 75#include <dev/hifn/hifn7751reg.h> 76#include <dev/hifn/hifn7751var.h> 77 78/* 79 * Prototypes and count for the pci_device structure 80 */ 81static int hifn_probe(device_t); 82static int hifn_attach(device_t); 83static int hifn_detach(device_t); 84static int hifn_suspend(device_t); 85static int hifn_resume(device_t); 86static void hifn_shutdown(device_t); 87 88static device_method_t hifn_methods[] = { 89 /* Device interface */ 90 DEVMETHOD(device_probe, hifn_probe), 91 DEVMETHOD(device_attach, hifn_attach), 92 DEVMETHOD(device_detach, hifn_detach), 93 DEVMETHOD(device_suspend, hifn_suspend), 94 DEVMETHOD(device_resume, hifn_resume), 95 DEVMETHOD(device_shutdown, hifn_shutdown), 96 97 /* bus interface */ 98 DEVMETHOD(bus_print_child, bus_generic_print_child), 99 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 100 101 { 0, 0 } 102}; 103static driver_t hifn_driver = { 104 "hifn", 105 hifn_methods, 106 sizeof (struct hifn_softc) 107}; 108static devclass_t hifn_devclass; 109 110DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 111MODULE_DEPEND(hifn, crypto, 1, 1, 1); 112 113static void hifn_reset_board(struct hifn_softc *, int); 114static void hifn_reset_puc(struct hifn_softc *); 115static void hifn_puc_wait(struct hifn_softc *); 116static int hifn_enable_crypto(struct hifn_softc *); 117static void hifn_set_retry(struct hifn_softc *sc); 118static void hifn_init_dma(struct hifn_softc *); 119static void hifn_init_pci_registers(struct hifn_softc *); 120static int hifn_sramsize(struct hifn_softc *); 121static int hifn_dramsize(struct hifn_softc *); 122static int hifn_ramtype(struct hifn_softc *); 123static void hifn_sessions(struct hifn_softc *); 124static void hifn_intr(void *); 125static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 126static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 127static int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 128static int hifn_freesession(void *, u_int64_t); 129static int hifn_process(void *, struct cryptop *, int); 130static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 131static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 132static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 133static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 134static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 135static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 136static int hifn_init_pubrng(struct hifn_softc *); 137static void hifn_rng(void *); 138static void hifn_tick(void *); 139static void hifn_abort(struct hifn_softc *); 140static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 141 142static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 143static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 144 145static __inline__ u_int32_t 146READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 147{ 148 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 149 sc->sc_bar0_lastreg = (bus_size_t) -1; 150 return (v); 151} 152#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 153 154static __inline__ u_int32_t 155READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 156{ 157 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 158 sc->sc_bar1_lastreg = (bus_size_t) -1; 159 return (v); 160} 161#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 162 163SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 164 165#ifdef HIFN_DEBUG 166static int hifn_debug = 0; 167SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 168 0, "control debugging msgs"); 169#endif 170 171static struct hifn_stats hifnstats; 172SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 173 hifn_stats, "driver statistics"); 174static int hifn_maxbatch = 1; 175SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 176 0, "max ops to batch w/o interrupt"); 177 178/* 179 * Probe for a supported device. The PCI vendor and device 180 * IDs are used to detect devices we know how to handle. 181 */ 182static int 183hifn_probe(device_t dev) 184{ 185 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 186 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 187 return (0); 188 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 189 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 190 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 191 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 192 return (0); 193 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 194 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 195 return (0); 196 return (ENXIO); 197} 198 199static void 200hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 201{ 202 bus_addr_t *paddr = (bus_addr_t*) arg; 203 *paddr = segs->ds_addr; 204} 205 206static const char* 207hifn_partname(struct hifn_softc *sc) 208{ 209 /* XXX sprintf numbers when not decoded */ 210 switch (pci_get_vendor(sc->sc_dev)) { 211 case PCI_VENDOR_HIFN: 212 switch (pci_get_device(sc->sc_dev)) { 213 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 214 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 215 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 216 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 217 } 218 return "Hifn unknown-part"; 219 case PCI_VENDOR_INVERTEX: 220 switch (pci_get_device(sc->sc_dev)) { 221 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 222 } 223 return "Invertex unknown-part"; 224 case PCI_VENDOR_NETSEC: 225 switch (pci_get_device(sc->sc_dev)) { 226 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 227 } 228 return "NetSec unknown-part"; 229 } 230 return "Unknown-vendor unknown-part"; 231} 232 233/* 234 * Attach an interface that successfully probed. 235 */ 236static int 237hifn_attach(device_t dev) 238{ 239 struct hifn_softc *sc = device_get_softc(dev); 240 u_int32_t cmd; 241 caddr_t kva; 242 int rseg, rid; 243 char rbase; 244 u_int16_t ena, rev; 245 246 KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 247 bzero(sc, sizeof (*sc)); 248 sc->sc_dev = dev; 249 250 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 251 252 /* XXX handle power management */ 253 254 /* 255 * The 7951 has a random number generator and 256 * public key support; note this. 257 */ 258 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 259 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 260 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 261 /* 262 * The 7811 has a random number generator and 263 * we also note it's identity 'cuz of some quirks. 264 */ 265 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 266 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 267 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 268 269 /* 270 * Configure support for memory-mapped access to 271 * registers and for DMA operations. 272 */ 273#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 274 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 275 cmd |= PCIM_ENA; 276 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 277 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 278 if ((cmd & PCIM_ENA) != PCIM_ENA) { 279 device_printf(dev, "failed to enable %s\n", 280 (cmd & PCIM_ENA) == 0 ? 281 "memory mapping & bus mastering" : 282 (cmd & PCIM_CMD_MEMEN) == 0 ? 283 "memory mapping" : "bus mastering"); 284 goto fail_pci; 285 } 286#undef PCIM_ENA 287 288 /* 289 * Setup PCI resources. Note that we record the bus 290 * tag and handle for each register mapping, this is 291 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 292 * and WRITE_REG_1 macros throughout the driver. 293 */ 294 rid = HIFN_BAR0; 295 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 296 0, ~0, 1, RF_ACTIVE); 297 if (sc->sc_bar0res == NULL) { 298 device_printf(dev, "cannot map bar%d register space\n", 0); 299 goto fail_pci; 300 } 301 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 302 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 303 sc->sc_bar0_lastreg = (bus_size_t) -1; 304 305 rid = HIFN_BAR1; 306 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 307 0, ~0, 1, RF_ACTIVE); 308 if (sc->sc_bar1res == NULL) { 309 device_printf(dev, "cannot map bar%d register space\n", 1); 310 goto fail_io0; 311 } 312 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 313 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 314 sc->sc_bar1_lastreg = (bus_size_t) -1; 315 316 hifn_set_retry(sc); 317 318 /* 319 * Setup the area where the Hifn DMA's descriptors 320 * and associated data structures. 321 */ 322 if (bus_dma_tag_create(NULL, /* parent */ 323 1, 0, /* alignment,boundary */ 324 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 325 BUS_SPACE_MAXADDR, /* highaddr */ 326 NULL, NULL, /* filter, filterarg */ 327 HIFN_MAX_DMALEN, /* maxsize */ 328 MAX_SCATTER, /* nsegments */ 329 HIFN_MAX_SEGLEN, /* maxsegsize */ 330 BUS_DMA_ALLOCNOW, /* flags */ 331 &sc->sc_dmat)) { 332 device_printf(dev, "cannot allocate DMA tag\n"); 333 goto fail_io1; 334 } 335 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 336 device_printf(dev, "cannot create dma map\n"); 337 bus_dma_tag_destroy(sc->sc_dmat); 338 goto fail_io1; 339 } 340 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 341 device_printf(dev, "cannot alloc dma buffer\n"); 342 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 343 bus_dma_tag_destroy(sc->sc_dmat); 344 goto fail_io1; 345 } 346 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 347 sizeof (*sc->sc_dma), 348 hifn_dmamap_cb, &sc->sc_dma_physaddr, 349 BUS_DMA_NOWAIT)) { 350 device_printf(dev, "cannot load dma map\n"); 351 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 352 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 353 bus_dma_tag_destroy(sc->sc_dmat); 354 goto fail_io1; 355 } 356 sc->sc_dma = (struct hifn_dma *)kva; 357 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 358 359 KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 360 KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 361 KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 362 KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 363 364 /* 365 * Reset the board and do the ``secret handshake'' 366 * to enable the crypto support. Then complete the 367 * initialization procedure by setting up the interrupt 368 * and hooking in to the system crypto support so we'll 369 * get used for system services like the crypto device, 370 * IPsec, RNG device, etc. 371 */ 372 hifn_reset_board(sc, 0); 373 374 if (hifn_enable_crypto(sc) != 0) { 375 device_printf(dev, "crypto enabling failed\n"); 376 goto fail_mem; 377 } 378 hifn_reset_puc(sc); 379 380 hifn_init_dma(sc); 381 hifn_init_pci_registers(sc); 382 383 if (hifn_ramtype(sc)) 384 goto fail_mem; 385 386 if (sc->sc_drammodel == 0) 387 hifn_sramsize(sc); 388 else 389 hifn_dramsize(sc); 390 391 /* 392 * Workaround for NetSec 7751 rev A: half ram size because two 393 * of the address lines were left floating 394 */ 395 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 396 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 397 pci_get_revid(dev) == 0x61) /*XXX???*/ 398 sc->sc_ramsize >>= 1; 399 400 /* 401 * Arrange the interrupt line. 402 */ 403 rid = 0; 404 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 405 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 406 if (sc->sc_irq == NULL) { 407 device_printf(dev, "could not map interrupt\n"); 408 goto fail_mem; 409 } 410 /* 411 * NB: Network code assumes we are blocked with splimp() 412 * so make sure the IRQ is marked appropriately. 413 */ 414 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 415 hifn_intr, sc, &sc->sc_intrhand)) { 416 device_printf(dev, "could not setup interrupt\n"); 417 goto fail_intr2; 418 } 419 420 hifn_sessions(sc); 421 422 /* 423 * NB: Keep only the low 16 bits; this masks the chip id 424 * from the 7951. 425 */ 426 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 427 428 rseg = sc->sc_ramsize / 1024; 429 rbase = 'K'; 430 if (sc->sc_ramsize >= (1024 * 1024)) { 431 rbase = 'M'; 432 rseg /= 1024; 433 } 434 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 435 hifn_partname(sc), rev, 436 rseg, rbase, sc->sc_drammodel ? 'd' : 's', 437 sc->sc_maxses); 438 439 sc->sc_cid = crypto_get_driverid(0); 440 if (sc->sc_cid < 0) { 441 device_printf(dev, "could not get crypto driver id\n"); 442 goto fail_intr; 443 } 444 445 WRITE_REG_0(sc, HIFN_0_PUCNFG, 446 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 447 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 448 449 switch (ena) { 450 case HIFN_PUSTAT_ENA_2: 451 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 452 hifn_newsession, hifn_freesession, hifn_process, sc); 453 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 454 hifn_newsession, hifn_freesession, hifn_process, sc); 455 /*FALLTHROUGH*/ 456 case HIFN_PUSTAT_ENA_1: 457 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 458 hifn_newsession, hifn_freesession, hifn_process, sc); 459 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 460 hifn_newsession, hifn_freesession, hifn_process, sc); 461 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 462 hifn_newsession, hifn_freesession, hifn_process, sc); 463 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 464 hifn_newsession, hifn_freesession, hifn_process, sc); 465 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 466 hifn_newsession, hifn_freesession, hifn_process, sc); 467 break; 468 } 469 470 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 471 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 472 473 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 474 hifn_init_pubrng(sc); 475 476 /* NB: 1 means the callout runs w/o Giant locked */ 477 callout_init(&sc->sc_tickto, 1); 478 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 479 480 return (0); 481 482fail_intr: 483 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 484fail_intr2: 485 /* XXX don't store rid */ 486 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 487fail_mem: 488 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 489 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 490 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 491 bus_dma_tag_destroy(sc->sc_dmat); 492 493 /* Turn off DMA polling */ 494 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 495 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 496fail_io1: 497 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 498fail_io0: 499 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 500fail_pci: 501 mtx_destroy(&sc->sc_mtx); 502 return (ENXIO); 503} 504 505/* 506 * Detach an interface that successfully probed. 507 */ 508static int 509hifn_detach(device_t dev) 510{ 511 struct hifn_softc *sc = device_get_softc(dev); 512 513 KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 514 515 HIFN_LOCK(sc); 516 517 /*XXX other resources */ 518 callout_stop(&sc->sc_tickto); 519 callout_stop(&sc->sc_rngto); 520 521 /* Turn off DMA polling */ 522 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 523 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 524 525 crypto_unregister_all(sc->sc_cid); 526 527 bus_generic_detach(dev); /*XXX should be no children, right? */ 528 529 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 530 /* XXX don't store rid */ 531 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 532 533 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 534 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 535 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 536 bus_dma_tag_destroy(sc->sc_dmat); 537 538 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 539 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 540 541 HIFN_UNLOCK(sc); 542 543 mtx_destroy(&sc->sc_mtx); 544 545 return (0); 546} 547 548/* 549 * Stop all chip I/O so that the kernel's probe routines don't 550 * get confused by errant DMAs when rebooting. 551 */ 552static void 553hifn_shutdown(device_t dev) 554{ 555#ifdef notyet 556 hifn_stop(device_get_softc(dev)); 557#endif 558} 559 560/* 561 * Device suspend routine. Stop the interface and save some PCI 562 * settings in case the BIOS doesn't restore them properly on 563 * resume. 564 */ 565static int 566hifn_suspend(device_t dev) 567{ 568 struct hifn_softc *sc = device_get_softc(dev); 569#ifdef notyet 570 int i; 571 572 hifn_stop(sc); 573 for (i = 0; i < 5; i++) 574 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 575 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 576 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 577 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 578 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 579#endif 580 sc->sc_suspended = 1; 581 582 return (0); 583} 584 585/* 586 * Device resume routine. Restore some PCI settings in case the BIOS 587 * doesn't, re-enable busmastering, and restart the interface if 588 * appropriate. 589 */ 590static int 591hifn_resume(device_t dev) 592{ 593 struct hifn_softc *sc = device_get_softc(dev); 594#ifdef notyet 595 int i; 596 597 /* better way to do this? */ 598 for (i = 0; i < 5; i++) 599 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 600 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 601 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 602 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 603 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 604 605 /* reenable busmastering */ 606 pci_enable_busmaster(dev); 607 pci_enable_io(dev, HIFN_RES); 608 609 /* reinitialize interface if necessary */ 610 if (ifp->if_flags & IFF_UP) 611 rl_init(sc); 612#endif 613 sc->sc_suspended = 0; 614 615 return (0); 616} 617 618static int 619hifn_init_pubrng(struct hifn_softc *sc) 620{ 621 u_int32_t r; 622 int i; 623 624 if ((sc->sc_flags & HIFN_IS_7811) == 0) { 625 /* Reset 7951 public key/rng engine */ 626 WRITE_REG_1(sc, HIFN_1_PUB_RESET, 627 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 628 629 for (i = 0; i < 100; i++) { 630 DELAY(1000); 631 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 632 HIFN_PUBRST_RESET) == 0) 633 break; 634 } 635 636 if (i == 100) { 637 device_printf(sc->sc_dev, "public key init failed\n"); 638 return (1); 639 } 640 } 641 642 /* Enable the rng, if available */ 643 if (sc->sc_flags & HIFN_HAS_RNG) { 644 if (sc->sc_flags & HIFN_IS_7811) { 645 r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 646 if (r & HIFN_7811_RNGENA_ENA) { 647 r &= ~HIFN_7811_RNGENA_ENA; 648 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 649 } 650 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 651 HIFN_7811_RNGCFG_DEFL); 652 r |= HIFN_7811_RNGENA_ENA; 653 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 654 } else 655 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 656 READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 657 HIFN_RNGCFG_ENA); 658 659 sc->sc_rngfirst = 1; 660 if (hz >= 100) 661 sc->sc_rnghz = hz / 100; 662 else 663 sc->sc_rnghz = 1; 664 /* NB: 1 means the callout runs w/o Giant locked */ 665 callout_init(&sc->sc_rngto, 1); 666 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 667 } 668 669 /* Enable public key engine, if available */ 670 if (sc->sc_flags & HIFN_HAS_PUBLIC) { 671 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 672 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 673 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 674 } 675 676 return (0); 677} 678 679static void 680hifn_rng(void *vsc) 681{ 682#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 683 struct hifn_softc *sc = vsc; 684 u_int32_t sts, num[2]; 685 int i; 686 687 if (sc->sc_flags & HIFN_IS_7811) { 688 for (i = 0; i < 5; i++) { 689 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 690 if (sts & HIFN_7811_RNGSTS_UFL) { 691 device_printf(sc->sc_dev, 692 "RNG underflow: disabling\n"); 693 return; 694 } 695 if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 696 break; 697 698 /* 699 * There are at least two words in the RNG FIFO 700 * at this point. 701 */ 702 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 703 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 704 /* NB: discard first data read */ 705 if (sc->sc_rngfirst) 706 sc->sc_rngfirst = 0; 707 else 708 random_harvest(num, RANDOM_BITS(2), RANDOM_PURE); 709 } 710 } else { 711 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 712 713 /* NB: discard first data read */ 714 if (sc->sc_rngfirst) 715 sc->sc_rngfirst = 0; 716 else 717 random_harvest(num, RANDOM_BITS(1), RANDOM_PURE); 718 } 719 720 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 721#undef RANDOM_BITS 722} 723 724static void 725hifn_puc_wait(struct hifn_softc *sc) 726{ 727 int i; 728 729 for (i = 5000; i > 0; i--) { 730 DELAY(1); 731 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 732 break; 733 } 734 if (!i) 735 device_printf(sc->sc_dev, "proc unit did not reset\n"); 736} 737 738/* 739 * Reset the processing unit. 740 */ 741static void 742hifn_reset_puc(struct hifn_softc *sc) 743{ 744 /* Reset processing unit */ 745 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 746 hifn_puc_wait(sc); 747} 748 749/* 750 * Set the Retry and TRDY registers; note that we set them to 751 * zero because the 7811 locks up when forced to retry (section 752 * 3.6 of "Specification Update SU-0014-04". Not clear if we 753 * should do this for all Hifn parts, but it doesn't seem to hurt. 754 */ 755static void 756hifn_set_retry(struct hifn_softc *sc) 757{ 758 /* NB: RETRY only responds to 8-bit reads/writes */ 759 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 760 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 761} 762 763/* 764 * Resets the board. Values in the regesters are left as is 765 * from the reset (i.e. initial values are assigned elsewhere). 766 */ 767static void 768hifn_reset_board(struct hifn_softc *sc, int full) 769{ 770 u_int32_t reg; 771 772 /* 773 * Set polling in the DMA configuration register to zero. 0x7 avoids 774 * resetting the board and zeros out the other fields. 775 */ 776 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 777 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 778 779 /* 780 * Now that polling has been disabled, we have to wait 1 ms 781 * before resetting the board. 782 */ 783 DELAY(1000); 784 785 /* Reset the DMA unit */ 786 if (full) { 787 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 788 DELAY(1000); 789 } else { 790 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 791 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 792 hifn_reset_puc(sc); 793 } 794 795 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 796 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 797 798 /* Bring dma unit out of reset */ 799 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 800 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 801 802 hifn_puc_wait(sc); 803 hifn_set_retry(sc); 804 805 if (sc->sc_flags & HIFN_IS_7811) { 806 for (reg = 0; reg < 1000; reg++) { 807 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 808 HIFN_MIPSRST_CRAMINIT) 809 break; 810 DELAY(1000); 811 } 812 if (reg == 1000) 813 printf(": cram init timeout\n"); 814 } 815} 816 817static u_int32_t 818hifn_next_signature(u_int32_t a, u_int cnt) 819{ 820 int i; 821 u_int32_t v; 822 823 for (i = 0; i < cnt; i++) { 824 825 /* get the parity */ 826 v = a & 0x80080125; 827 v ^= v >> 16; 828 v ^= v >> 8; 829 v ^= v >> 4; 830 v ^= v >> 2; 831 v ^= v >> 1; 832 833 a = (v & 1) ^ (a << 1); 834 } 835 836 return a; 837} 838 839struct pci2id { 840 u_short pci_vendor; 841 u_short pci_prod; 842 char card_id[13]; 843}; 844static struct pci2id pci2id[] = { 845 { 846 PCI_VENDOR_HIFN, 847 PCI_PRODUCT_HIFN_7951, 848 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 849 0x00, 0x00, 0x00, 0x00, 0x00 } 850 }, { 851 PCI_VENDOR_NETSEC, 852 PCI_PRODUCT_NETSEC_7751, 853 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 854 0x00, 0x00, 0x00, 0x00, 0x00 } 855 }, { 856 PCI_VENDOR_INVERTEX, 857 PCI_PRODUCT_INVERTEX_AEON, 858 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 859 0x00, 0x00, 0x00, 0x00, 0x00 } 860 }, { 861 PCI_VENDOR_HIFN, 862 PCI_PRODUCT_HIFN_7811, 863 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 864 0x00, 0x00, 0x00, 0x00, 0x00 } 865 }, { 866 /* 867 * Other vendors share this PCI ID as well, such as 868 * http://www.powercrypt.com, and obviously they also 869 * use the same key. 870 */ 871 PCI_VENDOR_HIFN, 872 PCI_PRODUCT_HIFN_7751, 873 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 874 0x00, 0x00, 0x00, 0x00, 0x00 } 875 }, 876}; 877 878/* 879 * Checks to see if crypto is already enabled. If crypto isn't enable, 880 * "hifn_enable_crypto" is called to enable it. The check is important, 881 * as enabling crypto twice will lock the board. 882 */ 883static int 884hifn_enable_crypto(struct hifn_softc *sc) 885{ 886 u_int32_t dmacfg, ramcfg, encl, addr, i; 887 char *offtbl = NULL; 888 889 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 890 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 891 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 892 offtbl = pci2id[i].card_id; 893 break; 894 } 895 } 896 if (offtbl == NULL) { 897 device_printf(sc->sc_dev, "Unknown card!\n"); 898 return (1); 899 } 900 901 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 902 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 903 904 /* 905 * The RAM config register's encrypt level bit needs to be set before 906 * every read performed on the encryption level register. 907 */ 908 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 909 910 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 911 912 /* 913 * Make sure we don't re-unlock. Two unlocks kills chip until the 914 * next reboot. 915 */ 916 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 917#ifdef HIFN_DEBUG 918 if (hifn_debug) 919 device_printf(sc->sc_dev, 920 "Strong crypto already enabled!\n"); 921#endif 922 goto report; 923 } 924 925 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 926#ifdef HIFN_DEBUG 927 if (hifn_debug) 928 device_printf(sc->sc_dev, 929 "Unknown encryption level 0x%x\n", encl); 930#endif 931 return 1; 932 } 933 934 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 935 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 936 DELAY(1000); 937 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 938 DELAY(1000); 939 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 940 DELAY(1000); 941 942 for (i = 0; i <= 12; i++) { 943 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 944 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 945 946 DELAY(1000); 947 } 948 949 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 950 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 951 952#ifdef HIFN_DEBUG 953 if (hifn_debug) { 954 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 955 device_printf(sc->sc_dev, "Engine is permanently " 956 "locked until next system reset!\n"); 957 else 958 device_printf(sc->sc_dev, "Engine enabled " 959 "successfully!\n"); 960 } 961#endif 962 963report: 964 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 965 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 966 967 switch (encl) { 968 case HIFN_PUSTAT_ENA_1: 969 case HIFN_PUSTAT_ENA_2: 970 break; 971 case HIFN_PUSTAT_ENA_0: 972 default: 973 device_printf(sc->sc_dev, "disabled"); 974 break; 975 } 976 977 return 0; 978} 979 980/* 981 * Give initial values to the registers listed in the "Register Space" 982 * section of the HIFN Software Development reference manual. 983 */ 984static void 985hifn_init_pci_registers(struct hifn_softc *sc) 986{ 987 /* write fixed values needed by the Initialization registers */ 988 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 989 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 990 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 991 992 /* write all 4 ring address registers */ 993 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 994 offsetof(struct hifn_dma, cmdr[0])); 995 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 996 offsetof(struct hifn_dma, srcr[0])); 997 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 998 offsetof(struct hifn_dma, dstr[0])); 999 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1000 offsetof(struct hifn_dma, resr[0])); 1001 1002 DELAY(2000); 1003 1004 /* write status register */ 1005 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1006 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1007 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1008 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1009 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1010 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1011 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1012 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1013 HIFN_DMACSR_S_WAIT | 1014 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1015 HIFN_DMACSR_C_WAIT | 1016 HIFN_DMACSR_ENGINE | 1017 ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1018 HIFN_DMACSR_PUBDONE : 0) | 1019 ((sc->sc_flags & HIFN_IS_7811) ? 1020 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1021 1022 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1023 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1024 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1025 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1026 ((sc->sc_flags & HIFN_IS_7811) ? 1027 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1028 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1029 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1030 1031 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1032 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1033 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1034 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1035 1036 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1037 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1038 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1039 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1040 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1041} 1042 1043/* 1044 * The maximum number of sessions supported by the card 1045 * is dependent on the amount of context ram, which 1046 * encryption algorithms are enabled, and how compression 1047 * is configured. This should be configured before this 1048 * routine is called. 1049 */ 1050static void 1051hifn_sessions(struct hifn_softc *sc) 1052{ 1053 u_int32_t pucnfg; 1054 int ctxsize; 1055 1056 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1057 1058 if (pucnfg & HIFN_PUCNFG_COMPSING) { 1059 if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1060 ctxsize = 128; 1061 else 1062 ctxsize = 512; 1063 sc->sc_maxses = 1 + 1064 ((sc->sc_ramsize - 32768) / ctxsize); 1065 } else 1066 sc->sc_maxses = sc->sc_ramsize / 16384; 1067 1068 if (sc->sc_maxses > 2048) 1069 sc->sc_maxses = 2048; 1070} 1071 1072/* 1073 * Determine ram type (sram or dram). Board should be just out of a reset 1074 * state when this is called. 1075 */ 1076static int 1077hifn_ramtype(struct hifn_softc *sc) 1078{ 1079 u_int8_t data[8], dataexpect[8]; 1080 int i; 1081 1082 for (i = 0; i < sizeof(data); i++) 1083 data[i] = dataexpect[i] = 0x55; 1084 if (hifn_writeramaddr(sc, 0, data)) 1085 return (-1); 1086 if (hifn_readramaddr(sc, 0, data)) 1087 return (-1); 1088 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1089 sc->sc_drammodel = 1; 1090 return (0); 1091 } 1092 1093 for (i = 0; i < sizeof(data); i++) 1094 data[i] = dataexpect[i] = 0xaa; 1095 if (hifn_writeramaddr(sc, 0, data)) 1096 return (-1); 1097 if (hifn_readramaddr(sc, 0, data)) 1098 return (-1); 1099 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1100 sc->sc_drammodel = 1; 1101 return (0); 1102 } 1103 1104 return (0); 1105} 1106 1107#define HIFN_SRAM_MAX (32 << 20) 1108#define HIFN_SRAM_STEP_SIZE 16384 1109#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1110 1111static int 1112hifn_sramsize(struct hifn_softc *sc) 1113{ 1114 u_int32_t a; 1115 u_int8_t data[8]; 1116 u_int8_t dataexpect[sizeof(data)]; 1117 int32_t i; 1118 1119 for (i = 0; i < sizeof(data); i++) 1120 data[i] = dataexpect[i] = i ^ 0x5a; 1121 1122 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1123 a = i * HIFN_SRAM_STEP_SIZE; 1124 bcopy(&i, data, sizeof(i)); 1125 hifn_writeramaddr(sc, a, data); 1126 } 1127 1128 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1129 a = i * HIFN_SRAM_STEP_SIZE; 1130 bcopy(&i, dataexpect, sizeof(i)); 1131 if (hifn_readramaddr(sc, a, data) < 0) 1132 return (0); 1133 if (bcmp(data, dataexpect, sizeof(data)) != 0) 1134 return (0); 1135 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1136 } 1137 1138 return (0); 1139} 1140 1141/* 1142 * XXX For dram boards, one should really try all of the 1143 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1144 * is already set up correctly. 1145 */ 1146static int 1147hifn_dramsize(struct hifn_softc *sc) 1148{ 1149 u_int32_t cnfg; 1150 1151 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1152 HIFN_PUCNFG_DRAMMASK; 1153 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1154 return (0); 1155} 1156 1157static void 1158hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1159{ 1160 struct hifn_dma *dma = sc->sc_dma; 1161 1162 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1163 dma->cmdi = 0; 1164 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1165 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1166 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1168 } 1169 *cmdp = dma->cmdi++; 1170 dma->cmdk = dma->cmdi; 1171 1172 if (dma->srci == HIFN_D_SRC_RSIZE) { 1173 dma->srci = 0; 1174 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1175 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1176 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1177 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1178 } 1179 *srcp = dma->srci++; 1180 dma->srck = dma->srci; 1181 1182 if (dma->dsti == HIFN_D_DST_RSIZE) { 1183 dma->dsti = 0; 1184 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1185 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1186 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1188 } 1189 *dstp = dma->dsti++; 1190 dma->dstk = dma->dsti; 1191 1192 if (dma->resi == HIFN_D_RES_RSIZE) { 1193 dma->resi = 0; 1194 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1195 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1196 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1197 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1198 } 1199 *resp = dma->resi++; 1200 dma->resk = dma->resi; 1201} 1202 1203static int 1204hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1205{ 1206 struct hifn_dma *dma = sc->sc_dma; 1207 hifn_base_command_t wc; 1208 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1209 int r, cmdi, resi, srci, dsti; 1210 1211 wc.masks = htole16(3 << 13); 1212 wc.session_num = htole16(addr >> 14); 1213 wc.total_source_count = htole16(8); 1214 wc.total_dest_count = htole16(addr & 0x3fff); 1215 1216 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1217 1218 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1219 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1220 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1221 1222 /* build write command */ 1223 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1224 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1225 bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1226 1227 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1228 + offsetof(struct hifn_dma, test_src)); 1229 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1230 + offsetof(struct hifn_dma, test_dst)); 1231 1232 dma->cmdr[cmdi].l = htole32(16 | masks); 1233 dma->srcr[srci].l = htole32(8 | masks); 1234 dma->dstr[dsti].l = htole32(4 | masks); 1235 dma->resr[resi].l = htole32(4 | masks); 1236 1237 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1238 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1239 1240 for (r = 10000; r >= 0; r--) { 1241 DELAY(10); 1242 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1243 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1244 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1245 break; 1246 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1247 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1248 } 1249 if (r == 0) { 1250 device_printf(sc->sc_dev, "writeramaddr -- " 1251 "result[%d](addr %d) still valid\n", resi, addr); 1252 r = -1; 1253 return (-1); 1254 } else 1255 r = 0; 1256 1257 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1258 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1259 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1260 1261 return (r); 1262} 1263 1264static int 1265hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1266{ 1267 struct hifn_dma *dma = sc->sc_dma; 1268 hifn_base_command_t rc; 1269 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1270 int r, cmdi, srci, dsti, resi; 1271 1272 rc.masks = htole16(2 << 13); 1273 rc.session_num = htole16(addr >> 14); 1274 rc.total_source_count = htole16(addr & 0x3fff); 1275 rc.total_dest_count = htole16(8); 1276 1277 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1278 1279 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1280 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1281 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1282 1283 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1284 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1285 1286 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1287 offsetof(struct hifn_dma, test_src)); 1288 dma->test_src = 0; 1289 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1290 offsetof(struct hifn_dma, test_dst)); 1291 dma->test_dst = 0; 1292 dma->cmdr[cmdi].l = htole32(8 | masks); 1293 dma->srcr[srci].l = htole32(8 | masks); 1294 dma->dstr[dsti].l = htole32(8 | masks); 1295 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1296 1297 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1298 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1299 1300 for (r = 10000; r >= 0; r--) { 1301 DELAY(10); 1302 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1303 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1304 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1305 break; 1306 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1307 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1308 } 1309 if (r == 0) { 1310 device_printf(sc->sc_dev, "readramaddr -- " 1311 "result[%d](addr %d) still valid\n", resi, addr); 1312 r = -1; 1313 } else { 1314 r = 0; 1315 bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1316 } 1317 1318 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1319 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1320 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1321 1322 return (r); 1323} 1324 1325/* 1326 * Initialize the descriptor rings. 1327 */ 1328static void 1329hifn_init_dma(struct hifn_softc *sc) 1330{ 1331 struct hifn_dma *dma = sc->sc_dma; 1332 int i; 1333 1334 hifn_set_retry(sc); 1335 1336 /* initialize static pointer values */ 1337 for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1338 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1339 offsetof(struct hifn_dma, command_bufs[i][0])); 1340 for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1341 dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1342 offsetof(struct hifn_dma, result_bufs[i][0])); 1343 1344 dma->cmdr[HIFN_D_CMD_RSIZE].p = 1345 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1346 dma->srcr[HIFN_D_SRC_RSIZE].p = 1347 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1348 dma->dstr[HIFN_D_DST_RSIZE].p = 1349 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1350 dma->resr[HIFN_D_RES_RSIZE].p = 1351 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1352 1353 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1354 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1355 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1356} 1357 1358/* 1359 * Writes out the raw command buffer space. Returns the 1360 * command buffer size. 1361 */ 1362static u_int 1363hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1364{ 1365#define MIN(a,b) ((a)<(b)?(a):(b)) 1366 u_int8_t *buf_pos; 1367 hifn_base_command_t *base_cmd; 1368 hifn_mac_command_t *mac_cmd; 1369 hifn_crypt_command_t *cry_cmd; 1370 int using_mac, using_crypt, len; 1371 u_int32_t dlen, slen; 1372 1373 buf_pos = buf; 1374 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1375 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1376 1377 base_cmd = (hifn_base_command_t *)buf_pos; 1378 base_cmd->masks = htole16(cmd->base_masks); 1379 slen = cmd->src_mapsize; 1380 if (cmd->sloplen) 1381 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1382 else 1383 dlen = cmd->dst_mapsize; 1384 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1385 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1386 dlen >>= 16; 1387 slen >>= 16; 1388 base_cmd->session_num = htole16(cmd->session_num | 1389 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1390 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1391 buf_pos += sizeof(hifn_base_command_t); 1392 1393 if (using_mac) { 1394 mac_cmd = (hifn_mac_command_t *)buf_pos; 1395 dlen = cmd->maccrd->crd_len; 1396 mac_cmd->source_count = htole16(dlen & 0xffff); 1397 dlen >>= 16; 1398 mac_cmd->masks = htole16(cmd->mac_masks | 1399 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1400 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1401 mac_cmd->reserved = 0; 1402 buf_pos += sizeof(hifn_mac_command_t); 1403 } 1404 1405 if (using_crypt) { 1406 cry_cmd = (hifn_crypt_command_t *)buf_pos; 1407 dlen = cmd->enccrd->crd_len; 1408 cry_cmd->source_count = htole16(dlen & 0xffff); 1409 dlen >>= 16; 1410 cry_cmd->masks = htole16(cmd->cry_masks | 1411 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1412 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1413 cry_cmd->reserved = 0; 1414 buf_pos += sizeof(hifn_crypt_command_t); 1415 } 1416 1417 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1418 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1419 buf_pos += HIFN_MAC_KEY_LENGTH; 1420 } 1421 1422 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1423 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1424 case HIFN_CRYPT_CMD_ALG_3DES: 1425 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1426 buf_pos += HIFN_3DES_KEY_LENGTH; 1427 break; 1428 case HIFN_CRYPT_CMD_ALG_DES: 1429 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1430 buf_pos += cmd->cklen; 1431 break; 1432 case HIFN_CRYPT_CMD_ALG_RC4: 1433 len = 256; 1434 do { 1435 int clen; 1436 1437 clen = MIN(cmd->cklen, len); 1438 bcopy(cmd->ck, buf_pos, clen); 1439 len -= clen; 1440 buf_pos += clen; 1441 } while (len > 0); 1442 bzero(buf_pos, 4); 1443 buf_pos += 4; 1444 break; 1445 } 1446 } 1447 1448 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1449 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1450 buf_pos += HIFN_IV_LENGTH; 1451 } 1452 1453 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1454 bzero(buf_pos, 8); 1455 buf_pos += 8; 1456 } 1457 1458 return (buf_pos - buf); 1459#undef MIN 1460} 1461 1462static int 1463hifn_dmamap_aligned(struct hifn_operand *op) 1464{ 1465 int i; 1466 1467 for (i = 0; i < op->nsegs; i++) { 1468 if (op->segs[i].ds_addr & 3) 1469 return (0); 1470 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1471 return (0); 1472 } 1473 return (1); 1474} 1475 1476static int 1477hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1478{ 1479 struct hifn_dma *dma = sc->sc_dma; 1480 struct hifn_operand *dst = &cmd->dst; 1481 u_int32_t p, l; 1482 int idx, used = 0, i; 1483 1484 idx = dma->dsti; 1485 for (i = 0; i < dst->nsegs - 1; i++) { 1486 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1487 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1488 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1489 HIFN_DSTR_SYNC(sc, idx, 1490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1491 used++; 1492 1493 if (++idx == HIFN_D_DST_RSIZE) { 1494 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1495 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1496 HIFN_DSTR_SYNC(sc, idx, 1497 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1498 idx = 0; 1499 } 1500 } 1501 1502 if (cmd->sloplen == 0) { 1503 p = dst->segs[i].ds_addr; 1504 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1505 dst->segs[i].ds_len; 1506 } else { 1507 p = sc->sc_dma_physaddr + 1508 offsetof(struct hifn_dma, slop[cmd->slopidx]); 1509 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1510 sizeof(u_int32_t); 1511 1512 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1513 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1514 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1515 HIFN_D_MASKDONEIRQ | 1516 (dst->segs[i].ds_len - cmd->sloplen)); 1517 HIFN_DSTR_SYNC(sc, idx, 1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1519 used++; 1520 1521 if (++idx == HIFN_D_DST_RSIZE) { 1522 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1523 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1524 HIFN_DSTR_SYNC(sc, idx, 1525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1526 idx = 0; 1527 } 1528 } 1529 } 1530 dma->dstr[idx].p = htole32(p); 1531 dma->dstr[idx].l = htole32(l); 1532 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1533 used++; 1534 1535 if (++idx == HIFN_D_DST_RSIZE) { 1536 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1537 HIFN_D_MASKDONEIRQ); 1538 HIFN_DSTR_SYNC(sc, idx, 1539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1540 idx = 0; 1541 } 1542 1543 dma->dsti = idx; 1544 dma->dstu += used; 1545 return (idx); 1546} 1547 1548static int 1549hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1550{ 1551 struct hifn_dma *dma = sc->sc_dma; 1552 struct hifn_operand *src = &cmd->src; 1553 int idx, i; 1554 u_int32_t last = 0; 1555 1556 idx = dma->srci; 1557 for (i = 0; i < src->nsegs; i++) { 1558 if (i == src->nsegs - 1) 1559 last = HIFN_D_LAST; 1560 1561 dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1562 dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1563 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1564 HIFN_SRCR_SYNC(sc, idx, 1565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1566 1567 if (++idx == HIFN_D_SRC_RSIZE) { 1568 dma->srcr[idx].l = htole32(HIFN_D_VALID | 1569 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1570 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1572 idx = 0; 1573 } 1574 } 1575 dma->srci = idx; 1576 dma->srcu += src->nsegs; 1577 return (idx); 1578} 1579 1580static void 1581hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1582{ 1583 struct hifn_operand *op = arg; 1584 1585 KASSERT(nsegs <= MAX_SCATTER, 1586 ("hifn_op_cb: too many DMA segments (%u > %u) " 1587 "returned when mapping operand", nsegs, MAX_SCATTER)); 1588 op->mapsize = mapsize; 1589 op->nsegs = nsegs; 1590 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1591} 1592 1593static int 1594hifn_crypto( 1595 struct hifn_softc *sc, 1596 struct hifn_command *cmd, 1597 struct cryptop *crp, 1598 int hint) 1599{ 1600 struct hifn_dma *dma = sc->sc_dma; 1601 u_int32_t cmdlen; 1602 int cmdi, resi, err = 0; 1603 1604 /* 1605 * need 1 cmd, and 1 res 1606 * 1607 * NB: check this first since it's easy. 1608 */ 1609 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1610 (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1611#ifdef HIFN_DEBUG 1612 if (hifn_debug) { 1613 device_printf(sc->sc_dev, 1614 "cmd/result exhaustion, cmdu %u resu %u\n", 1615 dma->cmdu, dma->resu); 1616 } 1617#endif 1618 hifnstats.hst_nomem_cr++; 1619 return (ERESTART); 1620 } 1621 1622 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1623 hifnstats.hst_nomem_map++; 1624 return (ENOMEM); 1625 } 1626 1627 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1628 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1629 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1630 hifnstats.hst_nomem_load++; 1631 err = ENOMEM; 1632 goto err_srcmap1; 1633 } 1634 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1635 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1636 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1637 hifnstats.hst_nomem_load++; 1638 err = ENOMEM; 1639 goto err_srcmap1; 1640 } 1641 } else { 1642 err = EINVAL; 1643 goto err_srcmap1; 1644 } 1645 1646 if (hifn_dmamap_aligned(&cmd->src)) { 1647 cmd->sloplen = cmd->src_mapsize & 3; 1648 cmd->dst = cmd->src; 1649 } else { 1650 if (crp->crp_flags & CRYPTO_F_IOV) { 1651 err = EINVAL; 1652 goto err_srcmap; 1653 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1654 int totlen, len; 1655 struct mbuf *m, *m0, *mlast; 1656 1657 KASSERT(cmd->dst_m == cmd->src_m, 1658 ("hifn_crypto: dst_m initialized improperly")); 1659 hifnstats.hst_unaligned++; 1660 /* 1661 * Source is not aligned on a longword boundary. 1662 * Copy the data to insure alignment. If we fail 1663 * to allocate mbufs or clusters while doing this 1664 * we return ERESTART so the operation is requeued 1665 * at the crypto later, but only if there are 1666 * ops already posted to the hardware; otherwise we 1667 * have no guarantee that we'll be re-entered. 1668 */ 1669 totlen = cmd->src_mapsize; 1670 if (cmd->src_m->m_flags & M_PKTHDR) { 1671 len = MHLEN; 1672 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1673 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1674 m_free(m0); 1675 m0 = NULL; 1676 } 1677 } else { 1678 len = MLEN; 1679 MGET(m0, M_DONTWAIT, MT_DATA); 1680 } 1681 if (m0 == NULL) { 1682 hifnstats.hst_nomem_mbuf++; 1683 err = dma->cmdu ? ERESTART : ENOMEM; 1684 goto err_srcmap; 1685 } 1686 if (totlen >= MINCLSIZE) { 1687 MCLGET(m0, M_DONTWAIT); 1688 if ((m0->m_flags & M_EXT) == 0) { 1689 hifnstats.hst_nomem_mcl++; 1690 err = dma->cmdu ? ERESTART : ENOMEM; 1691 m_freem(m0); 1692 goto err_srcmap; 1693 } 1694 len = MCLBYTES; 1695 } 1696 totlen -= len; 1697 m0->m_pkthdr.len = m0->m_len = len; 1698 mlast = m0; 1699 1700 while (totlen > 0) { 1701 MGET(m, M_DONTWAIT, MT_DATA); 1702 if (m == NULL) { 1703 hifnstats.hst_nomem_mbuf++; 1704 err = dma->cmdu ? ERESTART : ENOMEM; 1705 m_freem(m0); 1706 goto err_srcmap; 1707 } 1708 len = MLEN; 1709 if (totlen >= MINCLSIZE) { 1710 MCLGET(m, M_DONTWAIT); 1711 if ((m->m_flags & M_EXT) == 0) { 1712 hifnstats.hst_nomem_mcl++; 1713 err = dma->cmdu ? ERESTART : ENOMEM; 1714 mlast->m_next = m; 1715 m_freem(m0); 1716 goto err_srcmap; 1717 } 1718 len = MCLBYTES; 1719 } 1720 1721 m->m_len = len; 1722 m0->m_pkthdr.len += len; 1723 totlen -= len; 1724 1725 mlast->m_next = m; 1726 mlast = m; 1727 } 1728 cmd->dst_m = m0; 1729 } 1730 } 1731 1732 if (cmd->dst_map == NULL) { 1733 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1734 hifnstats.hst_nomem_map++; 1735 err = ENOMEM; 1736 goto err_srcmap; 1737 } 1738 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1739 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1740 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1741 hifnstats.hst_nomem_map++; 1742 err = ENOMEM; 1743 goto err_dstmap1; 1744 } 1745 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1746 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1747 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1748 hifnstats.hst_nomem_load++; 1749 err = ENOMEM; 1750 goto err_dstmap1; 1751 } 1752 } 1753 } 1754 1755#ifdef HIFN_DEBUG 1756 if (hifn_debug) { 1757 device_printf(sc->sc_dev, 1758 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1759 READ_REG_1(sc, HIFN_1_DMA_CSR), 1760 READ_REG_1(sc, HIFN_1_DMA_IER), 1761 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1762 cmd->src_nsegs, cmd->dst_nsegs); 1763 } 1764#endif 1765 1766 if (cmd->src_map == cmd->dst_map) { 1767 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1768 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1769 } else { 1770 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1771 BUS_DMASYNC_PREWRITE); 1772 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1773 BUS_DMASYNC_PREREAD); 1774 } 1775 1776 /* 1777 * need N src, and N dst 1778 */ 1779 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1780 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1781#ifdef HIFN_DEBUG 1782 if (hifn_debug) { 1783 device_printf(sc->sc_dev, 1784 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1785 dma->srcu, cmd->src_nsegs, 1786 dma->dstu, cmd->dst_nsegs); 1787 } 1788#endif 1789 hifnstats.hst_nomem_sd++; 1790 err = ERESTART; 1791 goto err_dstmap; 1792 } 1793 1794 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1795 dma->cmdi = 0; 1796 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1797 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1798 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1800 } 1801 cmdi = dma->cmdi++; 1802 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1803 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1804 1805 /* .p for command/result already set */ 1806 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1807 HIFN_D_MASKDONEIRQ); 1808 HIFN_CMDR_SYNC(sc, cmdi, 1809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1810 dma->cmdu++; 1811 if (sc->sc_c_busy == 0) { 1812 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1813 sc->sc_c_busy = 1; 1814 } 1815 1816 /* 1817 * We don't worry about missing an interrupt (which a "command wait" 1818 * interrupt salvages us from), unless there is more than one command 1819 * in the queue. 1820 */ 1821 if (dma->cmdu > 1) { 1822 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1823 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1824 } 1825 1826 hifnstats.hst_ipackets++; 1827 hifnstats.hst_ibytes += cmd->src_mapsize; 1828 1829 hifn_dmamap_load_src(sc, cmd); 1830 if (sc->sc_s_busy == 0) { 1831 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1832 sc->sc_s_busy = 1; 1833 } 1834 1835 /* 1836 * Unlike other descriptors, we don't mask done interrupt from 1837 * result descriptor. 1838 */ 1839#ifdef HIFN_DEBUG 1840 if (hifn_debug) 1841 printf("load res\n"); 1842#endif 1843 if (dma->resi == HIFN_D_RES_RSIZE) { 1844 dma->resi = 0; 1845 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1846 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1847 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1848 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1849 } 1850 resi = dma->resi++; 1851 KASSERT(dma->hifn_commands[resi] == NULL, 1852 ("hifn_crypto: command slot %u busy", resi)); 1853 dma->hifn_commands[resi] = cmd; 1854 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1855 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1856 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1857 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1858 sc->sc_curbatch++; 1859 if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1860 hifnstats.hst_maxbatch = sc->sc_curbatch; 1861 hifnstats.hst_totbatch++; 1862 } else { 1863 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1864 HIFN_D_VALID | HIFN_D_LAST); 1865 sc->sc_curbatch = 0; 1866 } 1867 HIFN_RESR_SYNC(sc, resi, 1868 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1869 dma->resu++; 1870 if (sc->sc_r_busy == 0) { 1871 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1872 sc->sc_r_busy = 1; 1873 } 1874 1875 if (cmd->sloplen) 1876 cmd->slopidx = resi; 1877 1878 hifn_dmamap_load_dst(sc, cmd); 1879 1880 if (sc->sc_d_busy == 0) { 1881 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1882 sc->sc_d_busy = 1; 1883 } 1884 1885#ifdef HIFN_DEBUG 1886 if (hifn_debug) { 1887 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1888 READ_REG_1(sc, HIFN_1_DMA_CSR), 1889 READ_REG_1(sc, HIFN_1_DMA_IER)); 1890 } 1891#endif 1892 1893 sc->sc_active = 5; 1894 KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1895 return (err); /* success */ 1896 1897err_dstmap: 1898 if (cmd->src_map != cmd->dst_map) 1899 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1900err_dstmap1: 1901 if (cmd->src_map != cmd->dst_map) 1902 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1903err_srcmap: 1904 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1905 if (cmd->src_m != cmd->dst_m) 1906 m_freem(cmd->dst_m); 1907 } 1908 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1909err_srcmap1: 1910 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1911 return (err); 1912} 1913 1914static void 1915hifn_tick(void* vsc) 1916{ 1917 struct hifn_softc *sc = vsc; 1918 1919 HIFN_LOCK(sc); 1920 if (sc->sc_active == 0) { 1921 struct hifn_dma *dma = sc->sc_dma; 1922 u_int32_t r = 0; 1923 1924 if (dma->cmdu == 0 && sc->sc_c_busy) { 1925 sc->sc_c_busy = 0; 1926 r |= HIFN_DMACSR_C_CTRL_DIS; 1927 } 1928 if (dma->srcu == 0 && sc->sc_s_busy) { 1929 sc->sc_s_busy = 0; 1930 r |= HIFN_DMACSR_S_CTRL_DIS; 1931 } 1932 if (dma->dstu == 0 && sc->sc_d_busy) { 1933 sc->sc_d_busy = 0; 1934 r |= HIFN_DMACSR_D_CTRL_DIS; 1935 } 1936 if (dma->resu == 0 && sc->sc_r_busy) { 1937 sc->sc_r_busy = 0; 1938 r |= HIFN_DMACSR_R_CTRL_DIS; 1939 } 1940 if (r) 1941 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1942 } else 1943 sc->sc_active--; 1944 HIFN_UNLOCK(sc); 1945 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1946} 1947 1948static void 1949hifn_intr(void *arg) 1950{ 1951 struct hifn_softc *sc = arg; 1952 struct hifn_dma *dma; 1953 u_int32_t dmacsr, restart; 1954 int i, u; 1955 1956 HIFN_LOCK(sc); 1957 dma = sc->sc_dma; 1958 1959 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1960 1961#ifdef HIFN_DEBUG 1962 if (hifn_debug) { 1963 device_printf(sc->sc_dev, 1964 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 1965 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 1966 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1967 dma->cmdk, dma->srck, dma->dstk, dma->resk, 1968 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 1969 } 1970#endif 1971 1972 /* Nothing in the DMA unit interrupted */ 1973 if ((dmacsr & sc->sc_dmaier) == 0) { 1974 hifnstats.hst_noirq++; 1975 HIFN_UNLOCK(sc); 1976 return; 1977 } 1978 1979 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 1980 1981 if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 1982 (dmacsr & HIFN_DMACSR_PUBDONE)) 1983 WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 1984 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 1985 1986 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 1987 if (restart) 1988 device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 1989 1990 if (sc->sc_flags & HIFN_IS_7811) { 1991 if (dmacsr & HIFN_DMACSR_ILLR) 1992 device_printf(sc->sc_dev, "illegal read\n"); 1993 if (dmacsr & HIFN_DMACSR_ILLW) 1994 device_printf(sc->sc_dev, "illegal write\n"); 1995 } 1996 1997 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 1998 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 1999 if (restart) { 2000 device_printf(sc->sc_dev, "abort, resetting.\n"); 2001 hifnstats.hst_abort++; 2002 hifn_abort(sc); 2003 HIFN_UNLOCK(sc); 2004 return; 2005 } 2006 2007 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2008 /* 2009 * If no slots to process and we receive a "waiting on 2010 * command" interrupt, we disable the "waiting on command" 2011 * (by clearing it). 2012 */ 2013 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2014 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2015 } 2016 2017 /* clear the rings */ 2018 i = dma->resk; u = dma->resu; 2019 while (u != 0) { 2020 HIFN_RESR_SYNC(sc, i, 2021 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2022 if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2023 HIFN_RESR_SYNC(sc, i, 2024 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2025 break; 2026 } 2027 2028 if (i != HIFN_D_RES_RSIZE) { 2029 struct hifn_command *cmd; 2030 u_int8_t *macbuf = NULL; 2031 2032 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2033 cmd = dma->hifn_commands[i]; 2034 KASSERT(cmd != NULL, 2035 ("hifn_intr: null command slot %u", i)); 2036 dma->hifn_commands[i] = NULL; 2037 2038 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2039 macbuf = dma->result_bufs[i]; 2040 macbuf += 12; 2041 } 2042 2043 hifn_callback(sc, cmd, macbuf); 2044 hifnstats.hst_opackets++; 2045 u--; 2046 } 2047 2048 if (++i == (HIFN_D_RES_RSIZE + 1)) 2049 i = 0; 2050 } 2051 dma->resk = i; dma->resu = u; 2052 2053 i = dma->srck; u = dma->srcu; 2054 while (u != 0) { 2055 if (i == HIFN_D_SRC_RSIZE) 2056 i = 0; 2057 HIFN_SRCR_SYNC(sc, i, 2058 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2059 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2060 HIFN_SRCR_SYNC(sc, i, 2061 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2062 break; 2063 } 2064 i++, u--; 2065 } 2066 dma->srck = i; dma->srcu = u; 2067 2068 i = dma->cmdk; u = dma->cmdu; 2069 while (u != 0) { 2070 HIFN_CMDR_SYNC(sc, i, 2071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2072 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2073 HIFN_CMDR_SYNC(sc, i, 2074 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2075 break; 2076 } 2077 if (i != HIFN_D_CMD_RSIZE) { 2078 u--; 2079 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2080 } 2081 if (++i == (HIFN_D_CMD_RSIZE + 1)) 2082 i = 0; 2083 } 2084 dma->cmdk = i; dma->cmdu = u; 2085 2086 if (sc->sc_needwakeup) { /* XXX check high watermark */ 2087 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2088#ifdef HIFN_DEBUG 2089 if (hifn_debug) 2090 device_printf(sc->sc_dev, 2091 "wakeup crypto (%x) u %d/%d/%d/%d\n", 2092 sc->sc_needwakeup, 2093 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2094#endif 2095 sc->sc_needwakeup &= ~wakeup; 2096 crypto_unblock(sc->sc_cid, wakeup); 2097 } 2098 HIFN_UNLOCK(sc); 2099} 2100 2101/* 2102 * Allocate a new 'session' and return an encoded session id. 'sidp' 2103 * contains our registration id, and should contain an encoded session 2104 * id on successful allocation. 2105 */ 2106static int 2107hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2108{ 2109 struct cryptoini *c; 2110 struct hifn_softc *sc = arg; 2111 int i, mac = 0, cry = 0; 2112 2113 KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2114 if (sidp == NULL || cri == NULL || sc == NULL) 2115 return (EINVAL); 2116 2117 for (i = 0; i < sc->sc_maxses; i++) 2118 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2119 break; 2120 if (i == sc->sc_maxses) 2121 return (ENOMEM); 2122 2123 for (c = cri; c != NULL; c = c->cri_next) { 2124 switch (c->cri_alg) { 2125 case CRYPTO_MD5: 2126 case CRYPTO_SHA1: 2127 case CRYPTO_MD5_HMAC: 2128 case CRYPTO_SHA1_HMAC: 2129 if (mac) 2130 return (EINVAL); 2131 mac = 1; 2132 break; 2133 case CRYPTO_DES_CBC: 2134 case CRYPTO_3DES_CBC: 2135 /* XXX this may read fewer, does it matter? */ 2136 read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2137 /*FALLTHROUGH*/ 2138 case CRYPTO_ARC4: 2139 if (cry) 2140 return (EINVAL); 2141 cry = 1; 2142 break; 2143 default: 2144 return (EINVAL); 2145 } 2146 } 2147 if (mac == 0 && cry == 0) 2148 return (EINVAL); 2149 2150 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2151 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2152 2153 return (0); 2154} 2155 2156/* 2157 * Deallocate a session. 2158 * XXX this routine should run a zero'd mac/encrypt key into context ram. 2159 * XXX to blow away any keys already stored there. 2160 */ 2161static int 2162hifn_freesession(void *arg, u_int64_t tid) 2163{ 2164 struct hifn_softc *sc = arg; 2165 int session; 2166 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 2167 2168 KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2169 if (sc == NULL) 2170 return (EINVAL); 2171 2172 session = HIFN_SESSION(sid); 2173 if (session >= sc->sc_maxses) 2174 return (EINVAL); 2175 2176 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2177 return (0); 2178} 2179 2180static int 2181hifn_process(void *arg, struct cryptop *crp, int hint) 2182{ 2183 struct hifn_softc *sc = arg; 2184 struct hifn_command *cmd = NULL; 2185 int session, err; 2186 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2187 2188 if (crp == NULL || crp->crp_callback == NULL) { 2189 hifnstats.hst_invalid++; 2190 return (EINVAL); 2191 } 2192 session = HIFN_SESSION(crp->crp_sid); 2193 2194 if (sc == NULL || session >= sc->sc_maxses) { 2195 err = EINVAL; 2196 goto errout; 2197 } 2198 2199 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2200 if (cmd == NULL) { 2201 hifnstats.hst_nomem++; 2202 err = ENOMEM; 2203 goto errout; 2204 } 2205 2206 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2207 cmd->src_m = (struct mbuf *)crp->crp_buf; 2208 cmd->dst_m = (struct mbuf *)crp->crp_buf; 2209 } else if (crp->crp_flags & CRYPTO_F_IOV) { 2210 cmd->src_io = (struct uio *)crp->crp_buf; 2211 cmd->dst_io = (struct uio *)crp->crp_buf; 2212 } else { 2213 err = EINVAL; 2214 goto errout; /* XXX we don't handle contiguous buffers! */ 2215 } 2216 2217 crd1 = crp->crp_desc; 2218 if (crd1 == NULL) { 2219 err = EINVAL; 2220 goto errout; 2221 } 2222 crd2 = crd1->crd_next; 2223 2224 if (crd2 == NULL) { 2225 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2226 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2227 crd1->crd_alg == CRYPTO_SHA1 || 2228 crd1->crd_alg == CRYPTO_MD5) { 2229 maccrd = crd1; 2230 enccrd = NULL; 2231 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2232 crd1->crd_alg == CRYPTO_3DES_CBC || 2233 crd1->crd_alg == CRYPTO_ARC4) { 2234 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2235 cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2236 maccrd = NULL; 2237 enccrd = crd1; 2238 } else { 2239 err = EINVAL; 2240 goto errout; 2241 } 2242 } else { 2243 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2244 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2245 crd1->crd_alg == CRYPTO_MD5 || 2246 crd1->crd_alg == CRYPTO_SHA1) && 2247 (crd2->crd_alg == CRYPTO_DES_CBC || 2248 crd2->crd_alg == CRYPTO_3DES_CBC || 2249 crd2->crd_alg == CRYPTO_ARC4) && 2250 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2251 cmd->base_masks = HIFN_BASE_CMD_DECODE; 2252 maccrd = crd1; 2253 enccrd = crd2; 2254 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2255 crd1->crd_alg == CRYPTO_ARC4 || 2256 crd1->crd_alg == CRYPTO_3DES_CBC) && 2257 (crd2->crd_alg == CRYPTO_MD5_HMAC || 2258 crd2->crd_alg == CRYPTO_SHA1_HMAC || 2259 crd2->crd_alg == CRYPTO_MD5 || 2260 crd2->crd_alg == CRYPTO_SHA1) && 2261 (crd1->crd_flags & CRD_F_ENCRYPT)) { 2262 enccrd = crd1; 2263 maccrd = crd2; 2264 } else { 2265 /* 2266 * We cannot order the 7751 as requested 2267 */ 2268 err = EINVAL; 2269 goto errout; 2270 } 2271 } 2272 2273 if (enccrd) { 2274 cmd->enccrd = enccrd; 2275 cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2276 switch (enccrd->crd_alg) { 2277 case CRYPTO_ARC4: 2278 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2279 if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2280 != sc->sc_sessions[session].hs_prev_op) 2281 sc->sc_sessions[session].hs_state = 2282 HS_STATE_USED; 2283 break; 2284 case CRYPTO_DES_CBC: 2285 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2286 HIFN_CRYPT_CMD_MODE_CBC | 2287 HIFN_CRYPT_CMD_NEW_IV; 2288 break; 2289 case CRYPTO_3DES_CBC: 2290 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2291 HIFN_CRYPT_CMD_MODE_CBC | 2292 HIFN_CRYPT_CMD_NEW_IV; 2293 break; 2294 default: 2295 err = EINVAL; 2296 goto errout; 2297 } 2298 if (enccrd->crd_alg != CRYPTO_ARC4) { 2299 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2300 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2301 bcopy(enccrd->crd_iv, cmd->iv, 2302 HIFN_IV_LENGTH); 2303 else 2304 bcopy(sc->sc_sessions[session].hs_iv, 2305 cmd->iv, HIFN_IV_LENGTH); 2306 2307 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2308 == 0) { 2309 if (crp->crp_flags & CRYPTO_F_IMBUF) 2310 m_copyback(cmd->src_m, 2311 enccrd->crd_inject, 2312 HIFN_IV_LENGTH, cmd->iv); 2313 else if (crp->crp_flags & CRYPTO_F_IOV) 2314 cuio_copyback(cmd->src_io, 2315 enccrd->crd_inject, 2316 HIFN_IV_LENGTH, cmd->iv); 2317 } 2318 } else { 2319 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2320 bcopy(enccrd->crd_iv, cmd->iv, 2321 HIFN_IV_LENGTH); 2322 else if (crp->crp_flags & CRYPTO_F_IMBUF) 2323 m_copydata(cmd->src_m, 2324 enccrd->crd_inject, 2325 HIFN_IV_LENGTH, cmd->iv); 2326 else if (crp->crp_flags & CRYPTO_F_IOV) 2327 cuio_copydata(cmd->src_io, 2328 enccrd->crd_inject, 2329 HIFN_IV_LENGTH, cmd->iv); 2330 } 2331 } 2332 2333 cmd->ck = enccrd->crd_key; 2334 cmd->cklen = enccrd->crd_klen >> 3; 2335 2336 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2337 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2338 } 2339 2340 if (maccrd) { 2341 cmd->maccrd = maccrd; 2342 cmd->base_masks |= HIFN_BASE_CMD_MAC; 2343 2344 switch (maccrd->crd_alg) { 2345 case CRYPTO_MD5: 2346 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2347 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2348 HIFN_MAC_CMD_POS_IPSEC; 2349 break; 2350 case CRYPTO_MD5_HMAC: 2351 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2352 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2353 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2354 break; 2355 case CRYPTO_SHA1: 2356 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2357 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2358 HIFN_MAC_CMD_POS_IPSEC; 2359 break; 2360 case CRYPTO_SHA1_HMAC: 2361 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2362 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2363 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2364 break; 2365 } 2366 2367 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2368 maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2369 sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2370 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2371 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2372 bzero(cmd->mac + (maccrd->crd_klen >> 3), 2373 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2374 } 2375 } 2376 2377 cmd->crp = crp; 2378 cmd->session_num = session; 2379 cmd->softc = sc; 2380 2381 err = hifn_crypto(sc, cmd, crp, hint); 2382 if (!err) { 2383 if (enccrd) 2384 sc->sc_sessions[session].hs_prev_op = 2385 enccrd->crd_flags & CRD_F_ENCRYPT; 2386 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2387 sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2388 return 0; 2389 } else if (err == ERESTART) { 2390 /* 2391 * There weren't enough resources to dispatch the request 2392 * to the part. Notify the caller so they'll requeue this 2393 * request and resubmit it again soon. 2394 */ 2395#ifdef HIFN_DEBUG 2396 if (hifn_debug) 2397 device_printf(sc->sc_dev, "requeue request\n"); 2398#endif 2399 free(cmd, M_DEVBUF); 2400 sc->sc_needwakeup |= CRYPTO_SYMQ; 2401 return (err); 2402 } 2403 2404errout: 2405 if (cmd != NULL) 2406 free(cmd, M_DEVBUF); 2407 if (err == EINVAL) 2408 hifnstats.hst_invalid++; 2409 else 2410 hifnstats.hst_nomem++; 2411 crp->crp_etype = err; 2412 crypto_done(crp); 2413 return (err); 2414} 2415 2416static void 2417hifn_abort(struct hifn_softc *sc) 2418{ 2419 struct hifn_dma *dma = sc->sc_dma; 2420 struct hifn_command *cmd; 2421 struct cryptop *crp; 2422 int i, u; 2423 2424 i = dma->resk; u = dma->resu; 2425 while (u != 0) { 2426 cmd = dma->hifn_commands[i]; 2427 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2428 dma->hifn_commands[i] = NULL; 2429 crp = cmd->crp; 2430 2431 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2432 /* Salvage what we can. */ 2433 u_int8_t *macbuf; 2434 2435 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2436 macbuf = dma->result_bufs[i]; 2437 macbuf += 12; 2438 } else 2439 macbuf = NULL; 2440 hifnstats.hst_opackets++; 2441 hifn_callback(sc, cmd, macbuf); 2442 } else { 2443 if (cmd->src_map == cmd->dst_map) { 2444 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2445 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2446 } else { 2447 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2448 BUS_DMASYNC_POSTWRITE); 2449 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2450 BUS_DMASYNC_POSTREAD); 2451 } 2452 2453 if (cmd->src_m != cmd->dst_m) { 2454 m_freem(cmd->src_m); 2455 crp->crp_buf = (caddr_t)cmd->dst_m; 2456 } 2457 2458 /* non-shared buffers cannot be restarted */ 2459 if (cmd->src_map != cmd->dst_map) { 2460 /* 2461 * XXX should be EAGAIN, delayed until 2462 * after the reset. 2463 */ 2464 crp->crp_etype = ENOMEM; 2465 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2466 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2467 } else 2468 crp->crp_etype = ENOMEM; 2469 2470 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2471 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2472 2473 free(cmd, M_DEVBUF); 2474 if (crp->crp_etype != EAGAIN) 2475 crypto_done(crp); 2476 } 2477 2478 if (++i == HIFN_D_RES_RSIZE) 2479 i = 0; 2480 u--; 2481 } 2482 dma->resk = i; dma->resu = u; 2483 2484 /* Force upload of key next time */ 2485 for (i = 0; i < sc->sc_maxses; i++) 2486 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2487 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2488 2489 hifn_reset_board(sc, 1); 2490 hifn_init_dma(sc); 2491 hifn_init_pci_registers(sc); 2492} 2493 2494static void 2495hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2496{ 2497 struct hifn_dma *dma = sc->sc_dma; 2498 struct cryptop *crp = cmd->crp; 2499 struct cryptodesc *crd; 2500 struct mbuf *m; 2501 int totlen, i, u; 2502 2503 if (cmd->src_map == cmd->dst_map) { 2504 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2505 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2506 } else { 2507 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2508 BUS_DMASYNC_POSTWRITE); 2509 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2510 BUS_DMASYNC_POSTREAD); 2511 } 2512 2513 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2514 if (cmd->src_m != cmd->dst_m) { 2515 crp->crp_buf = (caddr_t)cmd->dst_m; 2516 totlen = cmd->src_mapsize; 2517 for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2518 if (totlen < m->m_len) { 2519 m->m_len = totlen; 2520 totlen = 0; 2521 } else 2522 totlen -= m->m_len; 2523 } 2524 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2525 m_freem(cmd->src_m); 2526 } 2527 } 2528 2529 if (cmd->sloplen != 0) { 2530 if (crp->crp_flags & CRYPTO_F_IMBUF) 2531 m_copyback((struct mbuf *)crp->crp_buf, 2532 cmd->src_mapsize - cmd->sloplen, 2533 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2534 else if (crp->crp_flags & CRYPTO_F_IOV) 2535 cuio_copyback((struct uio *)crp->crp_buf, 2536 cmd->src_mapsize - cmd->sloplen, 2537 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2538 } 2539 2540 i = dma->dstk; u = dma->dstu; 2541 while (u != 0) { 2542 if (i == HIFN_D_DST_RSIZE) 2543 i = 0; 2544 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2546 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2547 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2548 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2549 break; 2550 } 2551 i++, u--; 2552 } 2553 dma->dstk = i; dma->dstu = u; 2554 2555 hifnstats.hst_obytes += cmd->dst_mapsize; 2556 2557 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2558 HIFN_BASE_CMD_CRYPT) { 2559 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2560 if (crd->crd_alg != CRYPTO_DES_CBC && 2561 crd->crd_alg != CRYPTO_3DES_CBC) 2562 continue; 2563 if (crp->crp_flags & CRYPTO_F_IMBUF) 2564 m_copydata((struct mbuf *)crp->crp_buf, 2565 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2566 HIFN_IV_LENGTH, 2567 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2568 else if (crp->crp_flags & CRYPTO_F_IOV) { 2569 cuio_copydata((struct uio *)crp->crp_buf, 2570 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2571 HIFN_IV_LENGTH, 2572 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2573 } 2574 break; 2575 } 2576 } 2577 2578 if (macbuf != NULL) { 2579 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2580 int len; 2581 2582 if (crd->crd_alg == CRYPTO_MD5) 2583 len = 16; 2584 else if (crd->crd_alg == CRYPTO_SHA1) 2585 len = 20; 2586 else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2587 crd->crd_alg == CRYPTO_SHA1_HMAC) 2588 len = 12; 2589 else 2590 continue; 2591 2592 if (crp->crp_flags & CRYPTO_F_IMBUF) 2593 m_copyback((struct mbuf *)crp->crp_buf, 2594 crd->crd_inject, len, macbuf); 2595 else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2596 bcopy((caddr_t)macbuf, crp->crp_mac, len); 2597 break; 2598 } 2599 } 2600 2601 if (cmd->src_map != cmd->dst_map) { 2602 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2603 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2604 } 2605 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2606 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2607 free(cmd, M_DEVBUF); 2608 crypto_done(crp); 2609} 2610 2611/* 2612 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2613 * and Group 1 registers; avoid conditions that could create 2614 * burst writes by doing a read in between the writes. 2615 * 2616 * NB: The read we interpose is always to the same register; 2617 * we do this because reading from an arbitrary (e.g. last) 2618 * register may not always work. 2619 */ 2620static void 2621hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2622{ 2623 if (sc->sc_flags & HIFN_IS_7811) { 2624 if (sc->sc_bar0_lastreg == reg - 4) 2625 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2626 sc->sc_bar0_lastreg = reg; 2627 } 2628 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2629} 2630 2631static void 2632hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2633{ 2634 if (sc->sc_flags & HIFN_IS_7811) { 2635 if (sc->sc_bar1_lastreg == reg - 4) 2636 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2637 sc->sc_bar1_lastreg = reg; 2638 } 2639 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2640} 2641