hifn7751.c revision 108466
1104477Ssam/* $FreeBSD: head/sys/dev/hifn/hifn7751.c 108466 2002-12-30 20:22:40Z sam $ */ 2104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 3104477Ssam 4104477Ssam/* 5104477Ssam * Invertex AEON / Hifn 7751 driver 6104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 7104477Ssam * Copyright (c) 1999 Theo de Raadt 8104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 9104477Ssam * http://www.netsec.net 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam * 42104477Ssam */ 43104477Ssam 44104477Ssam#define HIFN_DEBUG 45104477Ssam 46104477Ssam/* 47104477Ssam * Driver for the Hifn 7751 encryption processor. 48104477Ssam */ 49104477Ssam 50104477Ssam#include <sys/param.h> 51104477Ssam#include <sys/systm.h> 52104477Ssam#include <sys/proc.h> 53104477Ssam#include <sys/errno.h> 54104477Ssam#include <sys/malloc.h> 55104477Ssam#include <sys/kernel.h> 56104477Ssam#include <sys/mbuf.h> 57104477Ssam#include <sys/lock.h> 58104477Ssam#include <sys/mutex.h> 59104477Ssam#include <sys/sysctl.h> 60104477Ssam 61104477Ssam#include <vm/vm.h> 62104477Ssam#include <vm/pmap.h> 63104477Ssam 64104477Ssam#include <machine/clock.h> 65104477Ssam#include <machine/bus.h> 66104477Ssam#include <machine/resource.h> 67104477Ssam#include <sys/bus.h> 68104477Ssam#include <sys/rman.h> 69104477Ssam 70104477Ssam#include <opencrypto/cryptodev.h> 71104477Ssam#include <sys/random.h> 72104477Ssam 73104477Ssam#include <pci/pcivar.h> 74104477Ssam#include <pci/pcireg.h> 75104477Ssam#include <dev/hifn/hifn7751reg.h> 76104477Ssam#include <dev/hifn/hifn7751var.h> 77104477Ssam 78104477Ssam/* 79104477Ssam * Prototypes and count for the pci_device structure 80104477Ssam */ 81104477Ssamstatic int hifn_probe(device_t); 82104477Ssamstatic int hifn_attach(device_t); 83104477Ssamstatic int hifn_detach(device_t); 84104477Ssamstatic int hifn_suspend(device_t); 85104477Ssamstatic int hifn_resume(device_t); 86104477Ssamstatic void hifn_shutdown(device_t); 87104477Ssam 88104477Ssamstatic device_method_t hifn_methods[] = { 89104477Ssam /* Device interface */ 90104477Ssam DEVMETHOD(device_probe, hifn_probe), 91104477Ssam DEVMETHOD(device_attach, hifn_attach), 92104477Ssam DEVMETHOD(device_detach, hifn_detach), 93104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 94104477Ssam DEVMETHOD(device_resume, hifn_resume), 95104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 96104477Ssam 97104477Ssam /* bus interface */ 98104477Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 99104477Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 100104477Ssam 101104477Ssam { 0, 0 } 102104477Ssam}; 103104477Ssamstatic driver_t hifn_driver = { 104104477Ssam "hifn", 105104477Ssam hifn_methods, 106104477Ssam sizeof (struct hifn_softc) 107104477Ssam}; 108104477Ssamstatic devclass_t hifn_devclass; 109104477Ssam 110104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 111105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 112104477Ssam 113104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 114104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 115104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 116104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 117104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 118104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 119104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 120104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 121104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 122104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 123104477Ssamstatic void hifn_sessions(struct hifn_softc *); 124104477Ssamstatic void hifn_intr(void *); 125104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 126104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 127104477Ssamstatic int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 128104477Ssamstatic int hifn_freesession(void *, u_int64_t); 129104477Ssamstatic int hifn_process(void *, struct cryptop *, int); 130104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 131104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 132104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 133104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 134104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 135104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 136104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 137104477Ssamstatic void hifn_rng(void *); 138104477Ssamstatic void hifn_tick(void *); 139104477Ssamstatic void hifn_abort(struct hifn_softc *); 140104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 141104477Ssam 142104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 143104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 144104477Ssam 145104477Ssamstatic __inline__ u_int32_t 146104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 147104477Ssam{ 148104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 149104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 150104477Ssam return (v); 151104477Ssam} 152104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 153104477Ssam 154104477Ssamstatic __inline__ u_int32_t 155104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 156104477Ssam{ 157104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 158104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 159104477Ssam return (v); 160104477Ssam} 161104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 162104477Ssam 163104477Ssam#ifdef HIFN_DEBUG 164104477Ssamstatic int hifn_debug = 0; 165104477SsamSYSCTL_INT(_debug, OID_AUTO, hifn, CTLFLAG_RW, &hifn_debug, 166104477Ssam 0, "Hifn driver debugging printfs"); 167104477Ssam#endif 168104477Ssam 169104477Ssamstatic struct hifn_stats hifnstats; 170104477SsamSYSCTL_STRUCT(_kern, OID_AUTO, hifn_stats, CTLFLAG_RD, &hifnstats, 171104477Ssam hifn_stats, "Hifn driver statistics"); 172104477Ssamstatic int hifn_maxbatch = 2; /* XXX tune based on part+sys speed */ 173104477SsamSYSCTL_INT(_kern, OID_AUTO, hifn_maxbatch, CTLFLAG_RW, &hifn_maxbatch, 174104477Ssam 0, "Hifn driver: max ops to batch w/o interrupt"); 175104477Ssam 176104477Ssam/* 177104477Ssam * Probe for a supported device. The PCI vendor and device 178104477Ssam * IDs are used to detect devices we know how to handle. 179104477Ssam */ 180104477Ssamstatic int 181104477Ssamhifn_probe(device_t dev) 182104477Ssam{ 183104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 184104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 185104477Ssam return (0); 186104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 187104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 188104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 189104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 190104477Ssam return (0); 191104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 192104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 193104477Ssam return (0); 194104477Ssam return (ENXIO); 195104477Ssam} 196104477Ssam 197104477Ssamstatic void 198104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 199104477Ssam{ 200104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 201104477Ssam *paddr = segs->ds_addr; 202104477Ssam} 203104477Ssam 204104477Ssamstatic const char* 205104477Ssamhifn_partname(struct hifn_softc *sc) 206104477Ssam{ 207104477Ssam /* XXX sprintf numbers when not decoded */ 208104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 209104477Ssam case PCI_VENDOR_HIFN: 210104477Ssam switch (pci_get_device(sc->sc_dev)) { 211104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 212104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 213104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 214104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 215104477Ssam } 216104477Ssam return "Hifn unknown-part"; 217104477Ssam case PCI_VENDOR_INVERTEX: 218104477Ssam switch (pci_get_device(sc->sc_dev)) { 219104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 220104477Ssam } 221104477Ssam return "Invertex unknown-part"; 222104477Ssam case PCI_VENDOR_NETSEC: 223104477Ssam switch (pci_get_device(sc->sc_dev)) { 224104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 225104477Ssam } 226104477Ssam return "NetSec unknown-part"; 227104477Ssam } 228104477Ssam return "Unknown-vendor unknown-part"; 229104477Ssam} 230104477Ssam 231104477Ssam/* 232104477Ssam * Attach an interface that successfully probed. 233104477Ssam */ 234104477Ssamstatic int 235104477Ssamhifn_attach(device_t dev) 236104477Ssam{ 237104477Ssam struct hifn_softc *sc = device_get_softc(dev); 238104477Ssam u_int32_t cmd; 239104477Ssam caddr_t kva; 240104477Ssam int rseg, rid; 241104477Ssam char rbase; 242104477Ssam u_int16_t ena, rev; 243104477Ssam 244104477Ssam KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 245104477Ssam bzero(sc, sizeof (*sc)); 246104477Ssam sc->sc_dev = dev; 247104477Ssam 248104477Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 249104477Ssam 250104477Ssam /* XXX handle power management */ 251104477Ssam 252104477Ssam /* 253104477Ssam * The 7951 has a random number generator and 254104477Ssam * public key support; note this. 255104477Ssam */ 256104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 257104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 258104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 259104477Ssam /* 260104477Ssam * The 7811 has a random number generator and 261104477Ssam * we also note it's identity 'cuz of some quirks. 262104477Ssam */ 263104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 264104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 265104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 266104477Ssam 267104477Ssam /* 268104477Ssam * Configure support for memory-mapped access to 269104477Ssam * registers and for DMA operations. 270104477Ssam */ 271104477Ssam#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 272104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 273104477Ssam cmd |= PCIM_ENA; 274104477Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 275104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 276104477Ssam if ((cmd & PCIM_ENA) != PCIM_ENA) { 277104477Ssam device_printf(dev, "failed to enable %s\n", 278104477Ssam (cmd & PCIM_ENA) == 0 ? 279104477Ssam "memory mapping & bus mastering" : 280104477Ssam (cmd & PCIM_CMD_MEMEN) == 0 ? 281104477Ssam "memory mapping" : "bus mastering"); 282104477Ssam goto fail_pci; 283104477Ssam } 284104477Ssam#undef PCIM_ENA 285104477Ssam 286104477Ssam /* 287104477Ssam * Setup PCI resources. Note that we record the bus 288104477Ssam * tag and handle for each register mapping, this is 289104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 290104477Ssam * and WRITE_REG_1 macros throughout the driver. 291104477Ssam */ 292104477Ssam rid = HIFN_BAR0; 293104477Ssam sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 294104477Ssam 0, ~0, 1, RF_ACTIVE); 295104477Ssam if (sc->sc_bar0res == NULL) { 296104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 297104477Ssam goto fail_pci; 298104477Ssam } 299104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 300104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 301104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 302104477Ssam 303104477Ssam rid = HIFN_BAR1; 304104477Ssam sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 305104477Ssam 0, ~0, 1, RF_ACTIVE); 306104477Ssam if (sc->sc_bar1res == NULL) { 307104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 308104477Ssam goto fail_io0; 309104477Ssam } 310104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 311104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 312104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 313104477Ssam 314104477Ssam hifn_set_retry(sc); 315104477Ssam 316104477Ssam /* 317104477Ssam * Setup the area where the Hifn DMA's descriptors 318104477Ssam * and associated data structures. 319104477Ssam */ 320104477Ssam if (bus_dma_tag_create(NULL, /* parent */ 321104477Ssam 1, 0, /* alignment,boundary */ 322104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 323104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 324104477Ssam NULL, NULL, /* filter, filterarg */ 325104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 326104477Ssam MAX_SCATTER, /* nsegments */ 327104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 328104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 329104477Ssam &sc->sc_dmat)) { 330104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 331104477Ssam goto fail_io1; 332104477Ssam } 333104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 334104477Ssam device_printf(dev, "cannot create dma map\n"); 335104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 336104477Ssam goto fail_io1; 337104477Ssam } 338104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 339104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 340104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 341104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 342104477Ssam goto fail_io1; 343104477Ssam } 344104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 345104477Ssam sizeof (*sc->sc_dma), 346104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 347104477Ssam BUS_DMA_NOWAIT)) { 348104477Ssam device_printf(dev, "cannot load dma map\n"); 349104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 350104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 351104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 352104477Ssam goto fail_io1; 353104477Ssam } 354104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 355104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 356104477Ssam 357104477Ssam KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 358104477Ssam KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 359104477Ssam KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 360104477Ssam KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 361104477Ssam 362104477Ssam /* 363104477Ssam * Reset the board and do the ``secret handshake'' 364104477Ssam * to enable the crypto support. Then complete the 365104477Ssam * initialization procedure by setting up the interrupt 366104477Ssam * and hooking in to the system crypto support so we'll 367104477Ssam * get used for system services like the crypto device, 368104477Ssam * IPsec, RNG device, etc. 369104477Ssam */ 370104477Ssam hifn_reset_board(sc, 0); 371104477Ssam 372104477Ssam if (hifn_enable_crypto(sc) != 0) { 373104477Ssam device_printf(dev, "crypto enabling failed\n"); 374104477Ssam goto fail_mem; 375104477Ssam } 376104477Ssam hifn_reset_puc(sc); 377104477Ssam 378104477Ssam hifn_init_dma(sc); 379104477Ssam hifn_init_pci_registers(sc); 380104477Ssam 381104477Ssam if (hifn_ramtype(sc)) 382104477Ssam goto fail_mem; 383104477Ssam 384104477Ssam if (sc->sc_drammodel == 0) 385104477Ssam hifn_sramsize(sc); 386104477Ssam else 387104477Ssam hifn_dramsize(sc); 388104477Ssam 389104477Ssam /* 390104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 391104477Ssam * of the address lines were left floating 392104477Ssam */ 393104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 394104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 395104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 396104477Ssam sc->sc_ramsize >>= 1; 397104477Ssam 398104477Ssam /* 399104477Ssam * Arrange the interrupt line. 400104477Ssam */ 401104477Ssam rid = 0; 402104477Ssam sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 403104477Ssam 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 404104477Ssam if (sc->sc_irq == NULL) { 405104477Ssam device_printf(dev, "could not map interrupt\n"); 406104477Ssam goto fail_mem; 407104477Ssam } 408104477Ssam /* 409104477Ssam * NB: Network code assumes we are blocked with splimp() 410104477Ssam * so make sure the IRQ is marked appropriately. 411104477Ssam */ 412104477Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 413104477Ssam hifn_intr, sc, &sc->sc_intrhand)) { 414104477Ssam device_printf(dev, "could not setup interrupt\n"); 415104477Ssam goto fail_intr2; 416104477Ssam } 417104477Ssam 418104477Ssam hifn_sessions(sc); 419104477Ssam 420104477Ssam /* 421104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 422104477Ssam * from the 7951. 423104477Ssam */ 424104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 425104477Ssam 426104477Ssam rseg = sc->sc_ramsize / 1024; 427104477Ssam rbase = 'K'; 428104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 429104477Ssam rbase = 'M'; 430104477Ssam rseg /= 1024; 431104477Ssam } 432104477Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 433104477Ssam hifn_partname(sc), rev, 434104477Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's', 435104477Ssam sc->sc_maxses); 436104477Ssam 437104477Ssam sc->sc_cid = crypto_get_driverid(0); 438104477Ssam if (sc->sc_cid < 0) { 439104477Ssam device_printf(dev, "could not get crypto driver id\n"); 440104477Ssam goto fail_intr; 441104477Ssam } 442104477Ssam 443104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 444104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 445104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 446104477Ssam 447104477Ssam switch (ena) { 448104477Ssam case HIFN_PUSTAT_ENA_2: 449104477Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 450104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 451104477Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 452104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 453104477Ssam /*FALLTHROUGH*/ 454104477Ssam case HIFN_PUSTAT_ENA_1: 455104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 456104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 457104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 458104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 459104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 460104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 461104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 462104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 463104477Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 464104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 465104477Ssam break; 466104477Ssam } 467104477Ssam 468104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 469104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 470104477Ssam 471104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 472104477Ssam hifn_init_pubrng(sc); 473104477Ssam 474104918Ssam /* NB: 1 means the callout runs w/o Giant locked */ 475104918Ssam callout_init(&sc->sc_tickto, 1); 476104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 477104477Ssam 478104477Ssam return (0); 479104477Ssam 480104477Ssamfail_intr: 481104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 482104477Ssamfail_intr2: 483104477Ssam /* XXX don't store rid */ 484104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 485104477Ssamfail_mem: 486104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 487104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 488104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 489104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 490104477Ssam 491104477Ssam /* Turn off DMA polling */ 492104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 493104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 494104477Ssamfail_io1: 495104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 496104477Ssamfail_io0: 497104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 498104477Ssamfail_pci: 499104477Ssam mtx_destroy(&sc->sc_mtx); 500104477Ssam return (ENXIO); 501104477Ssam} 502104477Ssam 503104477Ssam/* 504104477Ssam * Detach an interface that successfully probed. 505104477Ssam */ 506104477Ssamstatic int 507104477Ssamhifn_detach(device_t dev) 508104477Ssam{ 509104477Ssam struct hifn_softc *sc = device_get_softc(dev); 510104477Ssam 511104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 512104477Ssam 513104477Ssam HIFN_LOCK(sc); 514104477Ssam 515104477Ssam /*XXX other resources */ 516104477Ssam callout_stop(&sc->sc_tickto); 517104477Ssam callout_stop(&sc->sc_rngto); 518104477Ssam 519104477Ssam /* Turn off DMA polling */ 520104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 521104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 522104477Ssam 523104477Ssam crypto_unregister_all(sc->sc_cid); 524104477Ssam 525104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 526104477Ssam 527104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 528104477Ssam /* XXX don't store rid */ 529104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 530104477Ssam 531104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 532104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 533104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 534104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 535104477Ssam 536104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 537104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 538104477Ssam 539104477Ssam HIFN_UNLOCK(sc); 540104477Ssam 541104477Ssam mtx_destroy(&sc->sc_mtx); 542104477Ssam 543104477Ssam return (0); 544104477Ssam} 545104477Ssam 546104477Ssam/* 547104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 548104477Ssam * get confused by errant DMAs when rebooting. 549104477Ssam */ 550104477Ssamstatic void 551104477Ssamhifn_shutdown(device_t dev) 552104477Ssam{ 553104477Ssam#ifdef notyet 554104477Ssam hifn_stop(device_get_softc(dev)); 555104477Ssam#endif 556104477Ssam} 557104477Ssam 558104477Ssam/* 559104477Ssam * Device suspend routine. Stop the interface and save some PCI 560104477Ssam * settings in case the BIOS doesn't restore them properly on 561104477Ssam * resume. 562104477Ssam */ 563104477Ssamstatic int 564104477Ssamhifn_suspend(device_t dev) 565104477Ssam{ 566104477Ssam struct hifn_softc *sc = device_get_softc(dev); 567104477Ssam#ifdef notyet 568104477Ssam int i; 569104477Ssam 570104477Ssam hifn_stop(sc); 571104477Ssam for (i = 0; i < 5; i++) 572104477Ssam sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 573104477Ssam sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 574104477Ssam sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 575104477Ssam sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 576104477Ssam sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 577104477Ssam#endif 578104477Ssam sc->sc_suspended = 1; 579104477Ssam 580104477Ssam return (0); 581104477Ssam} 582104477Ssam 583104477Ssam/* 584104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 585104477Ssam * doesn't, re-enable busmastering, and restart the interface if 586104477Ssam * appropriate. 587104477Ssam */ 588104477Ssamstatic int 589104477Ssamhifn_resume(device_t dev) 590104477Ssam{ 591104477Ssam struct hifn_softc *sc = device_get_softc(dev); 592104477Ssam#ifdef notyet 593104477Ssam int i; 594104477Ssam 595104477Ssam /* better way to do this? */ 596104477Ssam for (i = 0; i < 5; i++) 597104477Ssam pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 598104477Ssam pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 599104477Ssam pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 600104477Ssam pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 601104477Ssam pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 602104477Ssam 603104477Ssam /* reenable busmastering */ 604104477Ssam pci_enable_busmaster(dev); 605104477Ssam pci_enable_io(dev, HIFN_RES); 606104477Ssam 607104477Ssam /* reinitialize interface if necessary */ 608104477Ssam if (ifp->if_flags & IFF_UP) 609104477Ssam rl_init(sc); 610104477Ssam#endif 611104477Ssam sc->sc_suspended = 0; 612104477Ssam 613104477Ssam return (0); 614104477Ssam} 615104477Ssam 616104477Ssamstatic int 617104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 618104477Ssam{ 619104477Ssam u_int32_t r; 620104477Ssam int i; 621104477Ssam 622104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 623104477Ssam /* Reset 7951 public key/rng engine */ 624104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 625104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 626104477Ssam 627104477Ssam for (i = 0; i < 100; i++) { 628104477Ssam DELAY(1000); 629104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 630104477Ssam HIFN_PUBRST_RESET) == 0) 631104477Ssam break; 632104477Ssam } 633104477Ssam 634104477Ssam if (i == 100) { 635104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 636104477Ssam return (1); 637104477Ssam } 638104477Ssam } 639104477Ssam 640104477Ssam /* Enable the rng, if available */ 641104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 642104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 643104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 644104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 645104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 646104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 647104477Ssam } 648104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 649104477Ssam HIFN_7811_RNGCFG_DEFL); 650104477Ssam r |= HIFN_7811_RNGENA_ENA; 651104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 652104477Ssam } else 653104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 654104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 655104477Ssam HIFN_RNGCFG_ENA); 656104477Ssam 657104477Ssam sc->sc_rngfirst = 1; 658104477Ssam if (hz >= 100) 659104477Ssam sc->sc_rnghz = hz / 100; 660104477Ssam else 661104477Ssam sc->sc_rnghz = 1; 662105190Ssam /* NB: 1 means the callout runs w/o Giant locked */ 663105190Ssam callout_init(&sc->sc_rngto, 1); 664104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 665104477Ssam } 666104477Ssam 667104477Ssam /* Enable public key engine, if available */ 668104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 669104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 670104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 671104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 672104477Ssam } 673104477Ssam 674104477Ssam return (0); 675104477Ssam} 676104477Ssam 677104477Ssamstatic void 678104477Ssamhifn_rng(void *vsc) 679104477Ssam{ 680104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 681104477Ssam struct hifn_softc *sc = vsc; 682104477Ssam u_int32_t sts, num[2]; 683104477Ssam int i; 684104477Ssam 685104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 686104477Ssam for (i = 0; i < 5; i++) { 687104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 688104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 689104477Ssam device_printf(sc->sc_dev, 690104477Ssam "RNG underflow: disabling\n"); 691104477Ssam return; 692104477Ssam } 693104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 694104477Ssam break; 695104477Ssam 696104477Ssam /* 697104477Ssam * There are at least two words in the RNG FIFO 698104477Ssam * at this point. 699104477Ssam */ 700104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 701104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 702104477Ssam /* NB: discard first data read */ 703104477Ssam if (sc->sc_rngfirst) 704104477Ssam sc->sc_rngfirst = 0; 705104477Ssam else 706104477Ssam random_harvest(num, RANDOM_BITS(2), RANDOM_PURE); 707104477Ssam } 708104477Ssam } else { 709104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 710104477Ssam 711104477Ssam /* NB: discard first data read */ 712104477Ssam if (sc->sc_rngfirst) 713104477Ssam sc->sc_rngfirst = 0; 714104477Ssam else 715104477Ssam random_harvest(num, RANDOM_BITS(1), RANDOM_PURE); 716104477Ssam } 717104477Ssam 718104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 719104477Ssam#undef RANDOM_BITS 720104477Ssam} 721104477Ssam 722104477Ssamstatic void 723104477Ssamhifn_puc_wait(struct hifn_softc *sc) 724104477Ssam{ 725104477Ssam int i; 726104477Ssam 727104477Ssam for (i = 5000; i > 0; i--) { 728104477Ssam DELAY(1); 729104477Ssam if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 730104477Ssam break; 731104477Ssam } 732104477Ssam if (!i) 733104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 734104477Ssam} 735104477Ssam 736104477Ssam/* 737104477Ssam * Reset the processing unit. 738104477Ssam */ 739104477Ssamstatic void 740104477Ssamhifn_reset_puc(struct hifn_softc *sc) 741104477Ssam{ 742104477Ssam /* Reset processing unit */ 743104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 744104477Ssam hifn_puc_wait(sc); 745104477Ssam} 746104477Ssam 747104477Ssam/* 748104477Ssam * Set the Retry and TRDY registers; note that we set them to 749104477Ssam * zero because the 7811 locks up when forced to retry (section 750104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 751104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 752104477Ssam */ 753104477Ssamstatic void 754104477Ssamhifn_set_retry(struct hifn_softc *sc) 755104477Ssam{ 756104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 757104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 758104477Ssam pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 759104477Ssam} 760104477Ssam 761104477Ssam/* 762104477Ssam * Resets the board. Values in the regesters are left as is 763104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 764104477Ssam */ 765104477Ssamstatic void 766104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 767104477Ssam{ 768104477Ssam u_int32_t reg; 769104477Ssam 770104477Ssam /* 771104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 772104477Ssam * resetting the board and zeros out the other fields. 773104477Ssam */ 774104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 775104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 776104477Ssam 777104477Ssam /* 778104477Ssam * Now that polling has been disabled, we have to wait 1 ms 779104477Ssam * before resetting the board. 780104477Ssam */ 781104477Ssam DELAY(1000); 782104477Ssam 783104477Ssam /* Reset the DMA unit */ 784104477Ssam if (full) { 785104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 786104477Ssam DELAY(1000); 787104477Ssam } else { 788104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 789104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 790104477Ssam hifn_reset_puc(sc); 791104477Ssam } 792104477Ssam 793104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 794104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 795104477Ssam 796104477Ssam /* Bring dma unit out of reset */ 797104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 798104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 799104477Ssam 800104477Ssam hifn_puc_wait(sc); 801104477Ssam hifn_set_retry(sc); 802104477Ssam 803104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 804104477Ssam for (reg = 0; reg < 1000; reg++) { 805104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 806104477Ssam HIFN_MIPSRST_CRAMINIT) 807104477Ssam break; 808104477Ssam DELAY(1000); 809104477Ssam } 810104477Ssam if (reg == 1000) 811104477Ssam printf(": cram init timeout\n"); 812104477Ssam } 813104477Ssam} 814104477Ssam 815104477Ssamstatic u_int32_t 816104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 817104477Ssam{ 818104477Ssam int i; 819104477Ssam u_int32_t v; 820104477Ssam 821104477Ssam for (i = 0; i < cnt; i++) { 822104477Ssam 823104477Ssam /* get the parity */ 824104477Ssam v = a & 0x80080125; 825104477Ssam v ^= v >> 16; 826104477Ssam v ^= v >> 8; 827104477Ssam v ^= v >> 4; 828104477Ssam v ^= v >> 2; 829104477Ssam v ^= v >> 1; 830104477Ssam 831104477Ssam a = (v & 1) ^ (a << 1); 832104477Ssam } 833104477Ssam 834104477Ssam return a; 835104477Ssam} 836104477Ssam 837104477Ssamstruct pci2id { 838104477Ssam u_short pci_vendor; 839104477Ssam u_short pci_prod; 840104477Ssam char card_id[13]; 841104477Ssam}; 842104477Ssamstatic struct pci2id pci2id[] = { 843104477Ssam { 844104477Ssam PCI_VENDOR_HIFN, 845104477Ssam PCI_PRODUCT_HIFN_7951, 846104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 847104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 848104477Ssam }, { 849104477Ssam PCI_VENDOR_NETSEC, 850104477Ssam PCI_PRODUCT_NETSEC_7751, 851104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 852104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 853104477Ssam }, { 854104477Ssam PCI_VENDOR_INVERTEX, 855104477Ssam PCI_PRODUCT_INVERTEX_AEON, 856104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 857104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 858104477Ssam }, { 859104477Ssam PCI_VENDOR_HIFN, 860104477Ssam PCI_PRODUCT_HIFN_7811, 861104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 862104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 863104477Ssam }, { 864104477Ssam /* 865104477Ssam * Other vendors share this PCI ID as well, such as 866104477Ssam * http://www.powercrypt.com, and obviously they also 867104477Ssam * use the same key. 868104477Ssam */ 869104477Ssam PCI_VENDOR_HIFN, 870104477Ssam PCI_PRODUCT_HIFN_7751, 871104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 872104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 873104477Ssam }, 874104477Ssam}; 875104477Ssam 876104477Ssam/* 877104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 878104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 879104477Ssam * as enabling crypto twice will lock the board. 880104477Ssam */ 881104477Ssamstatic int 882104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 883104477Ssam{ 884104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 885104477Ssam char *offtbl = NULL; 886104477Ssam 887104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 888104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 889104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 890104477Ssam offtbl = pci2id[i].card_id; 891104477Ssam break; 892104477Ssam } 893104477Ssam } 894104477Ssam if (offtbl == NULL) { 895104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 896104477Ssam return (1); 897104477Ssam } 898104477Ssam 899104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 900104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 901104477Ssam 902104477Ssam /* 903104477Ssam * The RAM config register's encrypt level bit needs to be set before 904104477Ssam * every read performed on the encryption level register. 905104477Ssam */ 906104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 907104477Ssam 908104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 909104477Ssam 910104477Ssam /* 911104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 912104477Ssam * next reboot. 913104477Ssam */ 914104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 915104477Ssam#ifdef HIFN_DEBUG 916104477Ssam if (hifn_debug) 917104477Ssam device_printf(sc->sc_dev, 918104477Ssam "Strong crypto already enabled!\n"); 919104477Ssam#endif 920104477Ssam goto report; 921104477Ssam } 922104477Ssam 923104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 924104477Ssam#ifdef HIFN_DEBUG 925104477Ssam if (hifn_debug) 926104477Ssam device_printf(sc->sc_dev, 927104477Ssam "Unknown encryption level 0x%x\n", encl); 928104477Ssam#endif 929104477Ssam return 1; 930104477Ssam } 931104477Ssam 932104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 933104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 934104477Ssam DELAY(1000); 935104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 936104477Ssam DELAY(1000); 937104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 938104477Ssam DELAY(1000); 939104477Ssam 940104477Ssam for (i = 0; i <= 12; i++) { 941104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 942104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 943104477Ssam 944104477Ssam DELAY(1000); 945104477Ssam } 946104477Ssam 947104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 948104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 949104477Ssam 950104477Ssam#ifdef HIFN_DEBUG 951104477Ssam if (hifn_debug) { 952104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 953104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 954104477Ssam "locked until next system reset!\n"); 955104477Ssam else 956104477Ssam device_printf(sc->sc_dev, "Engine enabled " 957104477Ssam "successfully!\n"); 958104477Ssam } 959104477Ssam#endif 960104477Ssam 961104477Ssamreport: 962104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 963104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 964104477Ssam 965104477Ssam switch (encl) { 966104477Ssam case HIFN_PUSTAT_ENA_1: 967104477Ssam case HIFN_PUSTAT_ENA_2: 968104477Ssam break; 969104477Ssam case HIFN_PUSTAT_ENA_0: 970104477Ssam default: 971104477Ssam device_printf(sc->sc_dev, "disabled"); 972104477Ssam break; 973104477Ssam } 974104477Ssam 975104477Ssam return 0; 976104477Ssam} 977104477Ssam 978104477Ssam/* 979104477Ssam * Give initial values to the registers listed in the "Register Space" 980104477Ssam * section of the HIFN Software Development reference manual. 981104477Ssam */ 982104477Ssamstatic void 983104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 984104477Ssam{ 985104477Ssam /* write fixed values needed by the Initialization registers */ 986104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 987104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 988104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 989104477Ssam 990104477Ssam /* write all 4 ring address registers */ 991104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 992104477Ssam offsetof(struct hifn_dma, cmdr[0])); 993104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 994104477Ssam offsetof(struct hifn_dma, srcr[0])); 995104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 996104477Ssam offsetof(struct hifn_dma, dstr[0])); 997104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 998104477Ssam offsetof(struct hifn_dma, resr[0])); 999104477Ssam 1000104477Ssam DELAY(2000); 1001104477Ssam 1002104477Ssam /* write status register */ 1003104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1004104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1005104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1006104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1007104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1008104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1009104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1010104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1011104477Ssam HIFN_DMACSR_S_WAIT | 1012104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1013104477Ssam HIFN_DMACSR_C_WAIT | 1014104477Ssam HIFN_DMACSR_ENGINE | 1015104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1016104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1017104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1018104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1019104477Ssam 1020104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1021104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1022104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1023104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1024104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1025104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1026104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1027104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1028104477Ssam 1029104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1030104477Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1031104477Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1032104477Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1033104477Ssam 1034104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1035104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1036104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1037104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1038104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1039104477Ssam} 1040104477Ssam 1041104477Ssam/* 1042104477Ssam * The maximum number of sessions supported by the card 1043104477Ssam * is dependent on the amount of context ram, which 1044104477Ssam * encryption algorithms are enabled, and how compression 1045104477Ssam * is configured. This should be configured before this 1046104477Ssam * routine is called. 1047104477Ssam */ 1048104477Ssamstatic void 1049104477Ssamhifn_sessions(struct hifn_softc *sc) 1050104477Ssam{ 1051104477Ssam u_int32_t pucnfg; 1052104477Ssam int ctxsize; 1053104477Ssam 1054104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1055104477Ssam 1056104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1057104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1058104477Ssam ctxsize = 128; 1059104477Ssam else 1060104477Ssam ctxsize = 512; 1061104477Ssam sc->sc_maxses = 1 + 1062104477Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1063104477Ssam } else 1064104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1065104477Ssam 1066104477Ssam if (sc->sc_maxses > 2048) 1067104477Ssam sc->sc_maxses = 2048; 1068104477Ssam} 1069104477Ssam 1070104477Ssam/* 1071104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1072104477Ssam * state when this is called. 1073104477Ssam */ 1074104477Ssamstatic int 1075104477Ssamhifn_ramtype(struct hifn_softc *sc) 1076104477Ssam{ 1077104477Ssam u_int8_t data[8], dataexpect[8]; 1078104477Ssam int i; 1079104477Ssam 1080104477Ssam for (i = 0; i < sizeof(data); i++) 1081104477Ssam data[i] = dataexpect[i] = 0x55; 1082104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1083104477Ssam return (-1); 1084104477Ssam if (hifn_readramaddr(sc, 0, data)) 1085104477Ssam return (-1); 1086104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1087104477Ssam sc->sc_drammodel = 1; 1088104477Ssam return (0); 1089104477Ssam } 1090104477Ssam 1091104477Ssam for (i = 0; i < sizeof(data); i++) 1092104477Ssam data[i] = dataexpect[i] = 0xaa; 1093104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1094104477Ssam return (-1); 1095104477Ssam if (hifn_readramaddr(sc, 0, data)) 1096104477Ssam return (-1); 1097104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1098104477Ssam sc->sc_drammodel = 1; 1099104477Ssam return (0); 1100104477Ssam } 1101104477Ssam 1102104477Ssam return (0); 1103104477Ssam} 1104104477Ssam 1105104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1106104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1107104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1108104477Ssam 1109104477Ssamstatic int 1110104477Ssamhifn_sramsize(struct hifn_softc *sc) 1111104477Ssam{ 1112104477Ssam u_int32_t a; 1113104477Ssam u_int8_t data[8]; 1114104477Ssam u_int8_t dataexpect[sizeof(data)]; 1115104477Ssam int32_t i; 1116104477Ssam 1117104477Ssam for (i = 0; i < sizeof(data); i++) 1118104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1119104477Ssam 1120104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1121104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1122104477Ssam bcopy(&i, data, sizeof(i)); 1123104477Ssam hifn_writeramaddr(sc, a, data); 1124104477Ssam } 1125104477Ssam 1126104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1127104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1128104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1129104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1130104477Ssam return (0); 1131104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1132104477Ssam return (0); 1133104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1134104477Ssam } 1135104477Ssam 1136104477Ssam return (0); 1137104477Ssam} 1138104477Ssam 1139104477Ssam/* 1140104477Ssam * XXX For dram boards, one should really try all of the 1141104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1142104477Ssam * is already set up correctly. 1143104477Ssam */ 1144104477Ssamstatic int 1145104477Ssamhifn_dramsize(struct hifn_softc *sc) 1146104477Ssam{ 1147104477Ssam u_int32_t cnfg; 1148104477Ssam 1149104477Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1150104477Ssam HIFN_PUCNFG_DRAMMASK; 1151104477Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1152104477Ssam return (0); 1153104477Ssam} 1154104477Ssam 1155104477Ssamstatic void 1156104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1157104477Ssam{ 1158104477Ssam struct hifn_dma *dma = sc->sc_dma; 1159104477Ssam 1160104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1161104477Ssam dma->cmdi = 0; 1162104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1163104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1164104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1165104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1166104477Ssam } 1167104477Ssam *cmdp = dma->cmdi++; 1168104477Ssam dma->cmdk = dma->cmdi; 1169104477Ssam 1170104477Ssam if (dma->srci == HIFN_D_SRC_RSIZE) { 1171104477Ssam dma->srci = 0; 1172104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1173104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1174104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1175104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1176104477Ssam } 1177104477Ssam *srcp = dma->srci++; 1178104477Ssam dma->srck = dma->srci; 1179104477Ssam 1180104477Ssam if (dma->dsti == HIFN_D_DST_RSIZE) { 1181104477Ssam dma->dsti = 0; 1182104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1183104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1184104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1185104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1186104477Ssam } 1187104477Ssam *dstp = dma->dsti++; 1188104477Ssam dma->dstk = dma->dsti; 1189104477Ssam 1190104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1191104477Ssam dma->resi = 0; 1192104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1193104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1194104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1195104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1196104477Ssam } 1197104477Ssam *resp = dma->resi++; 1198104477Ssam dma->resk = dma->resi; 1199104477Ssam} 1200104477Ssam 1201104477Ssamstatic int 1202104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1203104477Ssam{ 1204104477Ssam struct hifn_dma *dma = sc->sc_dma; 1205104477Ssam hifn_base_command_t wc; 1206104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1207104477Ssam int r, cmdi, resi, srci, dsti; 1208104477Ssam 1209104477Ssam wc.masks = htole16(3 << 13); 1210104477Ssam wc.session_num = htole16(addr >> 14); 1211104477Ssam wc.total_source_count = htole16(8); 1212104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1213104477Ssam 1214104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1215104477Ssam 1216104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1217104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1218104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1219104477Ssam 1220104477Ssam /* build write command */ 1221104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1222104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1223104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1224104477Ssam 1225104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1226104477Ssam + offsetof(struct hifn_dma, test_src)); 1227104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1228104477Ssam + offsetof(struct hifn_dma, test_dst)); 1229104477Ssam 1230104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1231104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1232104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1233104477Ssam dma->resr[resi].l = htole32(4 | masks); 1234104477Ssam 1235104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1236104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1237104477Ssam 1238104477Ssam for (r = 10000; r >= 0; r--) { 1239104477Ssam DELAY(10); 1240104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1241104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1242104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1243104477Ssam break; 1244104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1245104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1246104477Ssam } 1247104477Ssam if (r == 0) { 1248104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1249104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1250104477Ssam r = -1; 1251104477Ssam return (-1); 1252104477Ssam } else 1253104477Ssam r = 0; 1254104477Ssam 1255104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1256104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1257104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1258104477Ssam 1259104477Ssam return (r); 1260104477Ssam} 1261104477Ssam 1262104477Ssamstatic int 1263104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1264104477Ssam{ 1265104477Ssam struct hifn_dma *dma = sc->sc_dma; 1266104477Ssam hifn_base_command_t rc; 1267104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1268104477Ssam int r, cmdi, srci, dsti, resi; 1269104477Ssam 1270104477Ssam rc.masks = htole16(2 << 13); 1271104477Ssam rc.session_num = htole16(addr >> 14); 1272104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1273104477Ssam rc.total_dest_count = htole16(8); 1274104477Ssam 1275104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1276104477Ssam 1277104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1278104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1279104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1280104477Ssam 1281104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1282104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1283104477Ssam 1284104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1285104477Ssam offsetof(struct hifn_dma, test_src)); 1286104477Ssam dma->test_src = 0; 1287104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1288104477Ssam offsetof(struct hifn_dma, test_dst)); 1289104477Ssam dma->test_dst = 0; 1290104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1291104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1292104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1293104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1294104477Ssam 1295104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1296104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1297104477Ssam 1298104477Ssam for (r = 10000; r >= 0; r--) { 1299104477Ssam DELAY(10); 1300104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1301104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1302104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1303104477Ssam break; 1304104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1305104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1306104477Ssam } 1307104477Ssam if (r == 0) { 1308104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1309104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1310104477Ssam r = -1; 1311104477Ssam } else { 1312104477Ssam r = 0; 1313104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1314104477Ssam } 1315104477Ssam 1316104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1317104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1318104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1319104477Ssam 1320104477Ssam return (r); 1321104477Ssam} 1322104477Ssam 1323104477Ssam/* 1324104477Ssam * Initialize the descriptor rings. 1325104477Ssam */ 1326104477Ssamstatic void 1327104477Ssamhifn_init_dma(struct hifn_softc *sc) 1328104477Ssam{ 1329104477Ssam struct hifn_dma *dma = sc->sc_dma; 1330104477Ssam int i; 1331104477Ssam 1332104477Ssam hifn_set_retry(sc); 1333104477Ssam 1334104477Ssam /* initialize static pointer values */ 1335104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1336104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1337104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1338104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1339104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1340104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1341104477Ssam 1342104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1343104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1344104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1345104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1346104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1347104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1348104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1349104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1350104477Ssam 1351104477Ssam dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1352104477Ssam dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1353104477Ssam dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1354104477Ssam} 1355104477Ssam 1356104477Ssam/* 1357104477Ssam * Writes out the raw command buffer space. Returns the 1358104477Ssam * command buffer size. 1359104477Ssam */ 1360104477Ssamstatic u_int 1361104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1362104477Ssam{ 1363104477Ssam#define MIN(a,b) ((a)<(b)?(a):(b)) 1364104477Ssam u_int8_t *buf_pos; 1365104477Ssam hifn_base_command_t *base_cmd; 1366104477Ssam hifn_mac_command_t *mac_cmd; 1367104477Ssam hifn_crypt_command_t *cry_cmd; 1368104477Ssam int using_mac, using_crypt, len; 1369104477Ssam u_int32_t dlen, slen; 1370104477Ssam 1371104477Ssam buf_pos = buf; 1372104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1373104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1374104477Ssam 1375104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1376104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1377104477Ssam slen = cmd->src_mapsize; 1378104477Ssam if (cmd->sloplen) 1379104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1380104477Ssam else 1381104477Ssam dlen = cmd->dst_mapsize; 1382104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1383104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1384104477Ssam dlen >>= 16; 1385104477Ssam slen >>= 16; 1386104477Ssam base_cmd->session_num = htole16(cmd->session_num | 1387104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1388104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1389104477Ssam buf_pos += sizeof(hifn_base_command_t); 1390104477Ssam 1391104477Ssam if (using_mac) { 1392104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1393104477Ssam dlen = cmd->maccrd->crd_len; 1394104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1395104477Ssam dlen >>= 16; 1396104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1397104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1398104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1399104477Ssam mac_cmd->reserved = 0; 1400104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1401104477Ssam } 1402104477Ssam 1403104477Ssam if (using_crypt) { 1404104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1405104477Ssam dlen = cmd->enccrd->crd_len; 1406104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1407104477Ssam dlen >>= 16; 1408104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1409104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1410104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1411104477Ssam cry_cmd->reserved = 0; 1412104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1413104477Ssam } 1414104477Ssam 1415104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1416104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1417104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1418104477Ssam } 1419104477Ssam 1420104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1421104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1422104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1423104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1424104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1425104477Ssam break; 1426104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1427104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1428104477Ssam buf_pos += cmd->cklen; 1429104477Ssam break; 1430104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1431104477Ssam len = 256; 1432104477Ssam do { 1433104477Ssam int clen; 1434104477Ssam 1435104477Ssam clen = MIN(cmd->cklen, len); 1436104477Ssam bcopy(cmd->ck, buf_pos, clen); 1437104477Ssam len -= clen; 1438104477Ssam buf_pos += clen; 1439104477Ssam } while (len > 0); 1440104477Ssam bzero(buf_pos, 4); 1441104477Ssam buf_pos += 4; 1442104477Ssam break; 1443104477Ssam } 1444104477Ssam } 1445104477Ssam 1446104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1447104477Ssam bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1448104477Ssam buf_pos += HIFN_IV_LENGTH; 1449104477Ssam } 1450104477Ssam 1451104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1452104477Ssam bzero(buf_pos, 8); 1453104477Ssam buf_pos += 8; 1454104477Ssam } 1455104477Ssam 1456104477Ssam return (buf_pos - buf); 1457104477Ssam#undef MIN 1458104477Ssam} 1459104477Ssam 1460104477Ssamstatic int 1461104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1462104477Ssam{ 1463104477Ssam int i; 1464104477Ssam 1465104477Ssam for (i = 0; i < op->nsegs; i++) { 1466104477Ssam if (op->segs[i].ds_addr & 3) 1467104477Ssam return (0); 1468104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1469104477Ssam return (0); 1470104477Ssam } 1471104477Ssam return (1); 1472104477Ssam} 1473104477Ssam 1474104477Ssamstatic int 1475104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1476104477Ssam{ 1477104477Ssam struct hifn_dma *dma = sc->sc_dma; 1478104477Ssam struct hifn_operand *dst = &cmd->dst; 1479104477Ssam u_int32_t p, l; 1480104477Ssam int idx, used = 0, i; 1481104477Ssam 1482104477Ssam idx = dma->dsti; 1483104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1484104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1485104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1486104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1487104477Ssam HIFN_DSTR_SYNC(sc, idx, 1488104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1489104477Ssam used++; 1490104477Ssam 1491104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1492104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1493104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1494104477Ssam HIFN_DSTR_SYNC(sc, idx, 1495104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1496104477Ssam idx = 0; 1497104477Ssam } 1498104477Ssam } 1499104477Ssam 1500104477Ssam if (cmd->sloplen == 0) { 1501104477Ssam p = dst->segs[i].ds_addr; 1502104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1503104477Ssam dst->segs[i].ds_len; 1504104477Ssam } else { 1505104477Ssam p = sc->sc_dma_physaddr + 1506104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1507104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1508104477Ssam sizeof(u_int32_t); 1509104477Ssam 1510104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1511104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1512104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1513104477Ssam HIFN_D_MASKDONEIRQ | 1514104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1515104477Ssam HIFN_DSTR_SYNC(sc, idx, 1516104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1517104477Ssam used++; 1518104477Ssam 1519104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1520104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1521104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1522104477Ssam HIFN_DSTR_SYNC(sc, idx, 1523104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1524104477Ssam idx = 0; 1525104477Ssam } 1526104477Ssam } 1527104477Ssam } 1528104477Ssam dma->dstr[idx].p = htole32(p); 1529104477Ssam dma->dstr[idx].l = htole32(l); 1530104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1531104477Ssam used++; 1532104477Ssam 1533104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1534104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1535104477Ssam HIFN_D_MASKDONEIRQ); 1536104477Ssam HIFN_DSTR_SYNC(sc, idx, 1537104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1538104477Ssam idx = 0; 1539104477Ssam } 1540104477Ssam 1541104477Ssam dma->dsti = idx; 1542104477Ssam dma->dstu += used; 1543104477Ssam return (idx); 1544104477Ssam} 1545104477Ssam 1546104477Ssamstatic int 1547104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1548104477Ssam{ 1549104477Ssam struct hifn_dma *dma = sc->sc_dma; 1550104477Ssam struct hifn_operand *src = &cmd->src; 1551104477Ssam int idx, i; 1552104477Ssam u_int32_t last = 0; 1553104477Ssam 1554104477Ssam idx = dma->srci; 1555104477Ssam for (i = 0; i < src->nsegs; i++) { 1556104477Ssam if (i == src->nsegs - 1) 1557104477Ssam last = HIFN_D_LAST; 1558104477Ssam 1559104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1560104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1561104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1562104477Ssam HIFN_SRCR_SYNC(sc, idx, 1563104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1564104477Ssam 1565104477Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1566104477Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1567104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1568104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1569104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1570104477Ssam idx = 0; 1571104477Ssam } 1572104477Ssam } 1573104477Ssam dma->srci = idx; 1574104477Ssam dma->srcu += src->nsegs; 1575104477Ssam return (idx); 1576104477Ssam} 1577104477Ssam 1578104477Ssamstatic void 1579104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1580104477Ssam{ 1581104477Ssam struct hifn_operand *op = arg; 1582104477Ssam 1583104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1584104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1585104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1586104477Ssam op->mapsize = mapsize; 1587104477Ssam op->nsegs = nsegs; 1588104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1589104477Ssam} 1590104477Ssam 1591104477Ssamstatic int 1592104477Ssamhifn_crypto( 1593104477Ssam struct hifn_softc *sc, 1594104477Ssam struct hifn_command *cmd, 1595104477Ssam struct cryptop *crp, 1596104477Ssam int hint) 1597104477Ssam{ 1598104477Ssam struct hifn_dma *dma = sc->sc_dma; 1599104477Ssam u_int32_t cmdlen; 1600104477Ssam int cmdi, resi, err = 0; 1601104477Ssam 1602104477Ssam /* 1603104477Ssam * need 1 cmd, and 1 res 1604104477Ssam * 1605104477Ssam * NB: check this first since it's easy. 1606104477Ssam */ 1607104477Ssam if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1608104477Ssam (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1609104477Ssam#ifdef HIFN_DEBUG 1610104477Ssam if (hifn_debug) { 1611104477Ssam device_printf(sc->sc_dev, 1612104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1613104477Ssam dma->cmdu, dma->resu); 1614104477Ssam } 1615104477Ssam#endif 1616104477Ssam hifnstats.hst_nomem_cr++; 1617104477Ssam return (ERESTART); 1618104477Ssam } 1619104477Ssam 1620104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1621104477Ssam hifnstats.hst_nomem_map++; 1622104477Ssam return (ENOMEM); 1623104477Ssam } 1624104477Ssam 1625104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1626104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1627104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1628104477Ssam hifnstats.hst_nomem_load++; 1629104477Ssam err = ENOMEM; 1630104477Ssam goto err_srcmap1; 1631104477Ssam } 1632104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1633104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1634104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1635104477Ssam hifnstats.hst_nomem_load++; 1636104477Ssam err = ENOMEM; 1637104477Ssam goto err_srcmap1; 1638104477Ssam } 1639104477Ssam } else { 1640104477Ssam err = EINVAL; 1641104477Ssam goto err_srcmap1; 1642104477Ssam } 1643104477Ssam 1644104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1645104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1646104477Ssam cmd->dst = cmd->src; 1647104477Ssam } else { 1648104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1649104477Ssam err = EINVAL; 1650104477Ssam goto err_srcmap; 1651104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1652104477Ssam int totlen, len; 1653104477Ssam struct mbuf *m, *m0, *mlast; 1654104477Ssam 1655104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1656104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1657104477Ssam hifnstats.hst_unaligned++; 1658104477Ssam /* 1659104477Ssam * Source is not aligned on a longword boundary. 1660104477Ssam * Copy the data to insure alignment. If we fail 1661104477Ssam * to allocate mbufs or clusters while doing this 1662104477Ssam * we return ERESTART so the operation is requeued 1663104477Ssam * at the crypto later, but only if there are 1664104477Ssam * ops already posted to the hardware; otherwise we 1665104477Ssam * have no guarantee that we'll be re-entered. 1666104477Ssam */ 1667104477Ssam totlen = cmd->src_mapsize; 1668104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1669104477Ssam len = MHLEN; 1670104477Ssam MGETHDR(m0, M_DONTWAIT, MT_DATA); 1671108466Ssam if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1672108466Ssam m_free(m0); 1673108466Ssam m0 = NULL; 1674108466Ssam } 1675104477Ssam } else { 1676104477Ssam len = MLEN; 1677104477Ssam MGET(m0, M_DONTWAIT, MT_DATA); 1678104477Ssam } 1679104477Ssam if (m0 == NULL) { 1680104477Ssam hifnstats.hst_nomem_mbuf++; 1681104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1682104477Ssam goto err_srcmap; 1683104477Ssam } 1684104477Ssam if (totlen >= MINCLSIZE) { 1685104477Ssam MCLGET(m0, M_DONTWAIT); 1686104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1687104477Ssam hifnstats.hst_nomem_mcl++; 1688104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1689104477Ssam m_freem(m0); 1690104477Ssam goto err_srcmap; 1691104477Ssam } 1692104477Ssam len = MCLBYTES; 1693104477Ssam } 1694104477Ssam totlen -= len; 1695104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1696104477Ssam mlast = m0; 1697104477Ssam 1698104477Ssam while (totlen > 0) { 1699104477Ssam MGET(m, M_DONTWAIT, MT_DATA); 1700104477Ssam if (m == NULL) { 1701104477Ssam hifnstats.hst_nomem_mbuf++; 1702104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1703104477Ssam m_freem(m0); 1704104477Ssam goto err_srcmap; 1705104477Ssam } 1706104477Ssam len = MLEN; 1707104477Ssam if (totlen >= MINCLSIZE) { 1708104477Ssam MCLGET(m, M_DONTWAIT); 1709104477Ssam if ((m->m_flags & M_EXT) == 0) { 1710104477Ssam hifnstats.hst_nomem_mcl++; 1711104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1712104477Ssam mlast->m_next = m; 1713104477Ssam m_freem(m0); 1714104477Ssam goto err_srcmap; 1715104477Ssam } 1716104477Ssam len = MCLBYTES; 1717104477Ssam } 1718104477Ssam 1719104477Ssam m->m_len = len; 1720104477Ssam m0->m_pkthdr.len += len; 1721104477Ssam totlen -= len; 1722104477Ssam 1723104477Ssam mlast->m_next = m; 1724104477Ssam mlast = m; 1725104477Ssam } 1726104477Ssam cmd->dst_m = m0; 1727104477Ssam } 1728104477Ssam } 1729104477Ssam 1730104477Ssam if (cmd->dst_map == NULL) { 1731104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1732104477Ssam hifnstats.hst_nomem_map++; 1733104477Ssam err = ENOMEM; 1734104477Ssam goto err_srcmap; 1735104477Ssam } 1736104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1737104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1738104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1739104477Ssam hifnstats.hst_nomem_map++; 1740104477Ssam err = ENOMEM; 1741104477Ssam goto err_dstmap1; 1742104477Ssam } 1743104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1744104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1745104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1746104477Ssam hifnstats.hst_nomem_load++; 1747104477Ssam err = ENOMEM; 1748104477Ssam goto err_dstmap1; 1749104477Ssam } 1750104477Ssam } 1751104477Ssam } 1752104477Ssam 1753104477Ssam#ifdef HIFN_DEBUG 1754104477Ssam if (hifn_debug) { 1755104477Ssam device_printf(sc->sc_dev, 1756104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1757104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1758104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1759104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1760104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1761104477Ssam } 1762104477Ssam#endif 1763104477Ssam 1764104477Ssam if (cmd->src_map == cmd->dst_map) { 1765104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1766104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1767104477Ssam } else { 1768104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1769104477Ssam BUS_DMASYNC_PREWRITE); 1770104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1771104477Ssam BUS_DMASYNC_PREREAD); 1772104477Ssam } 1773104477Ssam 1774104477Ssam /* 1775104477Ssam * need N src, and N dst 1776104477Ssam */ 1777104477Ssam if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1778104477Ssam (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1779104477Ssam#ifdef HIFN_DEBUG 1780104477Ssam if (hifn_debug) { 1781104477Ssam device_printf(sc->sc_dev, 1782104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1783104477Ssam dma->srcu, cmd->src_nsegs, 1784104477Ssam dma->dstu, cmd->dst_nsegs); 1785104477Ssam } 1786104477Ssam#endif 1787104477Ssam hifnstats.hst_nomem_sd++; 1788104477Ssam err = ERESTART; 1789104477Ssam goto err_dstmap; 1790104477Ssam } 1791104477Ssam 1792104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1793104477Ssam dma->cmdi = 0; 1794104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1795104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1796104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1797104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1798104477Ssam } 1799104477Ssam cmdi = dma->cmdi++; 1800104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1801104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1802104477Ssam 1803104477Ssam /* .p for command/result already set */ 1804104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1805104477Ssam HIFN_D_MASKDONEIRQ); 1806104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 1807104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1808104477Ssam dma->cmdu++; 1809104477Ssam if (sc->sc_c_busy == 0) { 1810104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1811104477Ssam sc->sc_c_busy = 1; 1812104477Ssam } 1813104477Ssam 1814104477Ssam /* 1815104477Ssam * We don't worry about missing an interrupt (which a "command wait" 1816104477Ssam * interrupt salvages us from), unless there is more than one command 1817104477Ssam * in the queue. 1818104477Ssam */ 1819104477Ssam if (dma->cmdu > 1) { 1820104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1821104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1822104477Ssam } 1823104477Ssam 1824104477Ssam hifnstats.hst_ipackets++; 1825104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 1826104477Ssam 1827104477Ssam hifn_dmamap_load_src(sc, cmd); 1828104477Ssam if (sc->sc_s_busy == 0) { 1829104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1830104477Ssam sc->sc_s_busy = 1; 1831104477Ssam } 1832104477Ssam 1833104477Ssam /* 1834104477Ssam * Unlike other descriptors, we don't mask done interrupt from 1835104477Ssam * result descriptor. 1836104477Ssam */ 1837104477Ssam#ifdef HIFN_DEBUG 1838104477Ssam if (hifn_debug) 1839104477Ssam printf("load res\n"); 1840104477Ssam#endif 1841104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1842104477Ssam dma->resi = 0; 1843104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1844104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1845104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1846104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1847104477Ssam } 1848104477Ssam resi = dma->resi++; 1849104477Ssam KASSERT(dma->hifn_commands[resi] == NULL, 1850104477Ssam ("hifn_crypto: command slot %u busy", resi)); 1851104477Ssam dma->hifn_commands[resi] = cmd; 1852104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1853104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1854104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1855104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1856104477Ssam sc->sc_curbatch++; 1857104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1858104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 1859104477Ssam hifnstats.hst_totbatch++; 1860104477Ssam } else { 1861104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1862104477Ssam HIFN_D_VALID | HIFN_D_LAST); 1863104477Ssam sc->sc_curbatch = 0; 1864104477Ssam } 1865104477Ssam HIFN_RESR_SYNC(sc, resi, 1866104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1867104477Ssam dma->resu++; 1868104477Ssam if (sc->sc_r_busy == 0) { 1869104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1870104477Ssam sc->sc_r_busy = 1; 1871104477Ssam } 1872104477Ssam 1873104477Ssam if (cmd->sloplen) 1874104477Ssam cmd->slopidx = resi; 1875104477Ssam 1876104477Ssam hifn_dmamap_load_dst(sc, cmd); 1877104477Ssam 1878104477Ssam if (sc->sc_d_busy == 0) { 1879104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1880104477Ssam sc->sc_d_busy = 1; 1881104477Ssam } 1882104477Ssam 1883104477Ssam#ifdef HIFN_DEBUG 1884104477Ssam if (hifn_debug) { 1885104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1886104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1887104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 1888104477Ssam } 1889104477Ssam#endif 1890104477Ssam 1891104477Ssam sc->sc_active = 5; 1892104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1893104477Ssam return (err); /* success */ 1894104477Ssam 1895104477Ssamerr_dstmap: 1896104477Ssam if (cmd->src_map != cmd->dst_map) 1897104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1898104477Ssamerr_dstmap1: 1899104477Ssam if (cmd->src_map != cmd->dst_map) 1900104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1901104477Ssamerr_srcmap: 1902104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1903104477Ssam if (cmd->src_m != cmd->dst_m) 1904104477Ssam m_freem(cmd->dst_m); 1905104477Ssam } 1906104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1907104477Ssamerr_srcmap1: 1908104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1909104477Ssam return (err); 1910104477Ssam} 1911104477Ssam 1912104477Ssamstatic void 1913104477Ssamhifn_tick(void* vsc) 1914104477Ssam{ 1915104477Ssam struct hifn_softc *sc = vsc; 1916104477Ssam 1917104477Ssam HIFN_LOCK(sc); 1918104477Ssam if (sc->sc_active == 0) { 1919104477Ssam struct hifn_dma *dma = sc->sc_dma; 1920104477Ssam u_int32_t r = 0; 1921104477Ssam 1922104477Ssam if (dma->cmdu == 0 && sc->sc_c_busy) { 1923104477Ssam sc->sc_c_busy = 0; 1924104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 1925104477Ssam } 1926104477Ssam if (dma->srcu == 0 && sc->sc_s_busy) { 1927104477Ssam sc->sc_s_busy = 0; 1928104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 1929104477Ssam } 1930104477Ssam if (dma->dstu == 0 && sc->sc_d_busy) { 1931104477Ssam sc->sc_d_busy = 0; 1932104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 1933104477Ssam } 1934104477Ssam if (dma->resu == 0 && sc->sc_r_busy) { 1935104477Ssam sc->sc_r_busy = 0; 1936104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 1937104477Ssam } 1938104477Ssam if (r) 1939104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1940104477Ssam } else 1941104477Ssam sc->sc_active--; 1942104477Ssam HIFN_UNLOCK(sc); 1943104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1944104477Ssam} 1945104477Ssam 1946104477Ssamstatic void 1947104477Ssamhifn_intr(void *arg) 1948104477Ssam{ 1949104477Ssam struct hifn_softc *sc = arg; 1950104477Ssam struct hifn_dma *dma; 1951104477Ssam u_int32_t dmacsr, restart; 1952104477Ssam int i, u; 1953104477Ssam 1954104477Ssam HIFN_LOCK(sc); 1955104477Ssam dma = sc->sc_dma; 1956104477Ssam 1957104477Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1958104477Ssam 1959104477Ssam#ifdef HIFN_DEBUG 1960104477Ssam if (hifn_debug) { 1961104477Ssam device_printf(sc->sc_dev, 1962104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 1963104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 1964104477Ssam dma->cmdi, dma->srci, dma->dsti, dma->resi, 1965104477Ssam dma->cmdk, dma->srck, dma->dstk, dma->resk, 1966104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 1967104477Ssam } 1968104477Ssam#endif 1969104477Ssam 1970104477Ssam /* Nothing in the DMA unit interrupted */ 1971104477Ssam if ((dmacsr & sc->sc_dmaier) == 0) { 1972104477Ssam hifnstats.hst_noirq++; 1973104477Ssam HIFN_UNLOCK(sc); 1974104477Ssam return; 1975104477Ssam } 1976104477Ssam 1977104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 1978104477Ssam 1979104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 1980104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 1981104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 1982104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 1983104477Ssam 1984104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 1985104477Ssam if (restart) 1986104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 1987104477Ssam 1988104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 1989104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 1990104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 1991104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 1992104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 1993104477Ssam } 1994104477Ssam 1995104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 1996104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 1997104477Ssam if (restart) { 1998104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 1999104477Ssam hifnstats.hst_abort++; 2000104477Ssam hifn_abort(sc); 2001104477Ssam HIFN_UNLOCK(sc); 2002104477Ssam return; 2003104477Ssam } 2004104477Ssam 2005104477Ssam if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2006104477Ssam /* 2007104477Ssam * If no slots to process and we receive a "waiting on 2008104477Ssam * command" interrupt, we disable the "waiting on command" 2009104477Ssam * (by clearing it). 2010104477Ssam */ 2011104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2012104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2013104477Ssam } 2014104477Ssam 2015104477Ssam /* clear the rings */ 2016104477Ssam i = dma->resk; u = dma->resu; 2017104477Ssam while (u != 0) { 2018104477Ssam HIFN_RESR_SYNC(sc, i, 2019104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2020104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2021104477Ssam HIFN_RESR_SYNC(sc, i, 2022104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2023104477Ssam break; 2024104477Ssam } 2025104477Ssam 2026104477Ssam if (i != HIFN_D_RES_RSIZE) { 2027104477Ssam struct hifn_command *cmd; 2028104477Ssam u_int8_t *macbuf = NULL; 2029104477Ssam 2030104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2031104477Ssam cmd = dma->hifn_commands[i]; 2032104477Ssam KASSERT(cmd != NULL, 2033104477Ssam ("hifn_intr: null command slot %u", i)); 2034104477Ssam dma->hifn_commands[i] = NULL; 2035104477Ssam 2036104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2037104477Ssam macbuf = dma->result_bufs[i]; 2038104477Ssam macbuf += 12; 2039104477Ssam } 2040104477Ssam 2041104477Ssam hifn_callback(sc, cmd, macbuf); 2042104477Ssam hifnstats.hst_opackets++; 2043104477Ssam u--; 2044104477Ssam } 2045104477Ssam 2046104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2047104477Ssam i = 0; 2048104477Ssam } 2049104477Ssam dma->resk = i; dma->resu = u; 2050104477Ssam 2051104477Ssam i = dma->srck; u = dma->srcu; 2052104477Ssam while (u != 0) { 2053104477Ssam if (i == HIFN_D_SRC_RSIZE) 2054104477Ssam i = 0; 2055104477Ssam HIFN_SRCR_SYNC(sc, i, 2056104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2057104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2058104477Ssam HIFN_SRCR_SYNC(sc, i, 2059104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2060104477Ssam break; 2061104477Ssam } 2062104477Ssam i++, u--; 2063104477Ssam } 2064104477Ssam dma->srck = i; dma->srcu = u; 2065104477Ssam 2066104477Ssam i = dma->cmdk; u = dma->cmdu; 2067104477Ssam while (u != 0) { 2068104477Ssam HIFN_CMDR_SYNC(sc, i, 2069104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2070104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2071104477Ssam HIFN_CMDR_SYNC(sc, i, 2072104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2073104477Ssam break; 2074104477Ssam } 2075104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2076104477Ssam u--; 2077104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2078104477Ssam } 2079104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2080104477Ssam i = 0; 2081104477Ssam } 2082104477Ssam dma->cmdk = i; dma->cmdu = u; 2083104477Ssam 2084104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2085104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2086104477Ssam#ifdef HIFN_DEBUG 2087104477Ssam if (hifn_debug) 2088104477Ssam device_printf(sc->sc_dev, 2089104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2090104477Ssam sc->sc_needwakeup, 2091104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2092104477Ssam#endif 2093104477Ssam sc->sc_needwakeup &= ~wakeup; 2094104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2095104477Ssam } 2096104477Ssam HIFN_UNLOCK(sc); 2097104477Ssam} 2098104477Ssam 2099104477Ssam/* 2100104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2101104477Ssam * contains our registration id, and should contain an encoded session 2102104477Ssam * id on successful allocation. 2103104477Ssam */ 2104104477Ssamstatic int 2105104477Ssamhifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2106104477Ssam{ 2107104477Ssam struct cryptoini *c; 2108104477Ssam struct hifn_softc *sc = arg; 2109104477Ssam int i, mac = 0, cry = 0; 2110104477Ssam 2111104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2112104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2113104477Ssam return (EINVAL); 2114104477Ssam 2115104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2116104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2117104477Ssam break; 2118104477Ssam if (i == sc->sc_maxses) 2119104477Ssam return (ENOMEM); 2120104477Ssam 2121104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2122104477Ssam switch (c->cri_alg) { 2123104477Ssam case CRYPTO_MD5: 2124104477Ssam case CRYPTO_SHA1: 2125104477Ssam case CRYPTO_MD5_HMAC: 2126104477Ssam case CRYPTO_SHA1_HMAC: 2127104477Ssam if (mac) 2128104477Ssam return (EINVAL); 2129104477Ssam mac = 1; 2130104477Ssam break; 2131104477Ssam case CRYPTO_DES_CBC: 2132104477Ssam case CRYPTO_3DES_CBC: 2133104477Ssam /* XXX this may read fewer, does it matter? */ 2134104477Ssam read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2135104477Ssam /*FALLTHROUGH*/ 2136104477Ssam case CRYPTO_ARC4: 2137104477Ssam if (cry) 2138104477Ssam return (EINVAL); 2139104477Ssam cry = 1; 2140104477Ssam break; 2141104477Ssam default: 2142104477Ssam return (EINVAL); 2143104477Ssam } 2144104477Ssam } 2145104477Ssam if (mac == 0 && cry == 0) 2146104477Ssam return (EINVAL); 2147104477Ssam 2148104477Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2149104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2150104477Ssam 2151104477Ssam return (0); 2152104477Ssam} 2153104477Ssam 2154104477Ssam/* 2155104477Ssam * Deallocate a session. 2156104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2157104477Ssam * XXX to blow away any keys already stored there. 2158104477Ssam */ 2159104477Ssamstatic int 2160104477Ssamhifn_freesession(void *arg, u_int64_t tid) 2161104477Ssam{ 2162104477Ssam struct hifn_softc *sc = arg; 2163104477Ssam int session; 2164104477Ssam u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 2165104477Ssam 2166104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2167104477Ssam if (sc == NULL) 2168104477Ssam return (EINVAL); 2169104477Ssam 2170104477Ssam session = HIFN_SESSION(sid); 2171104477Ssam if (session >= sc->sc_maxses) 2172104477Ssam return (EINVAL); 2173104477Ssam 2174104477Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2175104477Ssam return (0); 2176104477Ssam} 2177104477Ssam 2178104477Ssamstatic int 2179104477Ssamhifn_process(void *arg, struct cryptop *crp, int hint) 2180104477Ssam{ 2181104477Ssam struct hifn_softc *sc = arg; 2182104477Ssam struct hifn_command *cmd = NULL; 2183104477Ssam int session, err; 2184104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2185104477Ssam 2186104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2187104477Ssam hifnstats.hst_invalid++; 2188104477Ssam return (EINVAL); 2189104477Ssam } 2190104477Ssam session = HIFN_SESSION(crp->crp_sid); 2191104477Ssam 2192104477Ssam if (sc == NULL || session >= sc->sc_maxses) { 2193104477Ssam err = EINVAL; 2194104477Ssam goto errout; 2195104477Ssam } 2196104477Ssam 2197104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2198104477Ssam if (cmd == NULL) { 2199104477Ssam hifnstats.hst_nomem++; 2200104477Ssam err = ENOMEM; 2201104477Ssam goto errout; 2202104477Ssam } 2203104477Ssam 2204104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2205104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2206104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2207104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2208104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2209104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2210104477Ssam } else { 2211104477Ssam err = EINVAL; 2212104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2213104477Ssam } 2214104477Ssam 2215104477Ssam crd1 = crp->crp_desc; 2216104477Ssam if (crd1 == NULL) { 2217104477Ssam err = EINVAL; 2218104477Ssam goto errout; 2219104477Ssam } 2220104477Ssam crd2 = crd1->crd_next; 2221104477Ssam 2222104477Ssam if (crd2 == NULL) { 2223104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2224104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2225104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2226104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2227104477Ssam maccrd = crd1; 2228104477Ssam enccrd = NULL; 2229104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2230104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2231104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2232104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2233104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2234104477Ssam maccrd = NULL; 2235104477Ssam enccrd = crd1; 2236104477Ssam } else { 2237104477Ssam err = EINVAL; 2238104477Ssam goto errout; 2239104477Ssam } 2240104477Ssam } else { 2241104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2242104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2243104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2244104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2245104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2246104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2247104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2248104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2249104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2250104477Ssam maccrd = crd1; 2251104477Ssam enccrd = crd2; 2252104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2253104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2254104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC) && 2255104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2256104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2257104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2258104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2259104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2260104477Ssam enccrd = crd1; 2261104477Ssam maccrd = crd2; 2262104477Ssam } else { 2263104477Ssam /* 2264104477Ssam * We cannot order the 7751 as requested 2265104477Ssam */ 2266104477Ssam err = EINVAL; 2267104477Ssam goto errout; 2268104477Ssam } 2269104477Ssam } 2270104477Ssam 2271104477Ssam if (enccrd) { 2272104477Ssam cmd->enccrd = enccrd; 2273104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2274104477Ssam switch (enccrd->crd_alg) { 2275104477Ssam case CRYPTO_ARC4: 2276104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2277104477Ssam if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2278104477Ssam != sc->sc_sessions[session].hs_prev_op) 2279104477Ssam sc->sc_sessions[session].hs_state = 2280104477Ssam HS_STATE_USED; 2281104477Ssam break; 2282104477Ssam case CRYPTO_DES_CBC: 2283104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2284104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2285104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2286104477Ssam break; 2287104477Ssam case CRYPTO_3DES_CBC: 2288104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2289104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2290104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2291104477Ssam break; 2292104477Ssam default: 2293104477Ssam err = EINVAL; 2294104477Ssam goto errout; 2295104477Ssam } 2296104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2297104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2298104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2299104477Ssam bcopy(enccrd->crd_iv, cmd->iv, 2300104477Ssam HIFN_IV_LENGTH); 2301104477Ssam else 2302104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2303104477Ssam cmd->iv, HIFN_IV_LENGTH); 2304104477Ssam 2305104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2306104477Ssam == 0) { 2307104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2308104477Ssam m_copyback(cmd->src_m, 2309104477Ssam enccrd->crd_inject, 2310104477Ssam HIFN_IV_LENGTH, cmd->iv); 2311104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2312104477Ssam cuio_copyback(cmd->src_io, 2313104477Ssam enccrd->crd_inject, 2314104477Ssam HIFN_IV_LENGTH, cmd->iv); 2315104477Ssam } 2316104477Ssam } else { 2317104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2318104477Ssam bcopy(enccrd->crd_iv, cmd->iv, 2319104477Ssam HIFN_IV_LENGTH); 2320104477Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 2321104477Ssam m_copydata(cmd->src_m, 2322104477Ssam enccrd->crd_inject, 2323104477Ssam HIFN_IV_LENGTH, cmd->iv); 2324104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2325104477Ssam cuio_copydata(cmd->src_io, 2326104477Ssam enccrd->crd_inject, 2327104477Ssam HIFN_IV_LENGTH, cmd->iv); 2328104477Ssam } 2329104477Ssam } 2330104477Ssam 2331104477Ssam cmd->ck = enccrd->crd_key; 2332104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2333104477Ssam 2334104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2335104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2336104477Ssam } 2337104477Ssam 2338104477Ssam if (maccrd) { 2339104477Ssam cmd->maccrd = maccrd; 2340104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2341104477Ssam 2342104477Ssam switch (maccrd->crd_alg) { 2343104477Ssam case CRYPTO_MD5: 2344104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2345104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2346104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2347104477Ssam break; 2348104477Ssam case CRYPTO_MD5_HMAC: 2349104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2350104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2351104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2352104477Ssam break; 2353104477Ssam case CRYPTO_SHA1: 2354104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2355104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2356104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2357104477Ssam break; 2358104477Ssam case CRYPTO_SHA1_HMAC: 2359104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2360104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2361104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2362104477Ssam break; 2363104477Ssam } 2364104477Ssam 2365104477Ssam if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2366104477Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2367104477Ssam sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2368104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2369104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2370104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2371104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2372104477Ssam } 2373104477Ssam } 2374104477Ssam 2375104477Ssam cmd->crp = crp; 2376104477Ssam cmd->session_num = session; 2377104477Ssam cmd->softc = sc; 2378104477Ssam 2379104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2380104477Ssam if (!err) { 2381104477Ssam if (enccrd) 2382104477Ssam sc->sc_sessions[session].hs_prev_op = 2383104477Ssam enccrd->crd_flags & CRD_F_ENCRYPT; 2384104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2385104477Ssam sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2386104477Ssam return 0; 2387104477Ssam } else if (err == ERESTART) { 2388104477Ssam /* 2389104477Ssam * There weren't enough resources to dispatch the request 2390104477Ssam * to the part. Notify the caller so they'll requeue this 2391104477Ssam * request and resubmit it again soon. 2392104477Ssam */ 2393104477Ssam#ifdef HIFN_DEBUG 2394104477Ssam if (hifn_debug) 2395104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2396104477Ssam#endif 2397104477Ssam free(cmd, M_DEVBUF); 2398104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2399104477Ssam return (err); 2400104477Ssam } 2401104477Ssam 2402104477Ssamerrout: 2403104477Ssam if (cmd != NULL) 2404104477Ssam free(cmd, M_DEVBUF); 2405104477Ssam if (err == EINVAL) 2406104477Ssam hifnstats.hst_invalid++; 2407104477Ssam else 2408104477Ssam hifnstats.hst_nomem++; 2409104477Ssam crp->crp_etype = err; 2410104477Ssam crypto_done(crp); 2411104477Ssam return (err); 2412104477Ssam} 2413104477Ssam 2414104477Ssamstatic void 2415104477Ssamhifn_abort(struct hifn_softc *sc) 2416104477Ssam{ 2417104477Ssam struct hifn_dma *dma = sc->sc_dma; 2418104477Ssam struct hifn_command *cmd; 2419104477Ssam struct cryptop *crp; 2420104477Ssam int i, u; 2421104477Ssam 2422104477Ssam i = dma->resk; u = dma->resu; 2423104477Ssam while (u != 0) { 2424104477Ssam cmd = dma->hifn_commands[i]; 2425104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2426104477Ssam dma->hifn_commands[i] = NULL; 2427104477Ssam crp = cmd->crp; 2428104477Ssam 2429104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2430104477Ssam /* Salvage what we can. */ 2431104477Ssam u_int8_t *macbuf; 2432104477Ssam 2433104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2434104477Ssam macbuf = dma->result_bufs[i]; 2435104477Ssam macbuf += 12; 2436104477Ssam } else 2437104477Ssam macbuf = NULL; 2438104477Ssam hifnstats.hst_opackets++; 2439104477Ssam hifn_callback(sc, cmd, macbuf); 2440104477Ssam } else { 2441104477Ssam if (cmd->src_map == cmd->dst_map) { 2442104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2443104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2444104477Ssam } else { 2445104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2446104477Ssam BUS_DMASYNC_POSTWRITE); 2447104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2448104477Ssam BUS_DMASYNC_POSTREAD); 2449104477Ssam } 2450104477Ssam 2451104477Ssam if (cmd->src_m != cmd->dst_m) { 2452104477Ssam m_freem(cmd->src_m); 2453104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2454104477Ssam } 2455104477Ssam 2456104477Ssam /* non-shared buffers cannot be restarted */ 2457104477Ssam if (cmd->src_map != cmd->dst_map) { 2458104477Ssam /* 2459104477Ssam * XXX should be EAGAIN, delayed until 2460104477Ssam * after the reset. 2461104477Ssam */ 2462104477Ssam crp->crp_etype = ENOMEM; 2463104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2464104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2465104477Ssam } else 2466104477Ssam crp->crp_etype = ENOMEM; 2467104477Ssam 2468104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2469104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2470104477Ssam 2471104477Ssam free(cmd, M_DEVBUF); 2472104477Ssam if (crp->crp_etype != EAGAIN) 2473104477Ssam crypto_done(crp); 2474104477Ssam } 2475104477Ssam 2476104477Ssam if (++i == HIFN_D_RES_RSIZE) 2477104477Ssam i = 0; 2478104477Ssam u--; 2479104477Ssam } 2480104477Ssam dma->resk = i; dma->resu = u; 2481104477Ssam 2482104477Ssam /* Force upload of key next time */ 2483104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2484104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2485104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2486104477Ssam 2487104477Ssam hifn_reset_board(sc, 1); 2488104477Ssam hifn_init_dma(sc); 2489104477Ssam hifn_init_pci_registers(sc); 2490104477Ssam} 2491104477Ssam 2492104477Ssamstatic void 2493104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2494104477Ssam{ 2495104477Ssam struct hifn_dma *dma = sc->sc_dma; 2496104477Ssam struct cryptop *crp = cmd->crp; 2497104477Ssam struct cryptodesc *crd; 2498104477Ssam struct mbuf *m; 2499104477Ssam int totlen, i, u; 2500104477Ssam 2501104477Ssam if (cmd->src_map == cmd->dst_map) { 2502104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2503104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2504104477Ssam } else { 2505104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2506104477Ssam BUS_DMASYNC_POSTWRITE); 2507104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2508104477Ssam BUS_DMASYNC_POSTREAD); 2509104477Ssam } 2510104477Ssam 2511104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2512104477Ssam if (cmd->src_m != cmd->dst_m) { 2513104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2514104477Ssam totlen = cmd->src_mapsize; 2515104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2516104477Ssam if (totlen < m->m_len) { 2517104477Ssam m->m_len = totlen; 2518104477Ssam totlen = 0; 2519104477Ssam } else 2520104477Ssam totlen -= m->m_len; 2521104477Ssam } 2522104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2523104477Ssam m_freem(cmd->src_m); 2524104477Ssam } 2525104477Ssam } 2526104477Ssam 2527104477Ssam if (cmd->sloplen != 0) { 2528104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2529104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2530104477Ssam cmd->src_mapsize - cmd->sloplen, 2531104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2532104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2533104477Ssam cuio_copyback((struct uio *)crp->crp_buf, 2534104477Ssam cmd->src_mapsize - cmd->sloplen, 2535104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2536104477Ssam } 2537104477Ssam 2538104477Ssam i = dma->dstk; u = dma->dstu; 2539104477Ssam while (u != 0) { 2540104477Ssam if (i == HIFN_D_DST_RSIZE) 2541104477Ssam i = 0; 2542104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2543104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2544104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2545104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2546104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2547104477Ssam break; 2548104477Ssam } 2549104477Ssam i++, u--; 2550104477Ssam } 2551104477Ssam dma->dstk = i; dma->dstu = u; 2552104477Ssam 2553104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2554104477Ssam 2555104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2556104477Ssam HIFN_BASE_CMD_CRYPT) { 2557104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2558104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2559104477Ssam crd->crd_alg != CRYPTO_3DES_CBC) 2560104477Ssam continue; 2561104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2562104477Ssam m_copydata((struct mbuf *)crp->crp_buf, 2563104477Ssam crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2564104477Ssam HIFN_IV_LENGTH, 2565104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2566104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) { 2567104477Ssam cuio_copydata((struct uio *)crp->crp_buf, 2568104477Ssam crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2569104477Ssam HIFN_IV_LENGTH, 2570104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2571104477Ssam } 2572104477Ssam break; 2573104477Ssam } 2574104477Ssam } 2575104477Ssam 2576104477Ssam if (macbuf != NULL) { 2577104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2578105275Ssam int len; 2579104477Ssam 2580105275Ssam if (crd->crd_alg == CRYPTO_MD5) 2581105275Ssam len = 16; 2582105275Ssam else if (crd->crd_alg == CRYPTO_SHA1) 2583105275Ssam len = 20; 2584105275Ssam else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2585105275Ssam crd->crd_alg == CRYPTO_SHA1_HMAC) 2586105275Ssam len = 12; 2587105275Ssam else 2588104477Ssam continue; 2589104477Ssam 2590104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2591104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2592104477Ssam crd->crd_inject, len, macbuf); 2593104477Ssam else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2594104477Ssam bcopy((caddr_t)macbuf, crp->crp_mac, len); 2595104477Ssam break; 2596104477Ssam } 2597104477Ssam } 2598104477Ssam 2599104477Ssam if (cmd->src_map != cmd->dst_map) { 2600104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2601104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2602104477Ssam } 2603104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2604104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2605104477Ssam free(cmd, M_DEVBUF); 2606104477Ssam crypto_done(crp); 2607104477Ssam} 2608104477Ssam 2609104477Ssam/* 2610104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2611104477Ssam * and Group 1 registers; avoid conditions that could create 2612104477Ssam * burst writes by doing a read in between the writes. 2613104477Ssam * 2614104477Ssam * NB: The read we interpose is always to the same register; 2615104477Ssam * we do this because reading from an arbitrary (e.g. last) 2616104477Ssam * register may not always work. 2617104477Ssam */ 2618104477Ssamstatic void 2619104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2620104477Ssam{ 2621104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2622104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2623104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2624104477Ssam sc->sc_bar0_lastreg = reg; 2625104477Ssam } 2626104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2627104477Ssam} 2628104477Ssam 2629104477Ssamstatic void 2630104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2631104477Ssam{ 2632104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2633104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2634104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2635104477Ssam sc->sc_bar1_lastreg = reg; 2636104477Ssam } 2637104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2638104477Ssam} 2639