1139749Simp/*- 2116491Sharti * Copyright (c) 2001-2003 3116491Sharti * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 4116491Sharti * All rights reserved. 5116491Sharti * 6116491Sharti * Redistribution and use in source and binary forms, with or without 7116491Sharti * modification, are permitted provided that the following conditions 8116491Sharti * are met: 9116491Sharti * 1. Redistributions of source code must retain the above copyright 10116491Sharti * notice, this list of conditions and the following disclaimer. 11116491Sharti * 2. Redistributions in binary form must reproduce the above copyright 12116491Sharti * notice, this list of conditions and the following disclaimer in the 13116491Sharti * documentation and/or other materials provided with the distribution. 14116491Sharti * 15116491Sharti * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16116491Sharti * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17116491Sharti * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18116491Sharti * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19116491Sharti * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20116491Sharti * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21116491Sharti * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22116491Sharti * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23116491Sharti * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24116491Sharti * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25116491Sharti * SUCH DAMAGE. 26116491Sharti * 27116491Sharti * Author: Hartmut Brandt <harti@freebsd.org> 28116491Sharti * 29116491Sharti * $FreeBSD$ 30116491Sharti * 31116491Sharti * Fore HE driver for NATM 32116491Sharti */ 33116491Sharti 34116491Sharti/* check configuration */ 35116491Sharti#if HE_CONFIG_VPI_BITS + HE_CONFIG_VCI_BITS > 12 36116491Sharti#error "hatm: too many bits configured for VPI/VCI" 37116491Sharti#endif 38116491Sharti 39116491Sharti#define HE_MAX_VCCS (1 << (HE_CONFIG_VPI_BITS + HE_CONFIG_VCI_BITS)) 40116491Sharti 41116491Sharti#define HE_VPI_MASK ((1 << (HE_CONFIG_VPI_BITS))-1) 42116491Sharti#define HE_VCI_MASK ((1 << (HE_CONFIG_VCI_BITS))-1) 43116491Sharti 44116491Sharti#define HE_VPI(CID) (((CID) >> HE_CONFIG_VCI_BITS) & HE_VPI_MASK) 45116491Sharti#define HE_VCI(CID) ((CID) & HE_VCI_MASK) 46116491Sharti 47116491Sharti#define HE_CID(VPI,VCI) ((((VPI) & HE_VPI_MASK) << HE_CONFIG_VCI_BITS) | \ 48116491Sharti ((VCI) & HE_VCI_MASK)) 49116491Sharti 50116491Sharti 51116491Sharti/* GEN_CNTL_0 register */ 52116491Sharti#define HE_PCIR_GEN_CNTL_0 0x40 53116491Sharti#define HE_PCIM_CTL0_64BIT (1 << 0) 54116491Sharti#define HE_PCIM_CTL0_IGNORE_TIMEOUT (1 << 1) 55116491Sharti#define HE_PCIM_CTL0_INIT_ENB (1 << 2) 56116491Sharti#define HE_PCIM_CTL0_MRM (1 << 4) 57116491Sharti#define HE_PCIM_CTL0_MRL (1 << 5) 58116491Sharti#define HE_PCIM_CTL0_BIGENDIAN (1 << 16) 59116491Sharti#define HE_PCIM_CTL0_INT_PROC_ENB (1 << 25) 60116491Sharti 61116491Sharti/* 62116491Sharti * Memory registers 63116491Sharti */ 64116491Sharti#define HE_REGO_FLASH 0x00000 65116491Sharti#define HE_REGO_RESET_CNTL 0x80000 66116491Sharti#define HE_REGM_RESET_STATE (1 << 6) 67116491Sharti#define HE_REGO_HOST_CNTL 0x80004 68116491Sharti#define HE_REGM_HOST_BUS64 (1 << 27) 69116491Sharti#define HE_REGM_HOST_DESC_RD64 (1 << 26) 70116491Sharti#define HE_REGM_HOST_DATA_RD64 (1 << 25) 71116491Sharti#define HE_REGM_HOST_DATA_WR64 (1 << 24) 72116491Sharti#define HE_REGM_HOST_PROM_SEL (1 << 12) 73116491Sharti#define HE_REGM_HOST_PROM_WREN (1 << 11) 74116491Sharti#define HE_REGM_HOST_PROM_DATA_OUT (1 << 10) 75116491Sharti#define HE_REGS_HOST_PROM_DATA_OUT 10 76116491Sharti#define HE_REGM_HOST_PROM_DATA_IN (1 << 9) 77116491Sharti#define HE_REGS_HOST_PROM_DATA_IN 9 78116491Sharti#define HE_REGM_HOST_PROM_CLOCK (1 << 8) 79116491Sharti#define HE_REGM_HOST_PROM_BITS (0x00001f00) 80116491Sharti#define HE_REGM_HOST_QUICK_RD (1 << 7) 81116491Sharti#define HE_REGM_HOST_QUICK_WR (1 << 6) 82116491Sharti#define HE_REGM_HOST_OUTFF_ENB (1 << 5) 83116491Sharti#define HE_REGM_HOST_CMDFF_ENB (1 << 4) 84116491Sharti#define HE_REGO_LB_SWAP 0x80008 85116491Sharti#define HE_REGM_LBSWAP_RNUM (0xf << 27) 86116491Sharti#define HE_REGS_LBSWAP_RNUM 27 87116491Sharti#define HE_REGM_LBSWAP_DATA_WR_SWAP (1 << 20) 88116491Sharti#define HE_REGM_LBSWAP_DESC_RD_SWAP (1 << 19) 89116491Sharti#define HE_REGM_LBSWAP_DATA_RD_SWAP (1 << 18) 90116491Sharti#define HE_REGM_LBSWAP_INTR_SWAP (1 << 17) 91116491Sharti#define HE_REGM_LBSWAP_DESC_WR_SWAP (1 << 16) 92116491Sharti#define HE_REGM_LBSWAP_BIG_ENDIAN (1 << 14) 93116491Sharti#define HE_REGM_LBSWAP_XFER_SIZE (1 << 7) 94116491Sharti 95116491Sharti#define HE_REGO_LB_MEM_ADDR 0x8000C 96116491Sharti#define HE_REGO_LB_MEM_DATA 0x80010 97116491Sharti#define HE_REGO_LB_MEM_ACCESS 0x80014 98116491Sharti#define HE_REGM_LB_MEM_HNDSHK (1 << 30) 99116491Sharti#define HE_REGM_LB_MEM_READ 0x3 100116491Sharti#define HE_REGM_LB_MEM_WRITE 0x7 101116491Sharti 102116491Sharti#define HE_REGO_SDRAM_CNTL 0x80018 103116491Sharti#define HE_REGM_SDRAM_64BIT (1 << 3) 104116491Sharti#define HE_REGO_INT_FIFO 0x8001C 105116491Sharti#define HE_REGM_INT_FIFO_CLRA (1 << 8) 106116491Sharti#define HE_REGM_INT_FIFO_CLRB (1 << 9) 107116491Sharti#define HE_REGM_INT_FIFO_CLRC (1 << 10) 108116491Sharti#define HE_REGM_INT_FIFO_CLRD (1 << 11) 109116491Sharti#define HE_REGO_ABORT_ADDR 0x80020 110116491Sharti 111116491Sharti#define HE_REGO_IRQ0_BASE 0x80080 112116491Sharti#define HE_REGO_IRQ_BASE(Q) (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x00) 113116491Sharti#define HE_REGM_IRQ_BASE_TAIL 0x3ff 114116491Sharti#define HE_REGO_IRQ_HEAD(Q) (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x04) 115116491Sharti#define HE_REGS_IRQ_HEAD_SIZE 22 116116491Sharti#define HE_REGS_IRQ_HEAD_THRESH 12 117116491Sharti#define HE_REGS_IRQ_HEAD_HEAD 2 118116491Sharti#define HE_REGO_IRQ_CNTL(Q) (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x08) 119116491Sharti#define HE_REGM_IRQ_A (0 << 2) 120116491Sharti#define HE_REGM_IRQ_B (1 << 2) 121116491Sharti#define HE_REGM_IRQ_C (2 << 2) 122116491Sharti#define HE_REGM_IRQ_D (3 << 2) 123116491Sharti#define HE_REGO_IRQ_DATA(Q) (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x0C) 124116491Sharti 125116491Sharti#define HE_REGO_GRP_1_0_MAP 0x800C0 126116491Sharti#define HE_REGO_GRP_3_2_MAP 0x800C4 127116491Sharti#define HE_REGO_GRP_5_4_MAP 0x800C8 128116491Sharti#define HE_REGO_GRP_7_6_MAP 0x800CC 129116491Sharti 130116491Sharti/* 131116491Sharti * Receive buffer pools 132116491Sharti */ 133116491Sharti#define HE_REGO_G0_RBPS_S 0x80400 134116491Sharti#define HE_REGO_G0_RBPS_T 0x80404 135116491Sharti#define HE_REGO_G0_RBPS_QI 0x80408 136116491Sharti#define HE_REGO_G0_RBPS_BL 0x8040C 137116491Sharti 138116491Sharti#define HE_REGO_RBP_S(K,G) (HE_REGO_G0_RBPS_S + (K) * 0x10 + (G) * 0x20) 139116491Sharti#define HE_REGO_RBP_T(K,G) (HE_REGO_G0_RBPS_T + (K) * 0x10 + (G) * 0x20) 140116491Sharti#define HE_REGO_RBP_QI(K,G) (HE_REGO_G0_RBPS_QI + (K) * 0x10 + (G) * 0x20) 141116491Sharti#define HE_REGO_RBP_BL(K,G) (HE_REGO_G0_RBPS_BL + (K) * 0x10 + (G) * 0x20) 142116491Sharti 143116491Sharti#define HE_REGS_RBP_HEAD 3 144116491Sharti#define HE_REGS_RBP_TAIL 3 145116491Sharti#define HE_REGS_RBP_SIZE 14 146116491Sharti#define HE_REGM_RBP_INTR_ENB (1 << 13) 147116491Sharti#define HE_REGS_RBP_THRESH 0 148116491Sharti 149116491Sharti/* 150116491Sharti * Receive buffer return queues 151116491Sharti */ 152116491Sharti#define HE_REGO_G0_RBRQ_ST 0x80500 153116491Sharti#define HE_REGO_G0_RBRQ_H 0x80504 154116491Sharti#define HE_REGO_G0_RBRQ_Q 0x80508 155116491Sharti#define HE_REGO_G0_RBRQ_I 0x8050C 156116491Sharti 157116491Sharti#define HE_REGO_RBRQ_ST(G) (HE_REGO_G0_RBRQ_ST + (G) * 0x10) 158116491Sharti#define HE_REGO_RBRQ_H(G) (HE_REGO_G0_RBRQ_H + (G) * 0x10) 159116491Sharti#define HE_REGO_RBRQ_Q(G) (HE_REGO_G0_RBRQ_Q + (G) * 0x10) 160116491Sharti#define HE_REGO_RBRQ_I(G) (HE_REGO_G0_RBRQ_I + (G) * 0x10) 161116491Sharti 162116491Sharti#define HE_REGS_RBRQ_HEAD 3 163116491Sharti#define HE_REGS_RBRQ_THRESH 13 164116491Sharti#define HE_REGS_RBRQ_SIZE 0 165116491Sharti#define HE_REGS_RBRQ_TIME 8 166116491Sharti#define HE_REGS_RBRQ_COUNT 0 167116491Sharti 168116491Sharti/* 169116491Sharti * Intermediate queues 170116491Sharti */ 171116491Sharti#define HE_REGO_G0_INMQ_S 0x80580 172116491Sharti#define HE_REGO_G0_INMQ_L 0x80584 173116491Sharti#define HE_REGO_INMQ_S(G) (HE_REGO_G0_INMQ_S + (G) * 8) 174116491Sharti#define HE_REGO_INMQ_L(G) (HE_REGO_G0_INMQ_L + (G) * 8) 175116491Sharti 176116491Sharti#define HE_REGO_RHCONFIG 0x805C0 177116491Sharti#define HE_REGM_RHCONFIG_PHYENB (1 << 10) 178116491Sharti#define HE_REGS_RHCONFIG_OAM_GID 7 179116491Sharti#define HE_REGS_RHCONFIG_PTMR_PRE 0 180116491Sharti 181116491Sharti/* 182116491Sharti * Transmit buffer return queues 183116491Sharti */ 184116491Sharti#define HE_REGO_TBRQ0_B_T 0x80600 185116491Sharti#define HE_REGO_TBRQ0_H 0x80604 186116491Sharti#define HE_REGO_TBRQ0_S 0x80608 187116491Sharti#define HE_REGO_TBRQ0_THRESH 0x8060C 188116491Sharti 189116491Sharti#define HE_REGO_TBRQ_B_T(G) (HE_REGO_TBRQ0_B_T + (G) * 0x10) 190116491Sharti#define HE_REGO_TBRQ_H(G) (HE_REGO_TBRQ0_H + (G) * 0x10) 191116491Sharti#define HE_REGO_TBRQ_S(G) (HE_REGO_TBRQ0_S + (G) * 0x10) 192116491Sharti#define HE_REGO_TBRQ_THRESH(G) (HE_REGO_TBRQ0_THRESH + (G) * 0x10) 193116491Sharti 194116491Sharti#define HE_REGS_TBRQ_HEAD 2 195116491Sharti 196116491Sharti/* 197116491Sharti * Transmit packet descriptor ready queue 198116491Sharti */ 199116491Sharti#define HE_REGO_TPDRQ_H 0x80680 200116491Sharti#define HE_REGS_TPDRQ_H_H 3 201116491Sharti/* #define HE_REGM_TPDRQ_H_H ((HE_CONFIG_TPDRQ_SIZE - 1) << 3) */ 202116491Sharti#define HE_REGO_TPDRQ_T 0x80684 203116491Sharti#define HE_REGS_TPDRQ_T_T 3 204116491Sharti/* #define HE_REGM_TPDRQ_T_T ((HE_CONFIG_TPDRQ_SIZE - 1) << 3) */ 205116491Sharti#define HE_REGO_TPDRQ_S 0x80688 206116491Sharti 207116491Sharti#define HE_REGO_UBUFF_BA 0x8068C 208116491Sharti 209116491Sharti#define HE_REGO_RLBF0_H 0x806C0 210116491Sharti#define HE_REGO_RLBF0_T 0x806C4 211116491Sharti#define HE_REGO_RLBF1_H 0x806C8 212116491Sharti#define HE_REGO_RLBF1_T 0x806CC 213116491Sharti#define HE_REGO_RLBF_H(N) (HE_REGO_RLBF0_H + (N) * 8) 214116491Sharti#define HE_REGO_RLBF_T(N) (HE_REGO_RLBF0_T + (N) * 8) 215116491Sharti 216116491Sharti#define HE_REGO_RLBC_H 0x806D0 217116491Sharti#define HE_REGO_RLBC_T 0x806D4 218116491Sharti#define HE_REGO_RLBC_H2 0x806D8 219116491Sharti#define HE_REGO_TLBF_H 0x806E0 220116491Sharti#define HE_REGO_TLBF_T 0x806E4 221116491Sharti 222116491Sharti#define HE_REGO_RLBF0_C 0x806E8 223116491Sharti#define HE_REGO_RLBF1_C 0x806EC 224116491Sharti#define HE_REGO_RLBF_C(N) (HE_REGO_RLBF0_C + (N) * 4) 225116491Sharti 226116491Sharti#define HE_REGO_RXTHRSH 0x806F0 227116491Sharti#define HE_REGO_LITHRSH 0x806F4 228116491Sharti 229116491Sharti#define HE_REGO_LBARB 0x80700 230116491Sharti#define HE_REGS_LBARB_SLICE 28 231116491Sharti#define HE_REGS_LBARB_RNUM 23 232116491Sharti#define HE_REGS_LBARB_THPRI 21 233116491Sharti#define HE_REGS_LBARB_RHPRI 19 234116491Sharti#define HE_REGS_LBARB_TLPRI 17 235116491Sharti#define HE_REGS_LBARB_RLPRI 15 236116491Sharti#define HE_REGS_LBARB_BUS_MULT 8 237116491Sharti#define HE_REGS_LBARB_NET_PREF 0 238116491Sharti 239116491Sharti#define HE_REGO_SDRAMCON 0x80704 240116491Sharti#define HE_REGM_SDRAMCON_BANK (1 << 14) 241116491Sharti#define HE_REGM_SDRAMCON_WIDE (1 << 13) 242116491Sharti#define HE_REGM_SDRAMCON_TWRWAIT (1 << 12) 243116491Sharti#define HE_REGM_SDRAMCON_TRPWAIT (1 << 11) 244116491Sharti#define HE_REGM_SDRAMCON_TRASWAIT (1 << 10) 245116491Sharti#define HE_REGS_SDRAMCON_REF 0 246116491Sharti 247116491Sharti#define HE_REGO_RCCSTAT 0x8070C 248116491Sharti#define HE_REGM_RCCSTAT_PROG (1 << 0) 249116491Sharti 250116491Sharti#define HE_REGO_TCMCONFIG 0x80740 251116491Sharti#define HE_REGS_TCMCONFIG_BANK_WAIT 6 252116491Sharti#define HE_REGS_TCMCONFIG_RW_WAIT 2 253116491Sharti#define HE_REGS_TCMCONFIG_TYPE 0 254116491Sharti 255116491Sharti#define HE_REGO_TSRB_BA 0x80744 256116491Sharti#define HE_REGO_TSRC_BA 0x80748 257116491Sharti#define HE_REGO_TMABR_BA 0x8074C 258116491Sharti#define HE_REGO_TPD_BA 0x80750 259116491Sharti#define HE_REGO_TSRD_BA 0x80758 260116491Sharti 261116491Sharti#define HE_REGO_TXCONFIG 0x80760 262116491Sharti#define HE_REGS_TXCONFIG_THRESH 22 263116491Sharti#define HE_REGM_TXCONFIG_UTMODE (1 << 21) 264116491Sharti#define HE_REGS_TXCONFIG_VCI_MASK 17 265116491Sharti#define HE_REGS_TXCONFIG_LBFREE 0 266116491Sharti 267116491Sharti#define HE_REGO_TXAAL5_PROTO 0x80764 268116491Sharti 269116491Sharti#define HE_REGO_RCMCONFIG 0x80780 270116491Sharti#define HE_REGS_RCMCONFIG_BANK_WAIT 6 271116491Sharti#define HE_REGS_RCMCONFIG_RW_WAIT 2 272116491Sharti#define HE_REGS_RCMCONFIG_TYPE 0 273116491Sharti 274116491Sharti#define HE_REGO_RCMRSRB_BA 0x80784 275116491Sharti#define HE_REGO_RCMLBM_BA 0x80788 276116491Sharti#define HE_REGO_RCMABR_BA 0x8078C 277116491Sharti 278116491Sharti#define HE_REGO_RCCONFIG 0x807C0 279116491Sharti#define HE_REGS_RCCONFIG_UTDELAY 11 280116491Sharti#define HE_REGM_RCCONFIG_WRAP_MODE (1 << 10) 281116491Sharti#define HE_REGM_RCCONFIG_UT_MODE (1 << 9) 282116491Sharti#define HE_REGM_RCCONFIG_RXENB (1 << 8) 283116491Sharti#define HE_REGS_RCCONFIG_VP 4 284116491Sharti#define HE_REGS_RCCONFIG_VC 0 285116491Sharti 286116491Sharti#define HE_REGO_MCC 0x807C4 287116491Sharti#define HE_REGO_OEC 0x807C8 288116491Sharti#define HE_REGO_DCC 0x807CC 289116491Sharti#define HE_REGO_CEC 0x807D0 290116491Sharti 291116491Sharti#define HE_REGO_HSP_BA 0x807F0 292116491Sharti 293116491Sharti#define HE_REGO_LBCONFIG 0x807F4 294116491Sharti 295116491Sharti#define HE_REGO_CON_DAT 0x807F8 296116491Sharti#define HE_REGO_CON_CTL 0x807FC 297258779Seadler#define HE_REGM_CON_MBOX (2U << 30) 298116491Sharti#define HE_REGM_CON_TCM (1 << 30) 299116491Sharti#define HE_REGM_CON_RCM (0 << 30) 300116491Sharti#define HE_REGM_CON_WE (1 << 29) 301116491Sharti#define HE_REGM_CON_STATUS (1 << 28) 302116491Sharti#define HE_REGM_CON_DIS3 (1 << 22) 303116491Sharti#define HE_REGM_CON_DIS2 (1 << 21) 304116491Sharti#define HE_REGM_CON_DIS1 (1 << 20) 305116491Sharti#define HE_REGM_CON_DIS0 (1 << 19) 306116491Sharti#define HE_REGS_CON_DIS 19 307116491Sharti#define HE_REGS_CON_ADDR 0 308116491Sharti 309116491Sharti#define HE_REGO_SUNI 0x80800 310116491Sharti#define HE_REGO_SUNI_END 0x80C00 311116491Sharti 312116491Sharti#define HE_REGO_END 0x100000 313116491Sharti 314116491Sharti/* 315116491Sharti * MBOX registers 316116491Sharti */ 317116491Sharti#define HE_REGO_CS_STPER0 0x000 318116491Sharti#define HE_REGO_CS_STPER(G) (HE_REGO_CS_STPER0 + (G)) 319116491Sharti#define HE_REGN_CS_STPER 32 320116491Sharti#define HE_REGO_CS_STTIM0 0x020 321116491Sharti#define HE_REGO_CS_STTIM(G) (HE_REGO_CS_STTIM0 + (G)) 322116491Sharti#define HE_REGO_CS_TGRLD0 0x040 323116491Sharti#define HE_REGO_CS_TGRLD(G) (HE_REGO_CS_TGRLD0 + (G)) 324116491Sharti#define HE_REGO_CS_ERTHR0 0x50 325116491Sharti#define HE_REGO_CS_ERTHR1 0x51 326116491Sharti#define HE_REGO_CS_ERTHR2 0x52 327116491Sharti#define HE_REGO_CS_ERTHR3 0x53 328116491Sharti#define HE_REGO_CS_ERTHR4 0x54 329116491Sharti#define HE_REGO_CS_ERCTL0 0x55 330116491Sharti#define HE_REGO_CS_ERCTL1 0x56 331116491Sharti#define HE_REGO_CS_ERCTL2 0x57 332116491Sharti#define HE_REGO_CS_ERSTAT0 0x58 333116491Sharti#define HE_REGO_CS_ERSTAT1 0x59 334116491Sharti#define HE_REGO_CS_RTCCT 0x60 335116491Sharti#define HE_REGO_CS_RTFWC 0x61 336116491Sharti#define HE_REGO_CS_RTFWR 0x62 337116491Sharti#define HE_REGO_CS_RTFTC 0x63 338116491Sharti#define HE_REGO_CS_RTATR 0x64 339116491Sharti#define HE_REGO_CS_TFBSET 0x70 340116491Sharti#define HE_REGO_CS_TFBADD 0x71 341116491Sharti#define HE_REGO_CS_TFBSUB 0x72 342116491Sharti#define HE_REGO_CS_WCRMAX 0x73 343116491Sharti#define HE_REGO_CS_WCRMIN 0x74 344116491Sharti#define HE_REGO_CS_WCRINC 0x75 345116491Sharti#define HE_REGO_CS_WCRDEC 0x76 346116491Sharti#define HE_REGO_CS_WCRCEIL 0x77 347116491Sharti#define HE_REGO_CS_BWDCNT 0x78 348116491Sharti#define HE_REGO_CS_OTPPER 0x80 349116491Sharti#define HE_REGO_CS_OTWPER 0x81 350116491Sharti#define HE_REGO_CS_OTTLIM 0x82 351116491Sharti#define HE_REGO_CS_OTTCNT 0x83 352116491Sharti#define HE_REGO_CS_HGRRT0 0x90 353116491Sharti#define HE_REGO_CS_HGRRT(G) (HE_REGO_CS_HGRRT0 + (G)) 354116491Sharti#define HE_REGO_CS_ORPTRS 0xA0 355116491Sharti#define HE_REGO_RCON_CLOSE 0x100 356116491Sharti#define HE_REGO_CS_END 0x101 357116491Sharti 358116491Sharti#define HE_REGT_CS_ERTHR { \ 359116491Sharti { /* 155 */ \ 360116491Sharti { 0x000800ea, 0x000400ea, 0x000200ea }, /* ERTHR0 */ \ 361116491Sharti { 0x000C3388, 0x00063388, 0x00033388 }, /* ERTHR1 */ \ 362116491Sharti { 0x00101018, 0x00081018, 0x00041018 }, /* ERTHR2 */ \ 363116491Sharti { 0x00181dac, 0x000c1dac, 0x00061dac }, /* ERTHR3 */ \ 364116491Sharti { 0x0028051a, 0x0014051a, 0x000a051a }, /* ERTHR4 */ \ 365116491Sharti }, { /* 622 */ \ 366116491Sharti { 0x000800fa, 0x000400fa, 0x000200fa }, /* ERTHR0 */ \ 367116491Sharti { 0x000c33cb, 0x000633cb, 0x000333cb }, /* ERTHR1 */ \ 368116491Sharti { 0x0010101b, 0x0008101b, 0x0004101b }, /* ERTHR2 */ \ 369116491Sharti { 0x00181dac, 0x000c1dac, 0x00061dac }, /* ERTHR3 */ \ 370116491Sharti { 0x00280600, 0x00140600, 0x000a0600 }, /* ERTHR4 */ \ 371116491Sharti } \ 372116491Sharti} 373116491Sharti 374116491Sharti#define HE_REGT_CS_ERCTL { \ 375116491Sharti { 0x0235e4b1, 0x4701, 0x64b1 }, /* 155 */ \ 376116491Sharti { 0x023de8b3, 0x1801, 0x68b3 } /* 622 */ \ 377116491Sharti} 378116491Sharti 379116491Sharti#define HE_REGT_CS_ERSTAT { \ 380116491Sharti { 0x1280, 0x64b1 }, /* 155 */ \ 381116491Sharti { 0x1280, 0x68b3 }, /* 622 */ \ 382116491Sharti} 383116491Sharti 384116491Sharti#define HE_REGT_CS_RTFWR { \ 385116491Sharti 0xf424, /* 155 */ \ 386116491Sharti 0x14585 /* 622 */ \ 387116491Sharti} 388116491Sharti 389116491Sharti#define HE_REGT_CS_RTATR { \ 390116491Sharti 0x4680, /* 155 */ \ 391116491Sharti 0x4680 /* 622 */ \ 392116491Sharti} 393116491Sharti 394116491Sharti#define HE_REGT_CS_BWALLOC { \ 395116491Sharti { 0x000563b7, 0x64b1, 0x5ab1, 0xe4b1, 0xdab1, 0x64b1 }, /* 155 */\ 396116491Sharti { 0x00159ece, 0x68b3, 0x5eb3, 0xe8b3, 0xdeb3, 0x68b3 }, /* 622 */\ 397116491Sharti} 398116491Sharti 399116491Sharti#define HE_REGT_CS_ORCF { \ 400116491Sharti { 0x6, 0x1e }, /* 155 */ \ 401116491Sharti { 0x5, 0x14 } /* 622 */ \ 402116491Sharti} 403116491Sharti 404116491Sharti/* 405116491Sharti * TSRs - NR is relative to the starting number of the block 406116491Sharti */ 407116491Sharti#define HE_REGO_TSRA(BASE,CID,NR) ((BASE) + ((CID) << 3) + (NR)) 408116491Sharti#define HE_REGO_TSRB(BASE,CID,NR) ((BASE) + ((CID) << 2) + (NR)) 409116491Sharti#define HE_REGO_TSRC(BASE,CID,NR) ((BASE) + ((CID) << 1) + (NR)) 410116491Sharti#define HE_REGO_TSRD(BASE,CID) ((BASE) + (CID)) 411116491Sharti 412116491Sharti#define HE_REGM_TSR0_CONN_STATE (7 << 28) 413116491Sharti#define HE_REGS_TSR0_CONN_STATE 28 414116491Sharti#define HE_REGM_TSR0_USE_WMIN (1 << 23) 415116491Sharti#define HE_REGM_TSR0_GROUP (7 << 18) 416116491Sharti#define HE_REGS_TSR0_GROUP 18 417116491Sharti#define HE_REGM_TSR0_TRAFFIC (3 << 16) 418116491Sharti#define HE_REGS_TSR0_TRAFFIC 16 419116491Sharti#define HE_REGM_TSR0_TRAFFIC_CBR 0 420116491Sharti#define HE_REGM_TSR0_TRAFFIC_UBR 1 421116491Sharti#define HE_REGM_TSR0_TRAFFIC_ABR 2 422116491Sharti#define HE_REGM_TSR0_PROT (1 << 15) 423116491Sharti#define HE_REGM_TSR0_AAL (3 << 12) 424116491Sharti#define HE_REGS_TSR0_AAL 12 425116491Sharti#define HE_REGM_TSR0_AAL_5 0 426116491Sharti#define HE_REGM_TSR0_AAL_0 1 427116491Sharti#define HE_REGM_TSR0_AAL_0T 2 428116491Sharti#define HE_REGM_TSR0_HALT_ER (1 << 11) 429116491Sharti#define HE_REGM_TSR0_MARK_CI (1 << 10) 430116491Sharti#define HE_REGM_TSR0_MARK_ER (1 << 9) 431116491Sharti#define HE_REGM_TSR0_UPDATE_GER (1 << 8) 432116491Sharti#define HE_REGM_TSR0_RC 0xff 433116491Sharti 434116491Sharti#define HE_REGM_TSR1_PCR (0x7fff << 16) 435116491Sharti#define HE_REGS_TSR1_PCR 16 436116491Sharti#define HE_REGM_TSR1_MCR (0x7fff << 0) 437116491Sharti#define HE_REGS_TSR1_MCR 0 438116491Sharti 439116491Sharti#define HE_REGM_TSR2_ACR (0x7fff << 16) 440116491Sharti#define HE_REGS_TSR2_ACR 16 441116491Sharti 442116491Sharti#define HE_REGM_TSR3_NRM (0xff << 24) 443116491Sharti#define HE_REGS_TSR3_NRM 24 444116491Sharti#define HE_REGM_TSR3_CRM (0xff << 0) 445116491Sharti#define HE_REGS_TSR3_CRM 0 446116491Sharti 447258780Seadler#define HE_REGM_TSR4_FLUSH (1U << 31) 448116491Sharti#define HE_REGM_TSR4_SESS_END (1 << 30) 449116491Sharti#define HE_REGM_TSR4_OAM_CRC10 (1 << 28) 450116491Sharti#define HE_REGM_TSR4_NULL_CRC10 (1 << 27) 451116491Sharti#define HE_REGM_TSR4_PROT (1 << 26) 452116491Sharti#define HE_REGM_TSR4_AAL (3 << 24) 453116491Sharti#define HE_REGS_TSR4_AAL 24 454116491Sharti#define HE_REGM_TSR4_AAL_5 0 455116491Sharti#define HE_REGM_TSR4_AAL_0 1 456116491Sharti#define HE_REGM_TSR4_AAL_0T 2 457116491Sharti 458116491Sharti#define HE_REGM_TSR9_INIT 0x00100000 459116491Sharti 460116491Sharti#define HE_REGM_TSR11_ICR (0x7fff << 16) 461116491Sharti#define HE_REGS_TSR11_ICR 16 462116491Sharti#define HE_REGM_TSR11_TRM (0x7 << 13) 463116491Sharti#define HE_REGS_TSR11_TRM 13 464116491Sharti#define HE_REGM_TSR11_NRM (0x7 << 10) 465116491Sharti#define HE_REGS_TSR11_NRM 10 466116491Sharti#define HE_REGM_TSR11_ADTF 0x3ff 467116491Sharti#define HE_REGS_TSR11_ADTF 0 468116491Sharti 469116491Sharti#define HE_REGM_TSR13_RDF (0xf << 23) 470116491Sharti#define HE_REGS_TSR13_RDF 23 471116491Sharti#define HE_REGM_TSR13_RIF (0xf << 19) 472116491Sharti#define HE_REGS_TSR13_RIF 19 473116491Sharti#define HE_REGM_TSR13_CDF (0x7 << 16) 474116491Sharti#define HE_REGS_TSR13_CDF 16 475116491Sharti#define HE_REGM_TSR13_CRM 0xffff 476116491Sharti#define HE_REGS_TSR13_CRM 0 477116491Sharti 478258780Seadler#define HE_REGM_TSR14_CBR_DELETE (1U << 31) 479116491Sharti#define HE_REGM_TSR14_ABR_CLOSE (1 << 16) 480116491Sharti 481116491Sharti/* 482116491Sharti * RSRs 483116491Sharti */ 484116491Sharti#define HE_REGO_RSRA(BASE,CID,NR) ((BASE) + ((CID) << 3) + (NR)) 485116491Sharti#define HE_REGO_RSRB(BASE,CID,NR) ((BASE) + ((CID) << 1) + (NR)) 486116491Sharti 487116491Sharti#define HE_REGM_RSR0_PTI7 (1 << 15) 488116491Sharti#define HE_REGM_RSR0_RM (1 << 14) 489116491Sharti#define HE_REGM_RSR0_F5OAM (1 << 13) 490116491Sharti#define HE_REGM_RSR0_STARTPDU (1 << 10) 491116491Sharti#define HE_REGM_RSR0_OPEN (1 << 6) 492116491Sharti#define HE_REGM_RSR0_PPD (1 << 5) 493116491Sharti#define HE_REGM_RSR0_EPD (1 << 4) 494116491Sharti#define HE_REGM_RSR0_TCPCS (1 << 3) 495116491Sharti#define HE_REGM_RSR0_AAL 0x7 496116491Sharti#define HE_REGM_RSR0_AAL_5 0x0 497116491Sharti#define HE_REGM_RSR0_AAL_0 0x1 498116491Sharti#define HE_REGM_RSR0_AAL_0T 0x2 499116491Sharti#define HE_REGM_RSR0_AAL_RAW 0x3 500116491Sharti#define HE_REGM_RSR0_AAL_RAWCRC10 0x4 501116491Sharti 502116491Sharti#define HE_REGM_RSR1_AQI (1 << 20) 503116491Sharti#define HE_REGM_RSR1_RBPL_ONLY (1 << 19) 504116491Sharti#define HE_REGM_RSR1_GROUP (7 << 16) 505116491Sharti#define HE_REGS_RSR1_GROUP 16 506116491Sharti 507116491Sharti#define HE_REGM_RSR4_AQI (1 << 30) 508116491Sharti#define HE_REGM_RSR4_GROUP (7 << 27) 509116491Sharti#define HE_REGS_RSR4_GROUP 27 510116491Sharti#define HE_REGM_RSR4_RBPL_ONLY (1 << 26) 511116491Sharti 512116491Sharti/* 513116491Sharti * Relative to RCMABR_BA 514116491Sharti */ 515116491Sharti#define HE_REGO_CM_GQTBL 0x000 516116491Sharti#define HE_REGL_CM_GQTBL 0x100 517116491Sharti#define HE_REGO_CM_RGTBL 0x100 518116491Sharti#define HE_REGL_CM_RGTBL 0x100 519116491Sharti#define HE_REGO_CM_TNRMTBL 0x200 520116491Sharti#define HE_REGL_CM_TNRMTBL 0x100 521116491Sharti#define HE_REGO_CM_ORCF 0x300 522116491Sharti#define HE_REGL_CM_ORCF 0x100 523116491Sharti#define HE_REGO_CM_RTGTBL 0x400 524116491Sharti#define HE_REGL_CM_RTGTBL 0x200 525116491Sharti#define HE_REGO_CM_IRCF 0x600 526116491Sharti#define HE_REGL_CM_IRCF 0x200 527116491Sharti 528116491Sharti/* 529116491Sharti * Interrupt Status 530116491Sharti */ 531116491Sharti#define HE_REGM_ITYPE 0xf8 532116491Sharti#define HE_REGM_IGROUP 0x07 533116491Sharti#define HE_REGM_ITYPE_TBRQ (0x0 << 3) 534116491Sharti#define HE_REGM_ITYPE_TPD (0x1 << 3) 535116491Sharti#define HE_REGM_ITYPE_RBPS (0x2 << 3) 536116491Sharti#define HE_REGM_ITYPE_RBPL (0x3 << 3) 537116491Sharti#define HE_REGM_ITYPE_RBRQ (0x4 << 3) 538116491Sharti#define HE_REGM_ITYPE_RBRQT (0x5 << 3) 539116491Sharti#define HE_REGM_ITYPE_PHYS (0x6 << 3) 540116491Sharti#define HE_REGM_ITYPE_UNKNOWN 0xf8 541116491Sharti#define HE_REGM_ITYPE_ERR 0x80 542116491Sharti#define HE_REGM_ITYPE_PERR 0x81 543116491Sharti#define HE_REGM_ITYPE_ABORT 0x82 544116491Sharti#define HE_REGM_ITYPE_INVALID 0xf8 545116491Sharti 546116491Sharti/* 547116491Sharti * Serial EEPROM 548116491Sharti */ 549116491Sharti#define HE_EEPROM_PROD_ID 0x08 550116491Sharti#define HE_EEPROM_PROD_ID_LEN 30 551116491Sharti#define HE_EEPROM_REV 0x26 552116491Sharti#define HE_EEPROM_REV_LEN 4 553116491Sharti#define HE_EEPROM_M_SN 0x3A 554116491Sharti#define HE_EEPROM_MEDIA 0x3E 555116491Sharti#define HE_EEPROM_MAC 0x42 556116491Sharti 557116491Sharti#define HE_MEDIA_UTP155 0x06 558116491Sharti#define HE_MEDIA_MMF155 0x26 559116491Sharti#define HE_MEDIA_MMF622 0x27 560116491Sharti#define HE_MEDIA_SMF155 0x46 561116491Sharti#define HE_MEDIA_SMF622 0x47 562116491Sharti 563116491Sharti#define HE_622_CLOCK 66667000 564116491Sharti#define HE_155_CLOCK 50000000 565116491Sharti 566116491Sharti/* 567116491Sharti * Statistics 568116491Sharti */ 569116491Shartistruct fatm_statshe { 570116491Sharti}; 571116491Sharti 572116491Sharti/* 573116491Sharti * Queue entries 574116491Sharti */ 575116491Sharti/* Receive Buffer Pool Queue entry */ 576116491Shartistruct he_rbpen { 577116491Sharti uint32_t phys; /* physical address */ 578116491Sharti uint32_t handle; /* handle or virtual address */ 579116491Sharti}; 580116491Sharti/* Receive Buffer Return Queue entry */ 581116491Shartistruct he_rbrqen { 582116491Sharti uint32_t addr; /* handle and flags */ 583116491Sharti uint32_t len; /* length and CID */ 584116491Sharti}; 585116491Sharti#define HE_REGM_RBRQ_ADDR 0xFFFFFFC0 586116491Sharti#define HE_REGS_RBRQ_ADDR 6 587116491Sharti#define HE_REGM_RBRQ_FLAGS 0x0000003F 588116491Sharti#define HE_REGM_RBRQ_HBUF_ERROR (1 << 0) 589116491Sharti#define HE_REGM_RBRQ_CON_CLOSED (1 << 1) 590116491Sharti#define HE_REGM_RBRQ_AAL5_PROT (1 << 2) 591116491Sharti#define HE_REGM_RBRQ_END_PDU (1 << 3) 592116491Sharti#define HE_REGM_RBRQ_LEN_ERROR (1 << 4) 593116491Sharti#define HE_REGM_RBRQ_CRC_ERROR (1 << 5) 594116491Sharti#define HE_REGM_RBRQ_CID (0x1fff << 16) 595116491Sharti#define HE_REGS_RBRQ_CID 16 596116491Sharti#define HE_REGM_RBRQ_LEN 0xffff 597116491Sharti 598116491Sharti/* Transmit Packet Descriptor Ready Queue entry */ 599116491Shartistruct he_tpdrqen { 600116491Sharti uint32_t tpd; /* physical address */ 601116491Sharti uint32_t cid; /* connection id */ 602116491Sharti}; 603116491Sharti/* Transmit buffer return queue */ 604116491Shartistruct he_tbrqen { 605116491Sharti uint32_t addr; /* handle and flags */ 606116491Sharti}; 607116491Sharti#define HE_REGM_TBRQ_ADDR 0xffffffc0 608116491Sharti#define HE_REGM_TBRQ_FLAGS 0x0000000a 609116491Sharti#define HE_REGM_TBRQ_EOS 0x00000008 610116491Sharti#define HE_REGM_TBRQ_MULT 0x00000002 611116491Sharti 612116491Shartistruct he_tpd { 613116491Sharti uint32_t addr; /* handle or virtual address and flags */ 614116491Sharti uint32_t res; /* reserved */ 615116491Sharti struct { 616116491Sharti uint32_t addr; /* buffer address */ 617116491Sharti uint32_t len; /* buffer length and flags */ 618116491Sharti } bufs[3]; 619116491Sharti}; 620116491Sharti#define HE_REGM_TPD_ADDR 0xffffffC0 621116491Sharti#define HE_REGS_TPD_ADDR 6 622116491Sharti#define HE_REGM_TPD_INTR 0x0001 623116491Sharti#define HE_REGM_TPD_CLP 0x0002 624116491Sharti#define HE_REGM_TPD_EOS 0x0004 625116491Sharti#define HE_REGM_TPD_PTI 0x0038 626116491Sharti#define HE_REGS_TPD_PTI 3 627116491Sharti#define HE_REGM_TPD_LST 0x80000000 628116491Sharti 629116491Sharti/* 630116491Sharti * The HOST STATUS PAGE 631116491Sharti */ 632116491Shartistruct he_hsp { 633116491Sharti struct { 634116491Sharti uint32_t tbrq_tail; 635116491Sharti uint32_t res1[15]; 636116491Sharti uint32_t rbrq_tail; 637116491Sharti uint32_t res2[15]; 638116491Sharti } group[8]; 639116491Sharti}; 640116491Sharti 641116491Sharti#define HE_MAX_PDU (65535) 642