if_gemvar.h revision 170273
1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp 27 * 28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 170273 2007-06-04 06:01:04Z yongari $ 29 */ 30 31#ifndef _IF_GEMVAR_H 32#define _IF_GEMVAR_H 33 34 35#include <sys/queue.h> 36#include <sys/callout.h> 37 38/* 39 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 40 */ 41 42/* 43 * Transmit descriptor list size. This is arbitrary, but allocate 44 * enough descriptors for 64 pending transmissions and 16 segments 45 * per packet. This limit is not actually enforced (packets with more segments 46 * can be sent, depending on the busdma backend); it is however used as an 47 * estimate for the tx window size. 48 */ 49#define GEM_NTXSEGS 16 50 51#define GEM_TXQUEUELEN 64 52#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 53#define GEM_MAXTXFREE (GEM_NTXDESC - 1) 54#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 55#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 56 57/* 58 * Receive descriptor list size. We have one Rx buffer per incoming 59 * packet, so this logic is a little simpler. 60 */ 61#define GEM_NRXDESC 128 62#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 63#define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK) 64#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 65 66/* 67 * How many ticks to wait until to retry on a RX descriptor that is still owned 68 * by the hardware. 69 */ 70#define GEM_RXOWN_TICKS (hz / 50) 71 72/* 73 * Control structures are DMA'd to the GEM chip. We allocate them in 74 * a single clump that maps to a single DMA segment to make several things 75 * easier. 76 */ 77struct gem_control_data { 78 /* 79 * The transmit descriptors. 80 */ 81 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 82 83 /* 84 * The receive descriptors. 85 */ 86 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 87}; 88 89#define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 90#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 91#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 92 93/* 94 * Software state for transmit job mbufs (may be elements of mbuf chains). 95 */ 96struct gem_txsoft { 97 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 98 bus_dmamap_t txs_dmamap; /* our DMA map */ 99 int txs_firstdesc; /* first descriptor in packet */ 100 int txs_lastdesc; /* last descriptor in packet */ 101 int txs_ndescs; /* number of descriptors */ 102 STAILQ_ENTRY(gem_txsoft) txs_q; 103}; 104 105STAILQ_HEAD(gem_txsq, gem_txsoft); 106 107/* 108 * Software state for receive jobs. 109 */ 110struct gem_rxsoft { 111 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 112 bus_dmamap_t rxs_dmamap; /* our DMA map */ 113 bus_addr_t rxs_paddr; /* physical address of the segment */ 114}; 115 116/* 117 * Software state per device. 118 */ 119struct gem_softc { 120 struct ifnet *sc_ifp; 121 device_t sc_miibus; 122 struct mii_data *sc_mii; /* MII media control */ 123 device_t sc_dev; /* generic device information */ 124 u_char sc_enaddr[6]; 125 struct callout sc_tick_ch; /* tick callout */ 126 struct callout sc_rx_ch; /* delayed rx callout */ 127 int sc_wdog_timer; /* watchdog timer */ 128 129 /* The following bus handles are to be provided by the bus front-end */ 130 void *sc_ih; 131 struct resource *sc_res[2]; 132 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */ 133 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */ 134 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */ 135 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */ 136 bus_dmamap_t sc_dmamap; /* bus dma handle */ 137 138 int sc_phys[2]; /* MII instance -> PHY map */ 139 140 int sc_mif_config; /* Selected MII reg setting */ 141 142 int sc_pci; /* XXXXX -- PCI buses are LE. */ 143 u_int sc_variant; /* which GEM are we dealing with? */ 144#define GEM_UNKNOWN 0 /* don't know */ 145#define GEM_SUN_GEM 1 /* Sun GEM variant */ 146#define GEM_APPLE_GMAC 2 /* Apple GMAC variant */ 147 148 u_int sc_flags; /* */ 149#define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 150 151 /* 152 * Ring buffer DMA stuff. 153 */ 154 bus_dma_segment_t sc_cdseg; /* control data memory */ 155 int sc_cdnseg; /* number of segments */ 156 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 157 bus_addr_t sc_cddma; 158 159 /* 160 * Software state for transmit and receive descriptors. 161 */ 162 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 163 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 164 165 /* 166 * Control data structures. 167 */ 168 struct gem_control_data *sc_control_data; 169#define sc_txdescs sc_control_data->gcd_txdescs 170#define sc_rxdescs sc_control_data->gcd_rxdescs 171 172 int sc_txfree; /* number of free Tx descriptors */ 173 int sc_txnext; /* next ready Tx descriptor */ 174 int sc_txwin; /* Tx descriptors since last Tx int */ 175 176 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 177 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 178 179 int sc_rxptr; /* next ready RX descriptor/descsoft */ 180 int sc_rxfifosize; /* Rx FIFO size (bytes) */ 181 182 /* ========== */ 183 int sc_inited; 184 int sc_debug; 185 int sc_ifflags; 186 int sc_csum_features; 187 188 struct mtx sc_mtx; 189}; 190 191#define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v)) 192#define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v)) 193 194#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 195#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 196 197#define GEM_CDSYNC(sc, ops) \ 198 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); \ 199 200#define GEM_INIT_RXDESC(sc, x) \ 201do { \ 202 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 203 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 204 struct mbuf *__m = __rxs->rxs_mbuf; \ 205 \ 206 __m->m_data = __m->m_ext.ext_buf; \ 207 __rxd->gd_addr = \ 208 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \ 209 __rxd->gd_flags = \ 210 GEM_DMA_WRITE((sc), \ 211 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 212 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 213} while (0) 214 215#define GEM_LOCK_INIT(_sc, _name) \ 216 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 217#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 218#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 219#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 220#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 221 222#ifdef _KERNEL 223extern devclass_t gem_devclass; 224 225int gem_attach(struct gem_softc *); 226void gem_detach(struct gem_softc *); 227void gem_suspend(struct gem_softc *); 228void gem_resume(struct gem_softc *); 229void gem_intr(void *); 230 231int gem_mediachange(struct ifnet *); 232void gem_mediastatus(struct ifnet *, struct ifmediareq *); 233 234void gem_reset(struct gem_softc *); 235 236/* MII methods & callbacks */ 237int gem_mii_readreg(device_t, int, int); 238int gem_mii_writereg(device_t, int, int, int); 239void gem_mii_statchg(device_t); 240 241#endif /* _KERNEL */ 242 243 244#endif 245