if_fxpreg.h revision 76630
1/* 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 76630 2001-05-15 18:52:40Z jlemon $ 29 */ 30 31#define FXP_VENDORID_INTEL 0x8086 32 33#define FXP_PCI_MMBA 0x10 34#define FXP_PCI_IOBA 0x14 35 36/* 37 * Control/status registers. 38 */ 39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44#define FXP_CSR_PORT 8 /* port (4 bytes) */ 45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 49 50/* 51 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 52 * 53 * volatile u_int8_t :2, 54 * scb_rus:4, 55 * scb_cus:2; 56 */ 57 58#define FXP_PORT_SOFTWARE_RESET 0 59#define FXP_PORT_SELFTEST 1 60#define FXP_PORT_SELECTIVE_RESET 2 61#define FXP_PORT_DUMP 3 62 63#define FXP_SCB_RUS_IDLE 0 64#define FXP_SCB_RUS_SUSPENDED 1 65#define FXP_SCB_RUS_NORESOURCES 2 66#define FXP_SCB_RUS_READY 4 67#define FXP_SCB_RUS_SUSP_NORBDS 9 68#define FXP_SCB_RUS_NORES_NORBDS 10 69#define FXP_SCB_RUS_READY_NORBDS 12 70 71#define FXP_SCB_CUS_IDLE 0 72#define FXP_SCB_CUS_SUSPENDED 1 73#define FXP_SCB_CUS_ACTIVE 2 74 75#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 76#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 77#define FXP_SCB_INTMASK_FCP 0x04 78#define FXP_SCB_INTMASK_ER 0x08 79#define FXP_SCB_INTMASK_RNR 0x10 80#define FXP_SCB_INTMASK_CNA 0x20 81#define FXP_SCB_INTMASK_FR 0x40 82#define FXP_SCB_INTMASK_CXTNO 0x80 83 84#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 85#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 86#define FXP_SCB_STATACK_SWI 0x04 87#define FXP_SCB_STATACK_MDI 0x08 88#define FXP_SCB_STATACK_RNR 0x10 89#define FXP_SCB_STATACK_CNA 0x20 90#define FXP_SCB_STATACK_FR 0x40 91#define FXP_SCB_STATACK_CXTNO 0x80 92 93#define FXP_SCB_COMMAND_CU_NOP 0x00 94#define FXP_SCB_COMMAND_CU_START 0x10 95#define FXP_SCB_COMMAND_CU_RESUME 0x20 96#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 97#define FXP_SCB_COMMAND_CU_DUMP 0x50 98#define FXP_SCB_COMMAND_CU_BASE 0x60 99#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 100 101#define FXP_SCB_COMMAND_RU_NOP 0 102#define FXP_SCB_COMMAND_RU_START 1 103#define FXP_SCB_COMMAND_RU_RESUME 2 104#define FXP_SCB_COMMAND_RU_ABORT 4 105#define FXP_SCB_COMMAND_RU_LOADHDS 5 106#define FXP_SCB_COMMAND_RU_BASE 6 107#define FXP_SCB_COMMAND_RU_RBDRESUME 7 108 109/* 110 * Command block definitions 111 */ 112struct fxp_cb_nop { 113 void *fill[2]; 114 volatile u_int16_t cb_status; 115 volatile u_int16_t cb_command; 116 volatile u_int32_t link_addr; 117}; 118struct fxp_cb_ias { 119 void *fill[2]; 120 volatile u_int16_t cb_status; 121 volatile u_int16_t cb_command; 122 volatile u_int32_t link_addr; 123 volatile u_int8_t macaddr[6]; 124}; 125/* I hate bit-fields :-( */ 126struct fxp_cb_config { 127 void *fill[2]; 128 volatile u_int16_t cb_status; 129 volatile u_int16_t cb_command; 130 volatile u_int32_t link_addr; 131 volatile u_int byte_count:6, 132 :2; 133 volatile u_int rx_fifo_limit:4, 134 tx_fifo_limit:3, 135 :1; 136 volatile u_int8_t adaptive_ifs; 137 volatile u_int mwi_enable:1, /* 8,9 */ 138 type_enable:1, /* 8,9 */ 139 read_align_en:1, /* 8,9 */ 140 end_wr_on_cl:1, /* 8,9 */ 141 :4; 142 volatile u_int rx_dma_bytecount:7, 143 :1; 144 volatile u_int tx_dma_bytecount:7, 145 dma_mbce:1; 146 volatile u_int late_scb:1, /* 7 */ 147 direct_dma_dis:1, /* 8,9 */ 148 tno_int_or_tco_en:1, /* 7,9 */ 149 ci_int:1, 150 ext_txcb_dis:1, /* 8,9 */ 151 ext_stats_dis:1, /* 8,9 */ 152 keep_overrun_rx:1, 153 save_bf:1; 154 volatile u_int disc_short_rx:1, 155 underrun_retry:2, 156 :3, 157 two_frames:1, /* 8,9 */ 158 dyn_tbd:1; /* 8,9 */ 159 volatile u_int mediatype:1, /* 7 */ 160 :6, 161 csma_dis:1; /* 8,9 */ 162 volatile u_int tcp_udp_cksum:1, /* 9 */ 163 :3, 164 vlan_tco:1, /* 8,9 */ 165 link_wake_en:1, /* 8,9 */ 166 arp_wake_en:1, /* 8 */ 167 mc_wake_en:1; /* 8 */ 168 volatile u_int :3, 169 nsai:1, 170 preamble_length:2, 171 loopback:2; 172 volatile u_int linear_priority:3, /* 7 */ 173 :5; 174 volatile u_int linear_pri_mode:1, /* 7 */ 175 :3, 176 interfrm_spacing:4; 177 volatile u_int :8; 178 volatile u_int :8; 179 volatile u_int promiscuous:1, 180 bcast_disable:1, 181 wait_after_win:1, /* 8,9 */ 182 :1, 183 ignore_ul:1, /* 8,9 */ 184 crc16_en:1, /* 9 */ 185 :1, 186 crscdt:1; 187 volatile u_int fc_delay_lsb:8; /* 8,9 */ 188 volatile u_int fc_delay_msb:8; /* 8,9 */ 189 volatile u_int stripping:1, 190 padding:1, 191 rcv_crc_xfer:1, 192 long_rx_en:1, /* 8,9 */ 193 pri_fc_thresh:3, /* 8,9 */ 194 :1; 195 volatile u_int ia_wake_en:1, /* 8 */ 196 magic_pkt_dis:1, /* 8,9,!9ER */ 197 tx_fc_dis:1, /* 8,9 */ 198 rx_fc_restop:1, /* 8,9 */ 199 rx_fc_restart:1, /* 8,9 */ 200 fc_filter:1, /* 8,9 */ 201 force_fdx:1, 202 fdx_pin_en:1; 203 volatile u_int :5, 204 pri_fc_loc:1, /* 8,9 */ 205 multi_ia:1, 206 :1; 207 volatile u_int :3, 208 mc_all:1, 209 :4; 210}; 211 212#define MAXMCADDR 80 213struct fxp_cb_mcs { 214 struct fxp_cb_tx *next; 215 struct mbuf *mb_head; 216 volatile u_int16_t cb_status; 217 volatile u_int16_t cb_command; 218 volatile u_int32_t link_addr; 219 volatile u_int16_t mc_cnt; 220 volatile u_int8_t mc_addr[MAXMCADDR][6]; 221}; 222 223/* 224 * Number of DMA segments in a TxCB. Note that this is carefully 225 * chosen to make the total struct size an even power of two. It's 226 * critical that no TxCB be split across a page boundry since 227 * no attempt is made to allocate physically contiguous memory. 228 * 229 */ 230#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 231#define FXP_NTXSEG 28 232#else 233#define FXP_NTXSEG 29 234#endif 235 236struct fxp_tbd { 237 volatile u_int32_t tb_addr; 238 volatile u_int32_t tb_size; 239}; 240struct fxp_cb_tx { 241 struct fxp_cb_tx *next; 242 struct mbuf *mb_head; 243 volatile u_int16_t cb_status; 244 volatile u_int16_t cb_command; 245 volatile u_int32_t link_addr; 246 volatile u_int32_t tbd_array_addr; 247 volatile u_int16_t byte_count; 248 volatile u_int8_t tx_threshold; 249 volatile u_int8_t tbd_number; 250 /* 251 * The following structure isn't actually part of the TxCB, 252 * unless the extended TxCB feature is being used. In this 253 * case, the first two elements of the structure below are 254 * fetched along with the TxCB. 255 */ 256 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 257}; 258 259/* 260 * Control Block (CB) definitions 261 */ 262 263/* status */ 264#define FXP_CB_STATUS_OK 0x2000 265#define FXP_CB_STATUS_C 0x8000 266/* commands */ 267#define FXP_CB_COMMAND_NOP 0x0 268#define FXP_CB_COMMAND_IAS 0x1 269#define FXP_CB_COMMAND_CONFIG 0x2 270#define FXP_CB_COMMAND_MCAS 0x3 271#define FXP_CB_COMMAND_XMIT 0x4 272#define FXP_CB_COMMAND_RESRV 0x5 273#define FXP_CB_COMMAND_DUMP 0x6 274#define FXP_CB_COMMAND_DIAG 0x7 275/* command flags */ 276#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 277#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 278#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 279#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 280 281/* 282 * RFA definitions 283 */ 284 285struct fxp_rfa { 286 volatile u_int16_t rfa_status; 287 volatile u_int16_t rfa_control; 288 volatile u_int8_t link_addr[4]; 289 volatile u_int8_t rbd_addr[4]; 290 volatile u_int16_t actual_size; 291 volatile u_int16_t size; 292}; 293#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 294#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 295#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 296#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 297#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 298#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 299#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 300#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 301#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 302#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 303#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 304#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 305#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 306#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 307#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 308 309/* 310 * Statistics dump area definitions 311 */ 312struct fxp_stats { 313 volatile u_int32_t tx_good; 314 volatile u_int32_t tx_maxcols; 315 volatile u_int32_t tx_latecols; 316 volatile u_int32_t tx_underruns; 317 volatile u_int32_t tx_lostcrs; 318 volatile u_int32_t tx_deffered; 319 volatile u_int32_t tx_single_collisions; 320 volatile u_int32_t tx_multiple_collisions; 321 volatile u_int32_t tx_total_collisions; 322 volatile u_int32_t rx_good; 323 volatile u_int32_t rx_crc_errors; 324 volatile u_int32_t rx_alignment_errors; 325 volatile u_int32_t rx_rnr_errors; 326 volatile u_int32_t rx_overrun_errors; 327 volatile u_int32_t rx_cdt_errors; 328 volatile u_int32_t rx_shortframes; 329 volatile u_int32_t completion_status; 330}; 331#define FXP_STATS_DUMP_COMPLETE 0xa005 332#define FXP_STATS_DR_COMPLETE 0xa007 333 334/* 335 * Serial EEPROM control register bits 336 */ 337#define FXP_EEPROM_EESK 0x01 /* shift clock */ 338#define FXP_EEPROM_EECS 0x02 /* chip select */ 339#define FXP_EEPROM_EEDI 0x04 /* data in */ 340#define FXP_EEPROM_EEDO 0x08 /* data out */ 341 342/* 343 * Serial EEPROM opcodes, including start bit 344 */ 345#define FXP_EEPROM_OPC_ERASE 0x4 346#define FXP_EEPROM_OPC_WRITE 0x5 347#define FXP_EEPROM_OPC_READ 0x6 348 349/* 350 * Management Data Interface opcodes 351 */ 352#define FXP_MDI_WRITE 0x1 353#define FXP_MDI_READ 0x2 354 355/* 356 * PHY device types 357 */ 358#define FXP_PHY_DEVICE_MASK 0x3f00 359#define FXP_PHY_SERIAL_ONLY 0x8000 360#define FXP_PHY_NONE 0 361#define FXP_PHY_82553A 1 362#define FXP_PHY_82553C 2 363#define FXP_PHY_82503 3 364#define FXP_PHY_DP83840 4 365#define FXP_PHY_80C240 5 366#define FXP_PHY_80C24 6 367#define FXP_PHY_82555 7 368#define FXP_PHY_DP83840A 10 369#define FXP_PHY_82555B 11 370