if_fxpreg.h revision 76526
1205859Sjoel/* 2159687Snetchild * Copyright (c) 1995, David Greenman 3159687Snetchild * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4159687Snetchild * All rights reserved. 5159687Snetchild * 6159687Snetchild * Redistribution and use in source and binary forms, with or without 7159687Snetchild * modification, are permitted provided that the following conditions 8159687Snetchild * are met: 9159687Snetchild * 1. Redistributions of source code must retain the above copyright 10159687Snetchild * notice unmodified, this list of conditions, and the following 11159687Snetchild * disclaimer. 12159687Snetchild * 2. Redistributions in binary form must reproduce the above copyright 13159687Snetchild * notice, this list of conditions and the following disclaimer in the 14159687Snetchild * documentation and/or other materials provided with the distribution. 15159687Snetchild * 16159687Snetchild * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17159687Snetchild * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18159687Snetchild * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19159687Snetchild * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20159687Snetchild * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21159687Snetchild * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22159687Snetchild * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23159687Snetchild * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24159687Snetchild * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25159687Snetchild * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26159687Snetchild * SUCH DAMAGE. 27159687Snetchild * 28159687Snetchild * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 76526 2001-05-12 23:59:48Z jlemon $ 29159687Snetchild */ 30159687Snetchild 31159687Snetchild#define FXP_VENDORID_INTEL 0x8086 32159687Snetchild 33159687Snetchild#define FXP_PCI_MMBA 0x10 34159687Snetchild#define FXP_PCI_IOBA 0x14 35159687Snetchild 36159687Snetchild/* 37159687Snetchild * Control/status registers. 38159687Snetchild */ 39159687Snetchild#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 40159687Snetchild#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 41159687Snetchild#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 42159687Snetchild#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 43159687Snetchild#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44159687Snetchild#define FXP_CSR_PORT 8 /* port (4 bytes) */ 45159687Snetchild#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46159687Snetchild#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47159687Snetchild#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48159687Snetchild#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 49159687Snetchild 50159687Snetchild/* 51159687Snetchild * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 52159687Snetchild * 53159687Snetchild * volatile u_int8_t :2, 54159687Snetchild * scb_rus:4, 55159687Snetchild * scb_cus:2; 56159687Snetchild */ 57159687Snetchild 58159687Snetchild#define FXP_PORT_SOFTWARE_RESET 0 59159687Snetchild#define FXP_PORT_SELFTEST 1 60159687Snetchild#define FXP_PORT_SELECTIVE_RESET 2 61159687Snetchild#define FXP_PORT_DUMP 3 62159687Snetchild 63159687Snetchild#define FXP_SCB_RUS_IDLE 0 64159687Snetchild#define FXP_SCB_RUS_SUSPENDED 1 65159687Snetchild#define FXP_SCB_RUS_NORESOURCES 2 66159687Snetchild#define FXP_SCB_RUS_READY 4 67159687Snetchild#define FXP_SCB_RUS_SUSP_NORBDS 9 68159687Snetchild#define FXP_SCB_RUS_NORES_NORBDS 10 69159687Snetchild#define FXP_SCB_RUS_READY_NORBDS 12 70159687Snetchild 71159687Snetchild#define FXP_SCB_CUS_IDLE 0 72159687Snetchild#define FXP_SCB_CUS_SUSPENDED 1 73159687Snetchild#define FXP_SCB_CUS_ACTIVE 2 74159687Snetchild 75159687Snetchild#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 76159687Snetchild#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 77159687Snetchild#define FXP_SCB_INTMASK_FCP 0x04 78159687Snetchild#define FXP_SCB_INTMASK_ER 0x08 79159687Snetchild#define FXP_SCB_INTMASK_RNR 0x10 80159687Snetchild#define FXP_SCB_INTMASK_CNA 0x20 81159687Snetchild#define FXP_SCB_INTMASK_FR 0x40 82159687Snetchild#define FXP_SCB_INTMASK_CXTNO 0x80 83159687Snetchild 84159687Snetchild#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 85159687Snetchild#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 86159687Snetchild#define FXP_SCB_STATACK_SWI 0x04 87159687Snetchild#define FXP_SCB_STATACK_MDI 0x08 88159687Snetchild#define FXP_SCB_STATACK_RNR 0x10 89159687Snetchild#define FXP_SCB_STATACK_CNA 0x20 90159687Snetchild#define FXP_SCB_STATACK_FR 0x40 91159687Snetchild#define FXP_SCB_STATACK_CXTNO 0x80 92159687Snetchild 93159687Snetchild#define FXP_SCB_COMMAND_CU_NOP 0x00 94159687Snetchild#define FXP_SCB_COMMAND_CU_START 0x10 95159687Snetchild#define FXP_SCB_COMMAND_CU_RESUME 0x20 96159687Snetchild#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 97159687Snetchild#define FXP_SCB_COMMAND_CU_DUMP 0x50 98159687Snetchild#define FXP_SCB_COMMAND_CU_BASE 0x60 99159687Snetchild#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 100159687Snetchild 101159687Snetchild#define FXP_SCB_COMMAND_RU_NOP 0 102159687Snetchild#define FXP_SCB_COMMAND_RU_START 1 103159687Snetchild#define FXP_SCB_COMMAND_RU_RESUME 2 104159687Snetchild#define FXP_SCB_COMMAND_RU_ABORT 4 105159687Snetchild#define FXP_SCB_COMMAND_RU_LOADHDS 5 106159687Snetchild#define FXP_SCB_COMMAND_RU_BASE 6 107159687Snetchild#define FXP_SCB_COMMAND_RU_RBDRESUME 7 108159687Snetchild 109159687Snetchild/* 110159687Snetchild * Command block definitions 111159687Snetchild */ 112159687Snetchildstruct fxp_cb_nop { 113159687Snetchild void *fill[2]; 114159687Snetchild volatile u_int16_t cb_status; 115159687Snetchild volatile u_int16_t cb_command; 116159687Snetchild volatile u_int32_t link_addr; 117159687Snetchild}; 118159687Snetchildstruct fxp_cb_ias { 119159687Snetchild void *fill[2]; 120159687Snetchild volatile u_int16_t cb_status; 121159687Snetchild volatile u_int16_t cb_command; 122159687Snetchild volatile u_int32_t link_addr; 123159687Snetchild volatile u_int8_t macaddr[6]; 124159687Snetchild}; 125159687Snetchild/* I hate bit-fields :-( */ 126159687Snetchildstruct fxp_cb_config { 127159687Snetchild void *fill[2]; 128159687Snetchild volatile u_int16_t cb_status; 129159687Snetchild volatile u_int16_t cb_command; 130159687Snetchild volatile u_int32_t link_addr; 131159687Snetchild volatile u_int byte_count:6, 132159687Snetchild :2; 133159687Snetchild volatile u_int rx_fifo_limit:4, 134159687Snetchild tx_fifo_limit:3, 135159687Snetchild :1; 136159687Snetchild volatile u_int8_t adaptive_ifs; 137159687Snetchild volatile u_int mwi_enable:1, /* 8,9 */ 138159687Snetchild type_enable:1, /* 8,9 */ 139159687Snetchild read_align_en:1, /* 8,9 */ 140159687Snetchild end_wr_on_cl:1, /* 8,9 */ 141159687Snetchild :4; 142159687Snetchild volatile u_int rx_dma_bytecount:7, 143159687Snetchild :1; 144159687Snetchild volatile u_int tx_dma_bytecount:7, 145159687Snetchild dma_mbce:1; 146159687Snetchild volatile u_int late_scb:1, /* 7 */ 147159687Snetchild direct_dma_dis:1, /* 8,9 */ 148159687Snetchild tno_int_or_tco_en:1, /* 7,9 */ 149159687Snetchild ci_int:1, 150159687Snetchild ext_txcb_dis:1, /* 8,9 */ 151159687Snetchild ext_stats_dis:1, /* 8,9 */ 152159687Snetchild keep_overrun_rx:1, 153159687Snetchild save_bf:1; 154159687Snetchild volatile u_int disc_short_rx:1, 155159687Snetchild underrun_retry:2, 156159687Snetchild :3, 157159687Snetchild two_frames:1, /* 8,9 */ 158159687Snetchild dyn_tbd:1; /* 8,9 */ 159159687Snetchild volatile u_int mediatype:1, /* 7 */ 160159687Snetchild :6, 161159687Snetchild csma_dis:1; /* 8,9 */ 162159687Snetchild volatile u_int tcp_udp_cksum:1, /* 9 */ 163159687Snetchild :3, 164159687Snetchild vlan_tco:1, /* 8,9 */ 165159687Snetchild link_wake_en:1, /* 8,9 */ 166159687Snetchild arp_wake_en:1, /* 8 */ 167159687Snetchild mc_wake_en:1; /* 8 */ 168159687Snetchild volatile u_int :3, 169159687Snetchild nsai:1, 170159687Snetchild preamble_length:2, 171159687Snetchild loopback:2; 172159687Snetchild volatile u_int linear_priority:3, /* 7 */ 173159687Snetchild :5; 174159687Snetchild volatile u_int linear_pri_mode:1, /* 7 */ 175159687Snetchild :3, 176159687Snetchild interfrm_spacing:4; 177159687Snetchild volatile u_int :8; 178159687Snetchild volatile u_int :8; 179159687Snetchild volatile u_int promiscuous:1, 180159687Snetchild bcast_disable:1, 181159687Snetchild wait_after_win:1, /* 8,9 */ 182159687Snetchild :1, 183159687Snetchild ignore_ul:1, /* 8,9 */ 184159687Snetchild crc16_en:1, /* 9 */ 185159687Snetchild :1, 186159687Snetchild crscdt:1; 187159687Snetchild volatile u_int fc_delay_lsb:8; /* 8,9 */ 188159687Snetchild volatile u_int fc_delay_msb:8; /* 8,9 */ 189159687Snetchild volatile u_int stripping:1, 190159687Snetchild padding:1, 191159687Snetchild rcv_crc_xfer:1, 192159687Snetchild long_rx_en:1, /* 8,9 */ 193159687Snetchild pri_fc_thresh:3, /* 8,9 */ 194159687Snetchild :1; 195159687Snetchild volatile u_int ia_wake_en:1, /* 8 */ 196159687Snetchild magic_pkt_dis:1, /* 8,9,!9ER */ 197159687Snetchild tx_fc_dis:1, /* 8,9 */ 198159687Snetchild rx_fc_restop:1, /* 8,9 */ 199159687Snetchild rx_fc_restart:1, /* 8,9 */ 200159687Snetchild fc_filter:1, /* 8,9 */ 201159687Snetchild force_fdx:1, 202159687Snetchild fdx_pin_en:1; 203159687Snetchild volatile u_int :5, 204159687Snetchild pri_fc_loc:1, /* 8,9 */ 205159687Snetchild multi_ia:1, 206159687Snetchild :1; 207159687Snetchild volatile u_int :3, 208159687Snetchild mc_all:1, 209159687Snetchild :4; 210159687Snetchild}; 211159687Snetchild 212159687Snetchild#define MAXMCADDR 80 213159687Snetchildstruct fxp_cb_mcs { 214159687Snetchild struct fxp_cb_tx *next; 215159687Snetchild struct mbuf *mb_head; 216159687Snetchild volatile u_int16_t cb_status; 217159687Snetchild volatile u_int16_t cb_command; 218159687Snetchild volatile u_int32_t link_addr; 219159687Snetchild volatile u_int16_t mc_cnt; 220159687Snetchild volatile u_int8_t mc_addr[MAXMCADDR][6]; 221159687Snetchild}; 222159687Snetchild 223159687Snetchild/* 224159687Snetchild * Number of DMA segments in a TxCB. Note that this is carefully 225159687Snetchild * chosen to make the total struct size an even power of two. It's 226159687Snetchild * critical that no TxCB be split across a page boundry since 227159687Snetchild * no attempt is made to allocate physically contiguous memory. 228159687Snetchild * 229159687Snetchild */ 230159687Snetchild#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 231159687Snetchild#define FXP_NTXSEG 28 232159687Snetchild#else 233159687Snetchild#define FXP_NTXSEG 29 234159687Snetchild#endif 235159687Snetchild 236159687Snetchildstruct fxp_tbd { 237159687Snetchild volatile u_int32_t tb_addr; 238159687Snetchild volatile u_int32_t tb_size; 239159687Snetchild}; 240159687Snetchildstruct fxp_cb_tx { 241159687Snetchild struct fxp_cb_tx *next; 242159687Snetchild struct mbuf *mb_head; 243159687Snetchild volatile u_int16_t cb_status; 244159687Snetchild volatile u_int16_t cb_command; 245159687Snetchild volatile u_int32_t link_addr; 246159687Snetchild volatile u_int32_t tbd_array_addr; 247159687Snetchild volatile u_int16_t byte_count; 248159687Snetchild volatile u_int8_t tx_threshold; 249159687Snetchild volatile u_int8_t tbd_number; 250159687Snetchild /* 251159687Snetchild * The following structure isn't actually part of the TxCB, 252159687Snetchild * unless the extended TxCB feature is being used. In this 253159687Snetchild * case, the first two elements of the structure below are 254159687Snetchild * fetched along with the TxCB. 255159687Snetchild */ 256159687Snetchild volatile struct fxp_tbd tbd[FXP_NTXSEG]; 257159687Snetchild}; 258159687Snetchild 259159687Snetchild/* 260159687Snetchild * Control Block (CB) definitions 261159687Snetchild */ 262159687Snetchild 263159687Snetchild/* status */ 264159687Snetchild#define FXP_CB_STATUS_OK 0x2000 265159687Snetchild#define FXP_CB_STATUS_C 0x8000 266159687Snetchild/* commands */ 267159687Snetchild#define FXP_CB_COMMAND_NOP 0x0 268159687Snetchild#define FXP_CB_COMMAND_IAS 0x1 269159687Snetchild#define FXP_CB_COMMAND_CONFIG 0x2 270159687Snetchild#define FXP_CB_COMMAND_MCAS 0x3 271159687Snetchild#define FXP_CB_COMMAND_XMIT 0x4 272159687Snetchild#define FXP_CB_COMMAND_RESRV 0x5 273159687Snetchild#define FXP_CB_COMMAND_DUMP 0x6 274159687Snetchild#define FXP_CB_COMMAND_DIAG 0x7 275159687Snetchild/* command flags */ 276159687Snetchild#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 277159687Snetchild#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 278159687Snetchild#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 279159687Snetchild#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 280159687Snetchild 281159687Snetchild/* 282159687Snetchild * RFA definitions 283159687Snetchild */ 284159687Snetchild 285159687Snetchildstruct fxp_rfa { 286159687Snetchild volatile u_int16_t rfa_status; 287159687Snetchild volatile u_int16_t rfa_control; 288159687Snetchild volatile u_int8_t link_addr[4]; 289159687Snetchild volatile u_int8_t rbd_addr[4]; 290159687Snetchild volatile u_int16_t actual_size; 291159687Snetchild volatile u_int16_t size; 292159687Snetchild}; 293159687Snetchild#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 294159687Snetchild#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 295159687Snetchild#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 296159687Snetchild#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 297159687Snetchild#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 298159687Snetchild#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 299159687Snetchild#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 300159687Snetchild#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 301159687Snetchild#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 302159687Snetchild#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 303159687Snetchild#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 304159687Snetchild#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 305159687Snetchild#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 306159687Snetchild#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 307159687Snetchild#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 308159687Snetchild 309159687Snetchild/* 310159687Snetchild * Statistics dump area definitions 311159687Snetchild */ 312159687Snetchildstruct fxp_stats { 313159687Snetchild volatile u_int32_t tx_good; 314159687Snetchild volatile u_int32_t tx_maxcols; 315159687Snetchild volatile u_int32_t tx_latecols; 316159687Snetchild volatile u_int32_t tx_underruns; 317159687Snetchild volatile u_int32_t tx_lostcrs; 318159687Snetchild volatile u_int32_t tx_deffered; 319159687Snetchild volatile u_int32_t tx_single_collisions; 320159687Snetchild volatile u_int32_t tx_multiple_collisions; 321159687Snetchild volatile u_int32_t tx_total_collisions; 322159687Snetchild volatile u_int32_t rx_good; 323159687Snetchild volatile u_int32_t rx_crc_errors; 324159687Snetchild volatile u_int32_t rx_alignment_errors; 325159687Snetchild volatile u_int32_t rx_rnr_errors; 326159687Snetchild volatile u_int32_t rx_overrun_errors; 327159687Snetchild volatile u_int32_t rx_cdt_errors; 328159687Snetchild volatile u_int32_t rx_shortframes; 329159687Snetchild volatile u_int32_t completion_status; 330159687Snetchild}; 331159687Snetchild#define FXP_STATS_DUMP_COMPLETE 0xa005 332159687Snetchild#define FXP_STATS_DR_COMPLETE 0xa007 333159687Snetchild 334159687Snetchild/* 335159687Snetchild * Serial EEPROM control register bits 336159687Snetchild */ 337159687Snetchild#define FXP_EEPROM_EESK 0x01 /* shift clock */ 338159687Snetchild#define FXP_EEPROM_EECS 0x02 /* chip select */ 339159687Snetchild#define FXP_EEPROM_EEDI 0x04 /* data in */ 340159687Snetchild#define FXP_EEPROM_EEDO 0x08 /* data out */ 341159687Snetchild 342159687Snetchild/* 343159687Snetchild * Serial EEPROM opcodes, including start bit 344159687Snetchild */ 345159687Snetchild#define FXP_EEPROM_OPC_ERASE 0x4 346159687Snetchild#define FXP_EEPROM_OPC_WRITE 0x5 347159687Snetchild#define FXP_EEPROM_OPC_READ 0x6 348159687Snetchild 349159687Snetchild/* 350159687Snetchild * Management Data Interface opcodes 351159687Snetchild */ 352159687Snetchild#define FXP_MDI_WRITE 0x1 353159687Snetchild#define FXP_MDI_READ 0x2 354159687Snetchild 355159687Snetchild/* 356159687Snetchild * PHY device types 357159687Snetchild */ 358159687Snetchild#define FXP_PHY_DEVICE_MASK 0x03f0 359159687Snetchild#define FXP_PHY_SERIAL_ONLY 0x8000 360159687Snetchild#define FXP_PHY_NONE 0 361159687Snetchild#define FXP_PHY_82553A 1 362159687Snetchild#define FXP_PHY_82553C 2 363159687Snetchild#define FXP_PHY_82503 3 364159687Snetchild#define FXP_PHY_DP83840 4 365159687Snetchild#define FXP_PHY_80C240 5 366159687Snetchild#define FXP_PHY_80C24 6 367159687Snetchild#define FXP_PHY_82555 7 368159687Snetchild#define FXP_PHY_DP83840A 10 369159687Snetchild#define FXP_PHY_82555B 11 370159687Snetchild