if_fxpreg.h revision 23964
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_fxpreg.h,v 1.6 1997/02/22 09:44:06 peter Exp $ 28 */ 29 30#define FXP_VENDORID_INTEL 0x8086 31#define FXP_DEVICEID_i82557 0x1229 32 33#define FXP_PCI_MMBA 0x10 34#define FXP_PCI_IOBA 0x14 35 36struct fxp_csr { 37 volatile u_int8_t :2, 38 scb_rus:4, 39 scb_cus:2; 40 volatile u_int8_t scb_statack; 41 volatile u_int8_t scb_command; 42 volatile u_int8_t scb_intrcntl; 43 volatile u_int32_t scb_general; 44 volatile u_int32_t port; 45 volatile u_int16_t flash_control; 46 volatile u_int16_t eeprom_control; 47 volatile u_int32_t mdi_control; 48}; 49 50#define FXP_PORT_SOFTWARE_RESET 0 51#define FXP_PORT_SELFTEST 1 52#define FXP_PORT_SELECTIVE_RESET 2 53#define FXP_PORT_DUMP 3 54 55#define FXP_SCB_RUS_IDLE 0 56#define FXP_SCB_RUS_SUSPENDED 1 57#define FXP_SCB_RUS_NORESOURCES 2 58#define FXP_SCB_RUS_READY 4 59#define FXP_SCB_RUS_SUSP_NORBDS 9 60#define FXP_SCB_RUS_NORES_NORBDS 10 61#define FXP_SCB_RUS_READY_NORBDS 12 62 63#define FXP_SCB_CUS_IDLE 0 64#define FXP_SCB_CUS_SUSPENDED 1 65#define FXP_SCB_CUS_ACTIVE 2 66 67#define FXP_SCB_STATACK_SWI 0x04 68#define FXP_SCB_STATACK_MDI 0x08 69#define FXP_SCB_STATACK_RNR 0x10 70#define FXP_SCB_STATACK_CNA 0x20 71#define FXP_SCB_STATACK_FR 0x40 72#define FXP_SCB_STATACK_CXTNO 0x80 73 74#define FXP_SCB_COMMAND_MASK 0xff 75#define FXP_SCB_COMMAND_CU_NOP 0x00 76#define FXP_SCB_COMMAND_CU_START 0x10 77#define FXP_SCB_COMMAND_CU_RESUME 0x20 78#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 79#define FXP_SCB_COMMAND_CU_DUMP 0x50 80#define FXP_SCB_COMMAND_CU_BASE 0x60 81#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 82 83#define FXP_SCB_COMMAND_RU_NOP 0 84#define FXP_SCB_COMMAND_RU_START 1 85#define FXP_SCB_COMMAND_RU_RESUME 2 86#define FXP_SCB_COMMAND_RU_ABORT 4 87#define FXP_SCB_COMMAND_RU_LOADHDS 5 88#define FXP_SCB_COMMAND_RU_BASE 6 89#define FXP_SCB_COMMAND_RU_RBDRESUME 7 90 91/* 92 * Command block definitions 93 */ 94struct fxp_cb_nop { 95 volatile u_int16_t cb_status; 96 volatile u_int16_t cb_command; 97 volatile u_int32_t link_addr; 98}; 99struct fxp_cb_ias { 100 volatile u_int16_t cb_status; 101 volatile u_int16_t cb_command; 102 volatile u_int32_t link_addr; 103 volatile u_int8_t macaddr[6]; 104}; 105/* I hate bit-fields :-( */ 106struct fxp_cb_config { 107 volatile u_int16_t cb_status; 108 volatile u_int16_t cb_command; 109 volatile u_int32_t link_addr; 110 volatile u_int8_t byte_count:6, 111 :2; 112 volatile u_int8_t rx_fifo_limit:4, 113 tx_fifo_limit:3, 114 :1; 115 volatile u_int8_t adaptive_ifs; 116 volatile u_int8_t :8; 117 volatile u_int8_t rx_dma_bytecount:7, 118 :1; 119 volatile u_int8_t tx_dma_bytecount:7, 120 dma_bce:1; 121 volatile u_int8_t late_scb:1, 122 :1, 123 tno_int:1, 124 ci_int:1, 125 :3, 126 save_bf:1; 127 volatile u_int8_t disc_short_rx:1, 128 underrun_retry:2, 129 :5; 130 volatile u_int8_t mediatype:1, 131 :7; 132 volatile u_int8_t :8; 133 volatile u_int8_t :3, 134 nsai:1, 135 preamble_length:2, 136 loopback:2; 137 volatile u_int8_t linear_priority:3, 138 :5; 139 volatile u_int8_t linear_pri_mode:1, 140 :3, 141 interfrm_spacing:4; 142 volatile u_int8_t :8; 143 volatile u_int8_t :8; 144 volatile u_int8_t promiscuous:1, 145 bcast_disable:1, 146 :5, 147 crscdt:1; 148 volatile u_int8_t :8; 149 volatile u_int8_t :8; 150 volatile u_int8_t stripping:1, 151 padding:1, 152 rcv_crc_xfer:1, 153 :5; 154 volatile u_int8_t :6, 155 force_fdx:1, 156 fdx_pin_en:1; 157 volatile u_int8_t :6, 158 multi_ia:1, 159 :1; 160 volatile u_int8_t :3, 161 mc_all:1, 162 :4; 163}; 164struct fxp_tbd { 165 volatile u_int32_t tb_addr; 166 volatile u_int32_t tb_size; 167}; 168 169struct fxp_cb_tx { 170 volatile u_int16_t cb_status; 171 volatile u_int16_t cb_command; 172 volatile u_int32_t link_addr; 173 volatile u_int32_t tbd_array_addr; 174 volatile u_int16_t byte_count; 175 volatile u_int8_t tx_threshold; 176 volatile u_int8_t tbd_number; 177 /* 178 * The following isn't actually part of the TxCB. 179 */ 180 volatile struct fxp_tbd tbd[29]; 181 struct mbuf *mb_head; 182 struct fxp_cb_tx *next; 183}; 184 185/* 186 * Control Block (CB) definitions 187 */ 188 189/* status */ 190#define FXP_CB_STATUS_OK 0x2000 191#define FXP_CB_STATUS_C 0x8000 192/* commands */ 193#define FXP_CB_COMMAND_NOP 0x0 194#define FXP_CB_COMMAND_IAS 0x1 195#define FXP_CB_COMMAND_CONFIG 0x2 196#define FXP_CB_COMMAND_MAS 0x3 197#define FXP_CB_COMMAND_XMIT 0x4 198#define FXP_CB_COMMAND_RESRV 0x5 199#define FXP_CB_COMMAND_DUMP 0x6 200#define FXP_CB_COMMAND_DIAG 0x7 201/* command flags */ 202#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 203#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 204#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 205#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 206 207/* 208 * RFA definitions 209 */ 210 211struct fxp_rfa { 212 volatile u_int16_t rfa_status; 213 volatile u_int16_t rfa_control; 214 volatile u_int32_t link_addr; 215 volatile u_int32_t rbd_addr; 216 volatile u_int16_t actual_size; 217 volatile u_int16_t size; 218}; 219#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 220#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 221#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 222#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 223#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 224#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 225#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 226#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 227#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 228#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 229#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 230#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 231#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 232#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 233#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 234 235/* 236 * Statistics dump area definitions 237 */ 238struct fxp_stats { 239 volatile u_int32_t tx_good; 240 volatile u_int32_t tx_maxcols; 241 volatile u_int32_t tx_latecols; 242 volatile u_int32_t tx_underruns; 243 volatile u_int32_t tx_lostcrs; 244 volatile u_int32_t tx_deffered; 245 volatile u_int32_t tx_single_collisions; 246 volatile u_int32_t tx_multiple_collisions; 247 volatile u_int32_t tx_total_collisions; 248 volatile u_int32_t rx_good; 249 volatile u_int32_t rx_crc_errors; 250 volatile u_int32_t rx_alignment_errors; 251 volatile u_int32_t rx_rnr_errors; 252 volatile u_int32_t rx_overrun_errors; 253 volatile u_int32_t rx_cdt_errors; 254 volatile u_int32_t rx_shortframes; 255 volatile u_int32_t completion_status; 256}; 257#define FXP_STATS_DUMP_COMPLETE 0xa005 258#define FXP_STATS_DR_COMPLETE 0xa007 259 260/* 261 * Serial EEPROM control register bits 262 */ 263/* shift clock */ 264#define FXP_EEPROM_EESK 0x01 265/* chip select */ 266#define FXP_EEPROM_EECS 0x02 267/* data in */ 268#define FXP_EEPROM_EEDI 0x04 269/* data out */ 270#define FXP_EEPROM_EEDO 0x08 271 272/* 273 * Serial EEPROM opcodes, including start bit 274 */ 275#define FXP_EEPROM_OPC_ERASE 0x4 276#define FXP_EEPROM_OPC_WRITE 0x5 277#define FXP_EEPROM_OPC_READ 0x6 278 279/* 280 * Management Data Interface opcodes 281 */ 282#define FXP_MDI_WRITE 0x1 283#define FXP_MDI_READ 0x2 284 285/* 286 * PHY device types 287 */ 288#define FXP_PHY_NONE 0 289#define FXP_PHY_82553A 1 290#define FXP_PHY_82553C 2 291#define FXP_PHY_82503 3 292#define FXP_PHY_DP83840 4 293#define FXP_PHY_80C240 5 294#define FXP_PHY_80C24 6 295 296/* 297 * DP84830 PHY, PCS Configuration Register 298 */ 299#define FXP_DP83840_PCR 0x17 300#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */ 301#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */ 302#define FXP_DP83840_PCR_BIT8 0x0100 303#define FXP_DP83840_PCR_BIT10 0x0400 304