if_fxpreg.h revision 185540
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 185540 2008-12-02 02:30:12Z yongari $ 29 */ 30 31#define FXP_VENDORID_INTEL 0x8086 32 33#define FXP_PCI_MMBA 0x10 34#define FXP_PCI_IOBA 0x14 35 36/* 37 * Control/status registers. 38 */ 39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44#define FXP_CSR_PORT 8 /* port (4 bytes) */ 45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 49#define FXP_CSR_PMDR 0x1B /* power management driver (1 byte) */ 50#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 51 52/* 53 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 54 * 55 * volatile uint8_t :2, 56 * scb_rus:4, 57 * scb_cus:2; 58 */ 59 60#define FXP_PORT_SOFTWARE_RESET 0 61#define FXP_PORT_SELFTEST 1 62#define FXP_PORT_SELECTIVE_RESET 2 63#define FXP_PORT_DUMP 3 64 65#define FXP_SCB_RUS_IDLE 0 66#define FXP_SCB_RUS_SUSPENDED 1 67#define FXP_SCB_RUS_NORESOURCES 2 68#define FXP_SCB_RUS_READY 4 69#define FXP_SCB_RUS_SUSP_NORBDS 9 70#define FXP_SCB_RUS_NORES_NORBDS 10 71#define FXP_SCB_RUS_READY_NORBDS 12 72 73#define FXP_SCB_CUS_IDLE 0 74#define FXP_SCB_CUS_SUSPENDED 1 75#define FXP_SCB_CUS_ACTIVE 2 76 77#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 78#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 79#define FXP_SCB_INTMASK_FCP 0x04 80#define FXP_SCB_INTMASK_ER 0x08 81#define FXP_SCB_INTMASK_RNR 0x10 82#define FXP_SCB_INTMASK_CNA 0x20 83#define FXP_SCB_INTMASK_FR 0x40 84#define FXP_SCB_INTMASK_CXTNO 0x80 85 86#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 87#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 88#define FXP_SCB_STATACK_SWI 0x04 89#define FXP_SCB_STATACK_MDI 0x08 90#define FXP_SCB_STATACK_RNR 0x10 91#define FXP_SCB_STATACK_CNA 0x20 92#define FXP_SCB_STATACK_FR 0x40 93#define FXP_SCB_STATACK_CXTNO 0x80 94 95#define FXP_SCB_COMMAND_CU_NOP 0x00 96#define FXP_SCB_COMMAND_CU_START 0x10 97#define FXP_SCB_COMMAND_CU_RESUME 0x20 98#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 99#define FXP_SCB_COMMAND_CU_DUMP 0x50 100#define FXP_SCB_COMMAND_CU_BASE 0x60 101#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 102 103#define FXP_SCB_COMMAND_RU_NOP 0 104#define FXP_SCB_COMMAND_RU_START 1 105#define FXP_SCB_COMMAND_RU_RESUME 2 106#define FXP_SCB_COMMAND_RU_ABORT 4 107#define FXP_SCB_COMMAND_RU_LOADHDS 5 108#define FXP_SCB_COMMAND_RU_BASE 6 109#define FXP_SCB_COMMAND_RU_RBDRESUME 7 110 111/* 112 * Command block definitions 113 */ 114struct fxp_cb_nop { 115 uint16_t cb_status; 116 uint16_t cb_command; 117 uint32_t link_addr; 118}; 119struct fxp_cb_ias { 120 uint16_t cb_status; 121 uint16_t cb_command; 122 uint32_t link_addr; 123 uint8_t macaddr[6]; 124}; 125 126/* I hate bit-fields :-( */ 127#if BYTE_ORDER == LITTLE_ENDIAN 128#define __FXP_BITFIELD2(a, b) a, b 129#define __FXP_BITFIELD3(a, b, c) a, b, c 130#define __FXP_BITFIELD4(a, b, c, d) a, b, c, d 131#define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e 132#define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f 133#define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g 134#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h 135#else 136#define __FXP_BITFIELD2(a, b) b, a 137#define __FXP_BITFIELD3(a, b, c) c, b, a 138#define __FXP_BITFIELD4(a, b, c, d) d, c, b, a 139#define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a 140#define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a 141#define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a 142#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a 143#endif 144 145struct fxp_cb_config { 146 uint16_t cb_status; 147 uint16_t cb_command; 148 uint32_t link_addr; 149 150 /* Bytes 0 - 21 -- common to all i8255x */ 151 u_int __FXP_BITFIELD2(byte_count:6, :2); 152 u_int __FXP_BITFIELD3(rx_fifo_limit:4, tx_fifo_limit:3, :1); 153 uint8_t adaptive_ifs; 154 u_int __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */ 155 type_enable:1, /* 8,9 */ 156 read_align_en:1, /* 8,9 */ 157 end_wr_on_cl:1, /* 8,9 */ 158 :4); 159 u_int __FXP_BITFIELD2(rx_dma_bytecount:7, :1); 160 u_int __FXP_BITFIELD2(tx_dma_bytecount:7, dma_mbce:1); 161 u_int __FXP_BITFIELD8(late_scb:1, /* 7 */ 162 direct_dma_dis:1, /* 8,9 */ 163 tno_int_or_tco_en:1, /* 7,9 */ 164 ci_int:1, 165 ext_txcb_dis:1, /* 8,9 */ 166 ext_stats_dis:1, /* 8,9 */ 167 keep_overrun_rx:1, 168 save_bf:1); 169 u_int __FXP_BITFIELD6(disc_short_rx:1, 170 underrun_retry:2, 171 :2, 172 ext_rfa:1, /* 550 */ 173 two_frames:1, /* 8,9 */ 174 dyn_tbd:1); /* 8,9 */ 175 u_int __FXP_BITFIELD3(mediatype:1, /* 7 */ 176 :6, 177 csma_dis:1); /* 8,9 */ 178 u_int __FXP_BITFIELD6(tcp_udp_cksum:1, /* 9 */ 179 :3, 180 vlan_tco:1, /* 8,9 */ 181 link_wake_en:1, /* 8,9 */ 182 arp_wake_en:1, /* 8 */ 183 mc_wake_en:1); /* 8 */ 184 u_int __FXP_BITFIELD4(:3, 185 nsai:1, 186 preamble_length:2, 187 loopback:2); 188 u_int __FXP_BITFIELD2(linear_priority:3, /* 7 */ 189 :5); 190 u_int __FXP_BITFIELD3(linear_pri_mode:1, /* 7 */ 191 :3, 192 interfrm_spacing:4); 193 u_int :8; 194 u_int :8; 195 u_int __FXP_BITFIELD8(promiscuous:1, 196 bcast_disable:1, 197 wait_after_win:1, /* 8,9 */ 198 :1, 199 ignore_ul:1, /* 8,9 */ 200 crc16_en:1, /* 9 */ 201 :1, 202 crscdt:1); 203 u_int fc_delay_lsb:8; /* 8,9 */ 204 u_int fc_delay_msb:8; /* 8,9 */ 205 u_int __FXP_BITFIELD6(stripping:1, 206 padding:1, 207 rcv_crc_xfer:1, 208 long_rx_en:1, /* 8,9 */ 209 pri_fc_thresh:3, /* 8,9 */ 210 :1); 211 u_int __FXP_BITFIELD8(ia_wake_en:1, /* 8 */ 212 magic_pkt_dis:1, /* 8,9,!9ER */ 213 tx_fc_dis:1, /* 8,9 */ 214 rx_fc_restop:1, /* 8,9 */ 215 rx_fc_restart:1, /* 8,9 */ 216 fc_filter:1, /* 8,9 */ 217 force_fdx:1, 218 fdx_pin_en:1); 219 u_int __FXP_BITFIELD4(:5, 220 pri_fc_loc:1, /* 8,9 */ 221 multi_ia:1, 222 :1); 223 u_int __FXP_BITFIELD3(:3, mc_all:1, :4); 224 225 /* Bytes 22 - 31 -- i82550 only */ 226 u_int __FXP_BITFIELD3(gamla_rx:1, 227 vlan_strip_en:1, 228 :6); 229 uint8_t pad[9]; 230}; 231 232#define MAXMCADDR 80 233struct fxp_cb_mcs { 234 uint16_t cb_status; 235 uint16_t cb_command; 236 uint32_t link_addr; 237 uint16_t mc_cnt; 238 uint8_t mc_addr[MAXMCADDR][6]; 239}; 240 241#define MAXUCODESIZE 192 242struct fxp_cb_ucode { 243 uint16_t cb_status; 244 uint16_t cb_command; 245 uint32_t link_addr; 246 uint32_t ucode[MAXUCODESIZE]; 247}; 248 249/* 250 * Number of DMA segments in a TxCB. 251 */ 252#define FXP_NTXSEG 32 253 254struct fxp_tbd { 255 uint32_t tb_addr; 256 uint32_t tb_size; 257}; 258 259struct fxp_ipcb { 260 /* 261 * The following fields are valid only when 262 * using the IPCB command block for TX checksum offload 263 * (and TCP large send, VLANs, and (I think) IPsec). To use 264 * them, you must enable extended TxCBs (available only 265 * on the 82559 and later) and use the IPCBXMIT command. 266 * Note that Intel defines the IPCB to be 32 bytes long, 267 * the last 8 bytes of which comprise the first entry 268 * in the TBD array (see note below). This means we only 269 * have to define 8 extra bytes here. 270 */ 271 uint16_t ipcb_schedule_low; 272 uint8_t ipcb_ip_schedule; 273 uint8_t ipcb_ip_activation_high; 274 uint16_t ipcb_vlan_id; 275 uint8_t ipcb_ip_header_offset; 276 uint8_t ipcb_tcp_header_offset; 277}; 278 279struct fxp_cb_tx { 280 uint16_t cb_status; 281 uint16_t cb_command; 282 uint32_t link_addr; 283 uint32_t tbd_array_addr; 284 uint16_t byte_count; 285 uint8_t tx_threshold; 286 uint8_t tbd_number; 287 288 /* 289 * The following structure isn't actually part of the TxCB, 290 * unless the extended TxCB feature is being used. In this 291 * case, the first two elements of the structure below are 292 * fetched along with the TxCB. 293 */ 294 union { 295 struct fxp_ipcb ipcb; 296 struct fxp_tbd tbd[FXP_NTXSEG + 1]; 297 } tx_cb_u; 298}; 299 300#define tbd tx_cb_u.tbd 301#define ipcb_schedule_low tx_cb_u.ipcb.ipcb_schedule_low 302#define ipcb_ip_schedule tx_cb_u.ipcb.ipcb_ip_schedule 303#define ipcb_ip_activation_high tx_cb_u.ipcb.ipcb_ip_activation_high 304#define ipcb_vlan_id tx_cb_u.ipcb.ipcb_vlan_id 305#define ipcb_ip_header_offset tx_cb_u.ipcb.ipcb_ip_header_offset 306#define ipcb_tcp_header_offset tx_cb_u.ipcb.ipcb_tcp_header_offset 307 308/* 309 * IPCB field definitions 310 */ 311#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 312#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 313#define FXP_IPCB_TCP_PACKET 0x40 314#define FXP_IPCB_LARGESEND_ENABLE 0x80 315#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 316#define FXP_IPCB_INSERTVLAN_ENABLE 0x02 317 318/* 319 * Control Block (CB) definitions 320 */ 321 322/* status */ 323#define FXP_CB_STATUS_OK 0x2000 324#define FXP_CB_STATUS_C 0x8000 325/* commands */ 326#define FXP_CB_COMMAND_NOP 0x0 327#define FXP_CB_COMMAND_IAS 0x1 328#define FXP_CB_COMMAND_CONFIG 0x2 329#define FXP_CB_COMMAND_MCAS 0x3 330#define FXP_CB_COMMAND_XMIT 0x4 331#define FXP_CB_COMMAND_UCODE 0x5 332#define FXP_CB_COMMAND_DUMP 0x6 333#define FXP_CB_COMMAND_DIAG 0x7 334#define FXP_CB_COMMAND_LOADFILT 0x8 335#define FXP_CB_COMMAND_IPCBXMIT 0x9 336 337/* command flags */ 338#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 339#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 340#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 341#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 342 343/* 344 * RFA definitions 345 */ 346 347struct fxp_rfa { 348 uint16_t rfa_status; 349 uint16_t rfa_control; 350 uint32_t link_addr; 351 uint32_t rbd_addr; 352 uint16_t actual_size; 353 uint16_t size; 354 355 /* 356 * The following fields are only available when using 357 * extended receive mode on an 82550/82551 chipset. 358 */ 359 uint16_t rfax_vlan_id; 360 uint8_t rfax_rx_parser_sts; 361 uint8_t rfax_rsvd0; 362 uint16_t rfax_security_sts; 363 uint8_t rfax_csum_sts; 364 uint8_t rfax_zerocopy_sts; 365 uint8_t rfax_pad[8]; 366} __packed; 367#define FXP_RFAX_LEN 16 368 369#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 370#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 371#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 372#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 373#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 374#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 375#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 376#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 377#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 378#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 379#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 380#define FXP_RFA_STATUS_VLAN 0x1000 /* VLAN tagged frame */ 381#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 382#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 383#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 384#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 385#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 386#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 387 388/* Bits in the 'csum_sts' byte */ 389#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 390#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 391#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 392#define FXP_RFDX_CS_IP_CSUM_VALID 0x02 393 394/* Bits in the 'packet parser' byte */ 395#define FXP_RFDX_P_PARSE_BIT 0x08 396#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 397#define FXP_RFDX_P_TCP_PACKET 0x00 398#define FXP_RFDX_P_UDP_PACKET 0x01 399#define FXP_RFDX_P_IP_PACKET 0x03 400 401/* 402 * Statistics dump area definitions 403 */ 404struct fxp_stats { 405 uint32_t tx_good; 406 uint32_t tx_maxcols; 407 uint32_t tx_latecols; 408 uint32_t tx_underruns; 409 uint32_t tx_lostcrs; 410 uint32_t tx_deffered; 411 uint32_t tx_single_collisions; 412 uint32_t tx_multiple_collisions; 413 uint32_t tx_total_collisions; 414 uint32_t rx_good; 415 uint32_t rx_crc_errors; 416 uint32_t rx_alignment_errors; 417 uint32_t rx_rnr_errors; 418 uint32_t rx_overrun_errors; 419 uint32_t rx_cdt_errors; 420 uint32_t rx_shortframes; 421 uint32_t completion_status; 422}; 423#define FXP_STATS_DUMP_COMPLETE 0xa005 424#define FXP_STATS_DR_COMPLETE 0xa007 425 426/* 427 * Serial EEPROM control register bits 428 */ 429#define FXP_EEPROM_EESK 0x01 /* shift clock */ 430#define FXP_EEPROM_EECS 0x02 /* chip select */ 431#define FXP_EEPROM_EEDI 0x04 /* data in */ 432#define FXP_EEPROM_EEDO 0x08 /* data out */ 433 434/* 435 * Serial EEPROM opcodes, including start bit 436 */ 437#define FXP_EEPROM_OPC_ERASE 0x4 438#define FXP_EEPROM_OPC_WRITE 0x5 439#define FXP_EEPROM_OPC_READ 0x6 440 441/* 442 * Management Data Interface opcodes 443 */ 444#define FXP_MDI_WRITE 0x1 445#define FXP_MDI_READ 0x2 446 447/* 448 * PHY device types 449 */ 450#define FXP_PHY_DEVICE_MASK 0x3f00 451#define FXP_PHY_SERIAL_ONLY 0x8000 452#define FXP_PHY_NONE 0 453#define FXP_PHY_82553A 1 454#define FXP_PHY_82553C 2 455#define FXP_PHY_82503 3 456#define FXP_PHY_DP83840 4 457#define FXP_PHY_80C240 5 458#define FXP_PHY_80C24 6 459#define FXP_PHY_82555 7 460#define FXP_PHY_DP83840A 10 461#define FXP_PHY_82555B 11 462 463/* 464 * Chip revision values. 465 */ 466#define FXP_REV_82557 1 /* catchall 82557 chip type */ 467#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 468#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 469#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 470#define FXP_REV_82559S_A 9 /* 82559S A stepping */ 471#define FXP_REV_82550 12 472#define FXP_REV_82550_C 13 /* 82550 C stepping */ 473#define FXP_REV_82551_E 14 /* 82551 */ 474#define FXP_REV_82551_F 15 /* 82551 */ 475#define FXP_REV_82551_10 16 /* 82551 */ 476