if_fxpreg.h revision 112982
1/* 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 112982 2003-04-02 16:47:16Z mux $ 29 */ 30 31#define FXP_VENDORID_INTEL 0x8086 32 33#define FXP_PCI_MMBA 0x10 34#define FXP_PCI_IOBA 0x14 35 36/* 37 * Control/status registers. 38 */ 39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44#define FXP_CSR_PORT 8 /* port (4 bytes) */ 45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 49#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 50 51/* 52 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 53 * 54 * volatile u_int8_t :2, 55 * scb_rus:4, 56 * scb_cus:2; 57 */ 58 59#define FXP_PORT_SOFTWARE_RESET 0 60#define FXP_PORT_SELFTEST 1 61#define FXP_PORT_SELECTIVE_RESET 2 62#define FXP_PORT_DUMP 3 63 64#define FXP_SCB_RUS_IDLE 0 65#define FXP_SCB_RUS_SUSPENDED 1 66#define FXP_SCB_RUS_NORESOURCES 2 67#define FXP_SCB_RUS_READY 4 68#define FXP_SCB_RUS_SUSP_NORBDS 9 69#define FXP_SCB_RUS_NORES_NORBDS 10 70#define FXP_SCB_RUS_READY_NORBDS 12 71 72#define FXP_SCB_CUS_IDLE 0 73#define FXP_SCB_CUS_SUSPENDED 1 74#define FXP_SCB_CUS_ACTIVE 2 75 76#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 77#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 78#define FXP_SCB_INTMASK_FCP 0x04 79#define FXP_SCB_INTMASK_ER 0x08 80#define FXP_SCB_INTMASK_RNR 0x10 81#define FXP_SCB_INTMASK_CNA 0x20 82#define FXP_SCB_INTMASK_FR 0x40 83#define FXP_SCB_INTMASK_CXTNO 0x80 84 85#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 86#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 87#define FXP_SCB_STATACK_SWI 0x04 88#define FXP_SCB_STATACK_MDI 0x08 89#define FXP_SCB_STATACK_RNR 0x10 90#define FXP_SCB_STATACK_CNA 0x20 91#define FXP_SCB_STATACK_FR 0x40 92#define FXP_SCB_STATACK_CXTNO 0x80 93 94#define FXP_SCB_COMMAND_CU_NOP 0x00 95#define FXP_SCB_COMMAND_CU_START 0x10 96#define FXP_SCB_COMMAND_CU_RESUME 0x20 97#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 98#define FXP_SCB_COMMAND_CU_DUMP 0x50 99#define FXP_SCB_COMMAND_CU_BASE 0x60 100#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 101 102#define FXP_SCB_COMMAND_RU_NOP 0 103#define FXP_SCB_COMMAND_RU_START 1 104#define FXP_SCB_COMMAND_RU_RESUME 2 105#define FXP_SCB_COMMAND_RU_ABORT 4 106#define FXP_SCB_COMMAND_RU_LOADHDS 5 107#define FXP_SCB_COMMAND_RU_BASE 6 108#define FXP_SCB_COMMAND_RU_RBDRESUME 7 109 110/* 111 * Command block definitions 112 */ 113struct fxp_cb_nop { 114 volatile u_int16_t cb_status; 115 volatile u_int16_t cb_command; 116 volatile u_int32_t link_addr; 117}; 118struct fxp_cb_ias { 119 volatile u_int16_t cb_status; 120 volatile u_int16_t cb_command; 121 volatile u_int32_t link_addr; 122 volatile u_int8_t macaddr[6]; 123}; 124/* I hate bit-fields :-( */ 125struct fxp_cb_config { 126 volatile u_int16_t cb_status; 127 volatile u_int16_t cb_command; 128 volatile u_int32_t link_addr; 129 volatile u_int byte_count:6, 130 :2; 131 volatile u_int rx_fifo_limit:4, 132 tx_fifo_limit:3, 133 :1; 134 volatile u_int8_t adaptive_ifs; 135 volatile u_int mwi_enable:1, /* 8,9 */ 136 type_enable:1, /* 8,9 */ 137 read_align_en:1, /* 8,9 */ 138 end_wr_on_cl:1, /* 8,9 */ 139 :4; 140 volatile u_int rx_dma_bytecount:7, 141 :1; 142 volatile u_int tx_dma_bytecount:7, 143 dma_mbce:1; 144 volatile u_int late_scb:1, /* 7 */ 145 direct_dma_dis:1, /* 8,9 */ 146 tno_int_or_tco_en:1, /* 7,9 */ 147 ci_int:1, 148 ext_txcb_dis:1, /* 8,9 */ 149 ext_stats_dis:1, /* 8,9 */ 150 keep_overrun_rx:1, 151 save_bf:1; 152 volatile u_int disc_short_rx:1, 153 underrun_retry:2, 154 :2, 155 ext_rfa:1, /* 550 */ 156 two_frames:1, /* 8,9 */ 157 dyn_tbd:1; /* 8,9 */ 158 volatile u_int mediatype:1, /* 7 */ 159 :6, 160 csma_dis:1; /* 8,9 */ 161 volatile u_int tcp_udp_cksum:1, /* 9 */ 162 :3, 163 vlan_tco:1, /* 8,9 */ 164 link_wake_en:1, /* 8,9 */ 165 arp_wake_en:1, /* 8 */ 166 mc_wake_en:1; /* 8 */ 167 volatile u_int :3, 168 nsai:1, 169 preamble_length:2, 170 loopback:2; 171 volatile u_int linear_priority:3, /* 7 */ 172 :5; 173 volatile u_int linear_pri_mode:1, /* 7 */ 174 :3, 175 interfrm_spacing:4; 176 volatile u_int :8; 177 volatile u_int :8; 178 volatile u_int promiscuous:1, 179 bcast_disable:1, 180 wait_after_win:1, /* 8,9 */ 181 :1, 182 ignore_ul:1, /* 8,9 */ 183 crc16_en:1, /* 9 */ 184 :1, 185 crscdt:1; 186 volatile u_int fc_delay_lsb:8; /* 8,9 */ 187 volatile u_int fc_delay_msb:8; /* 8,9 */ 188 volatile u_int stripping:1, 189 padding:1, 190 rcv_crc_xfer:1, 191 long_rx_en:1, /* 8,9 */ 192 pri_fc_thresh:3, /* 8,9 */ 193 :1; 194 volatile u_int ia_wake_en:1, /* 8 */ 195 magic_pkt_dis:1, /* 8,9,!9ER */ 196 tx_fc_dis:1, /* 8,9 */ 197 rx_fc_restop:1, /* 8,9 */ 198 rx_fc_restart:1, /* 8,9 */ 199 fc_filter:1, /* 8,9 */ 200 force_fdx:1, 201 fdx_pin_en:1; 202 volatile u_int :5, 203 pri_fc_loc:1, /* 8,9 */ 204 multi_ia:1, 205 :1; 206 volatile u_int :3, 207 mc_all:1, 208 :4; 209 volatile u_int8_t gamla_rx:1; /* 550 */ 210 volatile u_int8_t pad[9]; /* 550 */ 211}; 212 213#define MAXMCADDR 80 214struct fxp_cb_mcs { 215 volatile u_int16_t cb_status; 216 volatile u_int16_t cb_command; 217 volatile u_int32_t link_addr; 218 volatile u_int16_t mc_cnt; 219 volatile u_int8_t mc_addr[MAXMCADDR][6]; 220}; 221 222#define MAXUCODESIZE 192 223struct fxp_cb_ucode { 224 u_int16_t cb_status; 225 u_int16_t cb_command; 226 u_int32_t link_addr; 227 u_int32_t ucode[MAXUCODESIZE]; 228}; 229 230/* 231 * Number of DMA segments in a TxCB. 232 */ 233#define FXP_NTXSEG 32 234 235struct fxp_tbd { 236 volatile u_int32_t tb_addr; 237 volatile u_int32_t tb_size; 238}; 239 240struct fxp_ipcb { 241 /* 242 * The following fields are valid only when 243 * using the IPCB command block for TX checksum offload 244 * (and TCP large send, VLANs, and (I think) IPsec). To use 245 * them, you must enable extended TxCBs (available only 246 * on the 82559 and later) and use the IPCBXMIT command. 247 * Note that Intel defines the IPCB to be 32 bytes long, 248 * the last 8 bytes of which comprise the first entry 249 * in the TBD array (see note below). This means we only 250 * have to define 8 extra bytes here. 251 */ 252 volatile u_int16_t ipcb_schedule_low; 253 volatile u_int8_t ipcb_ip_schedule; 254 volatile u_int8_t ipcb_ip_activation_high; 255 volatile u_int16_t ipcb_vlan_id; 256 volatile u_int8_t ipcb_ip_header_offset; 257 volatile u_int8_t ipcb_tcp_header_offset; 258}; 259 260struct fxp_cb_tx { 261 volatile u_int16_t cb_status; 262 volatile u_int16_t cb_command; 263 volatile u_int32_t link_addr; 264 volatile u_int32_t tbd_array_addr; 265 volatile u_int16_t byte_count; 266 volatile u_int8_t tx_threshold; 267 volatile u_int8_t tbd_number; 268 269 /* 270 * The following structure isn't actually part of the TxCB, 271 * unless the extended TxCB feature is being used. In this 272 * case, the first two elements of the structure below are 273 * fetched along with the TxCB. 274 */ 275 union { 276 volatile struct fxp_ipcb; 277 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 278 } tx_cb_u; 279}; 280 281#define tbd tx_cb_u.tbd 282#define ipcb_schedule_low tx_cb_u.ipcb_schedule_low 283#define ipcb_ip_schedule tx_cb_u.ipcb_ip_schedule 284#define ipcb_ip_activation_high tx_cb_u.ipcb_ip_activation_high 285#define ipcb_vlan_id tx_cb_u.ipcb_vlan_id 286#define ipcb_ip_header_offset tx_cb_u.ipcb_ip_header_offset 287#define ipcb_tcp_header_offset tx_cb_u.ipcb_tcp_header_offset 288 289/* 290 * IPCB field definitions 291 */ 292#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 293#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 294#define FXP_IPCB_TCP_PACKET 0x40 295#define FXP_IPCB_LARGESEND_ENABLE 0x80 296#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 297#define FXP_IPCB_INSERTVLAN_ENABLE 0x02 298 299/* 300 * Control Block (CB) definitions 301 */ 302 303/* status */ 304#define FXP_CB_STATUS_OK 0x2000 305#define FXP_CB_STATUS_C 0x8000 306/* commands */ 307#define FXP_CB_COMMAND_NOP 0x0 308#define FXP_CB_COMMAND_IAS 0x1 309#define FXP_CB_COMMAND_CONFIG 0x2 310#define FXP_CB_COMMAND_MCAS 0x3 311#define FXP_CB_COMMAND_XMIT 0x4 312#define FXP_CB_COMMAND_UCODE 0x5 313#define FXP_CB_COMMAND_DUMP 0x6 314#define FXP_CB_COMMAND_DIAG 0x7 315#define FXP_CB_COMMAND_LOADFILT 0x8 316#define FXP_CB_COMMAND_IPCBXMIT 0x9 317 318/* command flags */ 319#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 320#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 321#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 322#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 323 324/* 325 * RFA definitions 326 */ 327 328struct fxp_rfa { 329 volatile u_int16_t rfa_status; 330 volatile u_int16_t rfa_control; 331 volatile u_int8_t link_addr[4]; 332 volatile u_int8_t rbd_addr[4]; 333 volatile u_int16_t actual_size; 334 volatile u_int16_t size; 335 336 /* 337 * The following fields are only available when using 338 * extended receive mode on an 82550/82551 chipset. 339 */ 340 volatile u_int16_t rfax_vlan_id; 341 volatile u_int8_t rfax_rx_parser_sts; 342 volatile u_int8_t rfax_rsvd0; 343 volatile u_int16_t rfax_security_sts; 344 volatile u_int8_t rfax_csum_sts; 345 volatile u_int8_t rfax_zerocopy_sts; 346 volatile u_int8_t rfax_pad[8]; 347}; 348#define FXP_RFAX_LEN 16 349 350#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 351#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 352#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 353#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 354#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 355#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 356#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 357#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 358#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 359#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 360#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 361#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 362#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 363#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 364#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 365#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 366#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 367 368/* Bits in the 'csum_sts' byte */ 369#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 370#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 371#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 372#define FXP_RFDX_CS_IP_CSUM_VALID 0x02 373 374/* Bits in the 'packet parser' byte */ 375#define FXP_RFDX_P_PARSE_BIT 0x08 376#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 377#define FXP_RFDX_P_TCP_PACKET 0x00 378#define FXP_RFDX_P_UDP_PACKET 0x01 379#define FXP_RFDX_P_IP_PACKET 0x03 380 381/* 382 * Statistics dump area definitions 383 */ 384struct fxp_stats { 385 volatile u_int32_t tx_good; 386 volatile u_int32_t tx_maxcols; 387 volatile u_int32_t tx_latecols; 388 volatile u_int32_t tx_underruns; 389 volatile u_int32_t tx_lostcrs; 390 volatile u_int32_t tx_deffered; 391 volatile u_int32_t tx_single_collisions; 392 volatile u_int32_t tx_multiple_collisions; 393 volatile u_int32_t tx_total_collisions; 394 volatile u_int32_t rx_good; 395 volatile u_int32_t rx_crc_errors; 396 volatile u_int32_t rx_alignment_errors; 397 volatile u_int32_t rx_rnr_errors; 398 volatile u_int32_t rx_overrun_errors; 399 volatile u_int32_t rx_cdt_errors; 400 volatile u_int32_t rx_shortframes; 401 volatile u_int32_t completion_status; 402}; 403#define FXP_STATS_DUMP_COMPLETE 0xa005 404#define FXP_STATS_DR_COMPLETE 0xa007 405 406/* 407 * Serial EEPROM control register bits 408 */ 409#define FXP_EEPROM_EESK 0x01 /* shift clock */ 410#define FXP_EEPROM_EECS 0x02 /* chip select */ 411#define FXP_EEPROM_EEDI 0x04 /* data in */ 412#define FXP_EEPROM_EEDO 0x08 /* data out */ 413 414/* 415 * Serial EEPROM opcodes, including start bit 416 */ 417#define FXP_EEPROM_OPC_ERASE 0x4 418#define FXP_EEPROM_OPC_WRITE 0x5 419#define FXP_EEPROM_OPC_READ 0x6 420 421/* 422 * Management Data Interface opcodes 423 */ 424#define FXP_MDI_WRITE 0x1 425#define FXP_MDI_READ 0x2 426 427/* 428 * PHY device types 429 */ 430#define FXP_PHY_DEVICE_MASK 0x3f00 431#define FXP_PHY_SERIAL_ONLY 0x8000 432#define FXP_PHY_NONE 0 433#define FXP_PHY_82553A 1 434#define FXP_PHY_82553C 2 435#define FXP_PHY_82503 3 436#define FXP_PHY_DP83840 4 437#define FXP_PHY_80C240 5 438#define FXP_PHY_80C24 6 439#define FXP_PHY_82555 7 440#define FXP_PHY_DP83840A 10 441#define FXP_PHY_82555B 11 442 443/* 444 * Chip revision values. 445 */ 446#define FXP_REV_82557 1 /* catchall 82557 chip type */ 447#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 448#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 449#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 450#define FXP_REV_82559S_A 9 /* 82559S A stepping */ 451#define FXP_REV_82550 12 452#define FXP_REV_82550_C 13 /* 82550 C stepping */ 453