if_fxpreg.h revision 29974
112510Sdg/* 212510Sdg * Copyright (c) 1995, David Greenman 312510Sdg * All rights reserved. 412510Sdg * 512510Sdg * Redistribution and use in source and binary forms, with or without 612510Sdg * modification, are permitted provided that the following conditions 712510Sdg * are met: 812510Sdg * 1. Redistributions of source code must retain the above copyright 912510Sdg * notice unmodified, this list of conditions, and the following 1012510Sdg * disclaimer. 1112510Sdg * 2. Redistributions in binary form must reproduce the above copyright 1212510Sdg * notice, this list of conditions and the following disclaimer in the 1312510Sdg * documentation and/or other materials provided with the distribution. 1412510Sdg * 1512510Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1612510Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1712510Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1812510Sdg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1912510Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2012510Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2112510Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2212510Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2312510Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2412510Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2512510Sdg * SUCH DAMAGE. 2612510Sdg * 2729974Sdg * $Id: if_fxpreg.h,v 1.10 1997/09/05 10:23:56 davidg Exp $ 2812510Sdg */ 2912510Sdg 3012510Sdg#define FXP_VENDORID_INTEL 0x8086 3112510Sdg#define FXP_DEVICEID_i82557 0x1229 3212510Sdg 3312510Sdg#define FXP_PCI_MMBA 0x10 3412510Sdg#define FXP_PCI_IOBA 0x14 3512510Sdg 3629138Sdg/* 3729138Sdg * Control/status registers. 3829138Sdg */ 3929138Sdg#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 4029138Sdg#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 4129138Sdg#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 4229138Sdg#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 4329138Sdg#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 4429138Sdg#define FXP_CSR_PORT 8 /* port (4 bytes) */ 4529138Sdg#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 4629138Sdg#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 4729138Sdg#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 4812510Sdg 4929138Sdg/* 5029138Sdg * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 5129138Sdg * 5229138Sdg * volatile u_int8_t :2, 5329138Sdg * scb_rus:4, 5429138Sdg * scb_cus:2; 5529138Sdg */ 5629138Sdg 5722255Sdg#define FXP_PORT_SOFTWARE_RESET 0 5822255Sdg#define FXP_PORT_SELFTEST 1 5922255Sdg#define FXP_PORT_SELECTIVE_RESET 2 6022255Sdg#define FXP_PORT_DUMP 3 6122255Sdg 6212510Sdg#define FXP_SCB_RUS_IDLE 0 6312510Sdg#define FXP_SCB_RUS_SUSPENDED 1 6412510Sdg#define FXP_SCB_RUS_NORESOURCES 2 6512510Sdg#define FXP_SCB_RUS_READY 4 6612510Sdg#define FXP_SCB_RUS_SUSP_NORBDS 9 6712510Sdg#define FXP_SCB_RUS_NORES_NORBDS 10 6812510Sdg#define FXP_SCB_RUS_READY_NORBDS 12 6912510Sdg 7012510Sdg#define FXP_SCB_CUS_IDLE 0 7112510Sdg#define FXP_SCB_CUS_SUSPENDED 1 7212510Sdg#define FXP_SCB_CUS_ACTIVE 2 7312510Sdg 7412510Sdg#define FXP_SCB_STATACK_SWI 0x04 7512510Sdg#define FXP_SCB_STATACK_MDI 0x08 7612510Sdg#define FXP_SCB_STATACK_RNR 0x10 7712510Sdg#define FXP_SCB_STATACK_CNA 0x20 7812510Sdg#define FXP_SCB_STATACK_FR 0x40 7912510Sdg#define FXP_SCB_STATACK_CXTNO 0x80 8012510Sdg 8112510Sdg#define FXP_SCB_COMMAND_CU_NOP 0x00 8212510Sdg#define FXP_SCB_COMMAND_CU_START 0x10 8312510Sdg#define FXP_SCB_COMMAND_CU_RESUME 0x20 8412510Sdg#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 8512510Sdg#define FXP_SCB_COMMAND_CU_DUMP 0x50 8612510Sdg#define FXP_SCB_COMMAND_CU_BASE 0x60 8712510Sdg#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 8812510Sdg 8912510Sdg#define FXP_SCB_COMMAND_RU_NOP 0 9012510Sdg#define FXP_SCB_COMMAND_RU_START 1 9112510Sdg#define FXP_SCB_COMMAND_RU_RESUME 2 9212510Sdg#define FXP_SCB_COMMAND_RU_ABORT 4 9312510Sdg#define FXP_SCB_COMMAND_RU_LOADHDS 5 9412510Sdg#define FXP_SCB_COMMAND_RU_BASE 6 9512510Sdg#define FXP_SCB_COMMAND_RU_RBDRESUME 7 9612510Sdg 9712510Sdg/* 9812510Sdg * Command block definitions 9912510Sdg */ 10012510Sdgstruct fxp_cb_nop { 10129974Sdg void *fill[2]; 10212510Sdg volatile u_int16_t cb_status; 10312510Sdg volatile u_int16_t cb_command; 10412510Sdg volatile u_int32_t link_addr; 10512510Sdg}; 10612510Sdgstruct fxp_cb_ias { 10729974Sdg void *fill[2]; 10812510Sdg volatile u_int16_t cb_status; 10912510Sdg volatile u_int16_t cb_command; 11012510Sdg volatile u_int32_t link_addr; 11112510Sdg volatile u_int8_t macaddr[6]; 11212510Sdg}; 11312510Sdg/* I hate bit-fields :-( */ 11412510Sdgstruct fxp_cb_config { 11529974Sdg void *fill[2]; 11612510Sdg volatile u_int16_t cb_status; 11712510Sdg volatile u_int16_t cb_command; 11812510Sdg volatile u_int32_t link_addr; 11912510Sdg volatile u_int8_t byte_count:6, 12012510Sdg :2; 12112510Sdg volatile u_int8_t rx_fifo_limit:4, 12212510Sdg tx_fifo_limit:3, 12312510Sdg :1; 12412510Sdg volatile u_int8_t adaptive_ifs; 12512510Sdg volatile u_int8_t :8; 12612510Sdg volatile u_int8_t rx_dma_bytecount:7, 12712510Sdg :1; 12812510Sdg volatile u_int8_t tx_dma_bytecount:7, 12912510Sdg dma_bce:1; 13012510Sdg volatile u_int8_t late_scb:1, 13112510Sdg :1, 13212510Sdg tno_int:1, 13312510Sdg ci_int:1, 13412510Sdg :3, 13512510Sdg save_bf:1; 13612510Sdg volatile u_int8_t disc_short_rx:1, 13712510Sdg underrun_retry:2, 13812510Sdg :5; 13912510Sdg volatile u_int8_t mediatype:1, 14012510Sdg :7; 14112510Sdg volatile u_int8_t :8; 14212510Sdg volatile u_int8_t :3, 14312510Sdg nsai:1, 14412510Sdg preamble_length:2, 14512510Sdg loopback:2; 14612510Sdg volatile u_int8_t linear_priority:3, 14712510Sdg :5; 14812510Sdg volatile u_int8_t linear_pri_mode:1, 14912510Sdg :3, 15012510Sdg interfrm_spacing:4; 15112510Sdg volatile u_int8_t :8; 15212510Sdg volatile u_int8_t :8; 15312510Sdg volatile u_int8_t promiscuous:1, 15412510Sdg bcast_disable:1, 15512510Sdg :5, 15612510Sdg crscdt:1; 15712510Sdg volatile u_int8_t :8; 15812510Sdg volatile u_int8_t :8; 15912510Sdg volatile u_int8_t stripping:1, 16012510Sdg padding:1, 16112510Sdg rcv_crc_xfer:1, 16212510Sdg :5; 16312510Sdg volatile u_int8_t :6, 16412510Sdg force_fdx:1, 16512510Sdg fdx_pin_en:1; 16612510Sdg volatile u_int8_t :6, 16712510Sdg multi_ia:1, 16812510Sdg :1; 16912510Sdg volatile u_int8_t :3, 17012510Sdg mc_all:1, 17112510Sdg :4; 17212510Sdg}; 17329974Sdg 17429974Sdg#define MAXMCADDR 80 17529974Sdgstruct fxp_cb_mcs { 17629974Sdg struct fxp_cb_tx *next; 17729974Sdg struct mbuf *mb_head; 17829974Sdg volatile u_int16_t cb_status; 17929974Sdg volatile u_int16_t cb_command; 18029974Sdg volatile u_int32_t link_addr; 18129974Sdg volatile u_int16_t mc_cnt; 18229974Sdg volatile u_int8_t mc_addr[MAXMCADDR][6]; 18329974Sdg}; 18429974Sdg 18529974Sdg/* 18629974Sdg * Number of DMA segments in a TxCB. Note that this is carefully 18729974Sdg * chosen to make the total struct size an even power of two. It's 18829974Sdg * critical that no TxCB be split across a page boundry since 18929974Sdg * no attempt is made to allocate physically contiguous memory. 19029974Sdg * 19129974Sdg */ 19229974Sdg#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 19329974Sdg#define FXP_NTXSEG 28 19429974Sdg#else 19529974Sdg#define FXP_NTXSEG 29 19629974Sdg#endif 19729974Sdg 19812510Sdgstruct fxp_tbd { 19912510Sdg volatile u_int32_t tb_addr; 20012510Sdg volatile u_int32_t tb_size; 20112510Sdg}; 20212510Sdgstruct fxp_cb_tx { 20329974Sdg struct fxp_cb_tx *next; 20429974Sdg struct mbuf *mb_head; 20512510Sdg volatile u_int16_t cb_status; 20612510Sdg volatile u_int16_t cb_command; 20712510Sdg volatile u_int32_t link_addr; 20812510Sdg volatile u_int32_t tbd_array_addr; 20912510Sdg volatile u_int16_t byte_count; 21012510Sdg volatile u_int8_t tx_threshold; 21112510Sdg volatile u_int8_t tbd_number; 21212510Sdg /* 21312510Sdg * The following isn't actually part of the TxCB. 21412510Sdg */ 21529974Sdg volatile struct fxp_tbd tbd[FXP_NTXSEG]; 21612510Sdg}; 21712510Sdg 21812510Sdg/* 21912510Sdg * Control Block (CB) definitions 22012510Sdg */ 22112510Sdg 22212510Sdg/* status */ 22312510Sdg#define FXP_CB_STATUS_OK 0x2000 22412510Sdg#define FXP_CB_STATUS_C 0x8000 22512510Sdg/* commands */ 22612510Sdg#define FXP_CB_COMMAND_NOP 0x0 22712510Sdg#define FXP_CB_COMMAND_IAS 0x1 22812510Sdg#define FXP_CB_COMMAND_CONFIG 0x2 22929974Sdg#define FXP_CB_COMMAND_MCAS 0x3 23012510Sdg#define FXP_CB_COMMAND_XMIT 0x4 23112510Sdg#define FXP_CB_COMMAND_RESRV 0x5 23212510Sdg#define FXP_CB_COMMAND_DUMP 0x6 23312510Sdg#define FXP_CB_COMMAND_DIAG 0x7 23412510Sdg/* command flags */ 23512510Sdg#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 23612510Sdg#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 23712510Sdg#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 23812510Sdg#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 23912510Sdg 24012510Sdg/* 24112510Sdg * RFA definitions 24212510Sdg */ 24312510Sdg 24412510Sdgstruct fxp_rfa { 24512510Sdg volatile u_int16_t rfa_status; 24612510Sdg volatile u_int16_t rfa_control; 24712510Sdg volatile u_int32_t link_addr; 24812510Sdg volatile u_int32_t rbd_addr; 24912510Sdg volatile u_int16_t actual_size; 25012510Sdg volatile u_int16_t size; 25112510Sdg}; 25212510Sdg#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 25312510Sdg#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 25412510Sdg#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 25512510Sdg#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 25612510Sdg#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 25712510Sdg#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 25812510Sdg#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 25912510Sdg#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 26012510Sdg#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 26112510Sdg#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 26212510Sdg#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 26312510Sdg#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 26412510Sdg#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 26512510Sdg#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 26612510Sdg#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 26712510Sdg 26812510Sdg/* 26912510Sdg * Statistics dump area definitions 27012510Sdg */ 27112510Sdgstruct fxp_stats { 27212510Sdg volatile u_int32_t tx_good; 27312510Sdg volatile u_int32_t tx_maxcols; 27412510Sdg volatile u_int32_t tx_latecols; 27512510Sdg volatile u_int32_t tx_underruns; 27612510Sdg volatile u_int32_t tx_lostcrs; 27712510Sdg volatile u_int32_t tx_deffered; 27812510Sdg volatile u_int32_t tx_single_collisions; 27912510Sdg volatile u_int32_t tx_multiple_collisions; 28012510Sdg volatile u_int32_t tx_total_collisions; 28112510Sdg volatile u_int32_t rx_good; 28212510Sdg volatile u_int32_t rx_crc_errors; 28312510Sdg volatile u_int32_t rx_alignment_errors; 28412510Sdg volatile u_int32_t rx_rnr_errors; 28512510Sdg volatile u_int32_t rx_overrun_errors; 28612510Sdg volatile u_int32_t rx_cdt_errors; 28712510Sdg volatile u_int32_t rx_shortframes; 28812510Sdg volatile u_int32_t completion_status; 28912510Sdg}; 29012510Sdg#define FXP_STATS_DUMP_COMPLETE 0xa005 29112510Sdg#define FXP_STATS_DR_COMPLETE 0xa007 29212510Sdg 29312510Sdg/* 29412510Sdg * Serial EEPROM control register bits 29512510Sdg */ 29612510Sdg/* shift clock */ 29712510Sdg#define FXP_EEPROM_EESK 0x01 29812510Sdg/* chip select */ 29912510Sdg#define FXP_EEPROM_EECS 0x02 30012510Sdg/* data in */ 30112510Sdg#define FXP_EEPROM_EEDI 0x04 30212510Sdg/* data out */ 30312510Sdg#define FXP_EEPROM_EEDO 0x08 30412510Sdg 30512510Sdg/* 30612510Sdg * Serial EEPROM opcodes, including start bit 30712510Sdg */ 30812510Sdg#define FXP_EEPROM_OPC_ERASE 0x4 30912510Sdg#define FXP_EEPROM_OPC_WRITE 0x5 31012510Sdg#define FXP_EEPROM_OPC_READ 0x6 31123964Sdg 31223964Sdg/* 31323964Sdg * Management Data Interface opcodes 31423964Sdg */ 31523964Sdg#define FXP_MDI_WRITE 0x1 31623964Sdg#define FXP_MDI_READ 0x2 31723964Sdg 31823964Sdg/* 31923964Sdg * PHY device types 32023964Sdg */ 32123964Sdg#define FXP_PHY_NONE 0 32223964Sdg#define FXP_PHY_82553A 1 32323964Sdg#define FXP_PHY_82553C 2 32423964Sdg#define FXP_PHY_82503 3 32523964Sdg#define FXP_PHY_DP83840 4 32623964Sdg#define FXP_PHY_80C240 5 32723964Sdg#define FXP_PHY_80C24 6 32826623Sdg#define FXP_PHY_82555 7 32924079Sdg#define FXP_PHY_DP83840A 10 33023964Sdg 33123964Sdg/* 33226623Sdg * PHY BMCR Basic Mode Control Register 33324079Sdg */ 33426623Sdg#define FXP_PHY_BMCR 0x0 33526623Sdg#define FXP_PHY_BMCR_FULLDUPLEX 0x0100 33626623Sdg#define FXP_PHY_BMCR_AUTOEN 0x1000 33726623Sdg#define FXP_PHY_BMCR_SPEED_100M 0x2000 33824079Sdg 33924079Sdg/* 34023964Sdg * DP84830 PHY, PCS Configuration Register 34123964Sdg */ 34223964Sdg#define FXP_DP83840_PCR 0x17 34323964Sdg#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */ 34423964Sdg#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */ 34523964Sdg#define FXP_DP83840_PCR_BIT8 0x0100 34623964Sdg#define FXP_DP83840_PCR_BIT10 0x0400 347