1139749Simp/*- 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3113584Ssimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17103285Sikob * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: stable/11/sys/dev/firewire/fwohcireg.h 332156 2018-04-06 21:50:09Z kevans $ 35103285Sikob * 36103285Sikob */ 37125747Sjhb#define PCI_CBMEM PCIR_BAR(0) 38103285Sikob 39132283Ssimokawa#define FW_VENDORID_NATSEMI 0x100B 40111076Ssimokawa#define FW_VENDORID_NEC 0x1033 41132283Ssimokawa#define FW_VENDORID_SIS 0x1039 42111076Ssimokawa#define FW_VENDORID_TI 0x104c 43111076Ssimokawa#define FW_VENDORID_SONY 0x104d 44111076Ssimokawa#define FW_VENDORID_VIA 0x1106 45111076Ssimokawa#define FW_VENDORID_RICOH 0x1180 46111076Ssimokawa#define FW_VENDORID_APPLE 0x106b 47111076Ssimokawa#define FW_VENDORID_LUCENT 0x11c1 48132283Ssimokawa#define FW_VENDORID_INTEL 0x8086 49132283Ssimokawa#define FW_VENDORID_ADAPTEC 0x9004 50146439Smarius#define FW_VENDORID_SUN 0x108e 51103285Sikob 52132283Ssimokawa#define FW_DEVICE_CS4210 (0x000f << 16) 53111076Ssimokawa#define FW_DEVICE_UPD861 (0x0063 << 16) 54111076Ssimokawa#define FW_DEVICE_UPD871 (0x00ce << 16) 55113957Ssimokawa#define FW_DEVICE_UPD72870 (0x00cd << 16) 56125239Ssimokawa#define FW_DEVICE_UPD72873 (0x00e7 << 16) 57113957Ssimokawa#define FW_DEVICE_UPD72874 (0x00f2 << 16) 58111076Ssimokawa#define FW_DEVICE_TITSB22 (0x8009 << 16) 59111076Ssimokawa#define FW_DEVICE_TITSB23 (0x8019 << 16) 60111076Ssimokawa#define FW_DEVICE_TITSB26 (0x8020 << 16) 61111076Ssimokawa#define FW_DEVICE_TITSB43 (0x8021 << 16) 62111076Ssimokawa#define FW_DEVICE_TITSB43A (0x8023 << 16) 63113957Ssimokawa#define FW_DEVICE_TITSB43AB23 (0x8024 << 16) 64115806Ssimokawa#define FW_DEVICE_TITSB82AA2 (0x8025 << 16) 65132283Ssimokawa#define FW_DEVICE_TITSB43AB21 (0x8026 << 16) 66113957Ssimokawa#define FW_DEVICE_TIPCI4410A (0x8017 << 16) 67111076Ssimokawa#define FW_DEVICE_TIPCI4450 (0x8011 << 16) 68113957Ssimokawa#define FW_DEVICE_TIPCI4451 (0x8027 << 16) 69133116Ssimokawa#define FW_DEVICE_CXD1947 (0x8009 << 16) 70133116Ssimokawa#define FW_DEVICE_CXD3222 (0x8039 << 16) 71111076Ssimokawa#define FW_DEVICE_VT6306 (0x3044 << 16) 72113957Ssimokawa#define FW_DEVICE_R5C551 (0x0551 << 16) 73111076Ssimokawa#define FW_DEVICE_R5C552 (0x0552 << 16) 74111076Ssimokawa#define FW_DEVICE_PANGEA (0x0030 << 16) 75332156Skevans#define FW_DEVICE_UNINORTH2 (0x0031 << 16) 76132283Ssimokawa#define FW_DEVICE_AIC5800 (0x5800 << 16) 77111076Ssimokawa#define FW_DEVICE_FW322 (0x5811 << 16) 78132283Ssimokawa#define FW_DEVICE_7007 (0x7007 << 16) 79132283Ssimokawa#define FW_DEVICE_82372FB (0x7605 << 16) 80146439Smarius#define FW_DEVICE_PCIO2FW (0x1102 << 16) 81103285Sikob 82103285Sikob#define PCI_INTERFACE_OHCI 0x10 83103285Sikob 84103285Sikob#define FW_OHCI_BASE_REG 0x10 85103285Sikob 86103285Sikob#define OHCI_DMA_ITCH 0x20 87103285Sikob#define OHCI_DMA_IRCH 0x20 88103285Sikob 89103285Sikob#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 90103285Sikob 91103285Sikob 92129585Sdfrtypedef uint32_t fwohcireg_t; 93103285Sikob 94113584Ssimokawa/* for PCI */ 95113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 96113584Ssimokawa#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 97113584Ssimokawa#define FWOHCI_DMA_READ(x) le32toh(x) 98113584Ssimokawa#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 99113584Ssimokawa#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 100113584Ssimokawa#else 101113584Ssimokawa#define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 102113584Ssimokawa#define FWOHCI_DMA_READ(x) (x) 103113584Ssimokawa#define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 104113584Ssimokawa#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 105113584Ssimokawa#endif 106113584Ssimokawa 107103285Sikobstruct fwohcidb { 108103285Sikob union { 109103285Sikob struct { 110129585Sdfr uint32_t cmd; 111129585Sdfr uint32_t addr; 112129585Sdfr uint32_t depend; 113129585Sdfr uint32_t res; 114103285Sikob } desc; 115129585Sdfr uint32_t immed[4]; 116103285Sikob } db; 117113584Ssimokawa#define OHCI_STATUS_SHIFT 16 118113584Ssimokawa#define OHCI_COUNT_MASK 0xffff 119113584Ssimokawa#define OHCI_OUTPUT_MORE (0 << 28) 120113584Ssimokawa#define OHCI_OUTPUT_LAST (1 << 28) 121113584Ssimokawa#define OHCI_INPUT_MORE (2 << 28) 122113584Ssimokawa#define OHCI_INPUT_LAST (3 << 28) 123113584Ssimokawa#define OHCI_STORE_QUAD (4 << 28) 124113584Ssimokawa#define OHCI_LOAD_QUAD (5 << 28) 125113584Ssimokawa#define OHCI_NOP (6 << 28) 126113584Ssimokawa#define OHCI_STOP (7 << 28) 127113584Ssimokawa#define OHCI_STORE (8 << 28) 128113584Ssimokawa#define OHCI_CMD_MASK (0xf << 28) 129103285Sikob 130113584Ssimokawa#define OHCI_UPDATE (1 << 27) 131103285Sikob 132113584Ssimokawa#define OHCI_KEY_ST0 (0 << 24) 133113584Ssimokawa#define OHCI_KEY_ST1 (1 << 24) 134113584Ssimokawa#define OHCI_KEY_ST2 (2 << 24) 135113584Ssimokawa#define OHCI_KEY_ST3 (3 << 24) 136113584Ssimokawa#define OHCI_KEY_REGS (5 << 24) 137113584Ssimokawa#define OHCI_KEY_SYS (6 << 24) 138113584Ssimokawa#define OHCI_KEY_DEVICE (7 << 24) 139113584Ssimokawa#define OHCI_KEY_MASK (7 << 24) 140103285Sikob 141113584Ssimokawa#define OHCI_INTERRUPT_NEVER (0 << 20) 142113584Ssimokawa#define OHCI_INTERRUPT_TRUE (1 << 20) 143113584Ssimokawa#define OHCI_INTERRUPT_FALSE (2 << 20) 144113584Ssimokawa#define OHCI_INTERRUPT_ALWAYS (3 << 20) 145103285Sikob 146113584Ssimokawa#define OHCI_BRANCH_NEVER (0 << 18) 147113584Ssimokawa#define OHCI_BRANCH_TRUE (1 << 18) 148113584Ssimokawa#define OHCI_BRANCH_FALSE (2 << 18) 149113584Ssimokawa#define OHCI_BRANCH_ALWAYS (3 << 18) 150113584Ssimokawa#define OHCI_BRANCH_MASK (3 << 18) 151103285Sikob 152113584Ssimokawa#define OHCI_WAIT_NEVER (0 << 16) 153113584Ssimokawa#define OHCI_WAIT_TRUE (1 << 16) 154113584Ssimokawa#define OHCI_WAIT_FALSE (2 << 16) 155113584Ssimokawa#define OHCI_WAIT_ALWAYS (3 << 16) 156103285Sikob}; 157103285Sikob 158103285Sikob#define OHCI_SPD_S100 0x4 159103285Sikob#define OHCI_SPD_S200 0x1 160103285Sikob#define OHCI_SPD_S400 0x2 161103285Sikob 162103285Sikob 163103285Sikob#define FWOHCIEV_NOSTAT 0 164103285Sikob#define FWOHCIEV_LONGP 2 165103285Sikob#define FWOHCIEV_MISSACK 3 166103285Sikob#define FWOHCIEV_UNDRRUN 4 167103285Sikob#define FWOHCIEV_OVRRUN 5 168103285Sikob#define FWOHCIEV_DESCERR 6 169103285Sikob#define FWOHCIEV_DTRDERR 7 170103285Sikob#define FWOHCIEV_DTWRERR 8 171103285Sikob#define FWOHCIEV_BUSRST 9 172103285Sikob#define FWOHCIEV_TIMEOUT 0xa 173103285Sikob#define FWOHCIEV_TCODERR 0xb 174103285Sikob#define FWOHCIEV_UNKNOWN 0xe 175103285Sikob#define FWOHCIEV_FLUSHED 0xf 176103285Sikob#define FWOHCIEV_ACKCOMPL 0x11 177103285Sikob#define FWOHCIEV_ACKPEND 0x12 178103285Sikob#define FWOHCIEV_ACKBSX 0x14 179103285Sikob#define FWOHCIEV_ACKBSA 0x15 180103285Sikob#define FWOHCIEV_ACKBSB 0x16 181103285Sikob#define FWOHCIEV_ACKTARD 0x1b 182103285Sikob#define FWOHCIEV_ACKDERR 0x1d 183103285Sikob#define FWOHCIEV_ACKTERR 0x1e 184103285Sikob 185103285Sikob#define FWOHCIEV_MASK 0x1f 186103285Sikob 187272214Skanstruct ohci_dma { 188124168Ssimokawa fwohcireg_t cntl; 189124168Ssimokawa 190124168Ssimokawa#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 191124168Ssimokawa 192124168Ssimokawa#define OHCI_CNTL_BUFFIL (0x1 << 31) 193124168Ssimokawa#define OHCI_CNTL_ISOHDR (0x1 << 30) 194124168Ssimokawa#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 195124168Ssimokawa#define OHCI_CNTL_MULTICH (0x1 << 28) 196124168Ssimokawa 197124168Ssimokawa#define OHCI_CNTL_DMA_RUN (0x1 << 15) 198124168Ssimokawa#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 199124168Ssimokawa#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 200124168Ssimokawa#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 201124168Ssimokawa#define OHCI_CNTL_DMA_BT (0x1 << 8) 202124168Ssimokawa#define OHCI_CNTL_DMA_BAD (0x1 << 7) 203124168Ssimokawa#define OHCI_CNTL_DMA_STAT (0xff) 204124168Ssimokawa 205124168Ssimokawa fwohcireg_t cntl_clr; 206124168Ssimokawa fwohcireg_t dummy0; 207124168Ssimokawa fwohcireg_t cmd; 208124168Ssimokawa fwohcireg_t match; 209124168Ssimokawa fwohcireg_t dummy1; 210124168Ssimokawa fwohcireg_t dummy2; 211124168Ssimokawa fwohcireg_t dummy3; 212124168Ssimokawa}; 213124168Ssimokawa 214272214Skanstruct ohci_itdma { 215124168Ssimokawa fwohcireg_t cntl; 216124168Ssimokawa fwohcireg_t cntl_clr; 217124168Ssimokawa fwohcireg_t dummy0; 218124168Ssimokawa fwohcireg_t cmd; 219124168Ssimokawa}; 220124168Ssimokawa 221103285Sikobstruct ohci_registers { 222103285Sikob fwohcireg_t ver; /* Version No. 0x0 */ 223103285Sikob fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 224103285Sikob fwohcireg_t retry; /* AT retries 0x8 */ 225103285Sikob#define FWOHCI_RETRY 0x8 226103285Sikob fwohcireg_t csr_data; /* CSR data 0xc */ 227103285Sikob fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 228103285Sikob fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 229103285Sikob fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 230103285Sikob fwohcireg_t bus_id; /* BUS_ID 0x1c */ 231103285Sikob fwohcireg_t bus_opt; /* BUS option 0x20 */ 232103285Sikob#define FWOHCIGUID_H 0x24 233103285Sikob#define FWOHCIGUID_L 0x28 234103285Sikob fwohcireg_t guid_hi; /* GUID hi 0x24 */ 235103285Sikob fwohcireg_t guid_lo; /* GUID lo 0x28 */ 236103285Sikob fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 237103285Sikob fwohcireg_t config_rom; /* config ROM map 0x34 */ 238103285Sikob fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 239103285Sikob fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 240272214Skan fwohcireg_t vendor; /* vendor ID 0x40 */ 241103285Sikob fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 242103285Sikob fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 243103285Sikob fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 244258780Seadler#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */ 245108662Ssimokawa#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 246108662Ssimokawa#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 247108662Ssimokawa#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 248108662Ssimokawa#define OHCI_HCC_LPS (1 << 19) /* LPS */ 249108662Ssimokawa#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 250108662Ssimokawa#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 251108662Ssimokawa#define OHCI_HCC_RESET (1 << 16) /* softReset */ 252103285Sikob fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 253103285Sikob fwohcireg_t dummy3[1]; /* dummy 0x60 */ 254103285Sikob fwohcireg_t sid_buf; /* self id buffer 0x64 */ 255103285Sikob fwohcireg_t sid_cnt; /* self id count 0x68 */ 256103285Sikob fwohcireg_t dummy4[1]; /* dummy 0x6c */ 257103285Sikob fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 258103285Sikob fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 259103285Sikob fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 260103285Sikob fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 261103285Sikob#define FWOHCI_INTSTAT 0x80 262103285Sikob#define FWOHCI_INTSTATCLR 0x84 263103285Sikob#define FWOHCI_INTMASK 0x88 264103285Sikob#define FWOHCI_INTMASKCLR 0x8c 265103285Sikob fwohcireg_t int_stat; /* 0x80 */ 266103285Sikob fwohcireg_t int_clear; /* 0x84 */ 267103285Sikob fwohcireg_t int_mask; /* 0x88 */ 268103285Sikob fwohcireg_t int_mask_clear; /* 0x8c */ 269103285Sikob fwohcireg_t it_int_stat; /* 0x90 */ 270103285Sikob fwohcireg_t it_int_clear; /* 0x94 */ 271103285Sikob fwohcireg_t it_int_mask; /* 0x98 */ 272103285Sikob fwohcireg_t it_mask_clear; /* 0x9c */ 273103285Sikob fwohcireg_t ir_int_stat; /* 0xa0 */ 274103285Sikob fwohcireg_t ir_int_clear; /* 0xa4 */ 275103285Sikob fwohcireg_t ir_int_mask; /* 0xa8 */ 276103285Sikob fwohcireg_t ir_mask_clear; /* 0xac */ 277103285Sikob fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 278103285Sikob fwohcireg_t fairness; /* fairness control 0xdc */ 279103285Sikob fwohcireg_t link_cntl; /* Chip control 0xe0*/ 280103285Sikob fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 281103285Sikob#define FWOHCI_NODEID 0xe8 282103285Sikob fwohcireg_t node; /* Node ID 0xe8 */ 283258780Seadler#define OHCI_NODE_VALID (1U << 31) 284103285Sikob#define OHCI_NODE_ROOT (1 << 30) 285103285Sikob 286103285Sikob#define OHCI_ASYSRCBUS 1 287103285Sikob 288103285Sikob fwohcireg_t phy_access; /* PHY cntl 0xec */ 289103285Sikob#define PHYDEV_RDDONE (1<<31) 290103285Sikob#define PHYDEV_RDCMD (1<<15) 291103285Sikob#define PHYDEV_WRCMD (1<<14) 292103285Sikob#define PHYDEV_REGADDR 8 293103285Sikob#define PHYDEV_WRDATA 0 294103285Sikob#define PHYDEV_RDADDR 24 295103285Sikob#define PHYDEV_RDDATA 16 296103285Sikob 297103285Sikob fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 298103285Sikob fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 299103285Sikob fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 300103285Sikob fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 301103285Sikob fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 302103285Sikob fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 303103285Sikob fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 304103285Sikob fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 305103285Sikob fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 306103285Sikob fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 307103285Sikob 308103285Sikob fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 309103285Sikob 310103285Sikob fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 311272214Skan 312103285Sikob /* 0x180, 0x184, 0x188, 0x18c */ 313103285Sikob /* 0x190, 0x194, 0x198, 0x19c */ 314103285Sikob /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 315103285Sikob /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 316103285Sikob /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 317103285Sikob /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 318103285Sikob /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 319103285Sikob /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 320103285Sikob struct ohci_dma dma_ch[0x4]; 321103285Sikob 322103285Sikob /* 0x200, 0x204, 0x208, 0x20c */ 323103285Sikob /* 0x210, 0x204, 0x208, 0x20c */ 324103285Sikob struct ohci_itdma dma_itch[0x20]; 325103285Sikob 326103285Sikob /* 0x400, 0x404, 0x408, 0x40c */ 327103285Sikob /* 0x410, 0x404, 0x408, 0x40c */ 328103285Sikob struct ohci_dma dma_irch[0x20]; 329103285Sikob}; 330103285Sikob 331332156Skevans#ifndef _STANDALONE 332272214Skanstruct fwohcidb_tr { 333103285Sikob STAILQ_ENTRY(fwohcidb_tr) link; 334103285Sikob struct fw_xfer *xfer; 335120660Ssimokawa struct fwohcidb *db; 336113584Ssimokawa bus_dmamap_t dma_map; 337103285Sikob caddr_t buf; 338113584Ssimokawa bus_addr_t bus_addr; 339103285Sikob int dbcnt; 340103285Sikob}; 341332156Skevans#endif 342103285Sikob 343103285Sikob/* 344103285Sikob * OHCI info structure. 345103285Sikob */ 346272214Skanstruct fwohci_txpkthdr { 347272214Skan union { 348129585Sdfr uint32_t ld[4]; 349103285Sikob struct { 350113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 351129585Sdfr uint32_t spd:16, /* XXX include reserved field */ 352129585Sdfr :8, 353129585Sdfr tcode:4, 354129585Sdfr :4; 355113584Ssimokawa#else 356129585Sdfr uint32_t :4, 357129585Sdfr tcode:4, 358129585Sdfr :8, 359129585Sdfr spd:16; /* XXX include reserved fields */ 360113584Ssimokawa#endif 361103285Sikob }common; 362103285Sikob struct { 363113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 364129585Sdfr uint32_t :8, 365129585Sdfr srcbus:1, 366129585Sdfr :4, 367129585Sdfr spd:3, 368129585Sdfr tlrt:8, 369129585Sdfr tcode:4, 370129585Sdfr :4; 371113584Ssimokawa#else 372129585Sdfr uint32_t :4, 373129585Sdfr tcode:4, 374129585Sdfr tlrt:8, 375129585Sdfr spd:3, 376129585Sdfr :4, 377129585Sdfr srcbus:1, 378129585Sdfr :8; 379113584Ssimokawa#endif 380113584Ssimokawa BIT16x2(dst, ); 381272214Skan } asycomm; 382103285Sikob struct { 383113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 384129585Sdfr uint32_t :13, 385129585Sdfr spd:3, 386129585Sdfr chtag:8, 387129585Sdfr tcode:4, 388129585Sdfr sy:4; 389113584Ssimokawa#else 390129585Sdfr uint32_t sy:4, 391129585Sdfr tcode:4, 392129585Sdfr chtag:8, 393129585Sdfr spd:3, 394129585Sdfr :13; 395113584Ssimokawa#endif 396113584Ssimokawa BIT16x2(len, ); 397272214Skan } stream; 398272214Skan } mode; 399103285Sikob}; 400272214Skan 401272214Skanstruct fwohci_trailer { 402169132Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 403169132Ssimokawa uint32_t stat:16, 404272214Skan time:16; 405169132Ssimokawa#else 406129585Sdfr uint32_t time:16, 407272214Skan stat:16; 408169132Ssimokawa#endif 409103285Sikob}; 410103285Sikob 411103285Sikob#define OHCI_CNTL_CYCSRC (0x1 << 22) 412103285Sikob#define OHCI_CNTL_CYCMTR (0x1 << 21) 413103285Sikob#define OHCI_CNTL_CYCTIMER (0x1 << 20) 414103285Sikob#define OHCI_CNTL_PHYPKT (0x1 << 10) 415103285Sikob#define OHCI_CNTL_SID (0x1 << 9) 416103285Sikob 417188508Ssbruno/* 418272214Skan * defined in OHCI 1.1 419188508Ssbruno * chapter 6.1 420188508Ssbruno */ 421103285Sikob#define OHCI_INT_DMA_ATRQ (0x1 << 0) 422103285Sikob#define OHCI_INT_DMA_ATRS (0x1 << 1) 423103285Sikob#define OHCI_INT_DMA_ARRQ (0x1 << 2) 424103285Sikob#define OHCI_INT_DMA_ARRS (0x1 << 3) 425103285Sikob#define OHCI_INT_DMA_PRRQ (0x1 << 4) 426103285Sikob#define OHCI_INT_DMA_PRRS (0x1 << 5) 427188508Ssbruno#define OHCI_INT_DMA_IT (0x1 << 6) 428188508Ssbruno#define OHCI_INT_DMA_IR (0x1 << 7) 429188508Ssbruno#define OHCI_INT_PW_ERR (0x1 << 8) 430188508Ssbruno#define OHCI_INT_LR_ERR (0x1 << 9) 431103285Sikob#define OHCI_INT_PHY_SID (0x1 << 16) 432103285Sikob#define OHCI_INT_PHY_BUS_R (0x1 << 17) 433108276Ssimokawa#define OHCI_INT_REG_FAIL (0x1 << 18) 434103285Sikob#define OHCI_INT_PHY_INT (0x1 << 19) 435103285Sikob#define OHCI_INT_CYC_START (0x1 << 20) 436103285Sikob#define OHCI_INT_CYC_64SECOND (0x1 << 21) 437103285Sikob#define OHCI_INT_CYC_LOST (0x1 << 22) 438103285Sikob#define OHCI_INT_CYC_ERR (0x1 << 23) 439103285Sikob#define OHCI_INT_ERR (0x1 << 24) 440103285Sikob#define OHCI_INT_CYC_LONG (0x1 << 25) 441103285Sikob#define OHCI_INT_PHY_REG (0x1 << 26) 442103285Sikob#define OHCI_INT_EN (0x1 << 31) 443103285Sikob 444103285Sikob#define IP_CHANNELS 0x0234 445103285Sikob#define FWOHCI_MAXREC 2048 446103285Sikob 447103285Sikob#define OHCI_ISORA 0x02 448103285Sikob#define OHCI_ISORB 0x04 449103285Sikob 450103285Sikob#define FWOHCITCODE_PHY 0xe 451