fwohci.c revision 167628
1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 167628 2007-03-16 04:25:02Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if defined(__DragonFly__) || __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#ifdef __DragonFly__ 62#include "firewire.h" 63#include "firewirereg.h" 64#include "fwdma.h" 65#include "fwohcireg.h" 66#include "fwohcivar.h" 67#include "firewire_phy.h" 68#else 69#include <dev/firewire/firewire.h> 70#include <dev/firewire/firewirereg.h> 71#include <dev/firewire/fwdma.h> 72#include <dev/firewire/fwohcireg.h> 73#include <dev/firewire/fwohcivar.h> 74#include <dev/firewire/firewire_phy.h> 75#endif 76 77#undef OHCI_DEBUG 78 79static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 80 "STOR","LOAD","NOP ","STOP",}; 81 82static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83 "UNDEF","REG","SYS","DEV"}; 84static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 85char fwohcicode[32][0x20]={ 86 "No stat","Undef","long","miss Ack err", 87 "underrun","overrun","desc err", "data read err", 88 "data write err","bus reset","timeout","tcode err", 89 "Undef","Undef","unknown event","flushed", 90 "Undef","ack complete","ack pend","Undef", 91 "ack busy_X","ack busy_A","ack busy_B","Undef", 92 "Undef","Undef","Undef","ack tardy", 93 "Undef","ack data_err","ack type_err",""}; 94 95#define MAX_SPEED 3 96extern char *linkspeed[]; 97uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr (struct firewire_comm *); 126static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 127static void fwohci_db_free (struct fwohci_dbch *); 128static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 129static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 130static void fwohci_start_atq (struct firewire_comm *); 131static void fwohci_start_ats (struct firewire_comm *); 132static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 133static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 134static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 135static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 136static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 137static int fwohci_irx_enable (struct firewire_comm *, int); 138static int fwohci_irx_disable (struct firewire_comm *, int); 139#if BYTE_ORDER == BIG_ENDIAN 140static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 141#endif 142static int fwohci_itxbuf_enable (struct firewire_comm *, int); 143static int fwohci_itx_disable (struct firewire_comm *, int); 144static void fwohci_timeout (void *); 145static void fwohci_set_intr (struct firewire_comm *, int); 146 147static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 148static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 149static void dump_db (struct fwohci_softc *, uint32_t); 150static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 151static void dump_dma (struct fwohci_softc *, uint32_t); 152static uint32_t fwohci_cyctimer (struct firewire_comm *); 153static void fwohci_rbuf_update (struct fwohci_softc *, int); 154static void fwohci_tbuf_update (struct fwohci_softc *, int); 155void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 156#if FWOHCI_TASKQUEUE 157static void fwohci_complete(void *, int); 158#endif 159 160/* 161 * memory allocated for DMA programs 162 */ 163#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 164 165#define NDB FWMAXQUEUE 166 167#define OHCI_VERSION 0x00 168#define OHCI_ATRETRY 0x08 169#define OHCI_CROMHDR 0x18 170#define OHCI_BUS_OPT 0x20 171#define OHCI_BUSIRMC (1 << 31) 172#define OHCI_BUSCMC (1 << 30) 173#define OHCI_BUSISC (1 << 29) 174#define OHCI_BUSBMC (1 << 28) 175#define OHCI_BUSPMC (1 << 27) 176#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 177 OHCI_BUSBMC | OHCI_BUSPMC 178 179#define OHCI_EUID_HI 0x24 180#define OHCI_EUID_LO 0x28 181 182#define OHCI_CROMPTR 0x34 183#define OHCI_HCCCTL 0x50 184#define OHCI_HCCCTLCLR 0x54 185#define OHCI_AREQHI 0x100 186#define OHCI_AREQHICLR 0x104 187#define OHCI_AREQLO 0x108 188#define OHCI_AREQLOCLR 0x10c 189#define OHCI_PREQHI 0x110 190#define OHCI_PREQHICLR 0x114 191#define OHCI_PREQLO 0x118 192#define OHCI_PREQLOCLR 0x11c 193#define OHCI_PREQUPPER 0x120 194 195#define OHCI_SID_BUF 0x64 196#define OHCI_SID_CNT 0x68 197#define OHCI_SID_ERR (1 << 31) 198#define OHCI_SID_CNT_MASK 0xffc 199 200#define OHCI_IT_STAT 0x90 201#define OHCI_IT_STATCLR 0x94 202#define OHCI_IT_MASK 0x98 203#define OHCI_IT_MASKCLR 0x9c 204 205#define OHCI_IR_STAT 0xa0 206#define OHCI_IR_STATCLR 0xa4 207#define OHCI_IR_MASK 0xa8 208#define OHCI_IR_MASKCLR 0xac 209 210#define OHCI_LNKCTL 0xe0 211#define OHCI_LNKCTLCLR 0xe4 212 213#define OHCI_PHYACCESS 0xec 214#define OHCI_CYCLETIMER 0xf0 215 216#define OHCI_DMACTL(off) (off) 217#define OHCI_DMACTLCLR(off) (off + 4) 218#define OHCI_DMACMD(off) (off + 0xc) 219#define OHCI_DMAMATCH(off) (off + 0x10) 220 221#define OHCI_ATQOFF 0x180 222#define OHCI_ATQCTL OHCI_ATQOFF 223#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 224#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 225#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 226 227#define OHCI_ATSOFF 0x1a0 228#define OHCI_ATSCTL OHCI_ATSOFF 229#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 230#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 231#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 232 233#define OHCI_ARQOFF 0x1c0 234#define OHCI_ARQCTL OHCI_ARQOFF 235#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 236#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 237#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 238 239#define OHCI_ARSOFF 0x1e0 240#define OHCI_ARSCTL OHCI_ARSOFF 241#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 242#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 243#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 244 245#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 246#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 247#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 248#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 249 250#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 251#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 252#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 253#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 254#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 255 256d_ioctl_t fwohci_ioctl; 257 258/* 259 * Communication with PHY device 260 */ 261static uint32_t 262fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 263{ 264 uint32_t fun; 265 266 addr &= 0xf; 267 data &= 0xff; 268 269 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 270 OWRITE(sc, OHCI_PHYACCESS, fun); 271 DELAY(100); 272 273 return(fwphy_rddata( sc, addr)); 274} 275 276static uint32_t 277fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 278{ 279 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 280 int i; 281 uint32_t bm; 282 283#define OHCI_CSR_DATA 0x0c 284#define OHCI_CSR_COMP 0x10 285#define OHCI_CSR_CONT 0x14 286#define OHCI_BUS_MANAGER_ID 0 287 288 OWRITE(sc, OHCI_CSR_DATA, node); 289 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 290 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 291 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 292 DELAY(10); 293 bm = OREAD(sc, OHCI_CSR_DATA); 294 if((bm & 0x3f) == 0x3f) 295 bm = node; 296 if (firewire_debug) 297 device_printf(sc->fc.dev, 298 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 299 300 return(bm); 301} 302 303static uint32_t 304fwphy_rddata(struct fwohci_softc *sc, u_int addr) 305{ 306 uint32_t fun, stat; 307 u_int i, retry = 0; 308 309 addr &= 0xf; 310#define MAX_RETRY 100 311again: 312 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 313 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 314 OWRITE(sc, OHCI_PHYACCESS, fun); 315 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 316 fun = OREAD(sc, OHCI_PHYACCESS); 317 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 318 break; 319 DELAY(100); 320 } 321 if(i >= MAX_RETRY) { 322 if (firewire_debug) 323 device_printf(sc->fc.dev, "phy read failed(1).\n"); 324 if (++retry < MAX_RETRY) { 325 DELAY(100); 326 goto again; 327 } 328 } 329 /* Make sure that SCLK is started */ 330 stat = OREAD(sc, FWOHCI_INTSTAT); 331 if ((stat & OHCI_INT_REG_FAIL) != 0 || 332 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 333 if (firewire_debug) 334 device_printf(sc->fc.dev, "phy read failed(2).\n"); 335 if (++retry < MAX_RETRY) { 336 DELAY(100); 337 goto again; 338 } 339 } 340 if (firewire_debug || retry >= MAX_RETRY) 341 device_printf(sc->fc.dev, 342 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 343#undef MAX_RETRY 344 return((fun >> PHYDEV_RDDATA )& 0xff); 345} 346/* Device specific ioctl. */ 347int 348fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 349{ 350 struct firewire_softc *sc; 351 struct fwohci_softc *fc; 352 int unit = DEV2UNIT(dev); 353 int err = 0; 354 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 355 uint32_t *dmach = (uint32_t *) data; 356 357 sc = devclass_get_softc(firewire_devclass, unit); 358 if(sc == NULL){ 359 return(EINVAL); 360 } 361 fc = (struct fwohci_softc *)sc->fc; 362 363 if (!data) 364 return(EINVAL); 365 366 switch (cmd) { 367 case FWOHCI_WRREG: 368#define OHCI_MAX_REG 0x800 369 if(reg->addr <= OHCI_MAX_REG){ 370 OWRITE(fc, reg->addr, reg->data); 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376 case FWOHCI_RDREG: 377 if(reg->addr <= OHCI_MAX_REG){ 378 reg->data = OREAD(fc, reg->addr); 379 }else{ 380 err = EINVAL; 381 } 382 break; 383/* Read DMA descriptors for debug */ 384 case DUMPDMA: 385 if(*dmach <= OHCI_MAX_DMA_CH ){ 386 dump_dma(fc, *dmach); 387 dump_db(fc, *dmach); 388 }else{ 389 err = EINVAL; 390 } 391 break; 392/* Read/Write Phy registers */ 393#define OHCI_MAX_PHY_REG 0xf 394 case FWOHCI_RDPHYREG: 395 if (reg->addr <= OHCI_MAX_PHY_REG) 396 reg->data = fwphy_rddata(fc, reg->addr); 397 else 398 err = EINVAL; 399 break; 400 case FWOHCI_WRPHYREG: 401 if (reg->addr <= OHCI_MAX_PHY_REG) 402 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 403 else 404 err = EINVAL; 405 break; 406 default: 407 err = EINVAL; 408 break; 409 } 410 return err; 411} 412 413static int 414fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 415{ 416 uint32_t reg, reg2; 417 int e1394a = 1; 418/* 419 * probe PHY parameters 420 * 0. to prove PHY version, whether compliance of 1394a. 421 * 1. to probe maximum speed supported by the PHY and 422 * number of port supported by core-logic. 423 * It is not actually available port on your PC . 424 */ 425 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 426 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 427 428 if((reg >> 5) != 7 ){ 429 sc->fc.mode &= ~FWPHYASYST; 430 sc->fc.nport = reg & FW_PHY_NP; 431 sc->fc.speed = reg & FW_PHY_SPD >> 6; 432 if (sc->fc.speed > MAX_SPEED) { 433 device_printf(dev, "invalid speed %d (fixed to %d).\n", 434 sc->fc.speed, MAX_SPEED); 435 sc->fc.speed = MAX_SPEED; 436 } 437 device_printf(dev, 438 "Phy 1394 only %s, %d ports.\n", 439 linkspeed[sc->fc.speed], sc->fc.nport); 440 }else{ 441 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 442 sc->fc.mode |= FWPHYASYST; 443 sc->fc.nport = reg & FW_PHY_NP; 444 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 445 if (sc->fc.speed > MAX_SPEED) { 446 device_printf(dev, "invalid speed %d (fixed to %d).\n", 447 sc->fc.speed, MAX_SPEED); 448 sc->fc.speed = MAX_SPEED; 449 } 450 device_printf(dev, 451 "Phy 1394a available %s, %d ports.\n", 452 linkspeed[sc->fc.speed], sc->fc.nport); 453 454 /* check programPhyEnable */ 455 reg2 = fwphy_rddata(sc, 5); 456#if 0 457 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 458#else /* XXX force to enable 1394a */ 459 if (e1394a) { 460#endif 461 if (firewire_debug) 462 device_printf(dev, 463 "Enable 1394a Enhancements\n"); 464 /* enable EAA EMC */ 465 reg2 |= 0x03; 466 /* set aPhyEnhanceEnable */ 467 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 468 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 469 } else { 470 /* for safe */ 471 reg2 &= ~0x83; 472 } 473 reg2 = fwphy_wrdata(sc, 5, reg2); 474 } 475 476 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 477 if((reg >> 5) == 7 ){ 478 reg = fwphy_rddata(sc, 4); 479 reg |= 1 << 6; 480 fwphy_wrdata(sc, 4, reg); 481 reg = fwphy_rddata(sc, 4); 482 } 483 return 0; 484} 485 486 487void 488fwohci_reset(struct fwohci_softc *sc, device_t dev) 489{ 490 int i, max_rec, speed; 491 uint32_t reg, reg2; 492 struct fwohcidb_tr *db_tr; 493 494 /* Disable interrupts */ 495 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 496 497 /* Now stopping all DMA channels */ 498 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 499 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 500 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 501 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 502 503 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 504 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 505 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 506 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 507 } 508 509 /* FLUSH FIFO and reset Transmitter/Reciever */ 510 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 511 if (firewire_debug) 512 device_printf(dev, "resetting OHCI..."); 513 i = 0; 514 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 515 if (i++ > 100) break; 516 DELAY(1000); 517 } 518 if (firewire_debug) 519 printf("done (loop=%d)\n", i); 520 521 /* Probe phy */ 522 fwohci_probe_phy(sc, dev); 523 524 /* Probe link */ 525 reg = OREAD(sc, OHCI_BUS_OPT); 526 reg2 = reg | OHCI_BUSFNC; 527 max_rec = (reg & 0x0000f000) >> 12; 528 speed = (reg & 0x00000007); 529 device_printf(dev, "Link %s, max_rec %d bytes.\n", 530 linkspeed[speed], MAXREC(max_rec)); 531 /* XXX fix max_rec */ 532 sc->fc.maxrec = sc->fc.speed + 8; 533 if (max_rec != sc->fc.maxrec) { 534 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 535 device_printf(dev, "max_rec %d -> %d\n", 536 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 537 } 538 if (firewire_debug) 539 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 540 OWRITE(sc, OHCI_BUS_OPT, reg2); 541 542 /* Initialize registers */ 543 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 544 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 545 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 546 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 547 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 548 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 549 550 /* Enable link */ 551 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 552 553 /* Force to start async RX DMA */ 554 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 555 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 556 fwohci_rx_enable(sc, &sc->arrq); 557 fwohci_rx_enable(sc, &sc->arrs); 558 559 /* Initialize async TX */ 560 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 561 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562 563 /* AT Retries */ 564 OWRITE(sc, FWOHCI_RETRY, 565 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 566 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 567 568 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 569 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 570 sc->atrq.bottom = sc->atrq.top; 571 sc->atrs.bottom = sc->atrs.top; 572 573 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 574 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 575 db_tr->xfer = NULL; 576 } 577 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 578 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 579 db_tr->xfer = NULL; 580 } 581 582 583 /* Enable interrupts */ 584 OWRITE(sc, FWOHCI_INTMASK, 585 OHCI_INT_ERR | OHCI_INT_PHY_SID 586 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 587 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 588 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 589 fwohci_set_intr(&sc->fc, 1); 590 591} 592 593int 594fwohci_init(struct fwohci_softc *sc, device_t dev) 595{ 596 int i, mver; 597 uint32_t reg; 598 uint8_t ui[8]; 599 600#if FWOHCI_TASKQUEUE 601 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 602#endif 603 604/* OHCI version */ 605 reg = OREAD(sc, OHCI_VERSION); 606 mver = (reg >> 16) & 0xff; 607 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 608 mver, reg & 0xff, (reg>>24) & 1); 609 if (mver < 1 || mver > 9) { 610 device_printf(dev, "invalid OHCI version\n"); 611 return (ENXIO); 612 } 613 614/* Available Isochronous DMA channel probe */ 615 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 616 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 617 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 618 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 619 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 620 for (i = 0; i < 0x20; i++) 621 if ((reg & (1 << i)) == 0) 622 break; 623 sc->fc.nisodma = i; 624 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 625 if (i == 0) 626 return (ENXIO); 627 628 sc->fc.arq = &sc->arrq.xferq; 629 sc->fc.ars = &sc->arrs.xferq; 630 sc->fc.atq = &sc->atrq.xferq; 631 sc->fc.ats = &sc->atrs.xferq; 632 633 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 634 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 635 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 636 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 637 638 sc->arrq.xferq.start = NULL; 639 sc->arrs.xferq.start = NULL; 640 sc->atrq.xferq.start = fwohci_start_atq; 641 sc->atrs.xferq.start = fwohci_start_ats; 642 643 sc->arrq.xferq.buf = NULL; 644 sc->arrs.xferq.buf = NULL; 645 sc->atrq.xferq.buf = NULL; 646 sc->atrs.xferq.buf = NULL; 647 648 sc->arrq.xferq.dmach = -1; 649 sc->arrs.xferq.dmach = -1; 650 sc->atrq.xferq.dmach = -1; 651 sc->atrs.xferq.dmach = -1; 652 653 sc->arrq.ndesc = 1; 654 sc->arrs.ndesc = 1; 655 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 656 sc->atrs.ndesc = 2; 657 658 sc->arrq.ndb = NDB; 659 sc->arrs.ndb = NDB / 2; 660 sc->atrq.ndb = NDB; 661 sc->atrs.ndb = NDB / 2; 662 663 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 664 sc->fc.it[i] = &sc->it[i].xferq; 665 sc->fc.ir[i] = &sc->ir[i].xferq; 666 sc->it[i].xferq.dmach = i; 667 sc->ir[i].xferq.dmach = i; 668 sc->it[i].ndb = 0; 669 sc->ir[i].ndb = 0; 670 } 671 672 sc->fc.tcode = tinfo; 673 sc->fc.dev = dev; 674 675 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 676 &sc->crom_dma, BUS_DMA_WAITOK); 677 if(sc->fc.config_rom == NULL){ 678 device_printf(dev, "config_rom alloc failed."); 679 return ENOMEM; 680 } 681 682#if 0 683 bzero(&sc->fc.config_rom[0], CROMSIZE); 684 sc->fc.config_rom[1] = 0x31333934; 685 sc->fc.config_rom[2] = 0xf000a002; 686 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 687 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 688 sc->fc.config_rom[5] = 0; 689 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 690 691 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 692#endif 693 694 695/* SID recieve buffer must align 2^11 */ 696#define OHCI_SIDSIZE (1 << 11) 697 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 698 &sc->sid_dma, BUS_DMA_WAITOK); 699 if (sc->sid_buf == NULL) { 700 device_printf(dev, "sid_buf alloc failed."); 701 return ENOMEM; 702 } 703 704 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 705 &sc->dummy_dma, BUS_DMA_WAITOK); 706 707 if (sc->dummy_dma.v_addr == NULL) { 708 device_printf(dev, "dummy_dma alloc failed."); 709 return ENOMEM; 710 } 711 712 fwohci_db_init(sc, &sc->arrq); 713 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 714 return ENOMEM; 715 716 fwohci_db_init(sc, &sc->arrs); 717 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 718 return ENOMEM; 719 720 fwohci_db_init(sc, &sc->atrq); 721 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 722 return ENOMEM; 723 724 fwohci_db_init(sc, &sc->atrs); 725 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 726 return ENOMEM; 727 728 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 729 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 730 for( i = 0 ; i < 8 ; i ++) 731 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 732 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 733 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 734 735 sc->fc.ioctl = fwohci_ioctl; 736 sc->fc.cyctimer = fwohci_cyctimer; 737 sc->fc.set_bmr = fwohci_set_bus_manager; 738 sc->fc.ibr = fwohci_ibr; 739 sc->fc.irx_enable = fwohci_irx_enable; 740 sc->fc.irx_disable = fwohci_irx_disable; 741 742 sc->fc.itx_enable = fwohci_itxbuf_enable; 743 sc->fc.itx_disable = fwohci_itx_disable; 744#if BYTE_ORDER == BIG_ENDIAN 745 sc->fc.irx_post = fwohci_irx_post; 746#else 747 sc->fc.irx_post = NULL; 748#endif 749 sc->fc.itx_post = NULL; 750 sc->fc.timeout = fwohci_timeout; 751 sc->fc.poll = fwohci_poll; 752 sc->fc.set_intr = fwohci_set_intr; 753 754 sc->intmask = sc->irstat = sc->itstat = 0; 755 756 fw_init(&sc->fc); 757 fwohci_reset(sc, dev); 758 759 return 0; 760} 761 762void 763fwohci_timeout(void *arg) 764{ 765 struct fwohci_softc *sc; 766 767 sc = (struct fwohci_softc *)arg; 768} 769 770uint32_t 771fwohci_cyctimer(struct firewire_comm *fc) 772{ 773 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 774 return(OREAD(sc, OHCI_CYCLETIMER)); 775} 776 777int 778fwohci_detach(struct fwohci_softc *sc, device_t dev) 779{ 780 int i; 781 782 if (sc->sid_buf != NULL) 783 fwdma_free(&sc->fc, &sc->sid_dma); 784 if (sc->fc.config_rom != NULL) 785 fwdma_free(&sc->fc, &sc->crom_dma); 786 787 fwohci_db_free(&sc->arrq); 788 fwohci_db_free(&sc->arrs); 789 790 fwohci_db_free(&sc->atrq); 791 fwohci_db_free(&sc->atrs); 792 793 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 794 fwohci_db_free(&sc->it[i]); 795 fwohci_db_free(&sc->ir[i]); 796 } 797 798 return 0; 799} 800 801#define LAST_DB(dbtr, db) do { \ 802 struct fwohcidb_tr *_dbtr = (dbtr); \ 803 int _cnt = _dbtr->dbcnt; \ 804 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 805} while (0) 806 807static void 808fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 809{ 810 struct fwohcidb_tr *db_tr; 811 struct fwohcidb *db; 812 bus_dma_segment_t *s; 813 int i; 814 815 db_tr = (struct fwohcidb_tr *)arg; 816 db = &db_tr->db[db_tr->dbcnt]; 817 if (error) { 818 if (firewire_debug || error != EFBIG) 819 printf("fwohci_execute_db: error=%d\n", error); 820 return; 821 } 822 for (i = 0; i < nseg; i++) { 823 s = &segs[i]; 824 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 825 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 826 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 827 db++; 828 db_tr->dbcnt++; 829 } 830} 831 832static void 833fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 834 bus_size_t size, int error) 835{ 836 fwohci_execute_db(arg, segs, nseg, error); 837} 838 839static void 840fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 841{ 842 int i, s; 843 int tcode, hdr_len, pl_off; 844 int fsegment = -1; 845 uint32_t off; 846 struct fw_xfer *xfer; 847 struct fw_pkt *fp; 848 struct fwohci_txpkthdr *ohcifp; 849 struct fwohcidb_tr *db_tr; 850 struct fwohcidb *db; 851 uint32_t *ld; 852 struct tcode_info *info; 853 static int maxdesc=0; 854 855 if(&sc->atrq == dbch){ 856 off = OHCI_ATQOFF; 857 }else if(&sc->atrs == dbch){ 858 off = OHCI_ATSOFF; 859 }else{ 860 return; 861 } 862 863 if (dbch->flags & FWOHCI_DBCH_FULL) 864 return; 865 866 s = splfw(); 867 db_tr = dbch->top; 868txloop: 869 xfer = STAILQ_FIRST(&dbch->xferq.q); 870 if(xfer == NULL){ 871 goto kick; 872 } 873 if(dbch->xferq.queued == 0 ){ 874 device_printf(sc->fc.dev, "TX queue empty\n"); 875 } 876 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 877 db_tr->xfer = xfer; 878 xfer->state = FWXF_START; 879 880 fp = &xfer->send.hdr; 881 tcode = fp->mode.common.tcode; 882 883 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 884 info = &tinfo[tcode]; 885 hdr_len = pl_off = info->hdr_len; 886 887 ld = &ohcifp->mode.ld[0]; 888 ld[0] = ld[1] = ld[2] = ld[3] = 0; 889 for( i = 0 ; i < pl_off ; i+= 4) 890 ld[i/4] = fp->mode.ld[i/4]; 891 892 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 893 if (tcode == FWTCODE_STREAM ){ 894 hdr_len = 8; 895 ohcifp->mode.stream.len = fp->mode.stream.len; 896 } else if (tcode == FWTCODE_PHY) { 897 hdr_len = 12; 898 ld[1] = fp->mode.ld[1]; 899 ld[2] = fp->mode.ld[2]; 900 ohcifp->mode.common.spd = 0; 901 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 902 } else { 903 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 904 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 905 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 906 } 907 db = &db_tr->db[0]; 908 FWOHCI_DMA_WRITE(db->db.desc.cmd, 909 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 910 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 911 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 912/* Specify bound timer of asy. responce */ 913 if(&sc->atrs == dbch){ 914 FWOHCI_DMA_WRITE(db->db.desc.res, 915 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 916 } 917#if BYTE_ORDER == BIG_ENDIAN 918 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 919 hdr_len = 12; 920 for (i = 0; i < hdr_len/4; i ++) 921 FWOHCI_DMA_WRITE(ld[i], ld[i]); 922#endif 923 924again: 925 db_tr->dbcnt = 2; 926 db = &db_tr->db[db_tr->dbcnt]; 927 if (xfer->send.pay_len > 0) { 928 int err; 929 /* handle payload */ 930 if (xfer->mbuf == NULL) { 931 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 932 &xfer->send.payload[0], xfer->send.pay_len, 933 fwohci_execute_db, db_tr, 934 /*flags*/0); 935 } else { 936 /* XXX we can handle only 6 (=8-2) mbuf chains */ 937 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 938 xfer->mbuf, 939 fwohci_execute_db2, db_tr, 940 /* flags */0); 941 if (err == EFBIG) { 942 struct mbuf *m0; 943 944 if (firewire_debug) 945 device_printf(sc->fc.dev, "EFBIG.\n"); 946 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 947 if (m0 != NULL) { 948 m_copydata(xfer->mbuf, 0, 949 xfer->mbuf->m_pkthdr.len, 950 mtod(m0, caddr_t)); 951 m0->m_len = m0->m_pkthdr.len = 952 xfer->mbuf->m_pkthdr.len; 953 m_freem(xfer->mbuf); 954 xfer->mbuf = m0; 955 goto again; 956 } 957 device_printf(sc->fc.dev, "m_getcl failed.\n"); 958 } 959 } 960 if (err) 961 printf("dmamap_load: err=%d\n", err); 962 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 963 BUS_DMASYNC_PREWRITE); 964#if 0 /* OHCI_OUTPUT_MODE == 0 */ 965 for (i = 2; i < db_tr->dbcnt; i++) 966 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 967 OHCI_OUTPUT_MORE); 968#endif 969 } 970 if (maxdesc < db_tr->dbcnt) { 971 maxdesc = db_tr->dbcnt; 972 if (firewire_debug) 973 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 974 } 975 /* last db */ 976 LAST_DB(db_tr, db); 977 FWOHCI_DMA_SET(db->db.desc.cmd, 978 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 979 FWOHCI_DMA_WRITE(db->db.desc.depend, 980 STAILQ_NEXT(db_tr, link)->bus_addr); 981 982 if(fsegment == -1 ) 983 fsegment = db_tr->dbcnt; 984 if (dbch->pdb_tr != NULL) { 985 LAST_DB(dbch->pdb_tr, db); 986 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 987 } 988 dbch->pdb_tr = db_tr; 989 db_tr = STAILQ_NEXT(db_tr, link); 990 if(db_tr != dbch->bottom){ 991 goto txloop; 992 } else { 993 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 994 dbch->flags |= FWOHCI_DBCH_FULL; 995 } 996kick: 997 /* kick asy q */ 998 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 999 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1000 1001 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1002 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1003 } else { 1004 if (firewire_debug) 1005 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1006 OREAD(sc, OHCI_DMACTL(off))); 1007 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1008 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1009 dbch->xferq.flag |= FWXFERQ_RUNNING; 1010 } 1011 1012 dbch->top = db_tr; 1013 splx(s); 1014 return; 1015} 1016 1017static void 1018fwohci_start_atq(struct firewire_comm *fc) 1019{ 1020 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021 fwohci_start( sc, &(sc->atrq)); 1022 return; 1023} 1024 1025static void 1026fwohci_start_ats(struct firewire_comm *fc) 1027{ 1028 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1029 fwohci_start( sc, &(sc->atrs)); 1030 return; 1031} 1032 1033void 1034fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1035{ 1036 int s, ch, err = 0; 1037 struct fwohcidb_tr *tr; 1038 struct fwohcidb *db; 1039 struct fw_xfer *xfer; 1040 uint32_t off; 1041 u_int stat, status; 1042 int packets; 1043 struct firewire_comm *fc = (struct firewire_comm *)sc; 1044 1045 if(&sc->atrq == dbch){ 1046 off = OHCI_ATQOFF; 1047 ch = ATRQ_CH; 1048 }else if(&sc->atrs == dbch){ 1049 off = OHCI_ATSOFF; 1050 ch = ATRS_CH; 1051 }else{ 1052 return; 1053 } 1054 s = splfw(); 1055 tr = dbch->bottom; 1056 packets = 0; 1057 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1058 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1059 while(dbch->xferq.queued > 0){ 1060 LAST_DB(tr, db); 1061 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1062 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1063 if (fc->status != FWBUSRESET) 1064 /* maybe out of order?? */ 1065 goto out; 1066 } 1067 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1068 BUS_DMASYNC_POSTWRITE); 1069 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1070#if 1 1071 if (firewire_debug) 1072 dump_db(sc, ch); 1073#endif 1074 if(status & OHCI_CNTL_DMA_DEAD) { 1075 /* Stop DMA */ 1076 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1077 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1078 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1079 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1080 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1081 } 1082 stat = status & FWOHCIEV_MASK; 1083 switch(stat){ 1084 case FWOHCIEV_ACKPEND: 1085 case FWOHCIEV_ACKCOMPL: 1086 err = 0; 1087 break; 1088 case FWOHCIEV_ACKBSA: 1089 case FWOHCIEV_ACKBSB: 1090 case FWOHCIEV_ACKBSX: 1091 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1092 err = EBUSY; 1093 break; 1094 case FWOHCIEV_FLUSHED: 1095 case FWOHCIEV_ACKTARD: 1096 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1097 err = EAGAIN; 1098 break; 1099 case FWOHCIEV_MISSACK: 1100 case FWOHCIEV_UNDRRUN: 1101 case FWOHCIEV_OVRRUN: 1102 case FWOHCIEV_DESCERR: 1103 case FWOHCIEV_DTRDERR: 1104 case FWOHCIEV_TIMEOUT: 1105 case FWOHCIEV_TCODERR: 1106 case FWOHCIEV_UNKNOWN: 1107 case FWOHCIEV_ACKDERR: 1108 case FWOHCIEV_ACKTERR: 1109 default: 1110 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1111 stat, fwohcicode[stat]); 1112 err = EINVAL; 1113 break; 1114 } 1115 if (tr->xfer != NULL) { 1116 xfer = tr->xfer; 1117 if (xfer->state == FWXF_RCVD) { 1118#if 0 1119 if (firewire_debug) 1120 printf("already rcvd\n"); 1121#endif 1122 fw_xfer_done(xfer); 1123 } else { 1124 xfer->state = FWXF_SENT; 1125 if (err == EBUSY && fc->status != FWBUSRESET) { 1126 xfer->state = FWXF_BUSY; 1127 xfer->resp = err; 1128 if (xfer->retry_req != NULL) 1129 xfer->retry_req(xfer); 1130 else { 1131 xfer->recv.pay_len = 0; 1132 fw_xfer_done(xfer); 1133 } 1134 } else if (stat != FWOHCIEV_ACKPEND) { 1135 if (stat != FWOHCIEV_ACKCOMPL) 1136 xfer->state = FWXF_SENTERR; 1137 xfer->resp = err; 1138 xfer->recv.pay_len = 0; 1139 fw_xfer_done(xfer); 1140 } 1141 } 1142 /* 1143 * The watchdog timer takes care of split 1144 * transcation timeout for ACKPEND case. 1145 */ 1146 } else { 1147 printf("this shouldn't happen\n"); 1148 } 1149 dbch->xferq.queued --; 1150 tr->xfer = NULL; 1151 1152 packets ++; 1153 tr = STAILQ_NEXT(tr, link); 1154 dbch->bottom = tr; 1155 if (dbch->bottom == dbch->top) { 1156 /* we reaches the end of context program */ 1157 if (firewire_debug && dbch->xferq.queued > 0) 1158 printf("queued > 0\n"); 1159 break; 1160 } 1161 } 1162out: 1163 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1164 printf("make free slot\n"); 1165 dbch->flags &= ~FWOHCI_DBCH_FULL; 1166 fwohci_start(sc, dbch); 1167 } 1168 splx(s); 1169} 1170 1171static void 1172fwohci_db_free(struct fwohci_dbch *dbch) 1173{ 1174 struct fwohcidb_tr *db_tr; 1175 int idb; 1176 1177 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1178 return; 1179 1180 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1181 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1182 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1183 db_tr->buf != NULL) { 1184 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1185 db_tr->buf, dbch->xferq.psize); 1186 db_tr->buf = NULL; 1187 } else if (db_tr->dma_map != NULL) 1188 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1189 } 1190 dbch->ndb = 0; 1191 db_tr = STAILQ_FIRST(&dbch->db_trq); 1192 fwdma_free_multiseg(dbch->am); 1193 free(db_tr, M_FW); 1194 STAILQ_INIT(&dbch->db_trq); 1195 dbch->flags &= ~FWOHCI_DBCH_INIT; 1196} 1197 1198static void 1199fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1200{ 1201 int idb; 1202 struct fwohcidb_tr *db_tr; 1203 1204 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1205 goto out; 1206 1207 /* create dma_tag for buffers */ 1208#define MAX_REQCOUNT 0xffff 1209 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1210 /*alignment*/ 1, /*boundary*/ 0, 1211 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1212 /*highaddr*/ BUS_SPACE_MAXADDR, 1213 /*filter*/NULL, /*filterarg*/NULL, 1214 /*maxsize*/ dbch->xferq.psize, 1215 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1216 /*maxsegsz*/ MAX_REQCOUNT, 1217 /*flags*/ 0, 1218#if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1219 /*lockfunc*/busdma_lock_mutex, 1220 /*lockarg*/&Giant, 1221#endif 1222 &dbch->dmat)) 1223 return; 1224 1225 /* allocate DB entries and attach one to each DMA channels */ 1226 /* DB entry must start at 16 bytes bounary. */ 1227 STAILQ_INIT(&dbch->db_trq); 1228 db_tr = (struct fwohcidb_tr *) 1229 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1230 M_FW, M_WAITOK | M_ZERO); 1231 if(db_tr == NULL){ 1232 printf("fwohci_db_init: malloc(1) failed\n"); 1233 return; 1234 } 1235 1236#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1237 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1238 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1239 if (dbch->am == NULL) { 1240 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1241 free(db_tr, M_FW); 1242 return; 1243 } 1244 /* Attach DB to DMA ch. */ 1245 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1246 db_tr->dbcnt = 0; 1247 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1248 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1249 /* create dmamap for buffers */ 1250 /* XXX do we need 4bytes alignment tag? */ 1251 /* XXX don't alloc dma_map for AR */ 1252 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1253 printf("bus_dmamap_create failed\n"); 1254 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1255 fwohci_db_free(dbch); 1256 return; 1257 } 1258 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1259 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1260 if (idb % dbch->xferq.bnpacket == 0) 1261 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1262 ].start = (caddr_t)db_tr; 1263 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1264 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1265 ].end = (caddr_t)db_tr; 1266 } 1267 db_tr++; 1268 } 1269 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1270 = STAILQ_FIRST(&dbch->db_trq); 1271out: 1272 dbch->xferq.queued = 0; 1273 dbch->pdb_tr = NULL; 1274 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1275 dbch->bottom = dbch->top; 1276 dbch->flags = FWOHCI_DBCH_INIT; 1277} 1278 1279static int 1280fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1281{ 1282 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1283 1284 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1285 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1286 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1287 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1288 /* XXX we cannot free buffers until the DMA really stops */ 1289 pause("fwitxd", hz); 1290 fwohci_db_free(&sc->it[dmach]); 1291 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1292 return 0; 1293} 1294 1295static int 1296fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1297{ 1298 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1299 1300 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1301 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1302 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1303 /* XXX we cannot free buffers until the DMA really stops */ 1304 pause("fwirxd", hz); 1305 fwohci_db_free(&sc->ir[dmach]); 1306 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1307 return 0; 1308} 1309 1310#if BYTE_ORDER == BIG_ENDIAN 1311static void 1312fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1313{ 1314 qld[0] = FWOHCI_DMA_READ(qld[0]); 1315 return; 1316} 1317#endif 1318 1319static int 1320fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1321{ 1322 int err = 0; 1323 int idb, z, i, dmach = 0, ldesc; 1324 uint32_t off = 0; 1325 struct fwohcidb_tr *db_tr; 1326 struct fwohcidb *db; 1327 1328 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1329 err = EINVAL; 1330 return err; 1331 } 1332 z = dbch->ndesc; 1333 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1334 if( &sc->it[dmach] == dbch){ 1335 off = OHCI_ITOFF(dmach); 1336 break; 1337 } 1338 } 1339 if(off == 0){ 1340 err = EINVAL; 1341 return err; 1342 } 1343 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1344 return err; 1345 dbch->xferq.flag |= FWXFERQ_RUNNING; 1346 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1347 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1348 } 1349 db_tr = dbch->top; 1350 for (idb = 0; idb < dbch->ndb; idb ++) { 1351 fwohci_add_tx_buf(dbch, db_tr, idb); 1352 if(STAILQ_NEXT(db_tr, link) == NULL){ 1353 break; 1354 } 1355 db = db_tr->db; 1356 ldesc = db_tr->dbcnt - 1; 1357 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1358 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1359 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1360 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1361 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1362 FWOHCI_DMA_SET( 1363 db[ldesc].db.desc.cmd, 1364 OHCI_INTERRUPT_ALWAYS); 1365 /* OHCI 1.1 and above */ 1366 FWOHCI_DMA_SET( 1367 db[0].db.desc.cmd, 1368 OHCI_INTERRUPT_ALWAYS); 1369 } 1370 } 1371 db_tr = STAILQ_NEXT(db_tr, link); 1372 } 1373 FWOHCI_DMA_CLEAR( 1374 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1375 return err; 1376} 1377 1378static int 1379fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1380{ 1381 int err = 0; 1382 int idb, z, i, dmach = 0, ldesc; 1383 uint32_t off = 0; 1384 struct fwohcidb_tr *db_tr; 1385 struct fwohcidb *db; 1386 1387 z = dbch->ndesc; 1388 if(&sc->arrq == dbch){ 1389 off = OHCI_ARQOFF; 1390 }else if(&sc->arrs == dbch){ 1391 off = OHCI_ARSOFF; 1392 }else{ 1393 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1394 if( &sc->ir[dmach] == dbch){ 1395 off = OHCI_IROFF(dmach); 1396 break; 1397 } 1398 } 1399 } 1400 if(off == 0){ 1401 err = EINVAL; 1402 return err; 1403 } 1404 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1405 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1406 return err; 1407 }else{ 1408 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1409 err = EBUSY; 1410 return err; 1411 } 1412 } 1413 dbch->xferq.flag |= FWXFERQ_RUNNING; 1414 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1415 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1416 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1417 } 1418 db_tr = dbch->top; 1419 for (idb = 0; idb < dbch->ndb; idb ++) { 1420 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1421 if (STAILQ_NEXT(db_tr, link) == NULL) 1422 break; 1423 db = db_tr->db; 1424 ldesc = db_tr->dbcnt - 1; 1425 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1426 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1427 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1428 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1429 FWOHCI_DMA_SET( 1430 db[ldesc].db.desc.cmd, 1431 OHCI_INTERRUPT_ALWAYS); 1432 FWOHCI_DMA_CLEAR( 1433 db[ldesc].db.desc.depend, 1434 0xf); 1435 } 1436 } 1437 db_tr = STAILQ_NEXT(db_tr, link); 1438 } 1439 FWOHCI_DMA_CLEAR( 1440 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1441 dbch->buf_offset = 0; 1442 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1443 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1444 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1445 return err; 1446 }else{ 1447 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1448 } 1449 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1450 return err; 1451} 1452 1453static int 1454fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1455{ 1456 int sec, cycle, cycle_match; 1457 1458 cycle = cycle_now & 0x1fff; 1459 sec = cycle_now >> 13; 1460#define CYCLE_MOD 0x10 1461#if 1 1462#define CYCLE_DELAY 8 /* min delay to start DMA */ 1463#else 1464#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1465#endif 1466 cycle = cycle + CYCLE_DELAY; 1467 if (cycle >= 8000) { 1468 sec ++; 1469 cycle -= 8000; 1470 } 1471 cycle = roundup2(cycle, CYCLE_MOD); 1472 if (cycle >= 8000) { 1473 sec ++; 1474 if (cycle == 8000) 1475 cycle = 0; 1476 else 1477 cycle = CYCLE_MOD; 1478 } 1479 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1480 1481 return(cycle_match); 1482} 1483 1484static int 1485fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1486{ 1487 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1488 int err = 0; 1489 unsigned short tag, ich; 1490 struct fwohci_dbch *dbch; 1491 int cycle_match, cycle_now, s, ldesc; 1492 uint32_t stat; 1493 struct fw_bulkxfer *first, *chunk, *prev; 1494 struct fw_xferq *it; 1495 1496 dbch = &sc->it[dmach]; 1497 it = &dbch->xferq; 1498 1499 tag = (it->flag >> 6) & 3; 1500 ich = it->flag & 0x3f; 1501 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1502 dbch->ndb = it->bnpacket * it->bnchunk; 1503 dbch->ndesc = 3; 1504 fwohci_db_init(sc, dbch); 1505 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1506 return ENOMEM; 1507 err = fwohci_tx_enable(sc, dbch); 1508 } 1509 if(err) 1510 return err; 1511 1512 ldesc = dbch->ndesc - 1; 1513 s = splfw(); 1514 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1515 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1516 struct fwohcidb *db; 1517 1518 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1519 BUS_DMASYNC_PREWRITE); 1520 fwohci_txbufdb(sc, dmach, chunk); 1521 if (prev != NULL) { 1522 db = ((struct fwohcidb_tr *)(prev->end))->db; 1523#if 0 /* XXX necessary? */ 1524 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1525 OHCI_BRANCH_ALWAYS); 1526#endif 1527#if 0 /* if bulkxfer->npacket changes */ 1528 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1529 ((struct fwohcidb_tr *) 1530 (chunk->start))->bus_addr | dbch->ndesc; 1531#else 1532 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1533 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1534#endif 1535 } 1536 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1537 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1538 prev = chunk; 1539 } 1540 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1541 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1542 splx(s); 1543 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1544 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1545 printf("stat 0x%x\n", stat); 1546 1547 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1548 return 0; 1549 1550#if 0 1551 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1552#endif 1553 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1554 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1555 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1556 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1557 1558 first = STAILQ_FIRST(&it->stdma); 1559 OWRITE(sc, OHCI_ITCMD(dmach), 1560 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1561 if (firewire_debug) { 1562 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1563#if 1 1564 dump_dma(sc, ITX_CH + dmach); 1565#endif 1566 } 1567 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1568#if 1 1569 /* Don't start until all chunks are buffered */ 1570 if (STAILQ_FIRST(&it->stfree) != NULL) 1571 goto out; 1572#endif 1573#if 1 1574 /* Clear cycle match counter bits */ 1575 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1576 1577 /* 2bit second + 13bit cycle */ 1578 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1579 cycle_match = fwohci_next_cycle(fc, cycle_now); 1580 1581 OWRITE(sc, OHCI_ITCTL(dmach), 1582 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1583 | OHCI_CNTL_DMA_RUN); 1584#else 1585 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1586#endif 1587 if (firewire_debug) { 1588 printf("cycle_match: 0x%04x->0x%04x\n", 1589 cycle_now, cycle_match); 1590 dump_dma(sc, ITX_CH + dmach); 1591 dump_db(sc, ITX_CH + dmach); 1592 } 1593 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1594 device_printf(sc->fc.dev, 1595 "IT DMA underrun (0x%08x)\n", stat); 1596 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1597 } 1598out: 1599 return err; 1600} 1601 1602static int 1603fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1604{ 1605 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1606 int err = 0, s, ldesc; 1607 unsigned short tag, ich; 1608 uint32_t stat; 1609 struct fwohci_dbch *dbch; 1610 struct fwohcidb_tr *db_tr; 1611 struct fw_bulkxfer *first, *prev, *chunk; 1612 struct fw_xferq *ir; 1613 1614 dbch = &sc->ir[dmach]; 1615 ir = &dbch->xferq; 1616 1617 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1618 tag = (ir->flag >> 6) & 3; 1619 ich = ir->flag & 0x3f; 1620 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1621 1622 ir->queued = 0; 1623 dbch->ndb = ir->bnpacket * ir->bnchunk; 1624 dbch->ndesc = 2; 1625 fwohci_db_init(sc, dbch); 1626 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1627 return ENOMEM; 1628 err = fwohci_rx_enable(sc, dbch); 1629 } 1630 if(err) 1631 return err; 1632 1633 first = STAILQ_FIRST(&ir->stfree); 1634 if (first == NULL) { 1635 device_printf(fc->dev, "IR DMA no free chunk\n"); 1636 return 0; 1637 } 1638 1639 ldesc = dbch->ndesc - 1; 1640 s = splfw(); 1641 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1642 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1643 struct fwohcidb *db; 1644 1645#if 1 /* XXX for if_fwe */ 1646 if (chunk->mbuf != NULL) { 1647 db_tr = (struct fwohcidb_tr *)(chunk->start); 1648 db_tr->dbcnt = 1; 1649 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1650 chunk->mbuf, fwohci_execute_db2, db_tr, 1651 /* flags */0); 1652 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1653 OHCI_UPDATE | OHCI_INPUT_LAST | 1654 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1655 } 1656#endif 1657 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1658 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1659 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1660 if (prev != NULL) { 1661 db = ((struct fwohcidb_tr *)(prev->end))->db; 1662 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1663 } 1664 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1665 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1666 prev = chunk; 1667 } 1668 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1669 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1670 splx(s); 1671 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1672 if (stat & OHCI_CNTL_DMA_ACTIVE) 1673 return 0; 1674 if (stat & OHCI_CNTL_DMA_RUN) { 1675 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1676 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1677 } 1678 1679 if (firewire_debug) 1680 printf("start IR DMA 0x%x\n", stat); 1681 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1682 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1683 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1684 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1685 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1686 OWRITE(sc, OHCI_IRCMD(dmach), 1687 ((struct fwohcidb_tr *)(first->start))->bus_addr 1688 | dbch->ndesc); 1689 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1690 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1691#if 0 1692 dump_db(sc, IRX_CH + dmach); 1693#endif 1694 return err; 1695} 1696 1697int 1698fwohci_stop(struct fwohci_softc *sc, device_t dev) 1699{ 1700 u_int i; 1701 1702/* Now stopping all DMA channel */ 1703 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1704 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1705 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1706 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1707 1708 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1709 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1710 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1711 } 1712 1713/* FLUSH FIFO and reset Transmitter/Reciever */ 1714 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1715 1716/* Stop interrupt */ 1717 OWRITE(sc, FWOHCI_INTMASKCLR, 1718 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1719 | OHCI_INT_PHY_INT 1720 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1721 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1722 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1723 | OHCI_INT_PHY_BUS_R); 1724 1725 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1726 fw_drain_txq(&sc->fc); 1727 1728/* XXX Link down? Bus reset? */ 1729 return 0; 1730} 1731 1732int 1733fwohci_resume(struct fwohci_softc *sc, device_t dev) 1734{ 1735 int i; 1736 struct fw_xferq *ir; 1737 struct fw_bulkxfer *chunk; 1738 1739 fwohci_reset(sc, dev); 1740 /* XXX resume isochronous receive automatically. (how about TX?) */ 1741 for(i = 0; i < sc->fc.nisodma; i ++) { 1742 ir = &sc->ir[i].xferq; 1743 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1744 device_printf(sc->fc.dev, 1745 "resume iso receive ch: %d\n", i); 1746 ir->flag &= ~FWXFERQ_RUNNING; 1747 /* requeue stdma to stfree */ 1748 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1749 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1750 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1751 } 1752 sc->fc.irx_enable(&sc->fc, i); 1753 } 1754 } 1755 1756 bus_generic_resume(dev); 1757 sc->fc.ibr(&sc->fc); 1758 return 0; 1759} 1760 1761#define ACK_ALL 1762static void 1763fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1764{ 1765 uint32_t irstat, itstat; 1766 u_int i; 1767 struct firewire_comm *fc = (struct firewire_comm *)sc; 1768 1769#ifdef OHCI_DEBUG 1770 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1771 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1772 stat & OHCI_INT_EN ? "DMA_EN ":"", 1773 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1774 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1775 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1776 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1777 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1778 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1779 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1780 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1781 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1782 stat & OHCI_INT_PHY_SID ? "SID ":"", 1783 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1784 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1785 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1786 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1787 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1788 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1789 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1790 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1791 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1792 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1793 stat, OREAD(sc, FWOHCI_INTMASK) 1794 ); 1795#endif 1796/* Bus reset */ 1797 if(stat & OHCI_INT_PHY_BUS_R ){ 1798 if (fc->status == FWBUSRESET) 1799 goto busresetout; 1800 /* Disable bus reset interrupt until sid recv. */ 1801 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1802 1803 device_printf(fc->dev, "BUS reset\n"); 1804 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1805 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1806 1807 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1808 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1809 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1810 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1811 1812#ifndef ACK_ALL 1813 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1814#endif 1815 fw_busreset(fc); 1816 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1817 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1818 } 1819busresetout: 1820 if((stat & OHCI_INT_DMA_IR )){ 1821#ifndef ACK_ALL 1822 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1823#endif 1824#if defined(__DragonFly__) || __FreeBSD_version < 500000 1825 irstat = sc->irstat; 1826 sc->irstat = 0; 1827#else 1828 irstat = atomic_readandclear_int(&sc->irstat); 1829#endif 1830 for(i = 0; i < fc->nisodma ; i++){ 1831 struct fwohci_dbch *dbch; 1832 1833 if((irstat & (1 << i)) != 0){ 1834 dbch = &sc->ir[i]; 1835 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1836 device_printf(sc->fc.dev, 1837 "dma(%d) not active\n", i); 1838 continue; 1839 } 1840 fwohci_rbuf_update(sc, i); 1841 } 1842 } 1843 } 1844 if((stat & OHCI_INT_DMA_IT )){ 1845#ifndef ACK_ALL 1846 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1847#endif 1848#if defined(__DragonFly__) || __FreeBSD_version < 500000 1849 itstat = sc->itstat; 1850 sc->itstat = 0; 1851#else 1852 itstat = atomic_readandclear_int(&sc->itstat); 1853#endif 1854 for(i = 0; i < fc->nisodma ; i++){ 1855 if((itstat & (1 << i)) != 0){ 1856 fwohci_tbuf_update(sc, i); 1857 } 1858 } 1859 } 1860 if((stat & OHCI_INT_DMA_PRRS )){ 1861#ifndef ACK_ALL 1862 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1863#endif 1864#if 0 1865 dump_dma(sc, ARRS_CH); 1866 dump_db(sc, ARRS_CH); 1867#endif 1868 fwohci_arcv(sc, &sc->arrs, count); 1869 } 1870 if((stat & OHCI_INT_DMA_PRRQ )){ 1871#ifndef ACK_ALL 1872 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1873#endif 1874#if 0 1875 dump_dma(sc, ARRQ_CH); 1876 dump_db(sc, ARRQ_CH); 1877#endif 1878 fwohci_arcv(sc, &sc->arrq, count); 1879 } 1880 if (stat & OHCI_INT_CYC_LOST) { 1881 if (sc->cycle_lost >= 0) 1882 sc->cycle_lost ++; 1883 if (sc->cycle_lost > 10) { 1884 sc->cycle_lost = -1; 1885#if 0 1886 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1887#endif 1888 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1889 device_printf(fc->dev, "too many cycle lost, " 1890 "no cycle master presents?\n"); 1891 } 1892 } 1893 if(stat & OHCI_INT_PHY_SID){ 1894 uint32_t *buf, node_id; 1895 int plen; 1896 1897#ifndef ACK_ALL 1898 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1899#endif 1900 /* Enable bus reset interrupt */ 1901 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1902 /* Allow async. request to us */ 1903 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1904 /* XXX insecure ?? */ 1905 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1906 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1907 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1908 /* Set ATRetries register */ 1909 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1910/* 1911** Checking whether the node is root or not. If root, turn on 1912** cycle master. 1913*/ 1914 node_id = OREAD(sc, FWOHCI_NODEID); 1915 plen = OREAD(sc, OHCI_SID_CNT); 1916 1917 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1918 node_id, (plen >> 16) & 0xff); 1919 if (!(node_id & OHCI_NODE_VALID)) { 1920 printf("Bus reset failure\n"); 1921 goto sidout; 1922 } 1923 1924 /* cycle timer */ 1925 sc->cycle_lost = 0; 1926 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 1927 if (node_id & OHCI_NODE_ROOT) { 1928 printf("CYCLEMASTER mode\n"); 1929 OWRITE(sc, OHCI_LNKCTL, 1930 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1931 } else { 1932 printf("non CYCLEMASTER mode\n"); 1933 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1934 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1935 } 1936 1937 fc->nodeid = node_id & 0x3f; 1938 1939 if (plen & OHCI_SID_ERR) { 1940 device_printf(fc->dev, "SID Error\n"); 1941 goto sidout; 1942 } 1943 plen &= OHCI_SID_CNT_MASK; 1944 if (plen < 4 || plen > OHCI_SIDSIZE) { 1945 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1946 goto sidout; 1947 } 1948 plen -= 4; /* chop control info */ 1949 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1950 if (buf == NULL) { 1951 device_printf(fc->dev, "malloc failed\n"); 1952 goto sidout; 1953 } 1954 for (i = 0; i < plen / 4; i ++) 1955 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1956#if 1 /* XXX needed?? */ 1957 /* pending all pre-bus_reset packets */ 1958 fwohci_txd(sc, &sc->atrq); 1959 fwohci_txd(sc, &sc->atrs); 1960 fwohci_arcv(sc, &sc->arrs, -1); 1961 fwohci_arcv(sc, &sc->arrq, -1); 1962 fw_drain_txq(fc); 1963#endif 1964 fw_sidrcv(fc, buf, plen); 1965 free(buf, M_FW); 1966 } 1967sidout: 1968 if((stat & OHCI_INT_DMA_ATRQ )){ 1969#ifndef ACK_ALL 1970 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1971#endif 1972 fwohci_txd(sc, &(sc->atrq)); 1973 } 1974 if((stat & OHCI_INT_DMA_ATRS )){ 1975#ifndef ACK_ALL 1976 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1977#endif 1978 fwohci_txd(sc, &(sc->atrs)); 1979 } 1980 if((stat & OHCI_INT_PW_ERR )){ 1981#ifndef ACK_ALL 1982 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1983#endif 1984 device_printf(fc->dev, "posted write error\n"); 1985 } 1986 if((stat & OHCI_INT_ERR )){ 1987#ifndef ACK_ALL 1988 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1989#endif 1990 device_printf(fc->dev, "unrecoverable error\n"); 1991 } 1992 if((stat & OHCI_INT_PHY_INT)) { 1993#ifndef ACK_ALL 1994 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1995#endif 1996 device_printf(fc->dev, "phy int\n"); 1997 } 1998 1999 return; 2000} 2001 2002#if FWOHCI_TASKQUEUE 2003static void 2004fwohci_complete(void *arg, int pending) 2005{ 2006 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2007 uint32_t stat; 2008 2009again: 2010 stat = atomic_readandclear_int(&sc->intstat); 2011 if (stat) 2012 fwohci_intr_body(sc, stat, -1); 2013 else 2014 return; 2015 goto again; 2016} 2017#endif 2018 2019static uint32_t 2020fwochi_check_stat(struct fwohci_softc *sc) 2021{ 2022 uint32_t stat, irstat, itstat; 2023 2024 stat = OREAD(sc, FWOHCI_INTSTAT); 2025 if (stat == 0xffffffff) { 2026 device_printf(sc->fc.dev, 2027 "device physically ejected?\n"); 2028 return(stat); 2029 } 2030#ifdef ACK_ALL 2031 if (stat) 2032 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2033#endif 2034 if (stat & OHCI_INT_DMA_IR) { 2035 irstat = OREAD(sc, OHCI_IR_STAT); 2036 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2037 atomic_set_int(&sc->irstat, irstat); 2038 } 2039 if (stat & OHCI_INT_DMA_IT) { 2040 itstat = OREAD(sc, OHCI_IT_STAT); 2041 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2042 atomic_set_int(&sc->itstat, itstat); 2043 } 2044 return(stat); 2045} 2046 2047void 2048fwohci_intr(void *arg) 2049{ 2050 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2051 uint32_t stat; 2052#if !FWOHCI_TASKQUEUE 2053 uint32_t bus_reset = 0; 2054#endif 2055 2056 if (!(sc->intmask & OHCI_INT_EN)) { 2057 /* polling mode */ 2058 return; 2059 } 2060 2061#if !FWOHCI_TASKQUEUE 2062again: 2063#endif 2064 stat = fwochi_check_stat(sc); 2065 if (stat == 0 || stat == 0xffffffff) 2066 return; 2067#if FWOHCI_TASKQUEUE 2068 atomic_set_int(&sc->intstat, stat); 2069 /* XXX mask bus reset intr. during bus reset phase */ 2070 if (stat) 2071 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2072#else 2073 /* We cannot clear bus reset event during bus reset phase */ 2074 if ((stat & ~bus_reset) == 0) 2075 return; 2076 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2077 fwohci_intr_body(sc, stat, -1); 2078 goto again; 2079#endif 2080} 2081 2082void 2083fwohci_poll(struct firewire_comm *fc, int quick, int count) 2084{ 2085 int s; 2086 uint32_t stat; 2087 struct fwohci_softc *sc; 2088 2089 2090 sc = (struct fwohci_softc *)fc; 2091 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2092 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2093 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2094#if 0 2095 if (!quick) { 2096#else 2097 if (1) { 2098#endif 2099 stat = fwochi_check_stat(sc); 2100 if (stat == 0 || stat == 0xffffffff) 2101 return; 2102 } 2103 s = splfw(); 2104 fwohci_intr_body(sc, stat, count); 2105 splx(s); 2106} 2107 2108static void 2109fwohci_set_intr(struct firewire_comm *fc, int enable) 2110{ 2111 struct fwohci_softc *sc; 2112 2113 sc = (struct fwohci_softc *)fc; 2114 if (firewire_debug) 2115 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2116 if (enable) { 2117 sc->intmask |= OHCI_INT_EN; 2118 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2119 } else { 2120 sc->intmask &= ~OHCI_INT_EN; 2121 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2122 } 2123} 2124 2125static void 2126fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2127{ 2128 struct firewire_comm *fc = &sc->fc; 2129 struct fwohcidb *db; 2130 struct fw_bulkxfer *chunk; 2131 struct fw_xferq *it; 2132 uint32_t stat, count; 2133 int s, w=0, ldesc; 2134 2135 it = fc->it[dmach]; 2136 ldesc = sc->it[dmach].ndesc - 1; 2137 s = splfw(); /* unnecessary ? */ 2138 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2139 if (firewire_debug) 2140 dump_db(sc, ITX_CH + dmach); 2141 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2142 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2143 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2144 >> OHCI_STATUS_SHIFT; 2145 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2146 /* timestamp */ 2147 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2148 & OHCI_COUNT_MASK; 2149 if (stat == 0) 2150 break; 2151 STAILQ_REMOVE_HEAD(&it->stdma, link); 2152 switch (stat & FWOHCIEV_MASK){ 2153 case FWOHCIEV_ACKCOMPL: 2154#if 0 2155 device_printf(fc->dev, "0x%08x\n", count); 2156#endif 2157 break; 2158 default: 2159 device_printf(fc->dev, 2160 "Isochronous transmit err %02x(%s)\n", 2161 stat, fwohcicode[stat & 0x1f]); 2162 } 2163 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2164 w++; 2165 } 2166 splx(s); 2167 if (w) 2168 wakeup(it); 2169} 2170 2171static void 2172fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2173{ 2174 struct firewire_comm *fc = &sc->fc; 2175 struct fwohcidb_tr *db_tr; 2176 struct fw_bulkxfer *chunk; 2177 struct fw_xferq *ir; 2178 uint32_t stat; 2179 int s, w=0, ldesc; 2180 2181 ir = fc->ir[dmach]; 2182 ldesc = sc->ir[dmach].ndesc - 1; 2183#if 0 2184 dump_db(sc, dmach); 2185#endif 2186 s = splfw(); 2187 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2188 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2189 db_tr = (struct fwohcidb_tr *)chunk->end; 2190 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2191 >> OHCI_STATUS_SHIFT; 2192 if (stat == 0) 2193 break; 2194 2195 if (chunk->mbuf != NULL) { 2196 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2197 BUS_DMASYNC_POSTREAD); 2198 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2199 } else if (ir->buf != NULL) { 2200 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2201 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2202 } else { 2203 /* XXX */ 2204 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2205 } 2206 2207 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2208 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2209 switch (stat & FWOHCIEV_MASK) { 2210 case FWOHCIEV_ACKCOMPL: 2211 chunk->resp = 0; 2212 break; 2213 default: 2214 chunk->resp = EINVAL; 2215 device_printf(fc->dev, 2216 "Isochronous receive err %02x(%s)\n", 2217 stat, fwohcicode[stat & 0x1f]); 2218 } 2219 w++; 2220 } 2221 splx(s); 2222 if (w) { 2223 if (ir->flag & FWXFERQ_HANDLER) 2224 ir->hand(ir); 2225 else 2226 wakeup(ir); 2227 } 2228} 2229 2230void 2231dump_dma(struct fwohci_softc *sc, uint32_t ch) 2232{ 2233 uint32_t off, cntl, stat, cmd, match; 2234 2235 if(ch == 0){ 2236 off = OHCI_ATQOFF; 2237 }else if(ch == 1){ 2238 off = OHCI_ATSOFF; 2239 }else if(ch == 2){ 2240 off = OHCI_ARQOFF; 2241 }else if(ch == 3){ 2242 off = OHCI_ARSOFF; 2243 }else if(ch < IRX_CH){ 2244 off = OHCI_ITCTL(ch - ITX_CH); 2245 }else{ 2246 off = OHCI_IRCTL(ch - IRX_CH); 2247 } 2248 cntl = stat = OREAD(sc, off); 2249 cmd = OREAD(sc, off + 0xc); 2250 match = OREAD(sc, off + 0x10); 2251 2252 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2253 ch, 2254 cntl, 2255 cmd, 2256 match); 2257 stat &= 0xffff ; 2258 if (stat) { 2259 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2260 ch, 2261 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2262 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2263 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2264 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2265 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2266 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2267 fwohcicode[stat & 0x1f], 2268 stat & 0x1f 2269 ); 2270 }else{ 2271 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2272 } 2273} 2274 2275void 2276dump_db(struct fwohci_softc *sc, uint32_t ch) 2277{ 2278 struct fwohci_dbch *dbch; 2279 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2280 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2281 int idb, jdb; 2282 uint32_t cmd, off; 2283 if(ch == 0){ 2284 off = OHCI_ATQOFF; 2285 dbch = &sc->atrq; 2286 }else if(ch == 1){ 2287 off = OHCI_ATSOFF; 2288 dbch = &sc->atrs; 2289 }else if(ch == 2){ 2290 off = OHCI_ARQOFF; 2291 dbch = &sc->arrq; 2292 }else if(ch == 3){ 2293 off = OHCI_ARSOFF; 2294 dbch = &sc->arrs; 2295 }else if(ch < IRX_CH){ 2296 off = OHCI_ITCTL(ch - ITX_CH); 2297 dbch = &sc->it[ch - ITX_CH]; 2298 }else { 2299 off = OHCI_IRCTL(ch - IRX_CH); 2300 dbch = &sc->ir[ch - IRX_CH]; 2301 } 2302 cmd = OREAD(sc, off + 0xc); 2303 2304 if( dbch->ndb == 0 ){ 2305 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2306 return; 2307 } 2308 pp = dbch->top; 2309 prev = pp->db; 2310 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2311 cp = STAILQ_NEXT(pp, link); 2312 if(cp == NULL){ 2313 curr = NULL; 2314 goto outdb; 2315 } 2316 np = STAILQ_NEXT(cp, link); 2317 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2318 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2319 curr = cp->db; 2320 if(np != NULL){ 2321 next = np->db; 2322 }else{ 2323 next = NULL; 2324 } 2325 goto outdb; 2326 } 2327 } 2328 pp = STAILQ_NEXT(pp, link); 2329 if(pp == NULL){ 2330 curr = NULL; 2331 goto outdb; 2332 } 2333 prev = pp->db; 2334 } 2335outdb: 2336 if( curr != NULL){ 2337#if 0 2338 printf("Prev DB %d\n", ch); 2339 print_db(pp, prev, ch, dbch->ndesc); 2340#endif 2341 printf("Current DB %d\n", ch); 2342 print_db(cp, curr, ch, dbch->ndesc); 2343#if 0 2344 printf("Next DB %d\n", ch); 2345 print_db(np, next, ch, dbch->ndesc); 2346#endif 2347 }else{ 2348 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2349 } 2350 return; 2351} 2352 2353void 2354print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2355 uint32_t ch, uint32_t max) 2356{ 2357 fwohcireg_t stat; 2358 int i, key; 2359 uint32_t cmd, res; 2360 2361 if(db == NULL){ 2362 printf("No Descriptor is found\n"); 2363 return; 2364 } 2365 2366 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2367 ch, 2368 "Current", 2369 "OP ", 2370 "KEY", 2371 "INT", 2372 "BR ", 2373 "len", 2374 "Addr", 2375 "Depend", 2376 "Stat", 2377 "Cnt"); 2378 for( i = 0 ; i <= max ; i ++){ 2379 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2380 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2381 key = cmd & OHCI_KEY_MASK; 2382 stat = res >> OHCI_STATUS_SHIFT; 2383#if defined(__DragonFly__) || __FreeBSD_version < 500000 2384 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2385 db_tr->bus_addr, 2386#else 2387 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2388 (uintmax_t)db_tr->bus_addr, 2389#endif 2390 dbcode[(cmd >> 28) & 0xf], 2391 dbkey[(cmd >> 24) & 0x7], 2392 dbcond[(cmd >> 20) & 0x3], 2393 dbcond[(cmd >> 18) & 0x3], 2394 cmd & OHCI_COUNT_MASK, 2395 FWOHCI_DMA_READ(db[i].db.desc.addr), 2396 FWOHCI_DMA_READ(db[i].db.desc.depend), 2397 stat, 2398 res & OHCI_COUNT_MASK); 2399 if(stat & 0xff00){ 2400 printf(" %s%s%s%s%s%s %s(%x)\n", 2401 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2402 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2403 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2404 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2405 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2406 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2407 fwohcicode[stat & 0x1f], 2408 stat & 0x1f 2409 ); 2410 }else{ 2411 printf(" Nostat\n"); 2412 } 2413 if(key == OHCI_KEY_ST2 ){ 2414 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2415 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2416 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2417 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2418 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2419 } 2420 if(key == OHCI_KEY_DEVICE){ 2421 return; 2422 } 2423 if((cmd & OHCI_BRANCH_MASK) 2424 == OHCI_BRANCH_ALWAYS){ 2425 return; 2426 } 2427 if((cmd & OHCI_CMD_MASK) 2428 == OHCI_OUTPUT_LAST){ 2429 return; 2430 } 2431 if((cmd & OHCI_CMD_MASK) 2432 == OHCI_INPUT_LAST){ 2433 return; 2434 } 2435 if(key == OHCI_KEY_ST2 ){ 2436 i++; 2437 } 2438 } 2439 return; 2440} 2441 2442void 2443fwohci_ibr(struct firewire_comm *fc) 2444{ 2445 struct fwohci_softc *sc; 2446 uint32_t fun; 2447 2448 device_printf(fc->dev, "Initiate bus reset\n"); 2449 sc = (struct fwohci_softc *)fc; 2450 2451 /* 2452 * Make sure our cached values from the config rom are 2453 * initialised. 2454 */ 2455 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2456 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2457 2458 /* 2459 * Set root hold-off bit so that non cyclemaster capable node 2460 * shouldn't became the root node. 2461 */ 2462#if 1 2463 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2464 fun |= FW_PHY_IBR | FW_PHY_RHB; 2465 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2466#else /* Short bus reset */ 2467 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2468 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2469 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2470#endif 2471} 2472 2473void 2474fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2475{ 2476 struct fwohcidb_tr *db_tr, *fdb_tr; 2477 struct fwohci_dbch *dbch; 2478 struct fwohcidb *db; 2479 struct fw_pkt *fp; 2480 struct fwohci_txpkthdr *ohcifp; 2481 unsigned short chtag; 2482 int idb; 2483 2484 dbch = &sc->it[dmach]; 2485 chtag = sc->it[dmach].xferq.flag & 0xff; 2486 2487 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2488 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2489/* 2490device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2491*/ 2492 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2493 db = db_tr->db; 2494 fp = (struct fw_pkt *)db_tr->buf; 2495 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2496 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2497 ohcifp->mode.common.spd = 0 & 0x7; 2498 ohcifp->mode.stream.len = fp->mode.stream.len; 2499 ohcifp->mode.stream.chtag = chtag; 2500 ohcifp->mode.stream.tcode = 0xa; 2501#if BYTE_ORDER == BIG_ENDIAN 2502 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2503 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2504#endif 2505 2506 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2507 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2508 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2509#if 0 /* if bulkxfer->npackets changes */ 2510 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2511 | OHCI_UPDATE 2512 | OHCI_BRANCH_ALWAYS; 2513 db[0].db.desc.depend = 2514 = db[dbch->ndesc - 1].db.desc.depend 2515 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2516#else 2517 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2518 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2519#endif 2520 bulkxfer->end = (caddr_t)db_tr; 2521 db_tr = STAILQ_NEXT(db_tr, link); 2522 } 2523 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2524 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2525 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2526#if 0 /* if bulkxfer->npackets changes */ 2527 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2528 /* OHCI 1.1 and above */ 2529 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2530#endif 2531/* 2532 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2533 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2534device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2535*/ 2536 return; 2537} 2538 2539static int 2540fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2541 int poffset) 2542{ 2543 struct fwohcidb *db = db_tr->db; 2544 struct fw_xferq *it; 2545 int err = 0; 2546 2547 it = &dbch->xferq; 2548 if(it->buf == 0){ 2549 err = EINVAL; 2550 return err; 2551 } 2552 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2553 db_tr->dbcnt = 3; 2554 2555 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2556 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2557 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2558 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2559 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2560 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2561 2562 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2563 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2564#if 1 2565 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2566 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2567#endif 2568 return 0; 2569} 2570 2571int 2572fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2573 int poffset, struct fwdma_alloc *dummy_dma) 2574{ 2575 struct fwohcidb *db = db_tr->db; 2576 struct fw_xferq *ir; 2577 int i, ldesc; 2578 bus_addr_t dbuf[2]; 2579 int dsiz[2]; 2580 2581 ir = &dbch->xferq; 2582 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2583 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2584 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2585 if (db_tr->buf == NULL) 2586 return(ENOMEM); 2587 db_tr->dbcnt = 1; 2588 dsiz[0] = ir->psize; 2589 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2590 BUS_DMASYNC_PREREAD); 2591 } else { 2592 db_tr->dbcnt = 0; 2593 if (dummy_dma != NULL) { 2594 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2595 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2596 } 2597 dsiz[db_tr->dbcnt] = ir->psize; 2598 if (ir->buf != NULL) { 2599 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2600 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2601 } 2602 db_tr->dbcnt++; 2603 } 2604 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2605 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2606 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2607 if (ir->flag & FWXFERQ_STREAM) { 2608 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2609 } 2610 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2611 } 2612 ldesc = db_tr->dbcnt - 1; 2613 if (ir->flag & FWXFERQ_STREAM) { 2614 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2615 } 2616 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2617 return 0; 2618} 2619 2620 2621static int 2622fwohci_arcv_swap(struct fw_pkt *fp, int len) 2623{ 2624 struct fw_pkt *fp0; 2625 uint32_t ld0; 2626 int slen, hlen; 2627#if BYTE_ORDER == BIG_ENDIAN 2628 int i; 2629#endif 2630 2631 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2632#if 0 2633 printf("ld0: x%08x\n", ld0); 2634#endif 2635 fp0 = (struct fw_pkt *)&ld0; 2636 /* determine length to swap */ 2637 switch (fp0->mode.common.tcode) { 2638 case FWTCODE_RREQQ: 2639 case FWTCODE_WRES: 2640 case FWTCODE_WREQQ: 2641 case FWTCODE_RRESQ: 2642 case FWOHCITCODE_PHY: 2643 slen = 12; 2644 break; 2645 case FWTCODE_RREQB: 2646 case FWTCODE_WREQB: 2647 case FWTCODE_LREQ: 2648 case FWTCODE_RRESB: 2649 case FWTCODE_LRES: 2650 slen = 16; 2651 break; 2652 default: 2653 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2654 return(0); 2655 } 2656 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2657 if (hlen > len) { 2658 if (firewire_debug) 2659 printf("splitted header\n"); 2660 return(-hlen); 2661 } 2662#if BYTE_ORDER == BIG_ENDIAN 2663 for(i = 0; i < slen/4; i ++) 2664 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2665#endif 2666 return(hlen); 2667} 2668 2669static int 2670fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2671{ 2672 struct tcode_info *info; 2673 int r; 2674 2675 info = &tinfo[fp->mode.common.tcode]; 2676 r = info->hdr_len + sizeof(uint32_t); 2677 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2678 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2679 2680 if (r == sizeof(uint32_t)) 2681 /* XXX */ 2682 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2683 fp->mode.common.tcode); 2684 2685 if (r > dbch->xferq.psize) { 2686 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2687 /* panic ? */ 2688 } 2689 2690 return r; 2691} 2692 2693static void 2694fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2695{ 2696 struct fwohcidb *db = &db_tr->db[0]; 2697 2698 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2699 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2700 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2701 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2702 dbch->bottom = db_tr; 2703} 2704 2705static void 2706fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2707{ 2708 struct fwohcidb_tr *db_tr; 2709 struct iovec vec[2]; 2710 struct fw_pkt pktbuf; 2711 int nvec; 2712 struct fw_pkt *fp; 2713 uint8_t *ld; 2714 uint32_t stat, off, status; 2715 u_int spd; 2716 int len, plen, hlen, pcnt, offset; 2717 int s; 2718 caddr_t buf; 2719 int resCount; 2720 2721 if(&sc->arrq == dbch){ 2722 off = OHCI_ARQOFF; 2723 }else if(&sc->arrs == dbch){ 2724 off = OHCI_ARSOFF; 2725 }else{ 2726 return; 2727 } 2728 2729 s = splfw(); 2730 db_tr = dbch->top; 2731 pcnt = 0; 2732 /* XXX we cannot handle a packet which lies in more than two buf */ 2733 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2734 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2735 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2736 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2737#if 0 2738 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2739#endif 2740 while (status & OHCI_CNTL_DMA_ACTIVE) { 2741 len = dbch->xferq.psize - resCount; 2742 ld = (uint8_t *)db_tr->buf; 2743 if (dbch->pdb_tr == NULL) { 2744 len -= dbch->buf_offset; 2745 ld += dbch->buf_offset; 2746 } 2747 if (len > 0) 2748 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2749 BUS_DMASYNC_POSTREAD); 2750 while (len > 0 ) { 2751 if (count >= 0 && count-- == 0) 2752 goto out; 2753 if(dbch->pdb_tr != NULL){ 2754 /* we have a fragment in previous buffer */ 2755 int rlen; 2756 2757 offset = dbch->buf_offset; 2758 if (offset < 0) 2759 offset = - offset; 2760 buf = dbch->pdb_tr->buf + offset; 2761 rlen = dbch->xferq.psize - offset; 2762 if (firewire_debug) 2763 printf("rlen=%d, offset=%d\n", 2764 rlen, dbch->buf_offset); 2765 if (dbch->buf_offset < 0) { 2766 /* splitted in header, pull up */ 2767 char *p; 2768 2769 p = (char *)&pktbuf; 2770 bcopy(buf, p, rlen); 2771 p += rlen; 2772 /* this must be too long but harmless */ 2773 rlen = sizeof(pktbuf) - rlen; 2774 if (rlen < 0) 2775 printf("why rlen < 0\n"); 2776 bcopy(db_tr->buf, p, rlen); 2777 ld += rlen; 2778 len -= rlen; 2779 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2780 if (hlen < 0) { 2781 printf("hlen < 0 shouldn't happen"); 2782 } 2783 offset = sizeof(pktbuf); 2784 vec[0].iov_base = (char *)&pktbuf; 2785 vec[0].iov_len = offset; 2786 } else { 2787 /* splitted in payload */ 2788 offset = rlen; 2789 vec[0].iov_base = buf; 2790 vec[0].iov_len = rlen; 2791 } 2792 fp=(struct fw_pkt *)vec[0].iov_base; 2793 nvec = 1; 2794 } else { 2795 /* no fragment in previous buffer */ 2796 fp=(struct fw_pkt *)ld; 2797 hlen = fwohci_arcv_swap(fp, len); 2798 if (hlen == 0) 2799 /* XXX need reset */ 2800 goto out; 2801 if (hlen < 0) { 2802 dbch->pdb_tr = db_tr; 2803 dbch->buf_offset = - dbch->buf_offset; 2804 /* sanity check */ 2805 if (resCount != 0) 2806 printf("resCount = %d !?\n", 2807 resCount); 2808 /* XXX clear pdb_tr */ 2809 goto out; 2810 } 2811 offset = 0; 2812 nvec = 0; 2813 } 2814 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2815 if (plen < 0) { 2816 /* minimum header size + trailer 2817 = sizeof(fw_pkt) so this shouldn't happens */ 2818 printf("plen(%d) is negative! offset=%d\n", 2819 plen, offset); 2820 /* XXX clear pdb_tr */ 2821 goto out; 2822 } 2823 if (plen > 0) { 2824 len -= plen; 2825 if (len < 0) { 2826 dbch->pdb_tr = db_tr; 2827 if (firewire_debug) 2828 printf("splitted payload\n"); 2829 /* sanity check */ 2830 if (resCount != 0) 2831 printf("resCount = %d !?\n", 2832 resCount); 2833 /* XXX clear pdb_tr */ 2834 goto out; 2835 } 2836 vec[nvec].iov_base = ld; 2837 vec[nvec].iov_len = plen; 2838 nvec ++; 2839 ld += plen; 2840 } 2841 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2842 if (nvec == 0) 2843 printf("nvec == 0\n"); 2844 2845/* DMA result-code will be written at the tail of packet */ 2846#if BYTE_ORDER == BIG_ENDIAN 2847 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2848#else 2849 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2850#endif 2851#if 0 2852 printf("plen: %d, stat %x\n", 2853 plen ,stat); 2854#endif 2855 spd = (stat >> 5) & 0x3; 2856 stat &= 0x1f; 2857 switch(stat){ 2858 case FWOHCIEV_ACKPEND: 2859#if 0 2860 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2861#endif 2862 /* fall through */ 2863 case FWOHCIEV_ACKCOMPL: 2864 { 2865 struct fw_rcv_buf rb; 2866 2867 if ((vec[nvec-1].iov_len -= 2868 sizeof(struct fwohci_trailer)) == 0) 2869 nvec--; 2870 rb.fc = &sc->fc; 2871 rb.vec = vec; 2872 rb.nvec = nvec; 2873 rb.spd = spd; 2874 fw_rcv(&rb); 2875 break; 2876 } 2877 case FWOHCIEV_BUSRST: 2878 if (sc->fc.status != FWBUSRESET) 2879 printf("got BUSRST packet!?\n"); 2880 break; 2881 default: 2882 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2883#if 0 /* XXX */ 2884 goto out; 2885#endif 2886 break; 2887 } 2888 pcnt ++; 2889 if (dbch->pdb_tr != NULL) { 2890 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2891 dbch->pdb_tr = NULL; 2892 } 2893 2894 } 2895out: 2896 if (resCount == 0) { 2897 /* done on this buffer */ 2898 if (dbch->pdb_tr == NULL) { 2899 fwohci_arcv_free_buf(dbch, db_tr); 2900 dbch->buf_offset = 0; 2901 } else 2902 if (dbch->pdb_tr != db_tr) 2903 printf("pdb_tr != db_tr\n"); 2904 db_tr = STAILQ_NEXT(db_tr, link); 2905 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2906 >> OHCI_STATUS_SHIFT; 2907 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2908 & OHCI_COUNT_MASK; 2909 /* XXX check buffer overrun */ 2910 dbch->top = db_tr; 2911 } else { 2912 dbch->buf_offset = dbch->xferq.psize - resCount; 2913 break; 2914 } 2915 /* XXX make sure DMA is not dead */ 2916 } 2917#if 0 2918 if (pcnt < 1) 2919 printf("fwohci_arcv: no packets\n"); 2920#endif 2921 splx(s); 2922} 2923