fwohci.c revision 124378
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 124378 2004-01-11 15:40:42Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#include <dev/firewire/firewire.h> 62#include <dev/firewire/firewirereg.h> 63#include <dev/firewire/fwdma.h> 64#include <dev/firewire/fwohcireg.h> 65#include <dev/firewire/fwohcivar.h> 66#include <dev/firewire/firewire_phy.h> 67 68#undef OHCI_DEBUG 69 70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71 "STOR","LOAD","NOP ","STOP",}; 72 73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74 "UNDEF","REG","SYS","DEV"}; 75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76char fwohcicode[32][0x20]={ 77 "No stat","Undef","long","miss Ack err", 78 "underrun","overrun","desc err", "data read err", 79 "data write err","bus reset","timeout","tcode err", 80 "Undef","Undef","unknown event","flushed", 81 "Undef","ack complete","ack pend","Undef", 82 "ack busy_X","ack busy_A","ack busy_B","Undef", 83 "Undef","Undef","Undef","ack tardy", 84 "Undef","ack data_err","ack type_err",""}; 85 86#define MAX_SPEED 3 87extern char *linkspeed[]; 88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89 90static struct tcode_info tinfo[] = { 91/* hdr_len block flag*/ 92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94/* 2 WRES */ {12, FWTI_RES}, 95/* 3 XXX */ { 0, 0}, 96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98/* 6 RRESQ */ {16, FWTI_RES}, 99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100/* 8 CYCS */ { 0, 0}, 101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104/* c XXX */ { 0, 0}, 105/* d XXX */ { 0, 0}, 106/* e PHY */ {12, FWTI_REQ}, 107/* f XXX */ { 0, 0} 108}; 109 110#define OHCI_WRITE_SIGMASK 0xffff0000 111#define OHCI_READ_SIGMASK 0xffff0000 112 113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115 116static void fwohci_ibr (struct firewire_comm *); 117static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 118static void fwohci_db_free (struct fwohci_dbch *); 119static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 120static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 121static void fwohci_start_atq (struct firewire_comm *); 122static void fwohci_start_ats (struct firewire_comm *); 123static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 124static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t); 125static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t); 126static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 127static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 128static int fwohci_irx_enable (struct firewire_comm *, int); 129static int fwohci_irx_disable (struct firewire_comm *, int); 130#if BYTE_ORDER == BIG_ENDIAN 131static void fwohci_irx_post (struct firewire_comm *, u_int32_t *); 132#endif 133static int fwohci_itxbuf_enable (struct firewire_comm *, int); 134static int fwohci_itx_disable (struct firewire_comm *, int); 135static void fwohci_timeout (void *); 136static void fwohci_set_intr (struct firewire_comm *, int); 137 138static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 139static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 140static void dump_db (struct fwohci_softc *, u_int32_t); 141static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t); 142static void dump_dma (struct fwohci_softc *, u_int32_t); 143static u_int32_t fwohci_cyctimer (struct firewire_comm *); 144static void fwohci_rbuf_update (struct fwohci_softc *, int); 145static void fwohci_tbuf_update (struct fwohci_softc *, int); 146void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 147#if FWOHCI_TASKQUEUE 148static void fwohci_complete(void *, int); 149#endif 150 151/* 152 * memory allocated for DMA programs 153 */ 154#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155 156#define NDB FWMAXQUEUE 157 158#define OHCI_VERSION 0x00 159#define OHCI_ATRETRY 0x08 160#define OHCI_CROMHDR 0x18 161#define OHCI_BUS_OPT 0x20 162#define OHCI_BUSIRMC (1 << 31) 163#define OHCI_BUSCMC (1 << 30) 164#define OHCI_BUSISC (1 << 29) 165#define OHCI_BUSBMC (1 << 28) 166#define OHCI_BUSPMC (1 << 27) 167#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 168 OHCI_BUSBMC | OHCI_BUSPMC 169 170#define OHCI_EUID_HI 0x24 171#define OHCI_EUID_LO 0x28 172 173#define OHCI_CROMPTR 0x34 174#define OHCI_HCCCTL 0x50 175#define OHCI_HCCCTLCLR 0x54 176#define OHCI_AREQHI 0x100 177#define OHCI_AREQHICLR 0x104 178#define OHCI_AREQLO 0x108 179#define OHCI_AREQLOCLR 0x10c 180#define OHCI_PREQHI 0x110 181#define OHCI_PREQHICLR 0x114 182#define OHCI_PREQLO 0x118 183#define OHCI_PREQLOCLR 0x11c 184#define OHCI_PREQUPPER 0x120 185 186#define OHCI_SID_BUF 0x64 187#define OHCI_SID_CNT 0x68 188#define OHCI_SID_ERR (1 << 31) 189#define OHCI_SID_CNT_MASK 0xffc 190 191#define OHCI_IT_STAT 0x90 192#define OHCI_IT_STATCLR 0x94 193#define OHCI_IT_MASK 0x98 194#define OHCI_IT_MASKCLR 0x9c 195 196#define OHCI_IR_STAT 0xa0 197#define OHCI_IR_STATCLR 0xa4 198#define OHCI_IR_MASK 0xa8 199#define OHCI_IR_MASKCLR 0xac 200 201#define OHCI_LNKCTL 0xe0 202#define OHCI_LNKCTLCLR 0xe4 203 204#define OHCI_PHYACCESS 0xec 205#define OHCI_CYCLETIMER 0xf0 206 207#define OHCI_DMACTL(off) (off) 208#define OHCI_DMACTLCLR(off) (off + 4) 209#define OHCI_DMACMD(off) (off + 0xc) 210#define OHCI_DMAMATCH(off) (off + 0x10) 211 212#define OHCI_ATQOFF 0x180 213#define OHCI_ATQCTL OHCI_ATQOFF 214#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 215#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 216#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 217 218#define OHCI_ATSOFF 0x1a0 219#define OHCI_ATSCTL OHCI_ATSOFF 220#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 221#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 222#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 223 224#define OHCI_ARQOFF 0x1c0 225#define OHCI_ARQCTL OHCI_ARQOFF 226#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 227#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 228#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 229 230#define OHCI_ARSOFF 0x1e0 231#define OHCI_ARSCTL OHCI_ARSOFF 232#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 233#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 234#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 235 236#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 237#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 238#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 239#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 240 241#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 242#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 243#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 244#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 245#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 246 247d_ioctl_t fwohci_ioctl; 248 249/* 250 * Communication with PHY device 251 */ 252static u_int32_t 253fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 254{ 255 u_int32_t fun; 256 257 addr &= 0xf; 258 data &= 0xff; 259 260 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 261 OWRITE(sc, OHCI_PHYACCESS, fun); 262 DELAY(100); 263 264 return(fwphy_rddata( sc, addr)); 265} 266 267static u_int32_t 268fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 269{ 270 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 271 int i; 272 u_int32_t bm; 273 274#define OHCI_CSR_DATA 0x0c 275#define OHCI_CSR_COMP 0x10 276#define OHCI_CSR_CONT 0x14 277#define OHCI_BUS_MANAGER_ID 0 278 279 OWRITE(sc, OHCI_CSR_DATA, node); 280 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 281 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 282 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 283 DELAY(10); 284 bm = OREAD(sc, OHCI_CSR_DATA); 285 if((bm & 0x3f) == 0x3f) 286 bm = node; 287 if (bootverbose) 288 device_printf(sc->fc.dev, 289 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 290 291 return(bm); 292} 293 294static u_int32_t 295fwphy_rddata(struct fwohci_softc *sc, u_int addr) 296{ 297 u_int32_t fun, stat; 298 u_int i, retry = 0; 299 300 addr &= 0xf; 301#define MAX_RETRY 100 302again: 303 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 304 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 305 OWRITE(sc, OHCI_PHYACCESS, fun); 306 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 307 fun = OREAD(sc, OHCI_PHYACCESS); 308 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 309 break; 310 DELAY(100); 311 } 312 if(i >= MAX_RETRY) { 313 if (bootverbose) 314 device_printf(sc->fc.dev, "phy read failed(1).\n"); 315 if (++retry < MAX_RETRY) { 316 DELAY(100); 317 goto again; 318 } 319 } 320 /* Make sure that SCLK is started */ 321 stat = OREAD(sc, FWOHCI_INTSTAT); 322 if ((stat & OHCI_INT_REG_FAIL) != 0 || 323 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 324 if (bootverbose) 325 device_printf(sc->fc.dev, "phy read failed(2).\n"); 326 if (++retry < MAX_RETRY) { 327 DELAY(100); 328 goto again; 329 } 330 } 331 if (bootverbose || retry >= MAX_RETRY) 332 device_printf(sc->fc.dev, 333 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 334#undef MAX_RETRY 335 return((fun >> PHYDEV_RDDATA )& 0xff); 336} 337/* Device specific ioctl. */ 338int 339fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 340{ 341 struct firewire_softc *sc; 342 struct fwohci_softc *fc; 343 int unit = DEV2UNIT(dev); 344 int err = 0; 345 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 346 u_int32_t *dmach = (u_int32_t *) data; 347 348 sc = devclass_get_softc(firewire_devclass, unit); 349 if(sc == NULL){ 350 return(EINVAL); 351 } 352 fc = (struct fwohci_softc *)sc->fc; 353 354 if (!data) 355 return(EINVAL); 356 357 switch (cmd) { 358 case FWOHCI_WRREG: 359#define OHCI_MAX_REG 0x800 360 if(reg->addr <= OHCI_MAX_REG){ 361 OWRITE(fc, reg->addr, reg->data); 362 reg->data = OREAD(fc, reg->addr); 363 }else{ 364 err = EINVAL; 365 } 366 break; 367 case FWOHCI_RDREG: 368 if(reg->addr <= OHCI_MAX_REG){ 369 reg->data = OREAD(fc, reg->addr); 370 }else{ 371 err = EINVAL; 372 } 373 break; 374/* Read DMA descriptors for debug */ 375 case DUMPDMA: 376 if(*dmach <= OHCI_MAX_DMA_CH ){ 377 dump_dma(fc, *dmach); 378 dump_db(fc, *dmach); 379 }else{ 380 err = EINVAL; 381 } 382 break; 383/* Read/Write Phy registers */ 384#define OHCI_MAX_PHY_REG 0xf 385 case FWOHCI_RDPHYREG: 386 if (reg->addr <= OHCI_MAX_PHY_REG) 387 reg->data = fwphy_rddata(fc, reg->addr); 388 else 389 err = EINVAL; 390 break; 391 case FWOHCI_WRPHYREG: 392 if (reg->addr <= OHCI_MAX_PHY_REG) 393 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 394 else 395 err = EINVAL; 396 break; 397 default: 398 err = EINVAL; 399 break; 400 } 401 return err; 402} 403 404static int 405fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406{ 407 u_int32_t reg, reg2; 408 int e1394a = 1; 409/* 410 * probe PHY parameters 411 * 0. to prove PHY version, whether compliance of 1394a. 412 * 1. to probe maximum speed supported by the PHY and 413 * number of port supported by core-logic. 414 * It is not actually available port on your PC . 415 */ 416 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447#if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449#else /* XXX force to enable 1394a */ 450 if (e1394a) { 451#endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475} 476 477 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 555 /* AT Retries */ 556 OWRITE(sc, FWOHCI_RETRY, 557 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559 560 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562 sc->atrq.bottom = sc->atrq.top; 563 sc->atrs.bottom = sc->atrs.top; 564 565 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567 db_tr->xfer = NULL; 568 } 569 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571 db_tr->xfer = NULL; 572 } 573 574 575 /* Enable interrupt */ 576 OWRITE(sc, FWOHCI_INTMASK, 577 OHCI_INT_ERR | OHCI_INT_PHY_SID 578 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581 fwohci_set_intr(&sc->fc, 1); 582 583} 584 585int 586fwohci_init(struct fwohci_softc *sc, device_t dev) 587{ 588 int i, mver; 589 u_int32_t reg; 590 u_int8_t ui[8]; 591 592#if FWOHCI_TASKQUEUE 593 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594#endif 595 596/* OHCI version */ 597 reg = OREAD(sc, OHCI_VERSION); 598 mver = (reg >> 16) & 0xff; 599 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 600 mver, reg & 0xff, (reg>>24) & 1); 601 if (mver < 1 || mver > 9) { 602 device_printf(dev, "invalid OHCI version\n"); 603 return (ENXIO); 604 } 605 606/* Available Isochrounous DMA channel probe */ 607 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 608 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 609 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 610 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 611 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 612 for (i = 0; i < 0x20; i++) 613 if ((reg & (1 << i)) == 0) 614 break; 615 sc->fc.nisodma = i; 616 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 617 if (i == 0) 618 return (ENXIO); 619 620 sc->fc.arq = &sc->arrq.xferq; 621 sc->fc.ars = &sc->arrs.xferq; 622 sc->fc.atq = &sc->atrq.xferq; 623 sc->fc.ats = &sc->atrs.xferq; 624 625 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 626 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 629 630 sc->arrq.xferq.start = NULL; 631 sc->arrs.xferq.start = NULL; 632 sc->atrq.xferq.start = fwohci_start_atq; 633 sc->atrs.xferq.start = fwohci_start_ats; 634 635 sc->arrq.xferq.buf = NULL; 636 sc->arrs.xferq.buf = NULL; 637 sc->atrq.xferq.buf = NULL; 638 sc->atrs.xferq.buf = NULL; 639 640 sc->arrq.xferq.dmach = -1; 641 sc->arrs.xferq.dmach = -1; 642 sc->atrq.xferq.dmach = -1; 643 sc->atrs.xferq.dmach = -1; 644 645 sc->arrq.ndesc = 1; 646 sc->arrs.ndesc = 1; 647 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 648 sc->atrs.ndesc = 2; 649 650 sc->arrq.ndb = NDB; 651 sc->arrs.ndb = NDB / 2; 652 sc->atrq.ndb = NDB; 653 sc->atrs.ndb = NDB / 2; 654 655 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 656 sc->fc.it[i] = &sc->it[i].xferq; 657 sc->fc.ir[i] = &sc->ir[i].xferq; 658 sc->it[i].xferq.dmach = i; 659 sc->ir[i].xferq.dmach = i; 660 sc->it[i].ndb = 0; 661 sc->ir[i].ndb = 0; 662 } 663 664 sc->fc.tcode = tinfo; 665 sc->fc.dev = dev; 666 667 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 668 &sc->crom_dma, BUS_DMA_WAITOK); 669 if(sc->fc.config_rom == NULL){ 670 device_printf(dev, "config_rom alloc failed."); 671 return ENOMEM; 672 } 673 674#if 0 675 bzero(&sc->fc.config_rom[0], CROMSIZE); 676 sc->fc.config_rom[1] = 0x31333934; 677 sc->fc.config_rom[2] = 0xf000a002; 678 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 679 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 680 sc->fc.config_rom[5] = 0; 681 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 682 683 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 684#endif 685 686 687/* SID recieve buffer must allign 2^11 */ 688#define OHCI_SIDSIZE (1 << 11) 689 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 690 &sc->sid_dma, BUS_DMA_WAITOK); 691 if (sc->sid_buf == NULL) { 692 device_printf(dev, "sid_buf alloc failed."); 693 return ENOMEM; 694 } 695 696 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 697 &sc->dummy_dma, BUS_DMA_WAITOK); 698 699 if (sc->dummy_dma.v_addr == NULL) { 700 device_printf(dev, "dummy_dma alloc failed."); 701 return ENOMEM; 702 } 703 704 fwohci_db_init(sc, &sc->arrq); 705 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 706 return ENOMEM; 707 708 fwohci_db_init(sc, &sc->arrs); 709 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 710 return ENOMEM; 711 712 fwohci_db_init(sc, &sc->atrq); 713 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 714 return ENOMEM; 715 716 fwohci_db_init(sc, &sc->atrs); 717 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 718 return ENOMEM; 719 720 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 721 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 722 for( i = 0 ; i < 8 ; i ++) 723 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 724 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 725 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 726 727 sc->fc.ioctl = fwohci_ioctl; 728 sc->fc.cyctimer = fwohci_cyctimer; 729 sc->fc.set_bmr = fwohci_set_bus_manager; 730 sc->fc.ibr = fwohci_ibr; 731 sc->fc.irx_enable = fwohci_irx_enable; 732 sc->fc.irx_disable = fwohci_irx_disable; 733 734 sc->fc.itx_enable = fwohci_itxbuf_enable; 735 sc->fc.itx_disable = fwohci_itx_disable; 736#if BYTE_ORDER == BIG_ENDIAN 737 sc->fc.irx_post = fwohci_irx_post; 738#else 739 sc->fc.irx_post = NULL; 740#endif 741 sc->fc.itx_post = NULL; 742 sc->fc.timeout = fwohci_timeout; 743 sc->fc.poll = fwohci_poll; 744 sc->fc.set_intr = fwohci_set_intr; 745 746 sc->intmask = sc->irstat = sc->itstat = 0; 747 748 fw_init(&sc->fc); 749 fwohci_reset(sc, dev); 750 751 return 0; 752} 753 754void 755fwohci_timeout(void *arg) 756{ 757 struct fwohci_softc *sc; 758 759 sc = (struct fwohci_softc *)arg; 760} 761 762u_int32_t 763fwohci_cyctimer(struct firewire_comm *fc) 764{ 765 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 766 return(OREAD(sc, OHCI_CYCLETIMER)); 767} 768 769int 770fwohci_detach(struct fwohci_softc *sc, device_t dev) 771{ 772 int i; 773 774 if (sc->sid_buf != NULL) 775 fwdma_free(&sc->fc, &sc->sid_dma); 776 if (sc->fc.config_rom != NULL) 777 fwdma_free(&sc->fc, &sc->crom_dma); 778 779 fwohci_db_free(&sc->arrq); 780 fwohci_db_free(&sc->arrs); 781 782 fwohci_db_free(&sc->atrq); 783 fwohci_db_free(&sc->atrs); 784 785 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 786 fwohci_db_free(&sc->it[i]); 787 fwohci_db_free(&sc->ir[i]); 788 } 789 790 return 0; 791} 792 793#define LAST_DB(dbtr, db) do { \ 794 struct fwohcidb_tr *_dbtr = (dbtr); \ 795 int _cnt = _dbtr->dbcnt; \ 796 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 797} while (0) 798 799static void 800fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 801{ 802 struct fwohcidb_tr *db_tr; 803 struct fwohcidb *db; 804 bus_dma_segment_t *s; 805 int i; 806 807 db_tr = (struct fwohcidb_tr *)arg; 808 db = &db_tr->db[db_tr->dbcnt]; 809 if (error) { 810 if (firewire_debug || error != EFBIG) 811 printf("fwohci_execute_db: error=%d\n", error); 812 return; 813 } 814 for (i = 0; i < nseg; i++) { 815 s = &segs[i]; 816 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 817 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 818 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 819 db++; 820 db_tr->dbcnt++; 821 } 822} 823 824static void 825fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 826 bus_size_t size, int error) 827{ 828 fwohci_execute_db(arg, segs, nseg, error); 829} 830 831static void 832fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 833{ 834 int i, s; 835 int tcode, hdr_len, pl_off; 836 int fsegment = -1; 837 u_int32_t off; 838 struct fw_xfer *xfer; 839 struct fw_pkt *fp; 840 struct fwohci_txpkthdr *ohcifp; 841 struct fwohcidb_tr *db_tr; 842 struct fwohcidb *db; 843 u_int32_t *ld; 844 struct tcode_info *info; 845 static int maxdesc=0; 846 847 if(&sc->atrq == dbch){ 848 off = OHCI_ATQOFF; 849 }else if(&sc->atrs == dbch){ 850 off = OHCI_ATSOFF; 851 }else{ 852 return; 853 } 854 855 if (dbch->flags & FWOHCI_DBCH_FULL) 856 return; 857 858 s = splfw(); 859 db_tr = dbch->top; 860txloop: 861 xfer = STAILQ_FIRST(&dbch->xferq.q); 862 if(xfer == NULL){ 863 goto kick; 864 } 865 if(dbch->xferq.queued == 0 ){ 866 device_printf(sc->fc.dev, "TX queue empty\n"); 867 } 868 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 869 db_tr->xfer = xfer; 870 xfer->state = FWXF_START; 871 872 fp = &xfer->send.hdr; 873 tcode = fp->mode.common.tcode; 874 875 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 876 info = &tinfo[tcode]; 877 hdr_len = pl_off = info->hdr_len; 878 879 ld = &ohcifp->mode.ld[0]; 880 ld[0] = ld[1] = ld[2] = ld[3] = 0; 881 for( i = 0 ; i < pl_off ; i+= 4) 882 ld[i/4] = fp->mode.ld[i/4]; 883 884 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 885 if (tcode == FWTCODE_STREAM ){ 886 hdr_len = 8; 887 ohcifp->mode.stream.len = fp->mode.stream.len; 888 } else if (tcode == FWTCODE_PHY) { 889 hdr_len = 12; 890 ld[1] = fp->mode.ld[1]; 891 ld[2] = fp->mode.ld[2]; 892 ohcifp->mode.common.spd = 0; 893 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 894 } else { 895 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 896 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 897 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 898 } 899 db = &db_tr->db[0]; 900 FWOHCI_DMA_WRITE(db->db.desc.cmd, 901 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 902 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 903 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 904/* Specify bound timer of asy. responce */ 905 if(&sc->atrs == dbch){ 906 FWOHCI_DMA_WRITE(db->db.desc.res, 907 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 908 } 909#if BYTE_ORDER == BIG_ENDIAN 910 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 911 hdr_len = 12; 912 for (i = 0; i < hdr_len/4; i ++) 913 FWOHCI_DMA_WRITE(ld[i], ld[i]); 914#endif 915 916again: 917 db_tr->dbcnt = 2; 918 db = &db_tr->db[db_tr->dbcnt]; 919 if (xfer->send.pay_len > 0) { 920 int err; 921 /* handle payload */ 922 if (xfer->mbuf == NULL) { 923 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 924 &xfer->send.payload[0], xfer->send.pay_len, 925 fwohci_execute_db, db_tr, 926 /*flags*/0); 927 } else { 928 /* XXX we can handle only 6 (=8-2) mbuf chains */ 929 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 930 xfer->mbuf, 931 fwohci_execute_db2, db_tr, 932 /* flags */0); 933 if (err == EFBIG) { 934 struct mbuf *m0; 935 936 if (firewire_debug) 937 device_printf(sc->fc.dev, "EFBIG.\n"); 938 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 939 if (m0 != NULL) { 940 m_copydata(xfer->mbuf, 0, 941 xfer->mbuf->m_pkthdr.len, 942 mtod(m0, caddr_t)); 943 m0->m_len = m0->m_pkthdr.len = 944 xfer->mbuf->m_pkthdr.len; 945 m_freem(xfer->mbuf); 946 xfer->mbuf = m0; 947 goto again; 948 } 949 device_printf(sc->fc.dev, "m_getcl failed.\n"); 950 } 951 } 952 if (err) 953 printf("dmamap_load: err=%d\n", err); 954 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 955 BUS_DMASYNC_PREWRITE); 956#if 0 /* OHCI_OUTPUT_MODE == 0 */ 957 for (i = 2; i < db_tr->dbcnt; i++) 958 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 959 OHCI_OUTPUT_MORE); 960#endif 961 } 962 if (maxdesc < db_tr->dbcnt) { 963 maxdesc = db_tr->dbcnt; 964 if (bootverbose) 965 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 966 } 967 /* last db */ 968 LAST_DB(db_tr, db); 969 FWOHCI_DMA_SET(db->db.desc.cmd, 970 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 971 FWOHCI_DMA_WRITE(db->db.desc.depend, 972 STAILQ_NEXT(db_tr, link)->bus_addr); 973 974 if(fsegment == -1 ) 975 fsegment = db_tr->dbcnt; 976 if (dbch->pdb_tr != NULL) { 977 LAST_DB(dbch->pdb_tr, db); 978 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 979 } 980 dbch->pdb_tr = db_tr; 981 db_tr = STAILQ_NEXT(db_tr, link); 982 if(db_tr != dbch->bottom){ 983 goto txloop; 984 } else { 985 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 986 dbch->flags |= FWOHCI_DBCH_FULL; 987 } 988kick: 989 /* kick asy q */ 990 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 991 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 992 993 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 994 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 995 } else { 996 if (bootverbose) 997 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 998 OREAD(sc, OHCI_DMACTL(off))); 999 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1000 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1001 dbch->xferq.flag |= FWXFERQ_RUNNING; 1002 } 1003 1004 dbch->top = db_tr; 1005 splx(s); 1006 return; 1007} 1008 1009static void 1010fwohci_start_atq(struct firewire_comm *fc) 1011{ 1012 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1013 fwohci_start( sc, &(sc->atrq)); 1014 return; 1015} 1016 1017static void 1018fwohci_start_ats(struct firewire_comm *fc) 1019{ 1020 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021 fwohci_start( sc, &(sc->atrs)); 1022 return; 1023} 1024 1025void 1026fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1027{ 1028 int s, ch, err = 0; 1029 struct fwohcidb_tr *tr; 1030 struct fwohcidb *db; 1031 struct fw_xfer *xfer; 1032 u_int32_t off; 1033 u_int stat, status; 1034 int packets; 1035 struct firewire_comm *fc = (struct firewire_comm *)sc; 1036 1037 if(&sc->atrq == dbch){ 1038 off = OHCI_ATQOFF; 1039 ch = ATRQ_CH; 1040 }else if(&sc->atrs == dbch){ 1041 off = OHCI_ATSOFF; 1042 ch = ATRS_CH; 1043 }else{ 1044 return; 1045 } 1046 s = splfw(); 1047 tr = dbch->bottom; 1048 packets = 0; 1049 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1050 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1051 while(dbch->xferq.queued > 0){ 1052 LAST_DB(tr, db); 1053 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1054 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1055 if (fc->status != FWBUSRESET) 1056 /* maybe out of order?? */ 1057 goto out; 1058 } 1059 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1060 BUS_DMASYNC_POSTWRITE); 1061 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1062#if 1 1063 if (firewire_debug) 1064 dump_db(sc, ch); 1065#endif 1066 if(status & OHCI_CNTL_DMA_DEAD) { 1067 /* Stop DMA */ 1068 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1069 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1070 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1071 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1072 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1073 } 1074 stat = status & FWOHCIEV_MASK; 1075 switch(stat){ 1076 case FWOHCIEV_ACKPEND: 1077 case FWOHCIEV_ACKCOMPL: 1078 err = 0; 1079 break; 1080 case FWOHCIEV_ACKBSA: 1081 case FWOHCIEV_ACKBSB: 1082 case FWOHCIEV_ACKBSX: 1083 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1084 err = EBUSY; 1085 break; 1086 case FWOHCIEV_FLUSHED: 1087 case FWOHCIEV_ACKTARD: 1088 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1089 err = EAGAIN; 1090 break; 1091 case FWOHCIEV_MISSACK: 1092 case FWOHCIEV_UNDRRUN: 1093 case FWOHCIEV_OVRRUN: 1094 case FWOHCIEV_DESCERR: 1095 case FWOHCIEV_DTRDERR: 1096 case FWOHCIEV_TIMEOUT: 1097 case FWOHCIEV_TCODERR: 1098 case FWOHCIEV_UNKNOWN: 1099 case FWOHCIEV_ACKDERR: 1100 case FWOHCIEV_ACKTERR: 1101 default: 1102 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1103 stat, fwohcicode[stat]); 1104 err = EINVAL; 1105 break; 1106 } 1107 if (tr->xfer != NULL) { 1108 xfer = tr->xfer; 1109 if (xfer->state == FWXF_RCVD) { 1110#if 0 1111 if (firewire_debug) 1112 printf("already rcvd\n"); 1113#endif 1114 fw_xfer_done(xfer); 1115 } else { 1116 xfer->state = FWXF_SENT; 1117 if (err == EBUSY && fc->status != FWBUSRESET) { 1118 xfer->state = FWXF_BUSY; 1119 xfer->resp = err; 1120 if (xfer->retry_req != NULL) 1121 xfer->retry_req(xfer); 1122 else { 1123 xfer->recv.pay_len = 0; 1124 fw_xfer_done(xfer); 1125 } 1126 } else if (stat != FWOHCIEV_ACKPEND) { 1127 if (stat != FWOHCIEV_ACKCOMPL) 1128 xfer->state = FWXF_SENTERR; 1129 xfer->resp = err; 1130 xfer->recv.pay_len = 0; 1131 fw_xfer_done(xfer); 1132 } 1133 } 1134 /* 1135 * The watchdog timer takes care of split 1136 * transcation timeout for ACKPEND case. 1137 */ 1138 } else { 1139 printf("this shouldn't happen\n"); 1140 } 1141 dbch->xferq.queued --; 1142 tr->xfer = NULL; 1143 1144 packets ++; 1145 tr = STAILQ_NEXT(tr, link); 1146 dbch->bottom = tr; 1147 if (dbch->bottom == dbch->top) { 1148 /* we reaches the end of context program */ 1149 if (firewire_debug && dbch->xferq.queued > 0) 1150 printf("queued > 0\n"); 1151 break; 1152 } 1153 } 1154out: 1155 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1156 printf("make free slot\n"); 1157 dbch->flags &= ~FWOHCI_DBCH_FULL; 1158 fwohci_start(sc, dbch); 1159 } 1160 splx(s); 1161} 1162 1163static void 1164fwohci_db_free(struct fwohci_dbch *dbch) 1165{ 1166 struct fwohcidb_tr *db_tr; 1167 int idb; 1168 1169 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1170 return; 1171 1172 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1173 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1174 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1175 db_tr->buf != NULL) { 1176 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1177 db_tr->buf, dbch->xferq.psize); 1178 db_tr->buf = NULL; 1179 } else if (db_tr->dma_map != NULL) 1180 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1181 } 1182 dbch->ndb = 0; 1183 db_tr = STAILQ_FIRST(&dbch->db_trq); 1184 fwdma_free_multiseg(dbch->am); 1185 free(db_tr, M_FW); 1186 STAILQ_INIT(&dbch->db_trq); 1187 dbch->flags &= ~FWOHCI_DBCH_INIT; 1188} 1189 1190static void 1191fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1192{ 1193 int idb; 1194 struct fwohcidb_tr *db_tr; 1195 1196 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1197 goto out; 1198 1199 /* create dma_tag for buffers */ 1200#define MAX_REQCOUNT 0xffff 1201 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1202 /*alignment*/ 1, /*boundary*/ 0, 1203 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1204 /*highaddr*/ BUS_SPACE_MAXADDR, 1205 /*filter*/NULL, /*filterarg*/NULL, 1206 /*maxsize*/ dbch->xferq.psize, 1207 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1208 /*maxsegsz*/ MAX_REQCOUNT, 1209 /*flags*/ 0, 1210#if __FreeBSD_version >= 501102 1211 /*lockfunc*/busdma_lock_mutex, 1212 /*lockarg*/&Giant, 1213#endif 1214 &dbch->dmat)) 1215 return; 1216 1217 /* allocate DB entries and attach one to each DMA channels */ 1218 /* DB entry must start at 16 bytes bounary. */ 1219 STAILQ_INIT(&dbch->db_trq); 1220 db_tr = (struct fwohcidb_tr *) 1221 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1222 M_FW, M_WAITOK | M_ZERO); 1223 if(db_tr == NULL){ 1224 printf("fwohci_db_init: malloc(1) failed\n"); 1225 return; 1226 } 1227 1228#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1229 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1230 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1231 if (dbch->am == NULL) { 1232 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1233 return; 1234 } 1235 /* Attach DB to DMA ch. */ 1236 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1237 db_tr->dbcnt = 0; 1238 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1239 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1240 /* create dmamap for buffers */ 1241 /* XXX do we need 4bytes alignment tag? */ 1242 /* XXX don't alloc dma_map for AR */ 1243 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1244 printf("bus_dmamap_create failed\n"); 1245 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1246 fwohci_db_free(dbch); 1247 return; 1248 } 1249 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1250 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1251 if (idb % dbch->xferq.bnpacket == 0) 1252 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1253 ].start = (caddr_t)db_tr; 1254 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1255 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1256 ].end = (caddr_t)db_tr; 1257 } 1258 db_tr++; 1259 } 1260 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1261 = STAILQ_FIRST(&dbch->db_trq); 1262out: 1263 dbch->xferq.queued = 0; 1264 dbch->pdb_tr = NULL; 1265 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1266 dbch->bottom = dbch->top; 1267 dbch->flags = FWOHCI_DBCH_INIT; 1268} 1269 1270static int 1271fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1272{ 1273 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1274 int sleepch; 1275 1276 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1277 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1278 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1279 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1280 /* XXX we cannot free buffers until the DMA really stops */ 1281 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1282 fwohci_db_free(&sc->it[dmach]); 1283 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1284 return 0; 1285} 1286 1287static int 1288fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1289{ 1290 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1291 int sleepch; 1292 1293 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1294 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1295 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1296 /* XXX we cannot free buffers until the DMA really stops */ 1297 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1298 fwohci_db_free(&sc->ir[dmach]); 1299 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1300 return 0; 1301} 1302 1303#if BYTE_ORDER == BIG_ENDIAN 1304static void 1305fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1306{ 1307 qld[0] = FWOHCI_DMA_READ(qld[0]); 1308 return; 1309} 1310#endif 1311 1312static int 1313fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1314{ 1315 int err = 0; 1316 int idb, z, i, dmach = 0, ldesc; 1317 u_int32_t off = 0; 1318 struct fwohcidb_tr *db_tr; 1319 struct fwohcidb *db; 1320 1321 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1322 err = EINVAL; 1323 return err; 1324 } 1325 z = dbch->ndesc; 1326 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1327 if( &sc->it[dmach] == dbch){ 1328 off = OHCI_ITOFF(dmach); 1329 break; 1330 } 1331 } 1332 if(off == 0){ 1333 err = EINVAL; 1334 return err; 1335 } 1336 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1337 return err; 1338 dbch->xferq.flag |= FWXFERQ_RUNNING; 1339 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1340 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1341 } 1342 db_tr = dbch->top; 1343 for (idb = 0; idb < dbch->ndb; idb ++) { 1344 fwohci_add_tx_buf(dbch, db_tr, idb); 1345 if(STAILQ_NEXT(db_tr, link) == NULL){ 1346 break; 1347 } 1348 db = db_tr->db; 1349 ldesc = db_tr->dbcnt - 1; 1350 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1351 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1352 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1353 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1354 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1355 FWOHCI_DMA_SET( 1356 db[ldesc].db.desc.cmd, 1357 OHCI_INTERRUPT_ALWAYS); 1358 /* OHCI 1.1 and above */ 1359 FWOHCI_DMA_SET( 1360 db[0].db.desc.cmd, 1361 OHCI_INTERRUPT_ALWAYS); 1362 } 1363 } 1364 db_tr = STAILQ_NEXT(db_tr, link); 1365 } 1366 FWOHCI_DMA_CLEAR( 1367 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1368 return err; 1369} 1370 1371static int 1372fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1373{ 1374 int err = 0; 1375 int idb, z, i, dmach = 0, ldesc; 1376 u_int32_t off = 0; 1377 struct fwohcidb_tr *db_tr; 1378 struct fwohcidb *db; 1379 1380 z = dbch->ndesc; 1381 if(&sc->arrq == dbch){ 1382 off = OHCI_ARQOFF; 1383 }else if(&sc->arrs == dbch){ 1384 off = OHCI_ARSOFF; 1385 }else{ 1386 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1387 if( &sc->ir[dmach] == dbch){ 1388 off = OHCI_IROFF(dmach); 1389 break; 1390 } 1391 } 1392 } 1393 if(off == 0){ 1394 err = EINVAL; 1395 return err; 1396 } 1397 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1398 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1399 return err; 1400 }else{ 1401 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1402 err = EBUSY; 1403 return err; 1404 } 1405 } 1406 dbch->xferq.flag |= FWXFERQ_RUNNING; 1407 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1408 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1409 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1410 } 1411 db_tr = dbch->top; 1412 for (idb = 0; idb < dbch->ndb; idb ++) { 1413 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1414 if (STAILQ_NEXT(db_tr, link) == NULL) 1415 break; 1416 db = db_tr->db; 1417 ldesc = db_tr->dbcnt - 1; 1418 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1419 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1420 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1421 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1422 FWOHCI_DMA_SET( 1423 db[ldesc].db.desc.cmd, 1424 OHCI_INTERRUPT_ALWAYS); 1425 FWOHCI_DMA_CLEAR( 1426 db[ldesc].db.desc.depend, 1427 0xf); 1428 } 1429 } 1430 db_tr = STAILQ_NEXT(db_tr, link); 1431 } 1432 FWOHCI_DMA_CLEAR( 1433 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1434 dbch->buf_offset = 0; 1435 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1436 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1437 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1438 return err; 1439 }else{ 1440 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1441 } 1442 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1443 return err; 1444} 1445 1446static int 1447fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1448{ 1449 int sec, cycle, cycle_match; 1450 1451 cycle = cycle_now & 0x1fff; 1452 sec = cycle_now >> 13; 1453#define CYCLE_MOD 0x10 1454#if 1 1455#define CYCLE_DELAY 8 /* min delay to start DMA */ 1456#else 1457#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1458#endif 1459 cycle = cycle + CYCLE_DELAY; 1460 if (cycle >= 8000) { 1461 sec ++; 1462 cycle -= 8000; 1463 } 1464 cycle = roundup2(cycle, CYCLE_MOD); 1465 if (cycle >= 8000) { 1466 sec ++; 1467 if (cycle == 8000) 1468 cycle = 0; 1469 else 1470 cycle = CYCLE_MOD; 1471 } 1472 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1473 1474 return(cycle_match); 1475} 1476 1477static int 1478fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1479{ 1480 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1481 int err = 0; 1482 unsigned short tag, ich; 1483 struct fwohci_dbch *dbch; 1484 int cycle_match, cycle_now, s, ldesc; 1485 u_int32_t stat; 1486 struct fw_bulkxfer *first, *chunk, *prev; 1487 struct fw_xferq *it; 1488 1489 dbch = &sc->it[dmach]; 1490 it = &dbch->xferq; 1491 1492 tag = (it->flag >> 6) & 3; 1493 ich = it->flag & 0x3f; 1494 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1495 dbch->ndb = it->bnpacket * it->bnchunk; 1496 dbch->ndesc = 3; 1497 fwohci_db_init(sc, dbch); 1498 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1499 return ENOMEM; 1500 err = fwohci_tx_enable(sc, dbch); 1501 } 1502 if(err) 1503 return err; 1504 1505 ldesc = dbch->ndesc - 1; 1506 s = splfw(); 1507 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1508 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1509 struct fwohcidb *db; 1510 1511 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1512 BUS_DMASYNC_PREWRITE); 1513 fwohci_txbufdb(sc, dmach, chunk); 1514 if (prev != NULL) { 1515 db = ((struct fwohcidb_tr *)(prev->end))->db; 1516#if 0 /* XXX necessary? */ 1517 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1518 OHCI_BRANCH_ALWAYS); 1519#endif 1520#if 0 /* if bulkxfer->npacket changes */ 1521 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1522 ((struct fwohcidb_tr *) 1523 (chunk->start))->bus_addr | dbch->ndesc; 1524#else 1525 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1526 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1527#endif 1528 } 1529 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1530 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1531 prev = chunk; 1532 } 1533 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1534 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1535 splx(s); 1536 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1537 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1538 printf("stat 0x%x\n", stat); 1539 1540 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1541 return 0; 1542 1543#if 0 1544 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1545#endif 1546 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1547 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1548 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1549 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1550 1551 first = STAILQ_FIRST(&it->stdma); 1552 OWRITE(sc, OHCI_ITCMD(dmach), 1553 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1554 if (firewire_debug) { 1555 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1556#if 1 1557 dump_dma(sc, ITX_CH + dmach); 1558#endif 1559 } 1560 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1561#if 1 1562 /* Don't start until all chunks are buffered */ 1563 if (STAILQ_FIRST(&it->stfree) != NULL) 1564 goto out; 1565#endif 1566#if 1 1567 /* Clear cycle match counter bits */ 1568 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1569 1570 /* 2bit second + 13bit cycle */ 1571 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1572 cycle_match = fwohci_next_cycle(fc, cycle_now); 1573 1574 OWRITE(sc, OHCI_ITCTL(dmach), 1575 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1576 | OHCI_CNTL_DMA_RUN); 1577#else 1578 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1579#endif 1580 if (firewire_debug) { 1581 printf("cycle_match: 0x%04x->0x%04x\n", 1582 cycle_now, cycle_match); 1583 dump_dma(sc, ITX_CH + dmach); 1584 dump_db(sc, ITX_CH + dmach); 1585 } 1586 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1587 device_printf(sc->fc.dev, 1588 "IT DMA underrun (0x%08x)\n", stat); 1589 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1590 } 1591out: 1592 return err; 1593} 1594 1595static int 1596fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1597{ 1598 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1599 int err = 0, s, ldesc; 1600 unsigned short tag, ich; 1601 u_int32_t stat; 1602 struct fwohci_dbch *dbch; 1603 struct fwohcidb_tr *db_tr; 1604 struct fw_bulkxfer *first, *prev, *chunk; 1605 struct fw_xferq *ir; 1606 1607 dbch = &sc->ir[dmach]; 1608 ir = &dbch->xferq; 1609 1610 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1611 tag = (ir->flag >> 6) & 3; 1612 ich = ir->flag & 0x3f; 1613 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1614 1615 ir->queued = 0; 1616 dbch->ndb = ir->bnpacket * ir->bnchunk; 1617 dbch->ndesc = 2; 1618 fwohci_db_init(sc, dbch); 1619 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1620 return ENOMEM; 1621 err = fwohci_rx_enable(sc, dbch); 1622 } 1623 if(err) 1624 return err; 1625 1626 first = STAILQ_FIRST(&ir->stfree); 1627 if (first == NULL) { 1628 device_printf(fc->dev, "IR DMA no free chunk\n"); 1629 return 0; 1630 } 1631 1632 ldesc = dbch->ndesc - 1; 1633 s = splfw(); 1634 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1635 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1636 struct fwohcidb *db; 1637 1638#if 1 /* XXX for if_fwe */ 1639 if (chunk->mbuf != NULL) { 1640 db_tr = (struct fwohcidb_tr *)(chunk->start); 1641 db_tr->dbcnt = 1; 1642 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1643 chunk->mbuf, fwohci_execute_db2, db_tr, 1644 /* flags */0); 1645 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1646 OHCI_UPDATE | OHCI_INPUT_LAST | 1647 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1648 } 1649#endif 1650 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1651 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1652 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1653 if (prev != NULL) { 1654 db = ((struct fwohcidb_tr *)(prev->end))->db; 1655 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1656 } 1657 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1658 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1659 prev = chunk; 1660 } 1661 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1662 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1663 splx(s); 1664 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1665 if (stat & OHCI_CNTL_DMA_ACTIVE) 1666 return 0; 1667 if (stat & OHCI_CNTL_DMA_RUN) { 1668 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1669 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1670 } 1671 1672 if (firewire_debug) 1673 printf("start IR DMA 0x%x\n", stat); 1674 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1675 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1676 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1677 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1678 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1679 OWRITE(sc, OHCI_IRCMD(dmach), 1680 ((struct fwohcidb_tr *)(first->start))->bus_addr 1681 | dbch->ndesc); 1682 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1683 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1684#if 0 1685 dump_db(sc, IRX_CH + dmach); 1686#endif 1687 return err; 1688} 1689 1690int 1691fwohci_stop(struct fwohci_softc *sc, device_t dev) 1692{ 1693 u_int i; 1694 1695/* Now stopping all DMA channel */ 1696 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1697 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1698 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1699 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1700 1701 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1702 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1703 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1704 } 1705 1706/* FLUSH FIFO and reset Transmitter/Reciever */ 1707 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1708 1709/* Stop interrupt */ 1710 OWRITE(sc, FWOHCI_INTMASKCLR, 1711 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1712 | OHCI_INT_PHY_INT 1713 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1714 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1715 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1716 | OHCI_INT_PHY_BUS_R); 1717 1718 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1719 fw_drain_txq(&sc->fc); 1720 1721/* XXX Link down? Bus reset? */ 1722 return 0; 1723} 1724 1725int 1726fwohci_resume(struct fwohci_softc *sc, device_t dev) 1727{ 1728 int i; 1729 struct fw_xferq *ir; 1730 struct fw_bulkxfer *chunk; 1731 1732 fwohci_reset(sc, dev); 1733 /* XXX resume isochronus receive automatically. (how about TX?) */ 1734 for(i = 0; i < sc->fc.nisodma; i ++) { 1735 ir = &sc->ir[i].xferq; 1736 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1737 device_printf(sc->fc.dev, 1738 "resume iso receive ch: %d\n", i); 1739 ir->flag &= ~FWXFERQ_RUNNING; 1740 /* requeue stdma to stfree */ 1741 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1742 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1743 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1744 } 1745 sc->fc.irx_enable(&sc->fc, i); 1746 } 1747 } 1748 1749 bus_generic_resume(dev); 1750 sc->fc.ibr(&sc->fc); 1751 return 0; 1752} 1753 1754#define ACK_ALL 1755static void 1756fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1757{ 1758 u_int32_t irstat, itstat; 1759 u_int i; 1760 struct firewire_comm *fc = (struct firewire_comm *)sc; 1761 1762#ifdef OHCI_DEBUG 1763 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1764 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1765 stat & OHCI_INT_EN ? "DMA_EN ":"", 1766 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1767 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1768 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1769 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1770 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1771 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1772 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1773 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1774 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1775 stat & OHCI_INT_PHY_SID ? "SID ":"", 1776 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1777 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1778 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1779 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1780 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1781 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1782 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1783 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1784 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1785 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1786 stat, OREAD(sc, FWOHCI_INTMASK) 1787 ); 1788#endif 1789/* Bus reset */ 1790 if(stat & OHCI_INT_PHY_BUS_R ){ 1791 if (fc->status == FWBUSRESET) 1792 goto busresetout; 1793 /* Disable bus reset interrupt until sid recv. */ 1794 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1795 1796 device_printf(fc->dev, "BUS reset\n"); 1797 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1798 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1799 1800 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1801 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1802 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1803 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1804 1805#ifndef ACK_ALL 1806 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1807#endif 1808 fw_busreset(fc); 1809 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1810 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1811 } 1812busresetout: 1813 if((stat & OHCI_INT_DMA_IR )){ 1814#ifndef ACK_ALL 1815 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1816#endif 1817#if __FreeBSD_version >= 500000 1818 irstat = atomic_readandclear_int(&sc->irstat); 1819#else 1820 irstat = sc->irstat; 1821 sc->irstat = 0; 1822#endif 1823 for(i = 0; i < fc->nisodma ; i++){ 1824 struct fwohci_dbch *dbch; 1825 1826 if((irstat & (1 << i)) != 0){ 1827 dbch = &sc->ir[i]; 1828 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1829 device_printf(sc->fc.dev, 1830 "dma(%d) not active\n", i); 1831 continue; 1832 } 1833 fwohci_rbuf_update(sc, i); 1834 } 1835 } 1836 } 1837 if((stat & OHCI_INT_DMA_IT )){ 1838#ifndef ACK_ALL 1839 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1840#endif 1841#if __FreeBSD_version >= 500000 1842 itstat = atomic_readandclear_int(&sc->itstat); 1843#else 1844 itstat = sc->itstat; 1845 sc->itstat = 0; 1846#endif 1847 for(i = 0; i < fc->nisodma ; i++){ 1848 if((itstat & (1 << i)) != 0){ 1849 fwohci_tbuf_update(sc, i); 1850 } 1851 } 1852 } 1853 if((stat & OHCI_INT_DMA_PRRS )){ 1854#ifndef ACK_ALL 1855 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1856#endif 1857#if 0 1858 dump_dma(sc, ARRS_CH); 1859 dump_db(sc, ARRS_CH); 1860#endif 1861 fwohci_arcv(sc, &sc->arrs, count); 1862 } 1863 if((stat & OHCI_INT_DMA_PRRQ )){ 1864#ifndef ACK_ALL 1865 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1866#endif 1867#if 0 1868 dump_dma(sc, ARRQ_CH); 1869 dump_db(sc, ARRQ_CH); 1870#endif 1871 fwohci_arcv(sc, &sc->arrq, count); 1872 } 1873 if(stat & OHCI_INT_PHY_SID){ 1874 u_int32_t *buf, node_id; 1875 int plen; 1876 1877#ifndef ACK_ALL 1878 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1879#endif 1880 /* Enable bus reset interrupt */ 1881 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1882 /* Allow async. request to us */ 1883 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1884 /* XXX insecure ?? */ 1885 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1886 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1887 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1888 /* Set ATRetries register */ 1889 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1890/* 1891** Checking whether the node is root or not. If root, turn on 1892** cycle master. 1893*/ 1894 node_id = OREAD(sc, FWOHCI_NODEID); 1895 plen = OREAD(sc, OHCI_SID_CNT); 1896 1897 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1898 node_id, (plen >> 16) & 0xff); 1899 if (!(node_id & OHCI_NODE_VALID)) { 1900 printf("Bus reset failure\n"); 1901 goto sidout; 1902 } 1903 if (node_id & OHCI_NODE_ROOT) { 1904 printf("CYCLEMASTER mode\n"); 1905 OWRITE(sc, OHCI_LNKCTL, 1906 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1907 } else { 1908 printf("non CYCLEMASTER mode\n"); 1909 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1910 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1911 } 1912 fc->nodeid = node_id & 0x3f; 1913 1914 if (plen & OHCI_SID_ERR) { 1915 device_printf(fc->dev, "SID Error\n"); 1916 goto sidout; 1917 } 1918 plen &= OHCI_SID_CNT_MASK; 1919 if (plen < 4 || plen > OHCI_SIDSIZE) { 1920 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1921 goto sidout; 1922 } 1923 plen -= 4; /* chop control info */ 1924 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1925 if (buf == NULL) { 1926 device_printf(fc->dev, "malloc failed\n"); 1927 goto sidout; 1928 } 1929 for (i = 0; i < plen / 4; i ++) 1930 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1931#if 1 1932 /* pending all pre-bus_reset packets */ 1933 fwohci_txd(sc, &sc->atrq); 1934 fwohci_txd(sc, &sc->atrs); 1935 fwohci_arcv(sc, &sc->arrs, -1); 1936 fwohci_arcv(sc, &sc->arrq, -1); 1937 fw_drain_txq(fc); 1938#endif 1939 fw_sidrcv(fc, buf, plen); 1940 free(buf, M_FW); 1941 } 1942sidout: 1943 if((stat & OHCI_INT_DMA_ATRQ )){ 1944#ifndef ACK_ALL 1945 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1946#endif 1947 fwohci_txd(sc, &(sc->atrq)); 1948 } 1949 if((stat & OHCI_INT_DMA_ATRS )){ 1950#ifndef ACK_ALL 1951 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1952#endif 1953 fwohci_txd(sc, &(sc->atrs)); 1954 } 1955 if((stat & OHCI_INT_PW_ERR )){ 1956#ifndef ACK_ALL 1957 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1958#endif 1959 device_printf(fc->dev, "posted write error\n"); 1960 } 1961 if((stat & OHCI_INT_ERR )){ 1962#ifndef ACK_ALL 1963 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1964#endif 1965 device_printf(fc->dev, "unrecoverable error\n"); 1966 } 1967 if((stat & OHCI_INT_PHY_INT)) { 1968#ifndef ACK_ALL 1969 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1970#endif 1971 device_printf(fc->dev, "phy int\n"); 1972 } 1973 1974 return; 1975} 1976 1977#if FWOHCI_TASKQUEUE 1978static void 1979fwohci_complete(void *arg, int pending) 1980{ 1981 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1982 u_int32_t stat; 1983 1984again: 1985 stat = atomic_readandclear_int(&sc->intstat); 1986 if (stat) 1987 fwohci_intr_body(sc, stat, -1); 1988 else 1989 return; 1990 goto again; 1991} 1992#endif 1993 1994static u_int32_t 1995fwochi_check_stat(struct fwohci_softc *sc) 1996{ 1997 u_int32_t stat, irstat, itstat; 1998 1999 stat = OREAD(sc, FWOHCI_INTSTAT); 2000 if (stat == 0xffffffff) { 2001 device_printf(sc->fc.dev, 2002 "device physically ejected?\n"); 2003 return(stat); 2004 } 2005#ifdef ACK_ALL 2006 if (stat) 2007 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2008#endif 2009 if (stat & OHCI_INT_DMA_IR) { 2010 irstat = OREAD(sc, OHCI_IR_STAT); 2011 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2012 atomic_set_int(&sc->irstat, irstat); 2013 } 2014 if (stat & OHCI_INT_DMA_IT) { 2015 itstat = OREAD(sc, OHCI_IT_STAT); 2016 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2017 atomic_set_int(&sc->itstat, itstat); 2018 } 2019 return(stat); 2020} 2021 2022void 2023fwohci_intr(void *arg) 2024{ 2025 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2026 u_int32_t stat; 2027#if !FWOHCI_TASKQUEUE 2028 u_int32_t bus_reset = 0; 2029#endif 2030 2031 if (!(sc->intmask & OHCI_INT_EN)) { 2032 /* polling mode */ 2033 return; 2034 } 2035 2036#if !FWOHCI_TASKQUEUE 2037again: 2038#endif 2039 stat = fwochi_check_stat(sc); 2040 if (stat == 0 || stat == 0xffffffff) 2041 return; 2042#if FWOHCI_TASKQUEUE 2043 atomic_set_int(&sc->intstat, stat); 2044 /* XXX mask bus reset intr. during bus reset phase */ 2045 if (stat) 2046 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2047#else 2048 /* We cannot clear bus reset event during bus reset phase */ 2049 if ((stat & ~bus_reset) == 0) 2050 return; 2051 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2052 fwohci_intr_body(sc, stat, -1); 2053 goto again; 2054#endif 2055} 2056 2057void 2058fwohci_poll(struct firewire_comm *fc, int quick, int count) 2059{ 2060 int s; 2061 u_int32_t stat; 2062 struct fwohci_softc *sc; 2063 2064 2065 sc = (struct fwohci_softc *)fc; 2066 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2067 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2068 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2069#if 0 2070 if (!quick) { 2071#else 2072 if (1) { 2073#endif 2074 stat = fwochi_check_stat(sc); 2075 if (stat == 0 || stat == 0xffffffff) 2076 return; 2077 } 2078 s = splfw(); 2079 fwohci_intr_body(sc, stat, count); 2080 splx(s); 2081} 2082 2083static void 2084fwohci_set_intr(struct firewire_comm *fc, int enable) 2085{ 2086 struct fwohci_softc *sc; 2087 2088 sc = (struct fwohci_softc *)fc; 2089 if (bootverbose) 2090 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2091 if (enable) { 2092 sc->intmask |= OHCI_INT_EN; 2093 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2094 } else { 2095 sc->intmask &= ~OHCI_INT_EN; 2096 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2097 } 2098} 2099 2100static void 2101fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2102{ 2103 struct firewire_comm *fc = &sc->fc; 2104 struct fwohcidb *db; 2105 struct fw_bulkxfer *chunk; 2106 struct fw_xferq *it; 2107 u_int32_t stat, count; 2108 int s, w=0, ldesc; 2109 2110 it = fc->it[dmach]; 2111 ldesc = sc->it[dmach].ndesc - 1; 2112 s = splfw(); /* unnecessary ? */ 2113 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2114 if (firewire_debug) 2115 dump_db(sc, ITX_CH + dmach); 2116 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2117 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2118 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2119 >> OHCI_STATUS_SHIFT; 2120 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2121 /* timestamp */ 2122 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2123 & OHCI_COUNT_MASK; 2124 if (stat == 0) 2125 break; 2126 STAILQ_REMOVE_HEAD(&it->stdma, link); 2127 switch (stat & FWOHCIEV_MASK){ 2128 case FWOHCIEV_ACKCOMPL: 2129#if 0 2130 device_printf(fc->dev, "0x%08x\n", count); 2131#endif 2132 break; 2133 default: 2134 device_printf(fc->dev, 2135 "Isochronous transmit err %02x(%s)\n", 2136 stat, fwohcicode[stat & 0x1f]); 2137 } 2138 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2139 w++; 2140 } 2141 splx(s); 2142 if (w) 2143 wakeup(it); 2144} 2145 2146static void 2147fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2148{ 2149 struct firewire_comm *fc = &sc->fc; 2150 struct fwohcidb_tr *db_tr; 2151 struct fw_bulkxfer *chunk; 2152 struct fw_xferq *ir; 2153 u_int32_t stat; 2154 int s, w=0, ldesc; 2155 2156 ir = fc->ir[dmach]; 2157 ldesc = sc->ir[dmach].ndesc - 1; 2158#if 0 2159 dump_db(sc, dmach); 2160#endif 2161 s = splfw(); 2162 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2163 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2164 db_tr = (struct fwohcidb_tr *)chunk->end; 2165 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2166 >> OHCI_STATUS_SHIFT; 2167 if (stat == 0) 2168 break; 2169 2170 if (chunk->mbuf != NULL) { 2171 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2172 BUS_DMASYNC_POSTREAD); 2173 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2174 } else if (ir->buf != NULL) { 2175 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2176 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2177 } else { 2178 /* XXX */ 2179 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2180 } 2181 2182 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2183 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2184 switch (stat & FWOHCIEV_MASK) { 2185 case FWOHCIEV_ACKCOMPL: 2186 chunk->resp = 0; 2187 break; 2188 default: 2189 chunk->resp = EINVAL; 2190 device_printf(fc->dev, 2191 "Isochronous receive err %02x(%s)\n", 2192 stat, fwohcicode[stat & 0x1f]); 2193 } 2194 w++; 2195 } 2196 splx(s); 2197 if (w) { 2198 if (ir->flag & FWXFERQ_HANDLER) 2199 ir->hand(ir); 2200 else 2201 wakeup(ir); 2202 } 2203} 2204 2205void 2206dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2207{ 2208 u_int32_t off, cntl, stat, cmd, match; 2209 2210 if(ch == 0){ 2211 off = OHCI_ATQOFF; 2212 }else if(ch == 1){ 2213 off = OHCI_ATSOFF; 2214 }else if(ch == 2){ 2215 off = OHCI_ARQOFF; 2216 }else if(ch == 3){ 2217 off = OHCI_ARSOFF; 2218 }else if(ch < IRX_CH){ 2219 off = OHCI_ITCTL(ch - ITX_CH); 2220 }else{ 2221 off = OHCI_IRCTL(ch - IRX_CH); 2222 } 2223 cntl = stat = OREAD(sc, off); 2224 cmd = OREAD(sc, off + 0xc); 2225 match = OREAD(sc, off + 0x10); 2226 2227 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2228 ch, 2229 cntl, 2230 cmd, 2231 match); 2232 stat &= 0xffff ; 2233 if (stat) { 2234 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2235 ch, 2236 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2237 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2238 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2239 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2240 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2241 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2242 fwohcicode[stat & 0x1f], 2243 stat & 0x1f 2244 ); 2245 }else{ 2246 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2247 } 2248} 2249 2250void 2251dump_db(struct fwohci_softc *sc, u_int32_t ch) 2252{ 2253 struct fwohci_dbch *dbch; 2254 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2255 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2256 int idb, jdb; 2257 u_int32_t cmd, off; 2258 if(ch == 0){ 2259 off = OHCI_ATQOFF; 2260 dbch = &sc->atrq; 2261 }else if(ch == 1){ 2262 off = OHCI_ATSOFF; 2263 dbch = &sc->atrs; 2264 }else if(ch == 2){ 2265 off = OHCI_ARQOFF; 2266 dbch = &sc->arrq; 2267 }else if(ch == 3){ 2268 off = OHCI_ARSOFF; 2269 dbch = &sc->arrs; 2270 }else if(ch < IRX_CH){ 2271 off = OHCI_ITCTL(ch - ITX_CH); 2272 dbch = &sc->it[ch - ITX_CH]; 2273 }else { 2274 off = OHCI_IRCTL(ch - IRX_CH); 2275 dbch = &sc->ir[ch - IRX_CH]; 2276 } 2277 cmd = OREAD(sc, off + 0xc); 2278 2279 if( dbch->ndb == 0 ){ 2280 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2281 return; 2282 } 2283 pp = dbch->top; 2284 prev = pp->db; 2285 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2286 if(pp == NULL){ 2287 curr = NULL; 2288 goto outdb; 2289 } 2290 cp = STAILQ_NEXT(pp, link); 2291 if(cp == NULL){ 2292 curr = NULL; 2293 goto outdb; 2294 } 2295 np = STAILQ_NEXT(cp, link); 2296 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2297 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2298 curr = cp->db; 2299 if(np != NULL){ 2300 next = np->db; 2301 }else{ 2302 next = NULL; 2303 } 2304 goto outdb; 2305 } 2306 } 2307 pp = STAILQ_NEXT(pp, link); 2308 prev = pp->db; 2309 } 2310outdb: 2311 if( curr != NULL){ 2312#if 0 2313 printf("Prev DB %d\n", ch); 2314 print_db(pp, prev, ch, dbch->ndesc); 2315#endif 2316 printf("Current DB %d\n", ch); 2317 print_db(cp, curr, ch, dbch->ndesc); 2318#if 0 2319 printf("Next DB %d\n", ch); 2320 print_db(np, next, ch, dbch->ndesc); 2321#endif 2322 }else{ 2323 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2324 } 2325 return; 2326} 2327 2328void 2329print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2330 u_int32_t ch, u_int32_t max) 2331{ 2332 fwohcireg_t stat; 2333 int i, key; 2334 u_int32_t cmd, res; 2335 2336 if(db == NULL){ 2337 printf("No Descriptor is found\n"); 2338 return; 2339 } 2340 2341 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2342 ch, 2343 "Current", 2344 "OP ", 2345 "KEY", 2346 "INT", 2347 "BR ", 2348 "len", 2349 "Addr", 2350 "Depend", 2351 "Stat", 2352 "Cnt"); 2353 for( i = 0 ; i <= max ; i ++){ 2354 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2355 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2356 key = cmd & OHCI_KEY_MASK; 2357 stat = res >> OHCI_STATUS_SHIFT; 2358#if __FreeBSD_version >= 500000 2359 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2360 (uintmax_t)db_tr->bus_addr, 2361#else 2362 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2363 db_tr->bus_addr, 2364#endif 2365 dbcode[(cmd >> 28) & 0xf], 2366 dbkey[(cmd >> 24) & 0x7], 2367 dbcond[(cmd >> 20) & 0x3], 2368 dbcond[(cmd >> 18) & 0x3], 2369 cmd & OHCI_COUNT_MASK, 2370 FWOHCI_DMA_READ(db[i].db.desc.addr), 2371 FWOHCI_DMA_READ(db[i].db.desc.depend), 2372 stat, 2373 res & OHCI_COUNT_MASK); 2374 if(stat & 0xff00){ 2375 printf(" %s%s%s%s%s%s %s(%x)\n", 2376 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2377 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2378 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2379 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2380 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2381 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2382 fwohcicode[stat & 0x1f], 2383 stat & 0x1f 2384 ); 2385 }else{ 2386 printf(" Nostat\n"); 2387 } 2388 if(key == OHCI_KEY_ST2 ){ 2389 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2390 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2391 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2392 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2393 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2394 } 2395 if(key == OHCI_KEY_DEVICE){ 2396 return; 2397 } 2398 if((cmd & OHCI_BRANCH_MASK) 2399 == OHCI_BRANCH_ALWAYS){ 2400 return; 2401 } 2402 if((cmd & OHCI_CMD_MASK) 2403 == OHCI_OUTPUT_LAST){ 2404 return; 2405 } 2406 if((cmd & OHCI_CMD_MASK) 2407 == OHCI_INPUT_LAST){ 2408 return; 2409 } 2410 if(key == OHCI_KEY_ST2 ){ 2411 i++; 2412 } 2413 } 2414 return; 2415} 2416 2417void 2418fwohci_ibr(struct firewire_comm *fc) 2419{ 2420 struct fwohci_softc *sc; 2421 u_int32_t fun; 2422 2423 device_printf(fc->dev, "Initiate bus reset\n"); 2424 sc = (struct fwohci_softc *)fc; 2425 2426 /* 2427 * Set root hold-off bit so that non cyclemaster capable node 2428 * shouldn't became the root node. 2429 */ 2430#if 1 2431 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2432 fun |= FW_PHY_IBR | FW_PHY_RHB; 2433 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2434#else /* Short bus reset */ 2435 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2436 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2437 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2438#endif 2439} 2440 2441void 2442fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2443{ 2444 struct fwohcidb_tr *db_tr, *fdb_tr; 2445 struct fwohci_dbch *dbch; 2446 struct fwohcidb *db; 2447 struct fw_pkt *fp; 2448 struct fwohci_txpkthdr *ohcifp; 2449 unsigned short chtag; 2450 int idb; 2451 2452 dbch = &sc->it[dmach]; 2453 chtag = sc->it[dmach].xferq.flag & 0xff; 2454 2455 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2456 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2457/* 2458device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2459*/ 2460 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2461 db = db_tr->db; 2462 fp = (struct fw_pkt *)db_tr->buf; 2463 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2464 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2465 ohcifp->mode.common.spd = 0 & 0x7; 2466 ohcifp->mode.stream.len = fp->mode.stream.len; 2467 ohcifp->mode.stream.chtag = chtag; 2468 ohcifp->mode.stream.tcode = 0xa; 2469#if BYTE_ORDER == BIG_ENDIAN 2470 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2471 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2472#endif 2473 2474 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2475 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2476 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2477#if 0 /* if bulkxfer->npackets changes */ 2478 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2479 | OHCI_UPDATE 2480 | OHCI_BRANCH_ALWAYS; 2481 db[0].db.desc.depend = 2482 = db[dbch->ndesc - 1].db.desc.depend 2483 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2484#else 2485 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2486 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2487#endif 2488 bulkxfer->end = (caddr_t)db_tr; 2489 db_tr = STAILQ_NEXT(db_tr, link); 2490 } 2491 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2492 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2493 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2494#if 0 /* if bulkxfer->npackets changes */ 2495 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2496 /* OHCI 1.1 and above */ 2497 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2498#endif 2499/* 2500 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2501 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2502device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2503*/ 2504 return; 2505} 2506 2507static int 2508fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2509 int poffset) 2510{ 2511 struct fwohcidb *db = db_tr->db; 2512 struct fw_xferq *it; 2513 int err = 0; 2514 2515 it = &dbch->xferq; 2516 if(it->buf == 0){ 2517 err = EINVAL; 2518 return err; 2519 } 2520 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2521 db_tr->dbcnt = 3; 2522 2523 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2524 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2525 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2526 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2527 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2528 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2529 2530 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2531 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2532#if 1 2533 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2534 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2535#endif 2536 return 0; 2537} 2538 2539int 2540fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2541 int poffset, struct fwdma_alloc *dummy_dma) 2542{ 2543 struct fwohcidb *db = db_tr->db; 2544 struct fw_xferq *ir; 2545 int i, ldesc; 2546 bus_addr_t dbuf[2]; 2547 int dsiz[2]; 2548 2549 ir = &dbch->xferq; 2550 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2551 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2552 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2553 if (db_tr->buf == NULL) 2554 return(ENOMEM); 2555 db_tr->dbcnt = 1; 2556 dsiz[0] = ir->psize; 2557 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2558 BUS_DMASYNC_PREREAD); 2559 } else { 2560 db_tr->dbcnt = 0; 2561 if (dummy_dma != NULL) { 2562 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2563 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2564 } 2565 dsiz[db_tr->dbcnt] = ir->psize; 2566 if (ir->buf != NULL) { 2567 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2568 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2569 } 2570 db_tr->dbcnt++; 2571 } 2572 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2573 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2574 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2575 if (ir->flag & FWXFERQ_STREAM) { 2576 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2577 } 2578 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2579 } 2580 ldesc = db_tr->dbcnt - 1; 2581 if (ir->flag & FWXFERQ_STREAM) { 2582 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2583 } 2584 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2585 return 0; 2586} 2587 2588 2589static int 2590fwohci_arcv_swap(struct fw_pkt *fp, int len) 2591{ 2592 struct fw_pkt *fp0; 2593 u_int32_t ld0; 2594 int slen, hlen; 2595#if BYTE_ORDER == BIG_ENDIAN 2596 int i; 2597#endif 2598 2599 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2600#if 0 2601 printf("ld0: x%08x\n", ld0); 2602#endif 2603 fp0 = (struct fw_pkt *)&ld0; 2604 /* determine length to swap */ 2605 switch (fp0->mode.common.tcode) { 2606 case FWTCODE_RREQQ: 2607 case FWTCODE_WRES: 2608 case FWTCODE_WREQQ: 2609 case FWTCODE_RRESQ: 2610 case FWOHCITCODE_PHY: 2611 slen = 12; 2612 break; 2613 case FWTCODE_RREQB: 2614 case FWTCODE_WREQB: 2615 case FWTCODE_LREQ: 2616 case FWTCODE_RRESB: 2617 case FWTCODE_LRES: 2618 slen = 16; 2619 break; 2620 default: 2621 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2622 return(0); 2623 } 2624 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2625 if (hlen > len) { 2626 if (firewire_debug) 2627 printf("splitted header\n"); 2628 return(-hlen); 2629 } 2630#if BYTE_ORDER == BIG_ENDIAN 2631 for(i = 0; i < slen/4; i ++) 2632 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2633#endif 2634 return(hlen); 2635} 2636 2637static int 2638fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2639{ 2640 struct tcode_info *info; 2641 int r; 2642 2643 info = &tinfo[fp->mode.common.tcode]; 2644 r = info->hdr_len + sizeof(u_int32_t); 2645 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2646 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); 2647 2648 if (r == sizeof(u_int32_t)) 2649 /* XXX */ 2650 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2651 fp->mode.common.tcode); 2652 2653 if (r > dbch->xferq.psize) { 2654 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2655 /* panic ? */ 2656 } 2657 2658 return r; 2659} 2660 2661static void 2662fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2663{ 2664 struct fwohcidb *db = &db_tr->db[0]; 2665 2666 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2667 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2668 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2669 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2670 dbch->bottom = db_tr; 2671} 2672 2673static void 2674fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2675{ 2676 struct fwohcidb_tr *db_tr; 2677 struct iovec vec[2]; 2678 struct fw_pkt pktbuf; 2679 int nvec; 2680 struct fw_pkt *fp; 2681 u_int8_t *ld; 2682 u_int32_t stat, off, status; 2683 u_int spd; 2684 int len, plen, hlen, pcnt, offset; 2685 int s; 2686 caddr_t buf; 2687 int resCount; 2688 2689 if(&sc->arrq == dbch){ 2690 off = OHCI_ARQOFF; 2691 }else if(&sc->arrs == dbch){ 2692 off = OHCI_ARSOFF; 2693 }else{ 2694 return; 2695 } 2696 2697 s = splfw(); 2698 db_tr = dbch->top; 2699 pcnt = 0; 2700 /* XXX we cannot handle a packet which lies in more than two buf */ 2701 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2702 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2703 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2704 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2705#if 0 2706 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2707#endif 2708 while (status & OHCI_CNTL_DMA_ACTIVE) { 2709 len = dbch->xferq.psize - resCount; 2710 ld = (u_int8_t *)db_tr->buf; 2711 if (dbch->pdb_tr == NULL) { 2712 len -= dbch->buf_offset; 2713 ld += dbch->buf_offset; 2714 } 2715 if (len > 0) 2716 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2717 BUS_DMASYNC_POSTREAD); 2718 while (len > 0 ) { 2719 if (count >= 0 && count-- == 0) 2720 goto out; 2721 if(dbch->pdb_tr != NULL){ 2722 /* we have a fragment in previous buffer */ 2723 int rlen; 2724 2725 offset = dbch->buf_offset; 2726 if (offset < 0) 2727 offset = - offset; 2728 buf = dbch->pdb_tr->buf + offset; 2729 rlen = dbch->xferq.psize - offset; 2730 if (firewire_debug) 2731 printf("rlen=%d, offset=%d\n", 2732 rlen, dbch->buf_offset); 2733 if (dbch->buf_offset < 0) { 2734 /* splitted in header, pull up */ 2735 char *p; 2736 2737 p = (char *)&pktbuf; 2738 bcopy(buf, p, rlen); 2739 p += rlen; 2740 /* this must be too long but harmless */ 2741 rlen = sizeof(pktbuf) - rlen; 2742 if (rlen < 0) 2743 printf("why rlen < 0\n"); 2744 bcopy(db_tr->buf, p, rlen); 2745 ld += rlen; 2746 len -= rlen; 2747 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2748 if (hlen < 0) { 2749 printf("hlen < 0 shouldn't happen"); 2750 } 2751 offset = sizeof(pktbuf); 2752 vec[0].iov_base = (char *)&pktbuf; 2753 vec[0].iov_len = offset; 2754 } else { 2755 /* splitted in payload */ 2756 offset = rlen; 2757 vec[0].iov_base = buf; 2758 vec[0].iov_len = rlen; 2759 } 2760 fp=(struct fw_pkt *)vec[0].iov_base; 2761 nvec = 1; 2762 } else { 2763 /* no fragment in previous buffer */ 2764 fp=(struct fw_pkt *)ld; 2765 hlen = fwohci_arcv_swap(fp, len); 2766 if (hlen == 0) 2767 /* XXX need reset */ 2768 goto out; 2769 if (hlen < 0) { 2770 dbch->pdb_tr = db_tr; 2771 dbch->buf_offset = - dbch->buf_offset; 2772 /* sanity check */ 2773 if (resCount != 0) 2774 printf("resCount = %d !?\n", 2775 resCount); 2776 /* XXX clear pdb_tr */ 2777 goto out; 2778 } 2779 offset = 0; 2780 nvec = 0; 2781 } 2782 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2783 if (plen < 0) { 2784 /* minimum header size + trailer 2785 = sizeof(fw_pkt) so this shouldn't happens */ 2786 printf("plen(%d) is negative! offset=%d\n", 2787 plen, offset); 2788 /* XXX clear pdb_tr */ 2789 goto out; 2790 } 2791 if (plen > 0) { 2792 len -= plen; 2793 if (len < 0) { 2794 dbch->pdb_tr = db_tr; 2795 if (firewire_debug) 2796 printf("splitted payload\n"); 2797 /* sanity check */ 2798 if (resCount != 0) 2799 printf("resCount = %d !?\n", 2800 resCount); 2801 /* XXX clear pdb_tr */ 2802 goto out; 2803 } 2804 vec[nvec].iov_base = ld; 2805 vec[nvec].iov_len = plen; 2806 nvec ++; 2807 ld += plen; 2808 } 2809 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2810 if (nvec == 0) 2811 printf("nvec == 0\n"); 2812 2813/* DMA result-code will be written at the tail of packet */ 2814#if BYTE_ORDER == BIG_ENDIAN 2815 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2816#else 2817 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2818#endif 2819#if 0 2820 printf("plen: %d, stat %x\n", 2821 plen ,stat); 2822#endif 2823 spd = (stat >> 5) & 0x3; 2824 stat &= 0x1f; 2825 switch(stat){ 2826 case FWOHCIEV_ACKPEND: 2827#if 0 2828 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2829#endif 2830 /* fall through */ 2831 case FWOHCIEV_ACKCOMPL: 2832 { 2833 struct fw_rcv_buf rb; 2834 2835 if ((vec[nvec-1].iov_len -= 2836 sizeof(struct fwohci_trailer)) == 0) 2837 nvec--; 2838 rb.fc = &sc->fc; 2839 rb.vec = vec; 2840 rb.nvec = nvec; 2841 rb.spd = spd; 2842 fw_rcv(&rb); 2843 break; 2844 } 2845 case FWOHCIEV_BUSRST: 2846 if (sc->fc.status != FWBUSRESET) 2847 printf("got BUSRST packet!?\n"); 2848 break; 2849 default: 2850 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2851#if 0 /* XXX */ 2852 goto out; 2853#endif 2854 break; 2855 } 2856 pcnt ++; 2857 if (dbch->pdb_tr != NULL) { 2858 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2859 dbch->pdb_tr = NULL; 2860 } 2861 2862 } 2863out: 2864 if (resCount == 0) { 2865 /* done on this buffer */ 2866 if (dbch->pdb_tr == NULL) { 2867 fwohci_arcv_free_buf(dbch, db_tr); 2868 dbch->buf_offset = 0; 2869 } else 2870 if (dbch->pdb_tr != db_tr) 2871 printf("pdb_tr != db_tr\n"); 2872 db_tr = STAILQ_NEXT(db_tr, link); 2873 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2874 >> OHCI_STATUS_SHIFT; 2875 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2876 & OHCI_COUNT_MASK; 2877 /* XXX check buffer overrun */ 2878 dbch->top = db_tr; 2879 } else { 2880 dbch->buf_offset = dbch->xferq.psize - resCount; 2881 break; 2882 } 2883 /* XXX make sure DMA is not dead */ 2884 } 2885#if 0 2886 if (pcnt < 1) 2887 printf("fwohci_arcv: no packets\n"); 2888#endif 2889 splx(s); 2890} 2891