fwohci.c revision 119155
1322014Snp/* 2322014Snp * Copyright (c) 2003 Hidetoshi Shimokawa 3322014Snp * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4322014Snp * All rights reserved. 5322014Snp * 6322014Snp * Redistribution and use in source and binary forms, with or without 7322014Snp * modification, are permitted provided that the following conditions 8322014Snp * are met: 9322014Snp * 1. Redistributions of source code must retain the above copyright 10322014Snp * notice, this list of conditions and the following disclaimer. 11322014Snp * 2. Redistributions in binary form must reproduce the above copyright 12322014Snp * notice, this list of conditions and the following disclaimer in the 13322014Snp * documentation and/or other materials provided with the distribution. 14322014Snp * 3. All advertising materials mentioning features or use of this software 15322014Snp * must display the acknowledgement as bellow: 16322014Snp * 17322014Snp * This product includes software developed by K. Kobayashi and H. Shimokawa 18322014Snp * 19322014Snp * 4. The name of the author may not be used to endorse or promote products 20322014Snp * derived from this software without specific prior written permission. 21322014Snp * 22322014Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23322014Snp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24322014Snp * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25322014Snp * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26322014Snp * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27322014Snp * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28322014Snp * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29322014Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30322014Snp * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31322014Snp * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32322014Snp * POSSIBILITY OF SUCH DAMAGE. 33322014Snp * 34322014Snp * $FreeBSD: head/sys/dev/firewire/fwohci.c 119155 2003-08-20 03:11:37Z simokawa $ 35322014Snp * 36322014Snp */ 37322014Snp 38322014Snp#define ATRQ_CH 0 39322014Snp#define ATRS_CH 1 40322014Snp#define ARRQ_CH 2 41322014Snp#define ARRS_CH 3 42322014Snp#define ITX_CH 4 43322014Snp#define IRX_CH 0x24 44322014Snp 45322014Snp#include <sys/param.h> 46322014Snp#include <sys/systm.h> 47322014Snp#include <sys/mbuf.h> 48322014Snp#include <sys/malloc.h> 49322014Snp#include <sys/sockio.h> 50322014Snp#include <sys/bus.h> 51322014Snp#include <sys/kernel.h> 52322014Snp#include <sys/conf.h> 53322014Snp#include <sys/endian.h> 54322014Snp 55322014Snp#include <machine/bus.h> 56322014Snp 57322014Snp#if __FreeBSD_version < 500000 58322014Snp#include <machine/clock.h> /* for DELAY() */ 59322014Snp#endif 60322014Snp 61322014Snp#include <dev/firewire/firewire.h> 62322014Snp#include <dev/firewire/firewirereg.h> 63322014Snp#include <dev/firewire/fwdma.h> 64322014Snp#include <dev/firewire/fwohcireg.h> 65322014Snp#include <dev/firewire/fwohcivar.h> 66322014Snp#include <dev/firewire/firewire_phy.h> 67322014Snp 68322014Snp#undef OHCI_DEBUG 69322014Snp 70322014Snpstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71322014Snp "STOR","LOAD","NOP ","STOP",}; 72322014Snp 73322014Snpstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74322014Snp "UNDEF","REG","SYS","DEV"}; 75322014Snpstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76322014Snpchar fwohcicode[32][0x20]={ 77322014Snp "No stat","Undef","long","miss Ack err", 78322014Snp "underrun","overrun","desc err", "data read err", 79322014Snp "data write err","bus reset","timeout","tcode err", 80322014Snp "Undef","Undef","unknown event","flushed", 81322014Snp "Undef","ack complete","ack pend","Undef", 82322014Snp "ack busy_X","ack busy_A","ack busy_B","Undef", 83322014Snp "Undef","Undef","Undef","ack tardy", 84322014Snp "Undef","ack data_err","ack type_err",""}; 85322014Snp 86322014Snp#define MAX_SPEED 3 87322014Snpextern char linkspeed[][0x10]; 88322014Snpu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89322014Snp 90322014Snpstatic struct tcode_info tinfo[] = { 91322014Snp/* hdr_len block flag*/ 92322014Snp/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93322014Snp/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94322014Snp/* 2 WRES */ {12, FWTI_RES}, 95322014Snp/* 3 XXX */ { 0, 0}, 96322014Snp/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97322014Snp/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98322014Snp/* 6 RRESQ */ {16, FWTI_RES}, 99322014Snp/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100322014Snp/* 8 CYCS */ { 0, 0}, 101322014Snp/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102322014Snp/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103322014Snp/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104322014Snp/* c XXX */ { 0, 0}, 105322014Snp/* d XXX */ { 0, 0}, 106322014Snp/* e PHY */ {12, FWTI_REQ}, 107322014Snp/* f XXX */ { 0, 0} 108322014Snp}; 109322014Snp 110322014Snp#define OHCI_WRITE_SIGMASK 0xffff0000 111322014Snp#define OHCI_READ_SIGMASK 0xffff0000 112322014Snp 113322014Snp#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114322014Snp#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115322014Snp 116322014Snpstatic void fwohci_ibr __P((struct firewire_comm *)); 117322014Snpstatic void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118322014Snpstatic void fwohci_db_free __P((struct fwohci_dbch *)); 119322014Snpstatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120322014Snpstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121322014Snpstatic void fwohci_start_atq __P((struct firewire_comm *)); 122322014Snpstatic void fwohci_start_ats __P((struct firewire_comm *)); 123322014Snpstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124322014Snpstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125322014Snpstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126322014Snpstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127322014Snpstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128322014Snpstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 129322014Snpstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 130322014Snp#if BYTE_ORDER == BIG_ENDIAN 131322014Snpstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132322014Snp#endif 133322014Snpstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134322014Snpstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 135322014Snpstatic void fwohci_timeout __P((void *)); 136322014Snpstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 137322014Snp 138322014Snpstatic int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139322014Snpstatic int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140322014Snpstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 141322014Snpstatic void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142322014Snpstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143322014Snpstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144322014Snpstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145322014Snpstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146322014Snpvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147322014Snp#if FWOHCI_TASKQUEUE 148322014Snpstatic void fwohci_complete(void *, int); 149322014Snp#endif 150322014Snp 151322014Snp/* 152322014Snp * memory allocated for DMA programs 153322014Snp */ 154322014Snp#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155322014Snp 156322014Snp#define NDB FWMAXQUEUE 157322014Snp 158322014Snp#define OHCI_VERSION 0x00 159322014Snp#define OHCI_ATRETRY 0x08 160322014Snp#define OHCI_CROMHDR 0x18 161322014Snp#define OHCI_BUS_OPT 0x20 162322014Snp#define OHCI_BUSIRMC (1 << 31) 163322014Snp#define OHCI_BUSCMC (1 << 30) 164322014Snp#define OHCI_BUSISC (1 << 29) 165322014Snp#define OHCI_BUSBMC (1 << 28) 166322014Snp#define OHCI_BUSPMC (1 << 27) 167322014Snp#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 168322014Snp OHCI_BUSBMC | OHCI_BUSPMC 169322014Snp 170322014Snp#define OHCI_EUID_HI 0x24 171322014Snp#define OHCI_EUID_LO 0x28 172322014Snp 173322014Snp#define OHCI_CROMPTR 0x34 174322014Snp#define OHCI_HCCCTL 0x50 175322014Snp#define OHCI_HCCCTLCLR 0x54 176322014Snp#define OHCI_AREQHI 0x100 177322014Snp#define OHCI_AREQHICLR 0x104 178322014Snp#define OHCI_AREQLO 0x108 179322014Snp#define OHCI_AREQLOCLR 0x10c 180322014Snp#define OHCI_PREQHI 0x110 181322014Snp#define OHCI_PREQHICLR 0x114 182322014Snp#define OHCI_PREQLO 0x118 183322014Snp#define OHCI_PREQLOCLR 0x11c 184322014Snp#define OHCI_PREQUPPER 0x120 185322014Snp 186322014Snp#define OHCI_SID_BUF 0x64 187322014Snp#define OHCI_SID_CNT 0x68 188322014Snp#define OHCI_SID_ERR (1 << 31) 189322014Snp#define OHCI_SID_CNT_MASK 0xffc 190322014Snp 191322014Snp#define OHCI_IT_STAT 0x90 192322014Snp#define OHCI_IT_STATCLR 0x94 193322014Snp#define OHCI_IT_MASK 0x98 194322014Snp#define OHCI_IT_MASKCLR 0x9c 195322014Snp 196322014Snp#define OHCI_IR_STAT 0xa0 197322014Snp#define OHCI_IR_STATCLR 0xa4 198322014Snp#define OHCI_IR_MASK 0xa8 199322014Snp#define OHCI_IR_MASKCLR 0xac 200322014Snp 201322014Snp#define OHCI_LNKCTL 0xe0 202322014Snp#define OHCI_LNKCTLCLR 0xe4 203322014Snp 204322014Snp#define OHCI_PHYACCESS 0xec 205322014Snp#define OHCI_CYCLETIMER 0xf0 206322014Snp 207322014Snp#define OHCI_DMACTL(off) (off) 208322014Snp#define OHCI_DMACTLCLR(off) (off + 4) 209322014Snp#define OHCI_DMACMD(off) (off + 0xc) 210322014Snp#define OHCI_DMAMATCH(off) (off + 0x10) 211322014Snp 212322014Snp#define OHCI_ATQOFF 0x180 213322014Snp#define OHCI_ATQCTL OHCI_ATQOFF 214322014Snp#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 215322014Snp#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 216322014Snp#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 217322014Snp 218322014Snp#define OHCI_ATSOFF 0x1a0 219322014Snp#define OHCI_ATSCTL OHCI_ATSOFF 220322014Snp#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 221322014Snp#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 222322014Snp#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 223322014Snp 224322014Snp#define OHCI_ARQOFF 0x1c0 225322014Snp#define OHCI_ARQCTL OHCI_ARQOFF 226322014Snp#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 227322014Snp#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 228322014Snp#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 229322014Snp 230322014Snp#define OHCI_ARSOFF 0x1e0 231322014Snp#define OHCI_ARSCTL OHCI_ARSOFF 232322014Snp#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 233322014Snp#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 234322014Snp#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 235322014Snp 236322014Snp#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 237322014Snp#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 238322014Snp#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 239322014Snp#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 240322014Snp 241322014Snp#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 242322014Snp#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 243322014Snp#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 244322014Snp#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 245322014Snp#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 246322014Snp 247322014Snpd_ioctl_t fwohci_ioctl; 248322014Snp 249322014Snp/* 250322014Snp * Communication with PHY device 251322014Snp */ 252322014Snpstatic u_int32_t 253322014Snpfwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 254322014Snp{ 255322014Snp u_int32_t fun; 256322014Snp 257322014Snp addr &= 0xf; 258322014Snp data &= 0xff; 259322014Snp 260322014Snp fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 261322014Snp OWRITE(sc, OHCI_PHYACCESS, fun); 262322014Snp DELAY(100); 263322014Snp 264322014Snp return(fwphy_rddata( sc, addr)); 265322014Snp} 266322014Snp 267322014Snpstatic u_int32_t 268322014Snpfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 269322014Snp{ 270322014Snp struct fwohci_softc *sc = (struct fwohci_softc *)fc; 271322014Snp int i; 272322014Snp u_int32_t bm; 273322014Snp 274322014Snp#define OHCI_CSR_DATA 0x0c 275322014Snp#define OHCI_CSR_COMP 0x10 276322014Snp#define OHCI_CSR_CONT 0x14 277322014Snp#define OHCI_BUS_MANAGER_ID 0 278322014Snp 279322014Snp OWRITE(sc, OHCI_CSR_DATA, node); 280322014Snp OWRITE(sc, OHCI_CSR_COMP, 0x3f); 281322014Snp OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 282322014Snp for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 283322014Snp DELAY(10); 284322014Snp bm = OREAD(sc, OHCI_CSR_DATA); 285322014Snp if((bm & 0x3f) == 0x3f) 286322014Snp bm = node; 287322014Snp if (bootverbose) 288322014Snp device_printf(sc->fc.dev, 289322014Snp "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 290322014Snp 291322014Snp return(bm); 292322014Snp} 293322014Snp 294322014Snpstatic u_int32_t 295322014Snpfwphy_rddata(struct fwohci_softc *sc, u_int addr) 296322014Snp{ 297322014Snp u_int32_t fun, stat; 298322014Snp u_int i, retry = 0; 299322014Snp 300322014Snp addr &= 0xf; 301322014Snp#define MAX_RETRY 100 302322014Snpagain: 303322014Snp OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 304322014Snp fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 305322014Snp OWRITE(sc, OHCI_PHYACCESS, fun); 306322014Snp for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 307322014Snp fun = OREAD(sc, OHCI_PHYACCESS); 308322014Snp if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 309322014Snp break; 310322014Snp DELAY(100); 311322014Snp } 312322014Snp if(i >= MAX_RETRY) { 313322014Snp if (bootverbose) 314322014Snp device_printf(sc->fc.dev, "phy read failed(1).\n"); 315322014Snp if (++retry < MAX_RETRY) { 316322014Snp DELAY(100); 317322014Snp goto again; 318322014Snp } 319322014Snp } 320322014Snp /* Make sure that SCLK is started */ 321322014Snp stat = OREAD(sc, FWOHCI_INTSTAT); 322322014Snp if ((stat & OHCI_INT_REG_FAIL) != 0 || 323322014Snp ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 324322014Snp if (bootverbose) 325322014Snp device_printf(sc->fc.dev, "phy read failed(2).\n"); 326322014Snp if (++retry < MAX_RETRY) { 327322014Snp DELAY(100); 328322014Snp goto again; 329322014Snp } 330322014Snp } 331322014Snp if (bootverbose || retry >= MAX_RETRY) 332322014Snp device_printf(sc->fc.dev, 333322014Snp "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 334322014Snp#undef MAX_RETRY 335322014Snp return((fun >> PHYDEV_RDDATA )& 0xff); 336322014Snp} 337322014Snp/* Device specific ioctl. */ 338322014Snpint 339322014Snpfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 340322014Snp{ 341322014Snp struct firewire_softc *sc; 342322014Snp struct fwohci_softc *fc; 343322014Snp int unit = DEV2UNIT(dev); 344322014Snp int err = 0; 345322014Snp struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 346322014Snp u_int32_t *dmach = (u_int32_t *) data; 347322014Snp 348322014Snp sc = devclass_get_softc(firewire_devclass, unit); 349322014Snp if(sc == NULL){ 350322014Snp return(EINVAL); 351322014Snp } 352322014Snp fc = (struct fwohci_softc *)sc->fc; 353322014Snp 354322014Snp if (!data) 355322014Snp return(EINVAL); 356322014Snp 357322014Snp switch (cmd) { 358322014Snp case FWOHCI_WRREG: 359322014Snp#define OHCI_MAX_REG 0x800 360322014Snp if(reg->addr <= OHCI_MAX_REG){ 361322014Snp OWRITE(fc, reg->addr, reg->data); 362322014Snp reg->data = OREAD(fc, reg->addr); 363322014Snp }else{ 364322014Snp err = EINVAL; 365322014Snp } 366322014Snp break; 367322014Snp case FWOHCI_RDREG: 368322014Snp if(reg->addr <= OHCI_MAX_REG){ 369322014Snp reg->data = OREAD(fc, reg->addr); 370322014Snp }else{ 371322014Snp err = EINVAL; 372322014Snp } 373322014Snp break; 374322014Snp/* Read DMA descriptors for debug */ 375322014Snp case DUMPDMA: 376322014Snp if(*dmach <= OHCI_MAX_DMA_CH ){ 377322014Snp dump_dma(fc, *dmach); 378322014Snp dump_db(fc, *dmach); 379322014Snp }else{ 380322014Snp err = EINVAL; 381322014Snp } 382322014Snp break; 383322014Snp/* Read/Write Phy registers */ 384322014Snp#define OHCI_MAX_PHY_REG 0xf 385322014Snp case FWOHCI_RDPHYREG: 386322014Snp if (reg->addr <= OHCI_MAX_PHY_REG) 387322014Snp reg->data = fwphy_rddata(fc, reg->addr); 388322014Snp else 389322014Snp err = EINVAL; 390322014Snp break; 391322014Snp case FWOHCI_WRPHYREG: 392322014Snp if (reg->addr <= OHCI_MAX_PHY_REG) 393322014Snp reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 394322014Snp else 395322014Snp err = EINVAL; 396322014Snp break; 397322014Snp default: 398322014Snp err = EINVAL; 399322014Snp break; 400322014Snp } 401322014Snp return err; 402322014Snp} 403322014Snp 404322014Snpstatic int 405322014Snpfwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406322014Snp{ 407322014Snp u_int32_t reg, reg2; 408322014Snp int e1394a = 1; 409322014Snp/* 410322014Snp * probe PHY parameters 411322014Snp * 0. to prove PHY version, whether compliance of 1394a. 412322014Snp * 1. to probe maximum speed supported by the PHY and 413322014Snp * number of port supported by core-logic. 414322014Snp * It is not actually available port on your PC . 415322014Snp */ 416322014Snp OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417322014Snp reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418322014Snp 419322014Snp if((reg >> 5) != 7 ){ 420322014Snp sc->fc.mode &= ~FWPHYASYST; 421322014Snp sc->fc.nport = reg & FW_PHY_NP; 422322014Snp sc->fc.speed = reg & FW_PHY_SPD >> 6; 423322014Snp if (sc->fc.speed > MAX_SPEED) { 424322014Snp device_printf(dev, "invalid speed %d (fixed to %d).\n", 425322014Snp sc->fc.speed, MAX_SPEED); 426322014Snp sc->fc.speed = MAX_SPEED; 427322014Snp } 428322014Snp device_printf(dev, 429322014Snp "Phy 1394 only %s, %d ports.\n", 430322014Snp linkspeed[sc->fc.speed], sc->fc.nport); 431322014Snp }else{ 432322014Snp reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433322014Snp sc->fc.mode |= FWPHYASYST; 434322014Snp sc->fc.nport = reg & FW_PHY_NP; 435322014Snp sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436322014Snp if (sc->fc.speed > MAX_SPEED) { 437322014Snp device_printf(dev, "invalid speed %d (fixed to %d).\n", 438322014Snp sc->fc.speed, MAX_SPEED); 439322014Snp sc->fc.speed = MAX_SPEED; 440322014Snp } 441322014Snp device_printf(dev, 442322014Snp "Phy 1394a available %s, %d ports.\n", 443322014Snp linkspeed[sc->fc.speed], sc->fc.nport); 444322014Snp 445322014Snp /* check programPhyEnable */ 446322014Snp reg2 = fwphy_rddata(sc, 5); 447322014Snp#if 0 448322014Snp if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449322014Snp#else /* XXX force to enable 1394a */ 450322014Snp if (e1394a) { 451322014Snp#endif 452322014Snp if (bootverbose) 453322014Snp device_printf(dev, 454322014Snp "Enable 1394a Enhancements\n"); 455322014Snp /* enable EAA EMC */ 456322014Snp reg2 |= 0x03; 457322014Snp /* set aPhyEnhanceEnable */ 458322014Snp OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459322014Snp OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460322014Snp } else { 461322014Snp /* for safe */ 462322014Snp reg2 &= ~0x83; 463322014Snp } 464322014Snp reg2 = fwphy_wrdata(sc, 5, reg2); 465322014Snp } 466322014Snp 467322014Snp reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468322014Snp if((reg >> 5) == 7 ){ 469322014Snp reg = fwphy_rddata(sc, 4); 470322014Snp reg |= 1 << 6; 471322014Snp fwphy_wrdata(sc, 4, reg); 472322014Snp reg = fwphy_rddata(sc, 4); 473322014Snp } 474322014Snp return 0; 475322014Snp} 476322014Snp 477322014Snp 478322014Snpvoid 479322014Snpfwohci_reset(struct fwohci_softc *sc, device_t dev) 480322014Snp{ 481322014Snp int i, max_rec, speed; 482322014Snp u_int32_t reg, reg2; 483322014Snp struct fwohcidb_tr *db_tr; 484322014Snp 485322014Snp /* Disable interrupt */ 486322014Snp OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487322014Snp 488322014Snp /* Now stopping all DMA channel */ 489322014Snp OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490322014Snp OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491322014Snp OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492322014Snp OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493322014Snp 494322014Snp OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495322014Snp for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496322014Snp OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497322014Snp OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498322014Snp } 499322014Snp 500322014Snp /* FLUSH FIFO and reset Transmitter/Reciever */ 501322014Snp OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502322014Snp if (bootverbose) 503322014Snp device_printf(dev, "resetting OHCI..."); 504322014Snp i = 0; 505322014Snp while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506322014Snp if (i++ > 100) break; 507322014Snp DELAY(1000); 508322014Snp } 509322014Snp if (bootverbose) 510322014Snp printf("done (loop=%d)\n", i); 511322014Snp 512322014Snp /* Probe phy */ 513322014Snp fwohci_probe_phy(sc, dev); 514322014Snp 515322014Snp /* Probe link */ 516322014Snp reg = OREAD(sc, OHCI_BUS_OPT); 517322014Snp reg2 = reg | OHCI_BUSFNC; 518322014Snp max_rec = (reg & 0x0000f000) >> 12; 519322014Snp speed = (reg & 0x00000007); 520322014Snp device_printf(dev, "Link %s, max_rec %d bytes.\n", 521322014Snp linkspeed[speed], MAXREC(max_rec)); 522322014Snp /* XXX fix max_rec */ 523322014Snp sc->fc.maxrec = sc->fc.speed + 8; 524322014Snp if (max_rec != sc->fc.maxrec) { 525322014Snp reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526322014Snp device_printf(dev, "max_rec %d -> %d\n", 527322014Snp MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528322014Snp } 529322014Snp if (bootverbose) 530322014Snp device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531322014Snp OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 555 /* AT Retries */ 556 OWRITE(sc, FWOHCI_RETRY, 557 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559 560 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562 sc->atrq.bottom = sc->atrq.top; 563 sc->atrs.bottom = sc->atrs.top; 564 565 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567 db_tr->xfer = NULL; 568 } 569 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571 db_tr->xfer = NULL; 572 } 573 574 575 /* Enable interrupt */ 576 OWRITE(sc, FWOHCI_INTMASK, 577 OHCI_INT_ERR | OHCI_INT_PHY_SID 578 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581 fwohci_set_intr(&sc->fc, 1); 582 583} 584 585int 586fwohci_init(struct fwohci_softc *sc, device_t dev) 587{ 588 int i; 589 u_int32_t reg; 590 u_int8_t ui[8]; 591 592#if FWOHCI_TASKQUEUE 593 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594#endif 595 596 reg = OREAD(sc, OHCI_VERSION); 597 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 598 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 599 600 if (((reg>>16) & 0xff) < 1) { 601 device_printf(dev, "invalid OHCI version\n"); 602 return (ENXIO); 603 } 604 605/* Available Isochrounous DMA channel probe */ 606 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 607 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 608 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 609 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 610 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 611 for (i = 0; i < 0x20; i++) 612 if ((reg & (1 << i)) == 0) 613 break; 614 sc->fc.nisodma = i; 615 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 616 if (i == 0) 617 return (ENXIO); 618 619 sc->fc.arq = &sc->arrq.xferq; 620 sc->fc.ars = &sc->arrs.xferq; 621 sc->fc.atq = &sc->atrq.xferq; 622 sc->fc.ats = &sc->atrs.xferq; 623 624 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 625 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 626 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628 629 sc->arrq.xferq.start = NULL; 630 sc->arrs.xferq.start = NULL; 631 sc->atrq.xferq.start = fwohci_start_atq; 632 sc->atrs.xferq.start = fwohci_start_ats; 633 634 sc->arrq.xferq.buf = NULL; 635 sc->arrs.xferq.buf = NULL; 636 sc->atrq.xferq.buf = NULL; 637 sc->atrs.xferq.buf = NULL; 638 639 sc->arrq.xferq.dmach = -1; 640 sc->arrs.xferq.dmach = -1; 641 sc->atrq.xferq.dmach = -1; 642 sc->atrs.xferq.dmach = -1; 643 644 sc->arrq.ndesc = 1; 645 sc->arrs.ndesc = 1; 646 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 647 sc->atrs.ndesc = 2; 648 649 sc->arrq.ndb = NDB; 650 sc->arrs.ndb = NDB / 2; 651 sc->atrq.ndb = NDB; 652 sc->atrs.ndb = NDB / 2; 653 654 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 655 sc->fc.it[i] = &sc->it[i].xferq; 656 sc->fc.ir[i] = &sc->ir[i].xferq; 657 sc->it[i].xferq.dmach = i; 658 sc->ir[i].xferq.dmach = i; 659 sc->it[i].ndb = 0; 660 sc->ir[i].ndb = 0; 661 } 662 663 sc->fc.tcode = tinfo; 664 sc->fc.dev = dev; 665 666 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 667 &sc->crom_dma, BUS_DMA_WAITOK); 668 if(sc->fc.config_rom == NULL){ 669 device_printf(dev, "config_rom alloc failed."); 670 return ENOMEM; 671 } 672 673#if 0 674 bzero(&sc->fc.config_rom[0], CROMSIZE); 675 sc->fc.config_rom[1] = 0x31333934; 676 sc->fc.config_rom[2] = 0xf000a002; 677 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 678 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 679 sc->fc.config_rom[5] = 0; 680 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 681 682 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 683#endif 684 685 686/* SID recieve buffer must allign 2^11 */ 687#define OHCI_SIDSIZE (1 << 11) 688 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 689 &sc->sid_dma, BUS_DMA_WAITOK); 690 if (sc->sid_buf == NULL) { 691 device_printf(dev, "sid_buf alloc failed."); 692 return ENOMEM; 693 } 694 695 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 696 &sc->dummy_dma, BUS_DMA_WAITOK); 697 698 if (sc->dummy_dma.v_addr == NULL) { 699 device_printf(dev, "dummy_dma alloc failed."); 700 return ENOMEM; 701 } 702 703 fwohci_db_init(sc, &sc->arrq); 704 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 705 return ENOMEM; 706 707 fwohci_db_init(sc, &sc->arrs); 708 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 709 return ENOMEM; 710 711 fwohci_db_init(sc, &sc->atrq); 712 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 713 return ENOMEM; 714 715 fwohci_db_init(sc, &sc->atrs); 716 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 717 return ENOMEM; 718 719 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 720 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 721 for( i = 0 ; i < 8 ; i ++) 722 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 723 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 724 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 725 726 sc->fc.ioctl = fwohci_ioctl; 727 sc->fc.cyctimer = fwohci_cyctimer; 728 sc->fc.set_bmr = fwohci_set_bus_manager; 729 sc->fc.ibr = fwohci_ibr; 730 sc->fc.irx_enable = fwohci_irx_enable; 731 sc->fc.irx_disable = fwohci_irx_disable; 732 733 sc->fc.itx_enable = fwohci_itxbuf_enable; 734 sc->fc.itx_disable = fwohci_itx_disable; 735#if BYTE_ORDER == BIG_ENDIAN 736 sc->fc.irx_post = fwohci_irx_post; 737#else 738 sc->fc.irx_post = NULL; 739#endif 740 sc->fc.itx_post = NULL; 741 sc->fc.timeout = fwohci_timeout; 742 sc->fc.poll = fwohci_poll; 743 sc->fc.set_intr = fwohci_set_intr; 744 745 sc->intmask = sc->irstat = sc->itstat = 0; 746 747 fw_init(&sc->fc); 748 fwohci_reset(sc, dev); 749 750 return 0; 751} 752 753void 754fwohci_timeout(void *arg) 755{ 756 struct fwohci_softc *sc; 757 758 sc = (struct fwohci_softc *)arg; 759} 760 761u_int32_t 762fwohci_cyctimer(struct firewire_comm *fc) 763{ 764 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 765 return(OREAD(sc, OHCI_CYCLETIMER)); 766} 767 768int 769fwohci_detach(struct fwohci_softc *sc, device_t dev) 770{ 771 int i; 772 773 if (sc->sid_buf != NULL) 774 fwdma_free(&sc->fc, &sc->sid_dma); 775 if (sc->fc.config_rom != NULL) 776 fwdma_free(&sc->fc, &sc->crom_dma); 777 778 fwohci_db_free(&sc->arrq); 779 fwohci_db_free(&sc->arrs); 780 781 fwohci_db_free(&sc->atrq); 782 fwohci_db_free(&sc->atrs); 783 784 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 785 fwohci_db_free(&sc->it[i]); 786 fwohci_db_free(&sc->ir[i]); 787 } 788 789 return 0; 790} 791 792#define LAST_DB(dbtr, db) do { \ 793 struct fwohcidb_tr *_dbtr = (dbtr); \ 794 int _cnt = _dbtr->dbcnt; \ 795 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 796} while (0) 797 798static void 799fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 800{ 801 struct fwohcidb_tr *db_tr; 802 volatile struct fwohcidb *db; 803 bus_dma_segment_t *s; 804 int i; 805 806 db_tr = (struct fwohcidb_tr *)arg; 807 db = &db_tr->db[db_tr->dbcnt]; 808 if (error) { 809 if (firewire_debug || error != EFBIG) 810 printf("fwohci_execute_db: error=%d\n", error); 811 return; 812 } 813 for (i = 0; i < nseg; i++) { 814 s = &segs[i]; 815 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 816 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 817 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 818 db++; 819 db_tr->dbcnt++; 820 } 821} 822 823static void 824fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 825 bus_size_t size, int error) 826{ 827 fwohci_execute_db(arg, segs, nseg, error); 828} 829 830static void 831fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 832{ 833 int i, s; 834 int tcode, hdr_len, pl_off, pl_len; 835 int fsegment = -1; 836 u_int32_t off; 837 struct fw_xfer *xfer; 838 struct fw_pkt *fp; 839 volatile struct fwohci_txpkthdr *ohcifp; 840 struct fwohcidb_tr *db_tr; 841 volatile struct fwohcidb *db; 842 volatile u_int32_t *ld; 843 struct tcode_info *info; 844 static int maxdesc=0; 845 846 if(&sc->atrq == dbch){ 847 off = OHCI_ATQOFF; 848 }else if(&sc->atrs == dbch){ 849 off = OHCI_ATSOFF; 850 }else{ 851 return; 852 } 853 854 if (dbch->flags & FWOHCI_DBCH_FULL) 855 return; 856 857 s = splfw(); 858 db_tr = dbch->top; 859txloop: 860 xfer = STAILQ_FIRST(&dbch->xferq.q); 861 if(xfer == NULL){ 862 goto kick; 863 } 864 if(dbch->xferq.queued == 0 ){ 865 device_printf(sc->fc.dev, "TX queue empty\n"); 866 } 867 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 868 db_tr->xfer = xfer; 869 xfer->state = FWXF_START; 870 871 fp = (struct fw_pkt *)xfer->send.buf; 872 tcode = fp->mode.common.tcode; 873 874 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 875 info = &tinfo[tcode]; 876 hdr_len = pl_off = info->hdr_len; 877 878 ld = &ohcifp->mode.ld[0]; 879 ld[0] = ld[1] = ld[2] = ld[3] = 0; 880 for( i = 0 ; i < pl_off ; i+= 4) 881 ld[i/4] = fp->mode.ld[i/4]; 882 883 ohcifp->mode.common.spd = xfer->spd & 0x7; 884 if (tcode == FWTCODE_STREAM ){ 885 hdr_len = 8; 886 ohcifp->mode.stream.len = fp->mode.stream.len; 887 } else if (tcode == FWTCODE_PHY) { 888 hdr_len = 12; 889 ld[1] = fp->mode.ld[1]; 890 ld[2] = fp->mode.ld[2]; 891 ohcifp->mode.common.spd = 0; 892 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 893 } else { 894 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 895 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 896 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 897 } 898 db = &db_tr->db[0]; 899 FWOHCI_DMA_WRITE(db->db.desc.cmd, 900 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 901 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 902 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 903/* Specify bound timer of asy. responce */ 904 if(&sc->atrs == dbch){ 905 FWOHCI_DMA_WRITE(db->db.desc.res, 906 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 907 } 908#if BYTE_ORDER == BIG_ENDIAN 909 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 910 hdr_len = 12; 911 for (i = 0; i < hdr_len/4; i ++) 912 FWOHCI_DMA_WRITE(ld[i], ld[i]); 913#endif 914 915again: 916 db_tr->dbcnt = 2; 917 db = &db_tr->db[db_tr->dbcnt]; 918 pl_len = xfer->send.len - pl_off; 919 if (pl_len > 0) { 920 int err; 921 /* handle payload */ 922 if (xfer->mbuf == NULL) { 923 caddr_t pl_addr; 924 925 pl_addr = xfer->send.buf + pl_off; 926 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 927 pl_addr, pl_len, 928 fwohci_execute_db, db_tr, 929 /*flags*/0); 930 } else { 931 /* XXX we can handle only 6 (=8-2) mbuf chains */ 932 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 933 xfer->mbuf, 934 fwohci_execute_db2, db_tr, 935 /* flags */0); 936 if (err == EFBIG) { 937 struct mbuf *m0; 938 939 if (firewire_debug) 940 device_printf(sc->fc.dev, "EFBIG.\n"); 941 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 942 if (m0 != NULL) { 943 m_copydata(xfer->mbuf, 0, 944 xfer->mbuf->m_pkthdr.len, 945 mtod(m0, caddr_t)); 946 m0->m_len = m0->m_pkthdr.len = 947 xfer->mbuf->m_pkthdr.len; 948 m_freem(xfer->mbuf); 949 xfer->mbuf = m0; 950 goto again; 951 } 952 device_printf(sc->fc.dev, "m_getcl failed.\n"); 953 } 954 } 955 if (err) 956 printf("dmamap_load: err=%d\n", err); 957 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 958 BUS_DMASYNC_PREWRITE); 959#if 0 /* OHCI_OUTPUT_MODE == 0 */ 960 for (i = 2; i < db_tr->dbcnt; i++) 961 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 962 OHCI_OUTPUT_MORE); 963#endif 964 } 965 if (maxdesc < db_tr->dbcnt) { 966 maxdesc = db_tr->dbcnt; 967 if (bootverbose) 968 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 969 } 970 /* last db */ 971 LAST_DB(db_tr, db); 972 FWOHCI_DMA_SET(db->db.desc.cmd, 973 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 974 FWOHCI_DMA_WRITE(db->db.desc.depend, 975 STAILQ_NEXT(db_tr, link)->bus_addr); 976 977 if(fsegment == -1 ) 978 fsegment = db_tr->dbcnt; 979 if (dbch->pdb_tr != NULL) { 980 LAST_DB(dbch->pdb_tr, db); 981 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 982 } 983 dbch->pdb_tr = db_tr; 984 db_tr = STAILQ_NEXT(db_tr, link); 985 if(db_tr != dbch->bottom){ 986 goto txloop; 987 } else { 988 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 989 dbch->flags |= FWOHCI_DBCH_FULL; 990 } 991kick: 992 /* kick asy q */ 993 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 994 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 995 996 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 997 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 998 } else { 999 if (bootverbose) 1000 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1001 OREAD(sc, OHCI_DMACTL(off))); 1002 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1003 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1004 dbch->xferq.flag |= FWXFERQ_RUNNING; 1005 } 1006 1007 dbch->top = db_tr; 1008 splx(s); 1009 return; 1010} 1011 1012static void 1013fwohci_start_atq(struct firewire_comm *fc) 1014{ 1015 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1016 fwohci_start( sc, &(sc->atrq)); 1017 return; 1018} 1019 1020static void 1021fwohci_start_ats(struct firewire_comm *fc) 1022{ 1023 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1024 fwohci_start( sc, &(sc->atrs)); 1025 return; 1026} 1027 1028void 1029fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1030{ 1031 int s, ch, err = 0; 1032 struct fwohcidb_tr *tr; 1033 volatile struct fwohcidb *db; 1034 struct fw_xfer *xfer; 1035 u_int32_t off; 1036 u_int stat, status; 1037 int packets; 1038 struct firewire_comm *fc = (struct firewire_comm *)sc; 1039 1040 if(&sc->atrq == dbch){ 1041 off = OHCI_ATQOFF; 1042 ch = ATRQ_CH; 1043 }else if(&sc->atrs == dbch){ 1044 off = OHCI_ATSOFF; 1045 ch = ATRS_CH; 1046 }else{ 1047 return; 1048 } 1049 s = splfw(); 1050 tr = dbch->bottom; 1051 packets = 0; 1052 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1053 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1054 while(dbch->xferq.queued > 0){ 1055 LAST_DB(tr, db); 1056 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1057 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1058 if (fc->status != FWBUSRESET) 1059 /* maybe out of order?? */ 1060 goto out; 1061 } 1062 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1063 BUS_DMASYNC_POSTWRITE); 1064 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1065#if 1 1066 if (firewire_debug) 1067 dump_db(sc, ch); 1068#endif 1069 if(status & OHCI_CNTL_DMA_DEAD) { 1070 /* Stop DMA */ 1071 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1072 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1073 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1074 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1075 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1076 } 1077 stat = status & FWOHCIEV_MASK; 1078 switch(stat){ 1079 case FWOHCIEV_ACKPEND: 1080 case FWOHCIEV_ACKCOMPL: 1081 err = 0; 1082 break; 1083 case FWOHCIEV_ACKBSA: 1084 case FWOHCIEV_ACKBSB: 1085 case FWOHCIEV_ACKBSX: 1086 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1087 err = EBUSY; 1088 break; 1089 case FWOHCIEV_FLUSHED: 1090 case FWOHCIEV_ACKTARD: 1091 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1092 err = EAGAIN; 1093 break; 1094 case FWOHCIEV_MISSACK: 1095 case FWOHCIEV_UNDRRUN: 1096 case FWOHCIEV_OVRRUN: 1097 case FWOHCIEV_DESCERR: 1098 case FWOHCIEV_DTRDERR: 1099 case FWOHCIEV_TIMEOUT: 1100 case FWOHCIEV_TCODERR: 1101 case FWOHCIEV_UNKNOWN: 1102 case FWOHCIEV_ACKDERR: 1103 case FWOHCIEV_ACKTERR: 1104 default: 1105 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1106 stat, fwohcicode[stat]); 1107 err = EINVAL; 1108 break; 1109 } 1110 if (tr->xfer != NULL) { 1111 xfer = tr->xfer; 1112 if (xfer->state == FWXF_RCVD) { 1113 if (firewire_debug) 1114 printf("already rcvd\n"); 1115 fw_xfer_done(xfer); 1116 } else { 1117 xfer->state = FWXF_SENT; 1118 if (err == EBUSY && fc->status != FWBUSRESET) { 1119 xfer->state = FWXF_BUSY; 1120 xfer->resp = err; 1121 if (xfer->retry_req != NULL) 1122 xfer->retry_req(xfer); 1123 else { 1124 xfer->recv.len = 0; 1125 fw_xfer_done(xfer); 1126 } 1127 } else if (stat != FWOHCIEV_ACKPEND) { 1128 if (stat != FWOHCIEV_ACKCOMPL) 1129 xfer->state = FWXF_SENTERR; 1130 xfer->resp = err; 1131 xfer->recv.len = 0; 1132 fw_xfer_done(xfer); 1133 } 1134 } 1135 /* 1136 * The watchdog timer takes care of split 1137 * transcation timeout for ACKPEND case. 1138 */ 1139 } else { 1140 printf("this shouldn't happen\n"); 1141 } 1142 dbch->xferq.queued --; 1143 tr->xfer = NULL; 1144 1145 packets ++; 1146 tr = STAILQ_NEXT(tr, link); 1147 dbch->bottom = tr; 1148 if (dbch->bottom == dbch->top) { 1149 /* we reaches the end of context program */ 1150 if (firewire_debug && dbch->xferq.queued > 0) 1151 printf("queued > 0\n"); 1152 break; 1153 } 1154 } 1155out: 1156 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1157 printf("make free slot\n"); 1158 dbch->flags &= ~FWOHCI_DBCH_FULL; 1159 fwohci_start(sc, dbch); 1160 } 1161 splx(s); 1162} 1163 1164static void 1165fwohci_db_free(struct fwohci_dbch *dbch) 1166{ 1167 struct fwohcidb_tr *db_tr; 1168 int idb; 1169 1170 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1171 return; 1172 1173 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1174 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1175 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1176 db_tr->buf != NULL) { 1177 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1178 db_tr->buf, dbch->xferq.psize); 1179 db_tr->buf = NULL; 1180 } else if (db_tr->dma_map != NULL) 1181 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1182 } 1183 dbch->ndb = 0; 1184 db_tr = STAILQ_FIRST(&dbch->db_trq); 1185 fwdma_free_multiseg(dbch->am); 1186 free(db_tr, M_FW); 1187 STAILQ_INIT(&dbch->db_trq); 1188 dbch->flags &= ~FWOHCI_DBCH_INIT; 1189} 1190 1191static void 1192fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1193{ 1194 int idb; 1195 struct fwohcidb_tr *db_tr; 1196 1197 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1198 goto out; 1199 1200 /* create dma_tag for buffers */ 1201#define MAX_REQCOUNT 0xffff 1202 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1203 /*alignment*/ 1, /*boundary*/ 0, 1204 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1205 /*highaddr*/ BUS_SPACE_MAXADDR, 1206 /*filter*/NULL, /*filterarg*/NULL, 1207 /*maxsize*/ dbch->xferq.psize, 1208 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1209 /*maxsegsz*/ MAX_REQCOUNT, 1210 /*flags*/ 0, 1211#if __FreeBSD_version >= 501102 1212 /*lockfunc*/busdma_lock_mutex, 1213 /*lockarg*/&Giant, 1214#endif 1215 &dbch->dmat)) 1216 return; 1217 1218 /* allocate DB entries and attach one to each DMA channels */ 1219 /* DB entry must start at 16 bytes bounary. */ 1220 STAILQ_INIT(&dbch->db_trq); 1221 db_tr = (struct fwohcidb_tr *) 1222 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1223 M_FW, M_WAITOK | M_ZERO); 1224 if(db_tr == NULL){ 1225 printf("fwohci_db_init: malloc(1) failed\n"); 1226 return; 1227 } 1228 1229#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1230 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1231 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1232 if (dbch->am == NULL) { 1233 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1234 return; 1235 } 1236 /* Attach DB to DMA ch. */ 1237 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1238 db_tr->dbcnt = 0; 1239 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1240 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1241 /* create dmamap for buffers */ 1242 /* XXX do we need 4bytes alignment tag? */ 1243 /* XXX don't alloc dma_map for AR */ 1244 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1245 printf("bus_dmamap_create failed\n"); 1246 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1247 fwohci_db_free(dbch); 1248 return; 1249 } 1250 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1251 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1252 if (idb % dbch->xferq.bnpacket == 0) 1253 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1254 ].start = (caddr_t)db_tr; 1255 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1256 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1257 ].end = (caddr_t)db_tr; 1258 } 1259 db_tr++; 1260 } 1261 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1262 = STAILQ_FIRST(&dbch->db_trq); 1263out: 1264 dbch->xferq.queued = 0; 1265 dbch->pdb_tr = NULL; 1266 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1267 dbch->bottom = dbch->top; 1268 dbch->flags = FWOHCI_DBCH_INIT; 1269} 1270 1271static int 1272fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1273{ 1274 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1275 int sleepch; 1276 1277 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1278 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1279 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1280 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1281 /* XXX we cannot free buffers until the DMA really stops */ 1282 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1283 fwohci_db_free(&sc->it[dmach]); 1284 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1285 return 0; 1286} 1287 1288static int 1289fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1290{ 1291 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1292 int sleepch; 1293 1294 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1295 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1296 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1297 /* XXX we cannot free buffers until the DMA really stops */ 1298 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1299 fwohci_db_free(&sc->ir[dmach]); 1300 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1301 return 0; 1302} 1303 1304#if BYTE_ORDER == BIG_ENDIAN 1305static void 1306fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1307{ 1308 qld[0] = FWOHCI_DMA_READ(qld[0]); 1309 return; 1310} 1311#endif 1312 1313static int 1314fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1315{ 1316 int err = 0; 1317 int idb, z, i, dmach = 0, ldesc; 1318 u_int32_t off = NULL; 1319 struct fwohcidb_tr *db_tr; 1320 volatile struct fwohcidb *db; 1321 1322 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1323 err = EINVAL; 1324 return err; 1325 } 1326 z = dbch->ndesc; 1327 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1328 if( &sc->it[dmach] == dbch){ 1329 off = OHCI_ITOFF(dmach); 1330 break; 1331 } 1332 } 1333 if(off == NULL){ 1334 err = EINVAL; 1335 return err; 1336 } 1337 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1338 return err; 1339 dbch->xferq.flag |= FWXFERQ_RUNNING; 1340 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1341 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1342 } 1343 db_tr = dbch->top; 1344 for (idb = 0; idb < dbch->ndb; idb ++) { 1345 fwohci_add_tx_buf(dbch, db_tr, idb); 1346 if(STAILQ_NEXT(db_tr, link) == NULL){ 1347 break; 1348 } 1349 db = db_tr->db; 1350 ldesc = db_tr->dbcnt - 1; 1351 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1352 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1353 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1354 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1355 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1356 FWOHCI_DMA_SET( 1357 db[ldesc].db.desc.cmd, 1358 OHCI_INTERRUPT_ALWAYS); 1359 /* OHCI 1.1 and above */ 1360 FWOHCI_DMA_SET( 1361 db[0].db.desc.cmd, 1362 OHCI_INTERRUPT_ALWAYS); 1363 } 1364 } 1365 db_tr = STAILQ_NEXT(db_tr, link); 1366 } 1367 FWOHCI_DMA_CLEAR( 1368 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1369 return err; 1370} 1371 1372static int 1373fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1374{ 1375 int err = 0; 1376 int idb, z, i, dmach = 0, ldesc; 1377 u_int32_t off = NULL; 1378 struct fwohcidb_tr *db_tr; 1379 volatile struct fwohcidb *db; 1380 1381 z = dbch->ndesc; 1382 if(&sc->arrq == dbch){ 1383 off = OHCI_ARQOFF; 1384 }else if(&sc->arrs == dbch){ 1385 off = OHCI_ARSOFF; 1386 }else{ 1387 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1388 if( &sc->ir[dmach] == dbch){ 1389 off = OHCI_IROFF(dmach); 1390 break; 1391 } 1392 } 1393 } 1394 if(off == NULL){ 1395 err = EINVAL; 1396 return err; 1397 } 1398 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1399 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1400 return err; 1401 }else{ 1402 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1403 err = EBUSY; 1404 return err; 1405 } 1406 } 1407 dbch->xferq.flag |= FWXFERQ_RUNNING; 1408 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1409 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1410 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1411 } 1412 db_tr = dbch->top; 1413 for (idb = 0; idb < dbch->ndb; idb ++) { 1414 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1415 if (STAILQ_NEXT(db_tr, link) == NULL) 1416 break; 1417 db = db_tr->db; 1418 ldesc = db_tr->dbcnt - 1; 1419 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1420 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1421 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1422 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1423 FWOHCI_DMA_SET( 1424 db[ldesc].db.desc.cmd, 1425 OHCI_INTERRUPT_ALWAYS); 1426 FWOHCI_DMA_CLEAR( 1427 db[ldesc].db.desc.depend, 1428 0xf); 1429 } 1430 } 1431 db_tr = STAILQ_NEXT(db_tr, link); 1432 } 1433 FWOHCI_DMA_CLEAR( 1434 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1435 dbch->buf_offset = 0; 1436 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1437 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1438 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1439 return err; 1440 }else{ 1441 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1442 } 1443 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1444 return err; 1445} 1446 1447static int 1448fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1449{ 1450 int sec, cycle, cycle_match; 1451 1452 cycle = cycle_now & 0x1fff; 1453 sec = cycle_now >> 13; 1454#define CYCLE_MOD 0x10 1455#if 1 1456#define CYCLE_DELAY 8 /* min delay to start DMA */ 1457#else 1458#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1459#endif 1460 cycle = cycle + CYCLE_DELAY; 1461 if (cycle >= 8000) { 1462 sec ++; 1463 cycle -= 8000; 1464 } 1465 cycle = roundup2(cycle, CYCLE_MOD); 1466 if (cycle >= 8000) { 1467 sec ++; 1468 if (cycle == 8000) 1469 cycle = 0; 1470 else 1471 cycle = CYCLE_MOD; 1472 } 1473 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1474 1475 return(cycle_match); 1476} 1477 1478static int 1479fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1480{ 1481 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1482 int err = 0; 1483 unsigned short tag, ich; 1484 struct fwohci_dbch *dbch; 1485 int cycle_match, cycle_now, s, ldesc; 1486 u_int32_t stat; 1487 struct fw_bulkxfer *first, *chunk, *prev; 1488 struct fw_xferq *it; 1489 1490 dbch = &sc->it[dmach]; 1491 it = &dbch->xferq; 1492 1493 tag = (it->flag >> 6) & 3; 1494 ich = it->flag & 0x3f; 1495 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1496 dbch->ndb = it->bnpacket * it->bnchunk; 1497 dbch->ndesc = 3; 1498 fwohci_db_init(sc, dbch); 1499 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1500 return ENOMEM; 1501 err = fwohci_tx_enable(sc, dbch); 1502 } 1503 if(err) 1504 return err; 1505 1506 ldesc = dbch->ndesc - 1; 1507 s = splfw(); 1508 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1509 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1510 volatile struct fwohcidb *db; 1511 1512 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1513 BUS_DMASYNC_PREWRITE); 1514 fwohci_txbufdb(sc, dmach, chunk); 1515 if (prev != NULL) { 1516 db = ((struct fwohcidb_tr *)(prev->end))->db; 1517#if 0 /* XXX necessary? */ 1518 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1519 OHCI_BRANCH_ALWAYS); 1520#endif 1521#if 0 /* if bulkxfer->npacket changes */ 1522 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1523 ((struct fwohcidb_tr *) 1524 (chunk->start))->bus_addr | dbch->ndesc; 1525#else 1526 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1527 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1528#endif 1529 } 1530 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1531 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1532 prev = chunk; 1533 } 1534 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1535 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1536 splx(s); 1537 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1538 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1539 printf("stat 0x%x\n", stat); 1540 1541 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1542 return 0; 1543 1544#if 0 1545 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1546#endif 1547 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1548 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1549 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1550 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1551 1552 first = STAILQ_FIRST(&it->stdma); 1553 OWRITE(sc, OHCI_ITCMD(dmach), 1554 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1555 if (firewire_debug) { 1556 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1557#if 1 1558 dump_dma(sc, ITX_CH + dmach); 1559#endif 1560 } 1561 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1562#if 1 1563 /* Don't start until all chunks are buffered */ 1564 if (STAILQ_FIRST(&it->stfree) != NULL) 1565 goto out; 1566#endif 1567#if 1 1568 /* Clear cycle match counter bits */ 1569 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1570 1571 /* 2bit second + 13bit cycle */ 1572 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1573 cycle_match = fwohci_next_cycle(fc, cycle_now); 1574 1575 OWRITE(sc, OHCI_ITCTL(dmach), 1576 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1577 | OHCI_CNTL_DMA_RUN); 1578#else 1579 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1580#endif 1581 if (firewire_debug) { 1582 printf("cycle_match: 0x%04x->0x%04x\n", 1583 cycle_now, cycle_match); 1584 dump_dma(sc, ITX_CH + dmach); 1585 dump_db(sc, ITX_CH + dmach); 1586 } 1587 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1588 device_printf(sc->fc.dev, 1589 "IT DMA underrun (0x%08x)\n", stat); 1590 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1591 } 1592out: 1593 return err; 1594} 1595 1596static int 1597fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1598{ 1599 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1600 int err = 0, s, ldesc; 1601 unsigned short tag, ich; 1602 u_int32_t stat; 1603 struct fwohci_dbch *dbch; 1604 struct fwohcidb_tr *db_tr; 1605 struct fw_bulkxfer *first, *prev, *chunk; 1606 struct fw_xferq *ir; 1607 1608 dbch = &sc->ir[dmach]; 1609 ir = &dbch->xferq; 1610 1611 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1612 tag = (ir->flag >> 6) & 3; 1613 ich = ir->flag & 0x3f; 1614 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1615 1616 ir->queued = 0; 1617 dbch->ndb = ir->bnpacket * ir->bnchunk; 1618 dbch->ndesc = 2; 1619 fwohci_db_init(sc, dbch); 1620 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1621 return ENOMEM; 1622 err = fwohci_rx_enable(sc, dbch); 1623 } 1624 if(err) 1625 return err; 1626 1627 first = STAILQ_FIRST(&ir->stfree); 1628 if (first == NULL) { 1629 device_printf(fc->dev, "IR DMA no free chunk\n"); 1630 return 0; 1631 } 1632 1633 ldesc = dbch->ndesc - 1; 1634 s = splfw(); 1635 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1636 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1637 volatile struct fwohcidb *db; 1638 1639#if 1 /* XXX for if_fwe */ 1640 if (chunk->mbuf != NULL) { 1641 db_tr = (struct fwohcidb_tr *)(chunk->start); 1642 db_tr->dbcnt = 1; 1643 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1644 chunk->mbuf, fwohci_execute_db2, db_tr, 1645 /* flags */0); 1646 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1647 OHCI_UPDATE | OHCI_INPUT_LAST | 1648 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1649 } 1650#endif 1651 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1652 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1653 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1654 if (prev != NULL) { 1655 db = ((struct fwohcidb_tr *)(prev->end))->db; 1656 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1657 } 1658 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1659 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1660 prev = chunk; 1661 } 1662 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1663 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1664 splx(s); 1665 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1666 if (stat & OHCI_CNTL_DMA_ACTIVE) 1667 return 0; 1668 if (stat & OHCI_CNTL_DMA_RUN) { 1669 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1670 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1671 } 1672 1673 if (firewire_debug) 1674 printf("start IR DMA 0x%x\n", stat); 1675 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1676 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1677 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1678 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1679 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1680 OWRITE(sc, OHCI_IRCMD(dmach), 1681 ((struct fwohcidb_tr *)(first->start))->bus_addr 1682 | dbch->ndesc); 1683 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1684 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1685#if 0 1686 dump_db(sc, IRX_CH + dmach); 1687#endif 1688 return err; 1689} 1690 1691int 1692fwohci_stop(struct fwohci_softc *sc, device_t dev) 1693{ 1694 u_int i; 1695 1696/* Now stopping all DMA channel */ 1697 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1698 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1699 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1700 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1701 1702 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1703 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1704 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1705 } 1706 1707/* FLUSH FIFO and reset Transmitter/Reciever */ 1708 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1709 1710/* Stop interrupt */ 1711 OWRITE(sc, FWOHCI_INTMASKCLR, 1712 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1713 | OHCI_INT_PHY_INT 1714 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1715 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1716 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1717 | OHCI_INT_PHY_BUS_R); 1718 1719 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1720 fw_drain_txq(&sc->fc); 1721 1722/* XXX Link down? Bus reset? */ 1723 return 0; 1724} 1725 1726int 1727fwohci_resume(struct fwohci_softc *sc, device_t dev) 1728{ 1729 int i; 1730 struct fw_xferq *ir; 1731 struct fw_bulkxfer *chunk; 1732 1733 fwohci_reset(sc, dev); 1734 /* XXX resume isochronus receive automatically. (how about TX?) */ 1735 for(i = 0; i < sc->fc.nisodma; i ++) { 1736 ir = &sc->ir[i].xferq; 1737 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1738 device_printf(sc->fc.dev, 1739 "resume iso receive ch: %d\n", i); 1740 ir->flag &= ~FWXFERQ_RUNNING; 1741 /* requeue stdma to stfree */ 1742 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1743 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1744 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1745 } 1746 sc->fc.irx_enable(&sc->fc, i); 1747 } 1748 } 1749 1750 bus_generic_resume(dev); 1751 sc->fc.ibr(&sc->fc); 1752 return 0; 1753} 1754 1755#define ACK_ALL 1756static void 1757fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1758{ 1759 u_int32_t irstat, itstat; 1760 u_int i; 1761 struct firewire_comm *fc = (struct firewire_comm *)sc; 1762 1763#ifdef OHCI_DEBUG 1764 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1765 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1766 stat & OHCI_INT_EN ? "DMA_EN ":"", 1767 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1768 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1769 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1770 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1771 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1772 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1773 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1774 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1775 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1776 stat & OHCI_INT_PHY_SID ? "SID ":"", 1777 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1778 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1779 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1780 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1781 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1782 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1783 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1784 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1785 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1786 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1787 stat, OREAD(sc, FWOHCI_INTMASK) 1788 ); 1789#endif 1790/* Bus reset */ 1791 if(stat & OHCI_INT_PHY_BUS_R ){ 1792 if (fc->status == FWBUSRESET) 1793 goto busresetout; 1794 /* Disable bus reset interrupt until sid recv. */ 1795 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1796 1797 device_printf(fc->dev, "BUS reset\n"); 1798 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1799 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1800 1801 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1802 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1803 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1804 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1805 1806#ifndef ACK_ALL 1807 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1808#endif 1809 fw_busreset(fc); 1810 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1811 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1812 } 1813busresetout: 1814 if((stat & OHCI_INT_DMA_IR )){ 1815#ifndef ACK_ALL 1816 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1817#endif 1818#if __FreeBSD_version >= 500000 1819 irstat = atomic_readandclear_int(&sc->irstat); 1820#else 1821 irstat = sc->irstat; 1822 sc->irstat = 0; 1823#endif 1824 for(i = 0; i < fc->nisodma ; i++){ 1825 struct fwohci_dbch *dbch; 1826 1827 if((irstat & (1 << i)) != 0){ 1828 dbch = &sc->ir[i]; 1829 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1830 device_printf(sc->fc.dev, 1831 "dma(%d) not active\n", i); 1832 continue; 1833 } 1834 fwohci_rbuf_update(sc, i); 1835 } 1836 } 1837 } 1838 if((stat & OHCI_INT_DMA_IT )){ 1839#ifndef ACK_ALL 1840 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1841#endif 1842#if __FreeBSD_version >= 500000 1843 itstat = atomic_readandclear_int(&sc->itstat); 1844#else 1845 itstat = sc->itstat; 1846 sc->itstat = 0; 1847#endif 1848 for(i = 0; i < fc->nisodma ; i++){ 1849 if((itstat & (1 << i)) != 0){ 1850 fwohci_tbuf_update(sc, i); 1851 } 1852 } 1853 } 1854 if((stat & OHCI_INT_DMA_PRRS )){ 1855#ifndef ACK_ALL 1856 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1857#endif 1858#if 0 1859 dump_dma(sc, ARRS_CH); 1860 dump_db(sc, ARRS_CH); 1861#endif 1862 fwohci_arcv(sc, &sc->arrs, count); 1863 } 1864 if((stat & OHCI_INT_DMA_PRRQ )){ 1865#ifndef ACK_ALL 1866 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1867#endif 1868#if 0 1869 dump_dma(sc, ARRQ_CH); 1870 dump_db(sc, ARRQ_CH); 1871#endif 1872 fwohci_arcv(sc, &sc->arrq, count); 1873 } 1874 if(stat & OHCI_INT_PHY_SID){ 1875 u_int32_t *buf, node_id; 1876 int plen; 1877 1878#ifndef ACK_ALL 1879 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1880#endif 1881 /* Enable bus reset interrupt */ 1882 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1883 /* Allow async. request to us */ 1884 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1885 /* XXX insecure ?? */ 1886 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1887 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1888 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1889 /* Set ATRetries register */ 1890 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1891/* 1892** Checking whether the node is root or not. If root, turn on 1893** cycle master. 1894*/ 1895 node_id = OREAD(sc, FWOHCI_NODEID); 1896 plen = OREAD(sc, OHCI_SID_CNT); 1897 1898 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1899 node_id, (plen >> 16) & 0xff); 1900 if (!(node_id & OHCI_NODE_VALID)) { 1901 printf("Bus reset failure\n"); 1902 goto sidout; 1903 } 1904 if (node_id & OHCI_NODE_ROOT) { 1905 printf("CYCLEMASTER mode\n"); 1906 OWRITE(sc, OHCI_LNKCTL, 1907 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1908 } else { 1909 printf("non CYCLEMASTER mode\n"); 1910 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1911 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1912 } 1913 fc->nodeid = node_id & 0x3f; 1914 1915 if (plen & OHCI_SID_ERR) { 1916 device_printf(fc->dev, "SID Error\n"); 1917 goto sidout; 1918 } 1919 plen &= OHCI_SID_CNT_MASK; 1920 if (plen < 4 || plen > OHCI_SIDSIZE) { 1921 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1922 goto sidout; 1923 } 1924 plen -= 4; /* chop control info */ 1925 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1926 if (buf == NULL) { 1927 device_printf(fc->dev, "malloc failed\n"); 1928 goto sidout; 1929 } 1930 for (i = 0; i < plen / 4; i ++) 1931 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1932#if 1 1933 /* pending all pre-bus_reset packets */ 1934 fwohci_txd(sc, &sc->atrq); 1935 fwohci_txd(sc, &sc->atrs); 1936 fwohci_arcv(sc, &sc->arrs, -1); 1937 fwohci_arcv(sc, &sc->arrq, -1); 1938 fw_drain_txq(fc); 1939#endif 1940 fw_sidrcv(fc, buf, plen); 1941 free(buf, M_FW); 1942 } 1943sidout: 1944 if((stat & OHCI_INT_DMA_ATRQ )){ 1945#ifndef ACK_ALL 1946 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1947#endif 1948 fwohci_txd(sc, &(sc->atrq)); 1949 } 1950 if((stat & OHCI_INT_DMA_ATRS )){ 1951#ifndef ACK_ALL 1952 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1953#endif 1954 fwohci_txd(sc, &(sc->atrs)); 1955 } 1956 if((stat & OHCI_INT_PW_ERR )){ 1957#ifndef ACK_ALL 1958 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1959#endif 1960 device_printf(fc->dev, "posted write error\n"); 1961 } 1962 if((stat & OHCI_INT_ERR )){ 1963#ifndef ACK_ALL 1964 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1965#endif 1966 device_printf(fc->dev, "unrecoverable error\n"); 1967 } 1968 if((stat & OHCI_INT_PHY_INT)) { 1969#ifndef ACK_ALL 1970 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1971#endif 1972 device_printf(fc->dev, "phy int\n"); 1973 } 1974 1975 return; 1976} 1977 1978#if FWOHCI_TASKQUEUE 1979static void 1980fwohci_complete(void *arg, int pending) 1981{ 1982 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1983 u_int32_t stat; 1984 1985again: 1986 stat = atomic_readandclear_int(&sc->intstat); 1987 if (stat) 1988 fwohci_intr_body(sc, stat, -1); 1989 else 1990 return; 1991 goto again; 1992} 1993#endif 1994 1995static u_int32_t 1996fwochi_check_stat(struct fwohci_softc *sc) 1997{ 1998 u_int32_t stat, irstat, itstat; 1999 2000 stat = OREAD(sc, FWOHCI_INTSTAT); 2001 if (stat == 0xffffffff) { 2002 device_printf(sc->fc.dev, 2003 "device physically ejected?\n"); 2004 return(stat); 2005 } 2006#ifdef ACK_ALL 2007 if (stat) 2008 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2009#endif 2010 if (stat & OHCI_INT_DMA_IR) { 2011 irstat = OREAD(sc, OHCI_IR_STAT); 2012 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2013 atomic_set_int(&sc->irstat, irstat); 2014 } 2015 if (stat & OHCI_INT_DMA_IT) { 2016 itstat = OREAD(sc, OHCI_IT_STAT); 2017 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2018 atomic_set_int(&sc->itstat, itstat); 2019 } 2020 return(stat); 2021} 2022 2023void 2024fwohci_intr(void *arg) 2025{ 2026 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2027 u_int32_t stat; 2028#if !FWOHCI_TASKQUEUE 2029 u_int32_t bus_reset = 0; 2030#endif 2031 2032 if (!(sc->intmask & OHCI_INT_EN)) { 2033 /* polling mode */ 2034 return; 2035 } 2036 2037#if !FWOHCI_TASKQUEUE 2038again: 2039#endif 2040 stat = fwochi_check_stat(sc); 2041 if (stat == 0 || stat == 0xffffffff) 2042 return; 2043#if FWOHCI_TASKQUEUE 2044 atomic_set_int(&sc->intstat, stat); 2045 /* XXX mask bus reset intr. during bus reset phase */ 2046 if (stat) 2047 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2048#else 2049 /* We cannot clear bus reset event during bus reset phase */ 2050 if ((stat & ~bus_reset) == 0) 2051 return; 2052 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2053 fwohci_intr_body(sc, stat, -1); 2054 goto again; 2055#endif 2056} 2057 2058void 2059fwohci_poll(struct firewire_comm *fc, int quick, int count) 2060{ 2061 int s; 2062 u_int32_t stat; 2063 struct fwohci_softc *sc; 2064 2065 2066 sc = (struct fwohci_softc *)fc; 2067 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2068 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2069 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2070#if 0 2071 if (!quick) { 2072#else 2073 if (1) { 2074#endif 2075 stat = fwochi_check_stat(sc); 2076 if (stat == 0 || stat == 0xffffffff) 2077 return; 2078 } 2079 s = splfw(); 2080 fwohci_intr_body(sc, stat, count); 2081 splx(s); 2082} 2083 2084static void 2085fwohci_set_intr(struct firewire_comm *fc, int enable) 2086{ 2087 struct fwohci_softc *sc; 2088 2089 sc = (struct fwohci_softc *)fc; 2090 if (bootverbose) 2091 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2092 if (enable) { 2093 sc->intmask |= OHCI_INT_EN; 2094 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2095 } else { 2096 sc->intmask &= ~OHCI_INT_EN; 2097 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2098 } 2099} 2100 2101static void 2102fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2103{ 2104 struct firewire_comm *fc = &sc->fc; 2105 volatile struct fwohcidb *db; 2106 struct fw_bulkxfer *chunk; 2107 struct fw_xferq *it; 2108 u_int32_t stat, count; 2109 int s, w=0, ldesc; 2110 2111 it = fc->it[dmach]; 2112 ldesc = sc->it[dmach].ndesc - 1; 2113 s = splfw(); /* unnecessary ? */ 2114 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2115 if (firewire_debug) 2116 dump_db(sc, ITX_CH + dmach); 2117 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2118 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2119 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2120 >> OHCI_STATUS_SHIFT; 2121 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2122 /* timestamp */ 2123 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2124 & OHCI_COUNT_MASK; 2125 if (stat == 0) 2126 break; 2127 STAILQ_REMOVE_HEAD(&it->stdma, link); 2128 switch (stat & FWOHCIEV_MASK){ 2129 case FWOHCIEV_ACKCOMPL: 2130#if 0 2131 device_printf(fc->dev, "0x%08x\n", count); 2132#endif 2133 break; 2134 default: 2135 device_printf(fc->dev, 2136 "Isochronous transmit err %02x(%s)\n", 2137 stat, fwohcicode[stat & 0x1f]); 2138 } 2139 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2140 w++; 2141 } 2142 splx(s); 2143 if (w) 2144 wakeup(it); 2145} 2146 2147static void 2148fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2149{ 2150 struct firewire_comm *fc = &sc->fc; 2151 volatile struct fwohcidb_tr *db_tr; 2152 struct fw_bulkxfer *chunk; 2153 struct fw_xferq *ir; 2154 u_int32_t stat; 2155 int s, w=0, ldesc; 2156 2157 ir = fc->ir[dmach]; 2158 ldesc = sc->ir[dmach].ndesc - 1; 2159#if 0 2160 dump_db(sc, dmach); 2161#endif 2162 s = splfw(); 2163 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2164 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2165 db_tr = (struct fwohcidb_tr *)chunk->end; 2166 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2167 >> OHCI_STATUS_SHIFT; 2168 if (stat == 0) 2169 break; 2170 2171 if (chunk->mbuf != NULL) { 2172 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2173 BUS_DMASYNC_POSTREAD); 2174 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2175 } else if (ir->buf != NULL) { 2176 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2177 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2178 } else { 2179 /* XXX */ 2180 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2181 } 2182 2183 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2184 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2185 switch (stat & FWOHCIEV_MASK) { 2186 case FWOHCIEV_ACKCOMPL: 2187 chunk->resp = 0; 2188 break; 2189 default: 2190 chunk->resp = EINVAL; 2191 device_printf(fc->dev, 2192 "Isochronous receive err %02x(%s)\n", 2193 stat, fwohcicode[stat & 0x1f]); 2194 } 2195 w++; 2196 } 2197 splx(s); 2198 if (w) { 2199 if (ir->flag & FWXFERQ_HANDLER) 2200 ir->hand(ir); 2201 else 2202 wakeup(ir); 2203 } 2204} 2205 2206void 2207dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2208{ 2209 u_int32_t off, cntl, stat, cmd, match; 2210 2211 if(ch == 0){ 2212 off = OHCI_ATQOFF; 2213 }else if(ch == 1){ 2214 off = OHCI_ATSOFF; 2215 }else if(ch == 2){ 2216 off = OHCI_ARQOFF; 2217 }else if(ch == 3){ 2218 off = OHCI_ARSOFF; 2219 }else if(ch < IRX_CH){ 2220 off = OHCI_ITCTL(ch - ITX_CH); 2221 }else{ 2222 off = OHCI_IRCTL(ch - IRX_CH); 2223 } 2224 cntl = stat = OREAD(sc, off); 2225 cmd = OREAD(sc, off + 0xc); 2226 match = OREAD(sc, off + 0x10); 2227 2228 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2229 ch, 2230 cntl, 2231 cmd, 2232 match); 2233 stat &= 0xffff ; 2234 if (stat) { 2235 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2236 ch, 2237 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2238 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2239 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2240 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2241 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2242 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2243 fwohcicode[stat & 0x1f], 2244 stat & 0x1f 2245 ); 2246 }else{ 2247 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2248 } 2249} 2250 2251void 2252dump_db(struct fwohci_softc *sc, u_int32_t ch) 2253{ 2254 struct fwohci_dbch *dbch; 2255 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2256 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2257 int idb, jdb; 2258 u_int32_t cmd, off; 2259 if(ch == 0){ 2260 off = OHCI_ATQOFF; 2261 dbch = &sc->atrq; 2262 }else if(ch == 1){ 2263 off = OHCI_ATSOFF; 2264 dbch = &sc->atrs; 2265 }else if(ch == 2){ 2266 off = OHCI_ARQOFF; 2267 dbch = &sc->arrq; 2268 }else if(ch == 3){ 2269 off = OHCI_ARSOFF; 2270 dbch = &sc->arrs; 2271 }else if(ch < IRX_CH){ 2272 off = OHCI_ITCTL(ch - ITX_CH); 2273 dbch = &sc->it[ch - ITX_CH]; 2274 }else { 2275 off = OHCI_IRCTL(ch - IRX_CH); 2276 dbch = &sc->ir[ch - IRX_CH]; 2277 } 2278 cmd = OREAD(sc, off + 0xc); 2279 2280 if( dbch->ndb == 0 ){ 2281 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2282 return; 2283 } 2284 pp = dbch->top; 2285 prev = pp->db; 2286 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2287 if(pp == NULL){ 2288 curr = NULL; 2289 goto outdb; 2290 } 2291 cp = STAILQ_NEXT(pp, link); 2292 if(cp == NULL){ 2293 curr = NULL; 2294 goto outdb; 2295 } 2296 np = STAILQ_NEXT(cp, link); 2297 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2298 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2299 curr = cp->db; 2300 if(np != NULL){ 2301 next = np->db; 2302 }else{ 2303 next = NULL; 2304 } 2305 goto outdb; 2306 } 2307 } 2308 pp = STAILQ_NEXT(pp, link); 2309 prev = pp->db; 2310 } 2311outdb: 2312 if( curr != NULL){ 2313#if 0 2314 printf("Prev DB %d\n", ch); 2315 print_db(pp, prev, ch, dbch->ndesc); 2316#endif 2317 printf("Current DB %d\n", ch); 2318 print_db(cp, curr, ch, dbch->ndesc); 2319#if 0 2320 printf("Next DB %d\n", ch); 2321 print_db(np, next, ch, dbch->ndesc); 2322#endif 2323 }else{ 2324 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2325 } 2326 return; 2327} 2328 2329void 2330print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2331 u_int32_t ch, u_int32_t max) 2332{ 2333 fwohcireg_t stat; 2334 int i, key; 2335 u_int32_t cmd, res; 2336 2337 if(db == NULL){ 2338 printf("No Descriptor is found\n"); 2339 return; 2340 } 2341 2342 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2343 ch, 2344 "Current", 2345 "OP ", 2346 "KEY", 2347 "INT", 2348 "BR ", 2349 "len", 2350 "Addr", 2351 "Depend", 2352 "Stat", 2353 "Cnt"); 2354 for( i = 0 ; i <= max ; i ++){ 2355 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2356 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2357 key = cmd & OHCI_KEY_MASK; 2358 stat = res >> OHCI_STATUS_SHIFT; 2359#if __FreeBSD_version >= 500000 2360 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2361 (uintmax_t)db_tr->bus_addr, 2362#else 2363 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2364 db_tr->bus_addr, 2365#endif 2366 dbcode[(cmd >> 28) & 0xf], 2367 dbkey[(cmd >> 24) & 0x7], 2368 dbcond[(cmd >> 20) & 0x3], 2369 dbcond[(cmd >> 18) & 0x3], 2370 cmd & OHCI_COUNT_MASK, 2371 FWOHCI_DMA_READ(db[i].db.desc.addr), 2372 FWOHCI_DMA_READ(db[i].db.desc.depend), 2373 stat, 2374 res & OHCI_COUNT_MASK); 2375 if(stat & 0xff00){ 2376 printf(" %s%s%s%s%s%s %s(%x)\n", 2377 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2378 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2379 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2380 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2381 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2382 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2383 fwohcicode[stat & 0x1f], 2384 stat & 0x1f 2385 ); 2386 }else{ 2387 printf(" Nostat\n"); 2388 } 2389 if(key == OHCI_KEY_ST2 ){ 2390 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2391 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2392 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2393 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2394 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2395 } 2396 if(key == OHCI_KEY_DEVICE){ 2397 return; 2398 } 2399 if((cmd & OHCI_BRANCH_MASK) 2400 == OHCI_BRANCH_ALWAYS){ 2401 return; 2402 } 2403 if((cmd & OHCI_CMD_MASK) 2404 == OHCI_OUTPUT_LAST){ 2405 return; 2406 } 2407 if((cmd & OHCI_CMD_MASK) 2408 == OHCI_INPUT_LAST){ 2409 return; 2410 } 2411 if(key == OHCI_KEY_ST2 ){ 2412 i++; 2413 } 2414 } 2415 return; 2416} 2417 2418void 2419fwohci_ibr(struct firewire_comm *fc) 2420{ 2421 struct fwohci_softc *sc; 2422 u_int32_t fun; 2423 2424 device_printf(fc->dev, "Initiate bus reset\n"); 2425 sc = (struct fwohci_softc *)fc; 2426 2427 /* 2428 * Set root hold-off bit so that non cyclemaster capable node 2429 * shouldn't became the root node. 2430 */ 2431#if 1 2432 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2433 fun |= FW_PHY_IBR | FW_PHY_RHB; 2434 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2435#else /* Short bus reset */ 2436 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2437 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2438 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2439#endif 2440} 2441 2442void 2443fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2444{ 2445 struct fwohcidb_tr *db_tr, *fdb_tr; 2446 struct fwohci_dbch *dbch; 2447 volatile struct fwohcidb *db; 2448 struct fw_pkt *fp; 2449 volatile struct fwohci_txpkthdr *ohcifp; 2450 unsigned short chtag; 2451 int idb; 2452 2453 dbch = &sc->it[dmach]; 2454 chtag = sc->it[dmach].xferq.flag & 0xff; 2455 2456 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2457 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2458/* 2459device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2460*/ 2461 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2462 db = db_tr->db; 2463 fp = (struct fw_pkt *)db_tr->buf; 2464 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2465 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2466 ohcifp->mode.common.spd = 0 & 0x7; 2467 ohcifp->mode.stream.len = fp->mode.stream.len; 2468 ohcifp->mode.stream.chtag = chtag; 2469 ohcifp->mode.stream.tcode = 0xa; 2470#if BYTE_ORDER == BIG_ENDIAN 2471 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2472 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2473#endif 2474 2475 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2476 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2477 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2478#if 0 /* if bulkxfer->npackets changes */ 2479 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2480 | OHCI_UPDATE 2481 | OHCI_BRANCH_ALWAYS; 2482 db[0].db.desc.depend = 2483 = db[dbch->ndesc - 1].db.desc.depend 2484 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2485#else 2486 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2487 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2488#endif 2489 bulkxfer->end = (caddr_t)db_tr; 2490 db_tr = STAILQ_NEXT(db_tr, link); 2491 } 2492 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2493 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2494 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2495#if 0 /* if bulkxfer->npackets changes */ 2496 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2497 /* OHCI 1.1 and above */ 2498 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2499#endif 2500/* 2501 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2502 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2503device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2504*/ 2505 return; 2506} 2507 2508static int 2509fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2510 int poffset) 2511{ 2512 volatile struct fwohcidb *db = db_tr->db; 2513 struct fw_xferq *it; 2514 int err = 0; 2515 2516 it = &dbch->xferq; 2517 if(it->buf == 0){ 2518 err = EINVAL; 2519 return err; 2520 } 2521 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2522 db_tr->dbcnt = 3; 2523 2524 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2525 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2526 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2527 bzero((void *)(uintptr_t)(volatile void *) 2528 &db[1].db.immed[0], sizeof(db[1].db.immed)); 2529 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2530 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2531 2532 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2533 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2534#if 1 2535 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2536 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2537#endif 2538 return 0; 2539} 2540 2541int 2542fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2543 int poffset, struct fwdma_alloc *dummy_dma) 2544{ 2545 volatile struct fwohcidb *db = db_tr->db; 2546 struct fw_xferq *ir; 2547 int i, ldesc; 2548 bus_addr_t dbuf[2]; 2549 int dsiz[2]; 2550 2551 ir = &dbch->xferq; 2552 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2553 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2554 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2555 if (db_tr->buf == NULL) 2556 return(ENOMEM); 2557 db_tr->dbcnt = 1; 2558 dsiz[0] = ir->psize; 2559 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2560 BUS_DMASYNC_PREREAD); 2561 } else { 2562 db_tr->dbcnt = 0; 2563 if (dummy_dma != NULL) { 2564 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2565 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2566 } 2567 dsiz[db_tr->dbcnt] = ir->psize; 2568 if (ir->buf != NULL) { 2569 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2570 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2571 } 2572 db_tr->dbcnt++; 2573 } 2574 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2575 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2576 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2577 if (ir->flag & FWXFERQ_STREAM) { 2578 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2579 } 2580 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2581 } 2582 ldesc = db_tr->dbcnt - 1; 2583 if (ir->flag & FWXFERQ_STREAM) { 2584 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2585 } 2586 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2587 return 0; 2588} 2589 2590 2591static int 2592fwohci_arcv_swap(struct fw_pkt *fp, int len) 2593{ 2594 struct fw_pkt *fp0; 2595 u_int32_t ld0; 2596 int slen; 2597#if BYTE_ORDER == BIG_ENDIAN 2598 int i; 2599#endif 2600 2601 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2602#if 0 2603 printf("ld0: x%08x\n", ld0); 2604#endif 2605 fp0 = (struct fw_pkt *)&ld0; 2606 switch (fp0->mode.common.tcode) { 2607 case FWTCODE_RREQQ: 2608 case FWTCODE_WRES: 2609 case FWTCODE_WREQQ: 2610 case FWTCODE_RRESQ: 2611 case FWOHCITCODE_PHY: 2612 slen = 12; 2613 break; 2614 case FWTCODE_RREQB: 2615 case FWTCODE_WREQB: 2616 case FWTCODE_LREQ: 2617 case FWTCODE_RRESB: 2618 case FWTCODE_LRES: 2619 slen = 16; 2620 break; 2621 default: 2622 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2623 return(0); 2624 } 2625 if (slen > len) { 2626 if (firewire_debug) 2627 printf("splitted header\n"); 2628 return(-slen); 2629 } 2630#if BYTE_ORDER == BIG_ENDIAN 2631 for(i = 0; i < slen/4; i ++) 2632 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2633#endif 2634 return(slen); 2635} 2636 2637#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2638static int 2639fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2640{ 2641 int r; 2642 2643 switch(fp->mode.common.tcode){ 2644 case FWTCODE_RREQQ: 2645 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2646 break; 2647 case FWTCODE_WRES: 2648 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2649 break; 2650 case FWTCODE_WREQQ: 2651 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2652 break; 2653 case FWTCODE_RREQB: 2654 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2655 break; 2656 case FWTCODE_RRESQ: 2657 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2658 break; 2659 case FWTCODE_WREQB: 2660 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2661 + sizeof(u_int32_t); 2662 break; 2663 case FWTCODE_LREQ: 2664 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2665 + sizeof(u_int32_t); 2666 break; 2667 case FWTCODE_RRESB: 2668 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2669 + sizeof(u_int32_t); 2670 break; 2671 case FWTCODE_LRES: 2672 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2673 + sizeof(u_int32_t); 2674 break; 2675 case FWOHCITCODE_PHY: 2676 r = 16; 2677 break; 2678 default: 2679 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2680 fp->mode.common.tcode); 2681 r = 0; 2682 } 2683 if (r > dbch->xferq.psize) { 2684 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2685 /* panic ? */ 2686 } 2687 return r; 2688} 2689 2690static void 2691fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2692{ 2693 volatile struct fwohcidb *db = &db_tr->db[0]; 2694 2695 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2696 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2697 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2698 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2699 dbch->bottom = db_tr; 2700} 2701 2702static void 2703fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2704{ 2705 struct fwohcidb_tr *db_tr; 2706 struct iovec vec[2]; 2707 struct fw_pkt pktbuf; 2708 int nvec; 2709 struct fw_pkt *fp; 2710 u_int8_t *ld; 2711 u_int32_t stat, off, status; 2712 u_int spd; 2713 int len, plen, hlen, pcnt, offset; 2714 int s; 2715 caddr_t buf; 2716 int resCount; 2717 2718 if(&sc->arrq == dbch){ 2719 off = OHCI_ARQOFF; 2720 }else if(&sc->arrs == dbch){ 2721 off = OHCI_ARSOFF; 2722 }else{ 2723 return; 2724 } 2725 2726 s = splfw(); 2727 db_tr = dbch->top; 2728 pcnt = 0; 2729 /* XXX we cannot handle a packet which lies in more than two buf */ 2730 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2731 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2732 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2733 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2734#if 0 2735 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2736#endif 2737 while (status & OHCI_CNTL_DMA_ACTIVE) { 2738 len = dbch->xferq.psize - resCount; 2739 ld = (u_int8_t *)db_tr->buf; 2740 if (dbch->pdb_tr == NULL) { 2741 len -= dbch->buf_offset; 2742 ld += dbch->buf_offset; 2743 } 2744 if (len > 0) 2745 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2746 BUS_DMASYNC_POSTREAD); 2747 while (len > 0 ) { 2748 if (count >= 0 && count-- == 0) 2749 goto out; 2750 if(dbch->pdb_tr != NULL){ 2751 /* we have a fragment in previous buffer */ 2752 int rlen; 2753 2754 offset = dbch->buf_offset; 2755 if (offset < 0) 2756 offset = - offset; 2757 buf = dbch->pdb_tr->buf + offset; 2758 rlen = dbch->xferq.psize - offset; 2759 if (firewire_debug) 2760 printf("rlen=%d, offset=%d\n", 2761 rlen, dbch->buf_offset); 2762 if (dbch->buf_offset < 0) { 2763 /* splitted in header, pull up */ 2764 char *p; 2765 2766 p = (char *)&pktbuf; 2767 bcopy(buf, p, rlen); 2768 p += rlen; 2769 /* this must be too long but harmless */ 2770 rlen = sizeof(pktbuf) - rlen; 2771 if (rlen < 0) 2772 printf("why rlen < 0\n"); 2773 bcopy(db_tr->buf, p, rlen); 2774 ld += rlen; 2775 len -= rlen; 2776 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2777 if (hlen < 0) { 2778 printf("hlen < 0 shouldn't happen"); 2779 } 2780 offset = sizeof(pktbuf); 2781 vec[0].iov_base = (char *)&pktbuf; 2782 vec[0].iov_len = offset; 2783 } else { 2784 /* splitted in payload */ 2785 offset = rlen; 2786 vec[0].iov_base = buf; 2787 vec[0].iov_len = rlen; 2788 } 2789 fp=(struct fw_pkt *)vec[0].iov_base; 2790 nvec = 1; 2791 } else { 2792 /* no fragment in previous buffer */ 2793 fp=(struct fw_pkt *)ld; 2794 hlen = fwohci_arcv_swap(fp, len); 2795 if (hlen == 0) 2796 /* XXX need reset */ 2797 goto out; 2798 if (hlen < 0) { 2799 dbch->pdb_tr = db_tr; 2800 dbch->buf_offset = - dbch->buf_offset; 2801 /* sanity check */ 2802 if (resCount != 0) 2803 printf("resCount != 0 !?\n"); 2804 goto out; 2805 } 2806 offset = 0; 2807 nvec = 0; 2808 } 2809 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2810 if (plen < 0) { 2811 /* minimum header size + trailer 2812 = sizeof(fw_pkt) so this shouldn't happens */ 2813 printf("plen is negative! offset=%d\n", offset); 2814 goto out; 2815 } 2816 if (plen > 0) { 2817 len -= plen; 2818 if (len < 0) { 2819 dbch->pdb_tr = db_tr; 2820 if (firewire_debug) 2821 printf("splitted payload\n"); 2822 /* sanity check */ 2823 if (resCount != 0) 2824 printf("resCount != 0 !?\n"); 2825 goto out; 2826 } 2827 vec[nvec].iov_base = ld; 2828 vec[nvec].iov_len = plen; 2829 nvec ++; 2830 ld += plen; 2831 } 2832 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2833 if (nvec == 0) 2834 printf("nvec == 0\n"); 2835 2836/* DMA result-code will be written at the tail of packet */ 2837#if BYTE_ORDER == BIG_ENDIAN 2838 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2839#else 2840 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2841#endif 2842#if 0 2843 printf("plen: %d, stat %x\n", plen ,stat); 2844#endif 2845 spd = (stat >> 5) & 0x3; 2846 stat &= 0x1f; 2847 switch(stat){ 2848 case FWOHCIEV_ACKPEND: 2849#if 0 2850 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2851#endif 2852 /* fall through */ 2853 case FWOHCIEV_ACKCOMPL: 2854 if ((vec[nvec-1].iov_len -= 2855 sizeof(struct fwohci_trailer)) == 0) 2856 nvec--; 2857 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2858 break; 2859 case FWOHCIEV_BUSRST: 2860 if (sc->fc.status != FWBUSRESET) 2861 printf("got BUSRST packet!?\n"); 2862 break; 2863 default: 2864 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2865#if 0 /* XXX */ 2866 goto out; 2867#endif 2868 break; 2869 } 2870 pcnt ++; 2871 if (dbch->pdb_tr != NULL) { 2872 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2873 dbch->pdb_tr = NULL; 2874 } 2875 2876 } 2877out: 2878 if (resCount == 0) { 2879 /* done on this buffer */ 2880 if (dbch->pdb_tr == NULL) { 2881 fwohci_arcv_free_buf(dbch, db_tr); 2882 dbch->buf_offset = 0; 2883 } else 2884 if (dbch->pdb_tr != db_tr) 2885 printf("pdb_tr != db_tr\n"); 2886 db_tr = STAILQ_NEXT(db_tr, link); 2887 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2888 >> OHCI_STATUS_SHIFT; 2889 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2890 & OHCI_COUNT_MASK; 2891 /* XXX check buffer overrun */ 2892 dbch->top = db_tr; 2893 } else { 2894 dbch->buf_offset = dbch->xferq.psize - resCount; 2895 break; 2896 } 2897 /* XXX make sure DMA is not dead */ 2898 } 2899#if 0 2900 if (pcnt < 1) 2901 printf("fwohci_arcv: no packets\n"); 2902#endif 2903 splx(s); 2904} 2905