fwohci.c revision 118416
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 118416 2003-08-04 05:43:02Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#include <dev/firewire/firewire.h> 62#include <dev/firewire/firewirereg.h> 63#include <dev/firewire/fwdma.h> 64#include <dev/firewire/fwohcireg.h> 65#include <dev/firewire/fwohcivar.h> 66#include <dev/firewire/firewire_phy.h> 67 68#undef OHCI_DEBUG 69 70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71 "STOR","LOAD","NOP ","STOP",}; 72 73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74 "UNDEF","REG","SYS","DEV"}; 75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76char fwohcicode[32][0x20]={ 77 "No stat","Undef","long","miss Ack err", 78 "underrun","overrun","desc err", "data read err", 79 "data write err","bus reset","timeout","tcode err", 80 "Undef","Undef","unknown event","flushed", 81 "Undef","ack complete","ack pend","Undef", 82 "ack busy_X","ack busy_A","ack busy_B","Undef", 83 "Undef","Undef","Undef","ack tardy", 84 "Undef","ack data_err","ack type_err",""}; 85 86#define MAX_SPEED 3 87extern char linkspeed[][0x10]; 88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89 90static struct tcode_info tinfo[] = { 91/* hdr_len block flag*/ 92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94/* 2 WRES */ {12, FWTI_RES}, 95/* 3 XXX */ { 0, 0}, 96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98/* 6 RRESQ */ {16, FWTI_RES}, 99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100/* 8 CYCS */ { 0, 0}, 101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104/* c XXX */ { 0, 0}, 105/* d XXX */ { 0, 0}, 106/* e PHY */ {12, FWTI_REQ}, 107/* f XXX */ { 0, 0} 108}; 109 110#define OHCI_WRITE_SIGMASK 0xffff0000 111#define OHCI_READ_SIGMASK 0xffff0000 112 113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115 116static void fwohci_ibr __P((struct firewire_comm *)); 117static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118static void fwohci_db_free __P((struct fwohci_dbch *)); 119static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121static void fwohci_start_atq __P((struct firewire_comm *)); 122static void fwohci_start_ats __P((struct firewire_comm *)); 123static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128static int fwohci_irx_enable __P((struct firewire_comm *, int)); 129static int fwohci_irx_disable __P((struct firewire_comm *, int)); 130#if BYTE_ORDER == BIG_ENDIAN 131static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132#endif 133static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134static int fwohci_itx_disable __P((struct firewire_comm *, int)); 135static void fwohci_timeout __P((void *)); 136static void fwohci_set_intr __P((struct firewire_comm *, int)); 137 138static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140static void dump_db __P((struct fwohci_softc *, u_int32_t)); 141static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147#if FWOHCI_TASKQUEUE 148static void fwohci_complete(void *, int); 149#endif 150 151/* 152 * memory allocated for DMA programs 153 */ 154#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155 156/* #define NDB 1024 */ 157#define NDB FWMAXQUEUE 158#define NDVDB (DVBUF * NDB) 159 160#define OHCI_VERSION 0x00 161#define OHCI_ATRETRY 0x08 162#define OHCI_CROMHDR 0x18 163#define OHCI_BUS_OPT 0x20 164#define OHCI_BUSIRMC (1 << 31) 165#define OHCI_BUSCMC (1 << 30) 166#define OHCI_BUSISC (1 << 29) 167#define OHCI_BUSBMC (1 << 28) 168#define OHCI_BUSPMC (1 << 27) 169#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 170 OHCI_BUSBMC | OHCI_BUSPMC 171 172#define OHCI_EUID_HI 0x24 173#define OHCI_EUID_LO 0x28 174 175#define OHCI_CROMPTR 0x34 176#define OHCI_HCCCTL 0x50 177#define OHCI_HCCCTLCLR 0x54 178#define OHCI_AREQHI 0x100 179#define OHCI_AREQHICLR 0x104 180#define OHCI_AREQLO 0x108 181#define OHCI_AREQLOCLR 0x10c 182#define OHCI_PREQHI 0x110 183#define OHCI_PREQHICLR 0x114 184#define OHCI_PREQLO 0x118 185#define OHCI_PREQLOCLR 0x11c 186#define OHCI_PREQUPPER 0x120 187 188#define OHCI_SID_BUF 0x64 189#define OHCI_SID_CNT 0x68 190#define OHCI_SID_ERR (1 << 31) 191#define OHCI_SID_CNT_MASK 0xffc 192 193#define OHCI_IT_STAT 0x90 194#define OHCI_IT_STATCLR 0x94 195#define OHCI_IT_MASK 0x98 196#define OHCI_IT_MASKCLR 0x9c 197 198#define OHCI_IR_STAT 0xa0 199#define OHCI_IR_STATCLR 0xa4 200#define OHCI_IR_MASK 0xa8 201#define OHCI_IR_MASKCLR 0xac 202 203#define OHCI_LNKCTL 0xe0 204#define OHCI_LNKCTLCLR 0xe4 205 206#define OHCI_PHYACCESS 0xec 207#define OHCI_CYCLETIMER 0xf0 208 209#define OHCI_DMACTL(off) (off) 210#define OHCI_DMACTLCLR(off) (off + 4) 211#define OHCI_DMACMD(off) (off + 0xc) 212#define OHCI_DMAMATCH(off) (off + 0x10) 213 214#define OHCI_ATQOFF 0x180 215#define OHCI_ATQCTL OHCI_ATQOFF 216#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 217#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 218#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 219 220#define OHCI_ATSOFF 0x1a0 221#define OHCI_ATSCTL OHCI_ATSOFF 222#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 223#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 224#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 225 226#define OHCI_ARQOFF 0x1c0 227#define OHCI_ARQCTL OHCI_ARQOFF 228#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 229#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 230#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 231 232#define OHCI_ARSOFF 0x1e0 233#define OHCI_ARSCTL OHCI_ARSOFF 234#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 235#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 236#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 237 238#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 239#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 240#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 241#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 242 243#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 244#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 245#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 246#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 247#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 248 249d_ioctl_t fwohci_ioctl; 250 251/* 252 * Communication with PHY device 253 */ 254static u_int32_t 255fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 256{ 257 u_int32_t fun; 258 259 addr &= 0xf; 260 data &= 0xff; 261 262 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 263 OWRITE(sc, OHCI_PHYACCESS, fun); 264 DELAY(100); 265 266 return(fwphy_rddata( sc, addr)); 267} 268 269static u_int32_t 270fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 271{ 272 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 273 int i; 274 u_int32_t bm; 275 276#define OHCI_CSR_DATA 0x0c 277#define OHCI_CSR_COMP 0x10 278#define OHCI_CSR_CONT 0x14 279#define OHCI_BUS_MANAGER_ID 0 280 281 OWRITE(sc, OHCI_CSR_DATA, node); 282 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 283 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 284 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 285 DELAY(10); 286 bm = OREAD(sc, OHCI_CSR_DATA); 287 if((bm & 0x3f) == 0x3f) 288 bm = node; 289 if (bootverbose) 290 device_printf(sc->fc.dev, 291 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 292 293 return(bm); 294} 295 296static u_int32_t 297fwphy_rddata(struct fwohci_softc *sc, u_int addr) 298{ 299 u_int32_t fun, stat; 300 u_int i, retry = 0; 301 302 addr &= 0xf; 303#define MAX_RETRY 100 304again: 305 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 306 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 307 OWRITE(sc, OHCI_PHYACCESS, fun); 308 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 309 fun = OREAD(sc, OHCI_PHYACCESS); 310 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 311 break; 312 DELAY(100); 313 } 314 if(i >= MAX_RETRY) { 315 if (bootverbose) 316 device_printf(sc->fc.dev, "phy read failed(1).\n"); 317 if (++retry < MAX_RETRY) { 318 DELAY(100); 319 goto again; 320 } 321 } 322 /* Make sure that SCLK is started */ 323 stat = OREAD(sc, FWOHCI_INTSTAT); 324 if ((stat & OHCI_INT_REG_FAIL) != 0 || 325 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 326 if (bootverbose) 327 device_printf(sc->fc.dev, "phy read failed(2).\n"); 328 if (++retry < MAX_RETRY) { 329 DELAY(100); 330 goto again; 331 } 332 } 333 if (bootverbose || retry >= MAX_RETRY) 334 device_printf(sc->fc.dev, 335 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 336#undef MAX_RETRY 337 return((fun >> PHYDEV_RDDATA )& 0xff); 338} 339/* Device specific ioctl. */ 340int 341fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 342{ 343 struct firewire_softc *sc; 344 struct fwohci_softc *fc; 345 int unit = DEV2UNIT(dev); 346 int err = 0; 347 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 348 u_int32_t *dmach = (u_int32_t *) data; 349 350 sc = devclass_get_softc(firewire_devclass, unit); 351 if(sc == NULL){ 352 return(EINVAL); 353 } 354 fc = (struct fwohci_softc *)sc->fc; 355 356 if (!data) 357 return(EINVAL); 358 359 switch (cmd) { 360 case FWOHCI_WRREG: 361#define OHCI_MAX_REG 0x800 362 if(reg->addr <= OHCI_MAX_REG){ 363 OWRITE(fc, reg->addr, reg->data); 364 reg->data = OREAD(fc, reg->addr); 365 }else{ 366 err = EINVAL; 367 } 368 break; 369 case FWOHCI_RDREG: 370 if(reg->addr <= OHCI_MAX_REG){ 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376/* Read DMA descriptors for debug */ 377 case DUMPDMA: 378 if(*dmach <= OHCI_MAX_DMA_CH ){ 379 dump_dma(fc, *dmach); 380 dump_db(fc, *dmach); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385 default: 386 break; 387 } 388 return err; 389} 390 391static int 392fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 393{ 394 u_int32_t reg, reg2; 395 int e1394a = 1; 396/* 397 * probe PHY parameters 398 * 0. to prove PHY version, whether compliance of 1394a. 399 * 1. to probe maximum speed supported by the PHY and 400 * number of port supported by core-logic. 401 * It is not actually available port on your PC . 402 */ 403 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 404 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 405 406 if((reg >> 5) != 7 ){ 407 sc->fc.mode &= ~FWPHYASYST; 408 sc->fc.nport = reg & FW_PHY_NP; 409 sc->fc.speed = reg & FW_PHY_SPD >> 6; 410 if (sc->fc.speed > MAX_SPEED) { 411 device_printf(dev, "invalid speed %d (fixed to %d).\n", 412 sc->fc.speed, MAX_SPEED); 413 sc->fc.speed = MAX_SPEED; 414 } 415 device_printf(dev, 416 "Phy 1394 only %s, %d ports.\n", 417 linkspeed[sc->fc.speed], sc->fc.nport); 418 }else{ 419 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 420 sc->fc.mode |= FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394a available %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 432 /* check programPhyEnable */ 433 reg2 = fwphy_rddata(sc, 5); 434#if 0 435 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 436#else /* XXX force to enable 1394a */ 437 if (e1394a) { 438#endif 439 if (bootverbose) 440 device_printf(dev, 441 "Enable 1394a Enhancements\n"); 442 /* enable EAA EMC */ 443 reg2 |= 0x03; 444 /* set aPhyEnhanceEnable */ 445 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 446 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 447 } else { 448 /* for safe */ 449 reg2 &= ~0x83; 450 } 451 reg2 = fwphy_wrdata(sc, 5, reg2); 452 } 453 454 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 455 if((reg >> 5) == 7 ){ 456 reg = fwphy_rddata(sc, 4); 457 reg |= 1 << 6; 458 fwphy_wrdata(sc, 4, reg); 459 reg = fwphy_rddata(sc, 4); 460 } 461 return 0; 462} 463 464 465void 466fwohci_reset(struct fwohci_softc *sc, device_t dev) 467{ 468 int i, max_rec, speed; 469 u_int32_t reg, reg2; 470 struct fwohcidb_tr *db_tr; 471 472 /* Disable interrupt */ 473 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 474 475 /* Now stopping all DMA channel */ 476 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 477 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 478 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 479 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 480 481 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 482 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 483 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 484 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 485 } 486 487 /* FLUSH FIFO and reset Transmitter/Reciever */ 488 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 489 if (bootverbose) 490 device_printf(dev, "resetting OHCI..."); 491 i = 0; 492 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 493 if (i++ > 100) break; 494 DELAY(1000); 495 } 496 if (bootverbose) 497 printf("done (loop=%d)\n", i); 498 499 /* Probe phy */ 500 fwohci_probe_phy(sc, dev); 501 502 /* Probe link */ 503 reg = OREAD(sc, OHCI_BUS_OPT); 504 reg2 = reg | OHCI_BUSFNC; 505 max_rec = (reg & 0x0000f000) >> 12; 506 speed = (reg & 0x00000007); 507 device_printf(dev, "Link %s, max_rec %d bytes.\n", 508 linkspeed[speed], MAXREC(max_rec)); 509 /* XXX fix max_rec */ 510 sc->fc.maxrec = sc->fc.speed + 8; 511 if (max_rec != sc->fc.maxrec) { 512 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 513 device_printf(dev, "max_rec %d -> %d\n", 514 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 515 } 516 if (bootverbose) 517 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 518 OWRITE(sc, OHCI_BUS_OPT, reg2); 519 520 /* Initialize registers */ 521 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 522 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 523 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 524 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 525 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 526 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 527 fw_busreset(&sc->fc); 528 529 /* Enable link */ 530 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 531 532 /* Force to start async RX DMA */ 533 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 534 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 535 fwohci_rx_enable(sc, &sc->arrq); 536 fwohci_rx_enable(sc, &sc->arrs); 537 538 /* Initialize async TX */ 539 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 540 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 541 542 /* AT Retries */ 543 OWRITE(sc, FWOHCI_RETRY, 544 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 545 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 546 547 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 548 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 549 sc->atrq.bottom = sc->atrq.top; 550 sc->atrs.bottom = sc->atrs.top; 551 552 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 553 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 554 db_tr->xfer = NULL; 555 } 556 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 558 db_tr->xfer = NULL; 559 } 560 561 562 /* Enable interrupt */ 563 OWRITE(sc, FWOHCI_INTMASK, 564 OHCI_INT_ERR | OHCI_INT_PHY_SID 565 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 566 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 567 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 568 fwohci_set_intr(&sc->fc, 1); 569 570} 571 572int 573fwohci_init(struct fwohci_softc *sc, device_t dev) 574{ 575 int i; 576 u_int32_t reg; 577 u_int8_t ui[8]; 578 579#if FWOHCI_TASKQUEUE 580 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 581#endif 582 583 reg = OREAD(sc, OHCI_VERSION); 584 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586 587 if (((reg>>16) & 0xff) < 1) { 588 device_printf(dev, "invalid OHCI version\n"); 589 return (ENXIO); 590 } 591 592/* Available Isochrounous DMA channel probe */ 593 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 595 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 596 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 597 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 598 for (i = 0; i < 0x20; i++) 599 if ((reg & (1 << i)) == 0) 600 break; 601 sc->fc.nisodma = i; 602 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 603 604 sc->fc.arq = &sc->arrq.xferq; 605 sc->fc.ars = &sc->arrs.xferq; 606 sc->fc.atq = &sc->atrq.xferq; 607 sc->fc.ats = &sc->atrs.xferq; 608 609 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 610 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 611 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 612 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 613 614 sc->arrq.xferq.start = NULL; 615 sc->arrs.xferq.start = NULL; 616 sc->atrq.xferq.start = fwohci_start_atq; 617 sc->atrs.xferq.start = fwohci_start_ats; 618 619 sc->arrq.xferq.buf = NULL; 620 sc->arrs.xferq.buf = NULL; 621 sc->atrq.xferq.buf = NULL; 622 sc->atrs.xferq.buf = NULL; 623 624 sc->arrq.xferq.dmach = -1; 625 sc->arrs.xferq.dmach = -1; 626 sc->atrq.xferq.dmach = -1; 627 sc->atrs.xferq.dmach = -1; 628 629 sc->arrq.ndesc = 1; 630 sc->arrs.ndesc = 1; 631 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 632 sc->atrs.ndesc = 2; 633 634 sc->arrq.ndb = NDB; 635 sc->arrs.ndb = NDB / 2; 636 sc->atrq.ndb = NDB; 637 sc->atrs.ndb = NDB / 2; 638 639 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 640 sc->fc.it[i] = &sc->it[i].xferq; 641 sc->fc.ir[i] = &sc->ir[i].xferq; 642 sc->it[i].xferq.dmach = i; 643 sc->ir[i].xferq.dmach = i; 644 sc->it[i].ndb = 0; 645 sc->ir[i].ndb = 0; 646 } 647 648 sc->fc.tcode = tinfo; 649 sc->fc.dev = dev; 650 651 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 652 &sc->crom_dma, BUS_DMA_WAITOK); 653 if(sc->fc.config_rom == NULL){ 654 device_printf(dev, "config_rom alloc failed."); 655 return ENOMEM; 656 } 657 658#if 0 659 bzero(&sc->fc.config_rom[0], CROMSIZE); 660 sc->fc.config_rom[1] = 0x31333934; 661 sc->fc.config_rom[2] = 0xf000a002; 662 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 663 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 664 sc->fc.config_rom[5] = 0; 665 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 666 667 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 668#endif 669 670 671/* SID recieve buffer must allign 2^11 */ 672#define OHCI_SIDSIZE (1 << 11) 673 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 674 &sc->sid_dma, BUS_DMA_WAITOK); 675 if (sc->sid_buf == NULL) { 676 device_printf(dev, "sid_buf alloc failed."); 677 return ENOMEM; 678 } 679 680 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 681 &sc->dummy_dma, BUS_DMA_WAITOK); 682 683 if (sc->dummy_dma.v_addr == NULL) { 684 device_printf(dev, "dummy_dma alloc failed."); 685 return ENOMEM; 686 } 687 688 fwohci_db_init(sc, &sc->arrq); 689 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 690 return ENOMEM; 691 692 fwohci_db_init(sc, &sc->arrs); 693 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 694 return ENOMEM; 695 696 fwohci_db_init(sc, &sc->atrq); 697 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 698 return ENOMEM; 699 700 fwohci_db_init(sc, &sc->atrs); 701 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 702 return ENOMEM; 703 704 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 705 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 706 for( i = 0 ; i < 8 ; i ++) 707 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 708 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 709 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 710 711 sc->fc.ioctl = fwohci_ioctl; 712 sc->fc.cyctimer = fwohci_cyctimer; 713 sc->fc.set_bmr = fwohci_set_bus_manager; 714 sc->fc.ibr = fwohci_ibr; 715 sc->fc.irx_enable = fwohci_irx_enable; 716 sc->fc.irx_disable = fwohci_irx_disable; 717 718 sc->fc.itx_enable = fwohci_itxbuf_enable; 719 sc->fc.itx_disable = fwohci_itx_disable; 720#if BYTE_ORDER == BIG_ENDIAN 721 sc->fc.irx_post = fwohci_irx_post; 722#else 723 sc->fc.irx_post = NULL; 724#endif 725 sc->fc.itx_post = NULL; 726 sc->fc.timeout = fwohci_timeout; 727 sc->fc.poll = fwohci_poll; 728 sc->fc.set_intr = fwohci_set_intr; 729 730 sc->intmask = sc->irstat = sc->itstat = 0; 731 732 fw_init(&sc->fc); 733 fwohci_reset(sc, dev); 734 735 return 0; 736} 737 738void 739fwohci_timeout(void *arg) 740{ 741 struct fwohci_softc *sc; 742 743 sc = (struct fwohci_softc *)arg; 744} 745 746u_int32_t 747fwohci_cyctimer(struct firewire_comm *fc) 748{ 749 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 750 return(OREAD(sc, OHCI_CYCLETIMER)); 751} 752 753int 754fwohci_detach(struct fwohci_softc *sc, device_t dev) 755{ 756 int i; 757 758 if (sc->sid_buf != NULL) 759 fwdma_free(&sc->fc, &sc->sid_dma); 760 if (sc->fc.config_rom != NULL) 761 fwdma_free(&sc->fc, &sc->crom_dma); 762 763 fwohci_db_free(&sc->arrq); 764 fwohci_db_free(&sc->arrs); 765 766 fwohci_db_free(&sc->atrq); 767 fwohci_db_free(&sc->atrs); 768 769 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 770 fwohci_db_free(&sc->it[i]); 771 fwohci_db_free(&sc->ir[i]); 772 } 773 774 return 0; 775} 776 777#define LAST_DB(dbtr, db) do { \ 778 struct fwohcidb_tr *_dbtr = (dbtr); \ 779 int _cnt = _dbtr->dbcnt; \ 780 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 781} while (0) 782 783static void 784fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 785{ 786 struct fwohcidb_tr *db_tr; 787 volatile struct fwohcidb *db; 788 bus_dma_segment_t *s; 789 int i; 790 791 db_tr = (struct fwohcidb_tr *)arg; 792 db = &db_tr->db[db_tr->dbcnt]; 793 if (error) { 794 if (firewire_debug || error != EFBIG) 795 printf("fwohci_execute_db: error=%d\n", error); 796 return; 797 } 798 for (i = 0; i < nseg; i++) { 799 s = &segs[i]; 800 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 801 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 802 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 803 db++; 804 db_tr->dbcnt++; 805 } 806} 807 808static void 809fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 810 bus_size_t size, int error) 811{ 812 fwohci_execute_db(arg, segs, nseg, error); 813} 814 815static void 816fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 817{ 818 int i, s; 819 int tcode, hdr_len, pl_off, pl_len; 820 int fsegment = -1; 821 u_int32_t off; 822 struct fw_xfer *xfer; 823 struct fw_pkt *fp; 824 volatile struct fwohci_txpkthdr *ohcifp; 825 struct fwohcidb_tr *db_tr; 826 volatile struct fwohcidb *db; 827 struct tcode_info *info; 828 static int maxdesc=0; 829 830 if(&sc->atrq == dbch){ 831 off = OHCI_ATQOFF; 832 }else if(&sc->atrs == dbch){ 833 off = OHCI_ATSOFF; 834 }else{ 835 return; 836 } 837 838 if (dbch->flags & FWOHCI_DBCH_FULL) 839 return; 840 841 s = splfw(); 842 db_tr = dbch->top; 843txloop: 844 xfer = STAILQ_FIRST(&dbch->xferq.q); 845 if(xfer == NULL){ 846 goto kick; 847 } 848 if(dbch->xferq.queued == 0 ){ 849 device_printf(sc->fc.dev, "TX queue empty\n"); 850 } 851 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 852 db_tr->xfer = xfer; 853 xfer->state = FWXF_START; 854 855 fp = (struct fw_pkt *)xfer->send.buf; 856 tcode = fp->mode.common.tcode; 857 858 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 859 info = &tinfo[tcode]; 860 hdr_len = pl_off = info->hdr_len; 861 for( i = 0 ; i < pl_off ; i+= 4){ 862 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 863 } 864 ohcifp->mode.common.spd = xfer->spd; 865 if (tcode == FWTCODE_STREAM ){ 866 hdr_len = 8; 867 ohcifp->mode.stream.len = fp->mode.stream.len; 868 } else if (tcode == FWTCODE_PHY) { 869 hdr_len = 12; 870 ohcifp->mode.ld[1] = fp->mode.ld[1]; 871 ohcifp->mode.ld[2] = fp->mode.ld[2]; 872 ohcifp->mode.common.spd = 0; 873 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 874 } else { 875 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 876 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 877 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 878 } 879 db = &db_tr->db[0]; 880 FWOHCI_DMA_WRITE(db->db.desc.cmd, 881 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 882 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 883/* Specify bound timer of asy. responce */ 884 if(&sc->atrs == dbch){ 885 FWOHCI_DMA_WRITE(db->db.desc.res, 886 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 887 } 888#if BYTE_ORDER == BIG_ENDIAN 889 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 890 hdr_len = 12; 891 for (i = 0; i < hdr_len/4; i ++) 892 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 893#endif 894 895again: 896 db_tr->dbcnt = 2; 897 db = &db_tr->db[db_tr->dbcnt]; 898 pl_len = xfer->send.len - pl_off; 899 if (pl_len > 0) { 900 int err; 901 /* handle payload */ 902 if (xfer->mbuf == NULL) { 903 caddr_t pl_addr; 904 905 pl_addr = xfer->send.buf + pl_off; 906 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 907 pl_addr, pl_len, 908 fwohci_execute_db, db_tr, 909 /*flags*/0); 910 } else { 911 /* XXX we can handle only 6 (=8-2) mbuf chains */ 912 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 913 xfer->mbuf, 914 fwohci_execute_db2, db_tr, 915 /* flags */0); 916 if (err == EFBIG) { 917 struct mbuf *m0; 918 919 if (firewire_debug) 920 device_printf(sc->fc.dev, "EFBIG.\n"); 921 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 922 if (m0 != NULL) { 923 m_copydata(xfer->mbuf, 0, 924 xfer->mbuf->m_pkthdr.len, 925 mtod(m0, caddr_t)); 926 m0->m_len = m0->m_pkthdr.len = 927 xfer->mbuf->m_pkthdr.len; 928 m_freem(xfer->mbuf); 929 xfer->mbuf = m0; 930 goto again; 931 } 932 device_printf(sc->fc.dev, "m_getcl failed.\n"); 933 } 934 } 935 if (err) 936 printf("dmamap_load: err=%d\n", err); 937 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 938 BUS_DMASYNC_PREWRITE); 939#if 0 /* OHCI_OUTPUT_MODE == 0 */ 940 for (i = 2; i < db_tr->dbcnt; i++) 941 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 942 OHCI_OUTPUT_MORE); 943#endif 944 } 945 if (maxdesc < db_tr->dbcnt) { 946 maxdesc = db_tr->dbcnt; 947 if (bootverbose) 948 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 949 } 950 /* last db */ 951 LAST_DB(db_tr, db); 952 FWOHCI_DMA_SET(db->db.desc.cmd, 953 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 954 FWOHCI_DMA_WRITE(db->db.desc.depend, 955 STAILQ_NEXT(db_tr, link)->bus_addr); 956 957 if(fsegment == -1 ) 958 fsegment = db_tr->dbcnt; 959 if (dbch->pdb_tr != NULL) { 960 LAST_DB(dbch->pdb_tr, db); 961 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 962 } 963 dbch->pdb_tr = db_tr; 964 db_tr = STAILQ_NEXT(db_tr, link); 965 if(db_tr != dbch->bottom){ 966 goto txloop; 967 } else { 968 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 969 dbch->flags |= FWOHCI_DBCH_FULL; 970 } 971kick: 972 /* kick asy q */ 973 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 974 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 975 976 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 977 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 978 } else { 979 if (bootverbose) 980 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 981 OREAD(sc, OHCI_DMACTL(off))); 982 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 983 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 984 dbch->xferq.flag |= FWXFERQ_RUNNING; 985 } 986 987 dbch->top = db_tr; 988 splx(s); 989 return; 990} 991 992static void 993fwohci_start_atq(struct firewire_comm *fc) 994{ 995 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 996 fwohci_start( sc, &(sc->atrq)); 997 return; 998} 999 1000static void 1001fwohci_start_ats(struct firewire_comm *fc) 1002{ 1003 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1004 fwohci_start( sc, &(sc->atrs)); 1005 return; 1006} 1007 1008void 1009fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1010{ 1011 int s, ch, err = 0; 1012 struct fwohcidb_tr *tr; 1013 volatile struct fwohcidb *db; 1014 struct fw_xfer *xfer; 1015 u_int32_t off; 1016 u_int stat, status; 1017 int packets; 1018 struct firewire_comm *fc = (struct firewire_comm *)sc; 1019 1020 if(&sc->atrq == dbch){ 1021 off = OHCI_ATQOFF; 1022 ch = ATRQ_CH; 1023 }else if(&sc->atrs == dbch){ 1024 off = OHCI_ATSOFF; 1025 ch = ATRS_CH; 1026 }else{ 1027 return; 1028 } 1029 s = splfw(); 1030 tr = dbch->bottom; 1031 packets = 0; 1032 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1033 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1034 while(dbch->xferq.queued > 0){ 1035 LAST_DB(tr, db); 1036 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1037 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1038 if (fc->status != FWBUSRESET) 1039 /* maybe out of order?? */ 1040 goto out; 1041 } 1042 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1043 BUS_DMASYNC_POSTWRITE); 1044 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1045#if 0 1046 dump_db(sc, ch); 1047#endif 1048 if(status & OHCI_CNTL_DMA_DEAD) { 1049 /* Stop DMA */ 1050 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1051 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1052 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1053 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1054 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1055 } 1056 stat = status & FWOHCIEV_MASK; 1057 switch(stat){ 1058 case FWOHCIEV_ACKPEND: 1059 case FWOHCIEV_ACKCOMPL: 1060 err = 0; 1061 break; 1062 case FWOHCIEV_ACKBSA: 1063 case FWOHCIEV_ACKBSB: 1064 case FWOHCIEV_ACKBSX: 1065 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1066 err = EBUSY; 1067 break; 1068 case FWOHCIEV_FLUSHED: 1069 case FWOHCIEV_ACKTARD: 1070 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1071 err = EAGAIN; 1072 break; 1073 case FWOHCIEV_MISSACK: 1074 case FWOHCIEV_UNDRRUN: 1075 case FWOHCIEV_OVRRUN: 1076 case FWOHCIEV_DESCERR: 1077 case FWOHCIEV_DTRDERR: 1078 case FWOHCIEV_TIMEOUT: 1079 case FWOHCIEV_TCODERR: 1080 case FWOHCIEV_UNKNOWN: 1081 case FWOHCIEV_ACKDERR: 1082 case FWOHCIEV_ACKTERR: 1083 default: 1084 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1085 stat, fwohcicode[stat]); 1086 err = EINVAL; 1087 break; 1088 } 1089 if (tr->xfer != NULL) { 1090 xfer = tr->xfer; 1091 if (xfer->state == FWXF_RCVD) { 1092 if (firewire_debug) 1093 printf("already rcvd\n"); 1094 fw_xfer_done(xfer); 1095 } else { 1096 xfer->state = FWXF_SENT; 1097 if (err == EBUSY && fc->status != FWBUSRESET) { 1098 xfer->state = FWXF_BUSY; 1099 xfer->resp = err; 1100 if (xfer->retry_req != NULL) 1101 xfer->retry_req(xfer); 1102 else { 1103 xfer->recv.len = 0; 1104 fw_xfer_done(xfer); 1105 } 1106 } else if (stat != FWOHCIEV_ACKPEND) { 1107 if (stat != FWOHCIEV_ACKCOMPL) 1108 xfer->state = FWXF_SENTERR; 1109 xfer->resp = err; 1110 xfer->recv.len = 0; 1111 fw_xfer_done(xfer); 1112 } 1113 } 1114 /* 1115 * The watchdog timer takes care of split 1116 * transcation timeout for ACKPEND case. 1117 */ 1118 } else { 1119 printf("this shouldn't happen\n"); 1120 } 1121 dbch->xferq.queued --; 1122 tr->xfer = NULL; 1123 1124 packets ++; 1125 tr = STAILQ_NEXT(tr, link); 1126 dbch->bottom = tr; 1127 if (dbch->bottom == dbch->top) { 1128 /* we reaches the end of context program */ 1129 if (firewire_debug && dbch->xferq.queued > 0) 1130 printf("queued > 0\n"); 1131 break; 1132 } 1133 } 1134out: 1135 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1136 printf("make free slot\n"); 1137 dbch->flags &= ~FWOHCI_DBCH_FULL; 1138 fwohci_start(sc, dbch); 1139 } 1140 splx(s); 1141} 1142 1143static void 1144fwohci_db_free(struct fwohci_dbch *dbch) 1145{ 1146 struct fwohcidb_tr *db_tr; 1147 int idb; 1148 1149 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1150 return; 1151 1152 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1153 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1154 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1155 db_tr->buf != NULL) { 1156 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1157 db_tr->buf, dbch->xferq.psize); 1158 db_tr->buf = NULL; 1159 } else if (db_tr->dma_map != NULL) 1160 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1161 } 1162 dbch->ndb = 0; 1163 db_tr = STAILQ_FIRST(&dbch->db_trq); 1164 fwdma_free_multiseg(dbch->am); 1165 free(db_tr, M_FW); 1166 STAILQ_INIT(&dbch->db_trq); 1167 dbch->flags &= ~FWOHCI_DBCH_INIT; 1168} 1169 1170static void 1171fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1172{ 1173 int idb; 1174 struct fwohcidb_tr *db_tr; 1175 1176 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1177 goto out; 1178 1179 /* create dma_tag for buffers */ 1180#define MAX_REQCOUNT 0xffff 1181 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1182 /*alignment*/ 1, /*boundary*/ 0, 1183 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1184 /*highaddr*/ BUS_SPACE_MAXADDR, 1185 /*filter*/NULL, /*filterarg*/NULL, 1186 /*maxsize*/ dbch->xferq.psize, 1187 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1188 /*maxsegsz*/ MAX_REQCOUNT, 1189 /*flags*/ 0, 1190#if __FreeBSD_version >= 501102 1191 /*lockfunc*/busdma_lock_mutex, 1192 /*lockarg*/&Giant, 1193#endif 1194 &dbch->dmat)) 1195 return; 1196 1197 /* allocate DB entries and attach one to each DMA channels */ 1198 /* DB entry must start at 16 bytes bounary. */ 1199 STAILQ_INIT(&dbch->db_trq); 1200 db_tr = (struct fwohcidb_tr *) 1201 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1202 M_FW, M_WAITOK | M_ZERO); 1203 if(db_tr == NULL){ 1204 printf("fwohci_db_init: malloc(1) failed\n"); 1205 return; 1206 } 1207 1208#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1209 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1210 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1211 if (dbch->am == NULL) { 1212 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1213 return; 1214 } 1215 /* Attach DB to DMA ch. */ 1216 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1217 db_tr->dbcnt = 0; 1218 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1219 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1220 /* create dmamap for buffers */ 1221 /* XXX do we need 4bytes alignment tag? */ 1222 /* XXX don't alloc dma_map for AR */ 1223 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1224 printf("bus_dmamap_create failed\n"); 1225 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1226 fwohci_db_free(dbch); 1227 return; 1228 } 1229 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1230 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1231 if (idb % dbch->xferq.bnpacket == 0) 1232 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1233 ].start = (caddr_t)db_tr; 1234 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1235 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1236 ].end = (caddr_t)db_tr; 1237 } 1238 db_tr++; 1239 } 1240 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1241 = STAILQ_FIRST(&dbch->db_trq); 1242out: 1243 dbch->xferq.queued = 0; 1244 dbch->pdb_tr = NULL; 1245 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1246 dbch->bottom = dbch->top; 1247 dbch->flags = FWOHCI_DBCH_INIT; 1248} 1249 1250static int 1251fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1252{ 1253 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1254 int sleepch; 1255 1256 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1257 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1258 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1259 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1260 /* XXX we cannot free buffers until the DMA really stops */ 1261 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1262 fwohci_db_free(&sc->it[dmach]); 1263 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1264 return 0; 1265} 1266 1267static int 1268fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1269{ 1270 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1271 int sleepch; 1272 1273 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1274 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1275 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1276 /* XXX we cannot free buffers until the DMA really stops */ 1277 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1278 fwohci_db_free(&sc->ir[dmach]); 1279 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1280 return 0; 1281} 1282 1283#if BYTE_ORDER == BIG_ENDIAN 1284static void 1285fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1286{ 1287 qld[0] = FWOHCI_DMA_READ(qld[0]); 1288 return; 1289} 1290#endif 1291 1292static int 1293fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1294{ 1295 int err = 0; 1296 int idb, z, i, dmach = 0, ldesc; 1297 u_int32_t off = NULL; 1298 struct fwohcidb_tr *db_tr; 1299 volatile struct fwohcidb *db; 1300 1301 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1302 err = EINVAL; 1303 return err; 1304 } 1305 z = dbch->ndesc; 1306 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1307 if( &sc->it[dmach] == dbch){ 1308 off = OHCI_ITOFF(dmach); 1309 break; 1310 } 1311 } 1312 if(off == NULL){ 1313 err = EINVAL; 1314 return err; 1315 } 1316 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1317 return err; 1318 dbch->xferq.flag |= FWXFERQ_RUNNING; 1319 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1320 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1321 } 1322 db_tr = dbch->top; 1323 for (idb = 0; idb < dbch->ndb; idb ++) { 1324 fwohci_add_tx_buf(dbch, db_tr, idb); 1325 if(STAILQ_NEXT(db_tr, link) == NULL){ 1326 break; 1327 } 1328 db = db_tr->db; 1329 ldesc = db_tr->dbcnt - 1; 1330 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1331 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1332 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1333 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1334 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1335 FWOHCI_DMA_SET( 1336 db[ldesc].db.desc.cmd, 1337 OHCI_INTERRUPT_ALWAYS); 1338 /* OHCI 1.1 and above */ 1339 FWOHCI_DMA_SET( 1340 db[0].db.desc.cmd, 1341 OHCI_INTERRUPT_ALWAYS); 1342 } 1343 } 1344 db_tr = STAILQ_NEXT(db_tr, link); 1345 } 1346 FWOHCI_DMA_CLEAR( 1347 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1348 return err; 1349} 1350 1351static int 1352fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1353{ 1354 int err = 0; 1355 int idb, z, i, dmach = 0, ldesc; 1356 u_int32_t off = NULL; 1357 struct fwohcidb_tr *db_tr; 1358 volatile struct fwohcidb *db; 1359 1360 z = dbch->ndesc; 1361 if(&sc->arrq == dbch){ 1362 off = OHCI_ARQOFF; 1363 }else if(&sc->arrs == dbch){ 1364 off = OHCI_ARSOFF; 1365 }else{ 1366 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1367 if( &sc->ir[dmach] == dbch){ 1368 off = OHCI_IROFF(dmach); 1369 break; 1370 } 1371 } 1372 } 1373 if(off == NULL){ 1374 err = EINVAL; 1375 return err; 1376 } 1377 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1378 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1379 return err; 1380 }else{ 1381 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1382 err = EBUSY; 1383 return err; 1384 } 1385 } 1386 dbch->xferq.flag |= FWXFERQ_RUNNING; 1387 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1388 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1389 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1390 } 1391 db_tr = dbch->top; 1392 for (idb = 0; idb < dbch->ndb; idb ++) { 1393 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1394 if (STAILQ_NEXT(db_tr, link) == NULL) 1395 break; 1396 db = db_tr->db; 1397 ldesc = db_tr->dbcnt - 1; 1398 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1399 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1400 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1401 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1402 FWOHCI_DMA_SET( 1403 db[ldesc].db.desc.cmd, 1404 OHCI_INTERRUPT_ALWAYS); 1405 FWOHCI_DMA_CLEAR( 1406 db[ldesc].db.desc.depend, 1407 0xf); 1408 } 1409 } 1410 db_tr = STAILQ_NEXT(db_tr, link); 1411 } 1412 FWOHCI_DMA_CLEAR( 1413 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1414 dbch->buf_offset = 0; 1415 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1416 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1417 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1418 return err; 1419 }else{ 1420 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1421 } 1422 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1423 return err; 1424} 1425 1426static int 1427fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1428{ 1429 int sec, cycle, cycle_match; 1430 1431 cycle = cycle_now & 0x1fff; 1432 sec = cycle_now >> 13; 1433#define CYCLE_MOD 0x10 1434#if 1 1435#define CYCLE_DELAY 8 /* min delay to start DMA */ 1436#else 1437#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1438#endif 1439 cycle = cycle + CYCLE_DELAY; 1440 if (cycle >= 8000) { 1441 sec ++; 1442 cycle -= 8000; 1443 } 1444 cycle = roundup2(cycle, CYCLE_MOD); 1445 if (cycle >= 8000) { 1446 sec ++; 1447 if (cycle == 8000) 1448 cycle = 0; 1449 else 1450 cycle = CYCLE_MOD; 1451 } 1452 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1453 1454 return(cycle_match); 1455} 1456 1457static int 1458fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1459{ 1460 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1461 int err = 0; 1462 unsigned short tag, ich; 1463 struct fwohci_dbch *dbch; 1464 int cycle_match, cycle_now, s, ldesc; 1465 u_int32_t stat; 1466 struct fw_bulkxfer *first, *chunk, *prev; 1467 struct fw_xferq *it; 1468 1469 dbch = &sc->it[dmach]; 1470 it = &dbch->xferq; 1471 1472 tag = (it->flag >> 6) & 3; 1473 ich = it->flag & 0x3f; 1474 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1475 dbch->ndb = it->bnpacket * it->bnchunk; 1476 dbch->ndesc = 3; 1477 fwohci_db_init(sc, dbch); 1478 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1479 return ENOMEM; 1480 err = fwohci_tx_enable(sc, dbch); 1481 } 1482 if(err) 1483 return err; 1484 1485 ldesc = dbch->ndesc - 1; 1486 s = splfw(); 1487 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1488 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1489 volatile struct fwohcidb *db; 1490 1491 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1492 BUS_DMASYNC_PREWRITE); 1493 fwohci_txbufdb(sc, dmach, chunk); 1494 if (prev != NULL) { 1495 db = ((struct fwohcidb_tr *)(prev->end))->db; 1496#if 0 /* XXX necessary? */ 1497 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1498 OHCI_BRANCH_ALWAYS); 1499#endif 1500#if 0 /* if bulkxfer->npacket changes */ 1501 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1502 ((struct fwohcidb_tr *) 1503 (chunk->start))->bus_addr | dbch->ndesc; 1504#else 1505 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1506 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1507#endif 1508 } 1509 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1510 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1511 prev = chunk; 1512 } 1513 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1514 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1515 splx(s); 1516 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1517 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1518 printf("stat 0x%x\n", stat); 1519 1520 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1521 return 0; 1522 1523#if 0 1524 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1525#endif 1526 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1527 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1528 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1529 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1530 1531 first = STAILQ_FIRST(&it->stdma); 1532 OWRITE(sc, OHCI_ITCMD(dmach), 1533 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1534 if (firewire_debug) { 1535 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1536#if 1 1537 dump_dma(sc, ITX_CH + dmach); 1538#endif 1539 } 1540 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1541#if 1 1542 /* Don't start until all chunks are buffered */ 1543 if (STAILQ_FIRST(&it->stfree) != NULL) 1544 goto out; 1545#endif 1546#if 1 1547 /* Clear cycle match counter bits */ 1548 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1549 1550 /* 2bit second + 13bit cycle */ 1551 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1552 cycle_match = fwohci_next_cycle(fc, cycle_now); 1553 1554 OWRITE(sc, OHCI_ITCTL(dmach), 1555 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1556 | OHCI_CNTL_DMA_RUN); 1557#else 1558 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1559#endif 1560 if (firewire_debug) { 1561 printf("cycle_match: 0x%04x->0x%04x\n", 1562 cycle_now, cycle_match); 1563 dump_dma(sc, ITX_CH + dmach); 1564 dump_db(sc, ITX_CH + dmach); 1565 } 1566 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1567 device_printf(sc->fc.dev, 1568 "IT DMA underrun (0x%08x)\n", stat); 1569 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1570 } 1571out: 1572 return err; 1573} 1574 1575static int 1576fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1577{ 1578 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1579 int err = 0, s, ldesc; 1580 unsigned short tag, ich; 1581 u_int32_t stat; 1582 struct fwohci_dbch *dbch; 1583 struct fwohcidb_tr *db_tr; 1584 struct fw_bulkxfer *first, *prev, *chunk; 1585 struct fw_xferq *ir; 1586 1587 dbch = &sc->ir[dmach]; 1588 ir = &dbch->xferq; 1589 1590 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1591 tag = (ir->flag >> 6) & 3; 1592 ich = ir->flag & 0x3f; 1593 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1594 1595 ir->queued = 0; 1596 dbch->ndb = ir->bnpacket * ir->bnchunk; 1597 dbch->ndesc = 2; 1598 fwohci_db_init(sc, dbch); 1599 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1600 return ENOMEM; 1601 err = fwohci_rx_enable(sc, dbch); 1602 } 1603 if(err) 1604 return err; 1605 1606 first = STAILQ_FIRST(&ir->stfree); 1607 if (first == NULL) { 1608 device_printf(fc->dev, "IR DMA no free chunk\n"); 1609 return 0; 1610 } 1611 1612 ldesc = dbch->ndesc - 1; 1613 s = splfw(); 1614 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1615 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1616 volatile struct fwohcidb *db; 1617 1618#if 1 /* XXX for if_fwe */ 1619 if (chunk->mbuf != NULL) { 1620 db_tr = (struct fwohcidb_tr *)(chunk->start); 1621 db_tr->dbcnt = 1; 1622 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1623 chunk->mbuf, fwohci_execute_db2, db_tr, 1624 /* flags */0); 1625 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1626 OHCI_UPDATE | OHCI_INPUT_LAST | 1627 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1628 } 1629#endif 1630 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1631 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1632 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1633 if (prev != NULL) { 1634 db = ((struct fwohcidb_tr *)(prev->end))->db; 1635 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1636 } 1637 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1638 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1639 prev = chunk; 1640 } 1641 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1642 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1643 splx(s); 1644 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1645 if (stat & OHCI_CNTL_DMA_ACTIVE) 1646 return 0; 1647 if (stat & OHCI_CNTL_DMA_RUN) { 1648 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1649 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1650 } 1651 1652 if (firewire_debug) 1653 printf("start IR DMA 0x%x\n", stat); 1654 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1655 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1656 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1657 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1658 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1659 OWRITE(sc, OHCI_IRCMD(dmach), 1660 ((struct fwohcidb_tr *)(first->start))->bus_addr 1661 | dbch->ndesc); 1662 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1663 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1664#if 0 1665 dump_db(sc, IRX_CH + dmach); 1666#endif 1667 return err; 1668} 1669 1670int 1671fwohci_stop(struct fwohci_softc *sc, device_t dev) 1672{ 1673 u_int i; 1674 1675/* Now stopping all DMA channel */ 1676 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1677 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1678 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1679 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1680 1681 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1682 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1683 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1684 } 1685 1686/* FLUSH FIFO and reset Transmitter/Reciever */ 1687 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1688 1689/* Stop interrupt */ 1690 OWRITE(sc, FWOHCI_INTMASKCLR, 1691 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1692 | OHCI_INT_PHY_INT 1693 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1694 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1695 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1696 | OHCI_INT_PHY_BUS_R); 1697 1698 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1699 fw_drain_txq(&sc->fc); 1700 1701/* XXX Link down? Bus reset? */ 1702 return 0; 1703} 1704 1705int 1706fwohci_resume(struct fwohci_softc *sc, device_t dev) 1707{ 1708 int i; 1709 struct fw_xferq *ir; 1710 struct fw_bulkxfer *chunk; 1711 1712 fwohci_reset(sc, dev); 1713 /* XXX resume isochronus receive automatically. (how about TX?) */ 1714 for(i = 0; i < sc->fc.nisodma; i ++) { 1715 ir = &sc->ir[i].xferq; 1716 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1717 device_printf(sc->fc.dev, 1718 "resume iso receive ch: %d\n", i); 1719 ir->flag &= ~FWXFERQ_RUNNING; 1720 /* requeue stdma to stfree */ 1721 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1722 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1723 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1724 } 1725 sc->fc.irx_enable(&sc->fc, i); 1726 } 1727 } 1728 1729 bus_generic_resume(dev); 1730 sc->fc.ibr(&sc->fc); 1731 return 0; 1732} 1733 1734#define ACK_ALL 1735static void 1736fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1737{ 1738 u_int32_t irstat, itstat; 1739 u_int i; 1740 struct firewire_comm *fc = (struct firewire_comm *)sc; 1741 1742#ifdef OHCI_DEBUG 1743 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1744 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1745 stat & OHCI_INT_EN ? "DMA_EN ":"", 1746 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1747 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1748 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1749 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1750 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1751 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1752 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1753 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1754 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1755 stat & OHCI_INT_PHY_SID ? "SID ":"", 1756 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1757 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1758 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1759 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1760 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1761 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1762 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1763 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1764 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1765 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1766 stat, OREAD(sc, FWOHCI_INTMASK) 1767 ); 1768#endif 1769/* Bus reset */ 1770 if(stat & OHCI_INT_PHY_BUS_R ){ 1771 if (fc->status == FWBUSRESET) 1772 goto busresetout; 1773 /* Disable bus reset interrupt until sid recv. */ 1774 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1775 1776 device_printf(fc->dev, "BUS reset\n"); 1777 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1778 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1779 1780 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1781 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1782 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1783 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1784 1785#ifndef ACK_ALL 1786 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1787#endif 1788 fw_busreset(fc); 1789 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1790 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1791 } 1792busresetout: 1793 if((stat & OHCI_INT_DMA_IR )){ 1794#ifndef ACK_ALL 1795 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1796#endif 1797#if __FreeBSD_version >= 500000 1798 irstat = atomic_readandclear_int(&sc->irstat); 1799#else 1800 irstat = sc->irstat; 1801 sc->irstat = 0; 1802#endif 1803 for(i = 0; i < fc->nisodma ; i++){ 1804 struct fwohci_dbch *dbch; 1805 1806 if((irstat & (1 << i)) != 0){ 1807 dbch = &sc->ir[i]; 1808 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1809 device_printf(sc->fc.dev, 1810 "dma(%d) not active\n", i); 1811 continue; 1812 } 1813 fwohci_rbuf_update(sc, i); 1814 } 1815 } 1816 } 1817 if((stat & OHCI_INT_DMA_IT )){ 1818#ifndef ACK_ALL 1819 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1820#endif 1821#if __FreeBSD_version >= 500000 1822 itstat = atomic_readandclear_int(&sc->itstat); 1823#else 1824 itstat = sc->itstat; 1825 sc->itstat = 0; 1826#endif 1827 for(i = 0; i < fc->nisodma ; i++){ 1828 if((itstat & (1 << i)) != 0){ 1829 fwohci_tbuf_update(sc, i); 1830 } 1831 } 1832 } 1833 if((stat & OHCI_INT_DMA_PRRS )){ 1834#ifndef ACK_ALL 1835 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1836#endif 1837#if 0 1838 dump_dma(sc, ARRS_CH); 1839 dump_db(sc, ARRS_CH); 1840#endif 1841 fwohci_arcv(sc, &sc->arrs, count); 1842 } 1843 if((stat & OHCI_INT_DMA_PRRQ )){ 1844#ifndef ACK_ALL 1845 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1846#endif 1847#if 0 1848 dump_dma(sc, ARRQ_CH); 1849 dump_db(sc, ARRQ_CH); 1850#endif 1851 fwohci_arcv(sc, &sc->arrq, count); 1852 } 1853 if(stat & OHCI_INT_PHY_SID){ 1854 u_int32_t *buf, node_id; 1855 int plen; 1856 1857#ifndef ACK_ALL 1858 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1859#endif 1860 /* Enable bus reset interrupt */ 1861 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1862 /* Allow async. request to us */ 1863 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1864 /* XXX insecure ?? */ 1865 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1866 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1867 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1868 /* Set ATRetries register */ 1869 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1870/* 1871** Checking whether the node is root or not. If root, turn on 1872** cycle master. 1873*/ 1874 node_id = OREAD(sc, FWOHCI_NODEID); 1875 plen = OREAD(sc, OHCI_SID_CNT); 1876 1877 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1878 node_id, (plen >> 16) & 0xff); 1879 if (!(node_id & OHCI_NODE_VALID)) { 1880 printf("Bus reset failure\n"); 1881 goto sidout; 1882 } 1883 if (node_id & OHCI_NODE_ROOT) { 1884 printf("CYCLEMASTER mode\n"); 1885 OWRITE(sc, OHCI_LNKCTL, 1886 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1887 } else { 1888 printf("non CYCLEMASTER mode\n"); 1889 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1890 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1891 } 1892 fc->nodeid = node_id & 0x3f; 1893 1894 if (plen & OHCI_SID_ERR) { 1895 device_printf(fc->dev, "SID Error\n"); 1896 goto sidout; 1897 } 1898 plen &= OHCI_SID_CNT_MASK; 1899 if (plen < 4 || plen > OHCI_SIDSIZE) { 1900 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1901 goto sidout; 1902 } 1903 plen -= 4; /* chop control info */ 1904 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1905 if (buf == NULL) { 1906 device_printf(fc->dev, "malloc failed\n"); 1907 goto sidout; 1908 } 1909 for (i = 0; i < plen / 4; i ++) 1910 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1911#if 1 1912 /* pending all pre-bus_reset packets */ 1913 fwohci_txd(sc, &sc->atrq); 1914 fwohci_txd(sc, &sc->atrs); 1915 fwohci_arcv(sc, &sc->arrs, -1); 1916 fwohci_arcv(sc, &sc->arrq, -1); 1917 fw_drain_txq(fc); 1918#endif 1919 fw_sidrcv(fc, buf, plen); 1920 free(buf, M_FW); 1921 } 1922sidout: 1923 if((stat & OHCI_INT_DMA_ATRQ )){ 1924#ifndef ACK_ALL 1925 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1926#endif 1927 fwohci_txd(sc, &(sc->atrq)); 1928 } 1929 if((stat & OHCI_INT_DMA_ATRS )){ 1930#ifndef ACK_ALL 1931 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1932#endif 1933 fwohci_txd(sc, &(sc->atrs)); 1934 } 1935 if((stat & OHCI_INT_PW_ERR )){ 1936#ifndef ACK_ALL 1937 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1938#endif 1939 device_printf(fc->dev, "posted write error\n"); 1940 } 1941 if((stat & OHCI_INT_ERR )){ 1942#ifndef ACK_ALL 1943 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1944#endif 1945 device_printf(fc->dev, "unrecoverable error\n"); 1946 } 1947 if((stat & OHCI_INT_PHY_INT)) { 1948#ifndef ACK_ALL 1949 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1950#endif 1951 device_printf(fc->dev, "phy int\n"); 1952 } 1953 1954 return; 1955} 1956 1957#if FWOHCI_TASKQUEUE 1958static void 1959fwohci_complete(void *arg, int pending) 1960{ 1961 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1962 u_int32_t stat; 1963 1964again: 1965 stat = atomic_readandclear_int(&sc->intstat); 1966 if (stat) 1967 fwohci_intr_body(sc, stat, -1); 1968 else 1969 return; 1970 goto again; 1971} 1972#endif 1973 1974static u_int32_t 1975fwochi_check_stat(struct fwohci_softc *sc) 1976{ 1977 u_int32_t stat, irstat, itstat; 1978 1979 stat = OREAD(sc, FWOHCI_INTSTAT); 1980 if (stat == 0xffffffff) { 1981 device_printf(sc->fc.dev, 1982 "device physically ejected?\n"); 1983 return(stat); 1984 } 1985#ifdef ACK_ALL 1986 if (stat) 1987 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1988#endif 1989 if (stat & OHCI_INT_DMA_IR) { 1990 irstat = OREAD(sc, OHCI_IR_STAT); 1991 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1992 atomic_set_int(&sc->irstat, irstat); 1993 } 1994 if (stat & OHCI_INT_DMA_IT) { 1995 itstat = OREAD(sc, OHCI_IT_STAT); 1996 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1997 atomic_set_int(&sc->itstat, itstat); 1998 } 1999 return(stat); 2000} 2001 2002void 2003fwohci_intr(void *arg) 2004{ 2005 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2006 u_int32_t stat; 2007#if !FWOHCI_TASKQUEUE 2008 u_int32_t bus_reset = 0; 2009#endif 2010 2011 if (!(sc->intmask & OHCI_INT_EN)) { 2012 /* polling mode */ 2013 return; 2014 } 2015 2016#if !FWOHCI_TASKQUEUE 2017again: 2018#endif 2019 stat = fwochi_check_stat(sc); 2020 if (stat == 0 || stat == 0xffffffff) 2021 return; 2022#if FWOHCI_TASKQUEUE 2023 atomic_set_int(&sc->intstat, stat); 2024 /* XXX mask bus reset intr. during bus reset phase */ 2025 if (stat) 2026 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2027#else 2028 /* We cannot clear bus reset event during bus reset phase */ 2029 if ((stat & ~bus_reset) == 0) 2030 return; 2031 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2032 fwohci_intr_body(sc, stat, -1); 2033 goto again; 2034#endif 2035} 2036 2037void 2038fwohci_poll(struct firewire_comm *fc, int quick, int count) 2039{ 2040 int s; 2041 u_int32_t stat; 2042 struct fwohci_softc *sc; 2043 2044 2045 sc = (struct fwohci_softc *)fc; 2046 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2047 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2048 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2049#if 0 2050 if (!quick) { 2051#else 2052 if (1) { 2053#endif 2054 stat = fwochi_check_stat(sc); 2055 if (stat == 0 || stat == 0xffffffff) 2056 return; 2057 } 2058 s = splfw(); 2059 fwohci_intr_body(sc, stat, count); 2060 splx(s); 2061} 2062 2063static void 2064fwohci_set_intr(struct firewire_comm *fc, int enable) 2065{ 2066 struct fwohci_softc *sc; 2067 2068 sc = (struct fwohci_softc *)fc; 2069 if (bootverbose) 2070 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2071 if (enable) { 2072 sc->intmask |= OHCI_INT_EN; 2073 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2074 } else { 2075 sc->intmask &= ~OHCI_INT_EN; 2076 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2077 } 2078} 2079 2080static void 2081fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2082{ 2083 struct firewire_comm *fc = &sc->fc; 2084 volatile struct fwohcidb *db; 2085 struct fw_bulkxfer *chunk; 2086 struct fw_xferq *it; 2087 u_int32_t stat, count; 2088 int s, w=0, ldesc; 2089 2090 it = fc->it[dmach]; 2091 ldesc = sc->it[dmach].ndesc - 1; 2092 s = splfw(); /* unnecessary ? */ 2093 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2094 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2095 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2096 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2097 >> OHCI_STATUS_SHIFT; 2098 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2099 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2100 & OHCI_COUNT_MASK; 2101 if (stat == 0) 2102 break; 2103 STAILQ_REMOVE_HEAD(&it->stdma, link); 2104 switch (stat & FWOHCIEV_MASK){ 2105 case FWOHCIEV_ACKCOMPL: 2106#if 0 2107 device_printf(fc->dev, "0x%08x\n", count); 2108#endif 2109 break; 2110 default: 2111 device_printf(fc->dev, 2112 "Isochronous transmit err %02x(%s)\n", 2113 stat, fwohcicode[stat & 0x1f]); 2114 } 2115 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2116 w++; 2117 } 2118 splx(s); 2119 if (w) 2120 wakeup(it); 2121} 2122 2123static void 2124fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2125{ 2126 struct firewire_comm *fc = &sc->fc; 2127 volatile struct fwohcidb_tr *db_tr; 2128 struct fw_bulkxfer *chunk; 2129 struct fw_xferq *ir; 2130 u_int32_t stat; 2131 int s, w=0, ldesc; 2132 2133 ir = fc->ir[dmach]; 2134 ldesc = sc->ir[dmach].ndesc - 1; 2135#if 0 2136 dump_db(sc, dmach); 2137#endif 2138 s = splfw(); 2139 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2140 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2141 db_tr = (struct fwohcidb_tr *)chunk->end; 2142 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2143 >> OHCI_STATUS_SHIFT; 2144 if (stat == 0) 2145 break; 2146 2147 if (chunk->mbuf != NULL) { 2148 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2149 BUS_DMASYNC_POSTREAD); 2150 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2151 } else if (ir->buf != NULL) { 2152 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2153 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2154 } else { 2155 /* XXX */ 2156 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2157 } 2158 2159 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2160 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2161 switch (stat & FWOHCIEV_MASK) { 2162 case FWOHCIEV_ACKCOMPL: 2163 chunk->resp = 0; 2164 break; 2165 default: 2166 chunk->resp = EINVAL; 2167 device_printf(fc->dev, 2168 "Isochronous receive err %02x(%s)\n", 2169 stat, fwohcicode[stat & 0x1f]); 2170 } 2171 w++; 2172 } 2173 splx(s); 2174 if (w) { 2175 if (ir->flag & FWXFERQ_HANDLER) 2176 ir->hand(ir); 2177 else 2178 wakeup(ir); 2179 } 2180} 2181 2182void 2183dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2184{ 2185 u_int32_t off, cntl, stat, cmd, match; 2186 2187 if(ch == 0){ 2188 off = OHCI_ATQOFF; 2189 }else if(ch == 1){ 2190 off = OHCI_ATSOFF; 2191 }else if(ch == 2){ 2192 off = OHCI_ARQOFF; 2193 }else if(ch == 3){ 2194 off = OHCI_ARSOFF; 2195 }else if(ch < IRX_CH){ 2196 off = OHCI_ITCTL(ch - ITX_CH); 2197 }else{ 2198 off = OHCI_IRCTL(ch - IRX_CH); 2199 } 2200 cntl = stat = OREAD(sc, off); 2201 cmd = OREAD(sc, off + 0xc); 2202 match = OREAD(sc, off + 0x10); 2203 2204 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2205 ch, 2206 cntl, 2207 cmd, 2208 match); 2209 stat &= 0xffff ; 2210 if (stat) { 2211 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2212 ch, 2213 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2214 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2215 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2216 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2217 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2218 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2219 fwohcicode[stat & 0x1f], 2220 stat & 0x1f 2221 ); 2222 }else{ 2223 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2224 } 2225} 2226 2227void 2228dump_db(struct fwohci_softc *sc, u_int32_t ch) 2229{ 2230 struct fwohci_dbch *dbch; 2231 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2232 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2233 int idb, jdb; 2234 u_int32_t cmd, off; 2235 if(ch == 0){ 2236 off = OHCI_ATQOFF; 2237 dbch = &sc->atrq; 2238 }else if(ch == 1){ 2239 off = OHCI_ATSOFF; 2240 dbch = &sc->atrs; 2241 }else if(ch == 2){ 2242 off = OHCI_ARQOFF; 2243 dbch = &sc->arrq; 2244 }else if(ch == 3){ 2245 off = OHCI_ARSOFF; 2246 dbch = &sc->arrs; 2247 }else if(ch < IRX_CH){ 2248 off = OHCI_ITCTL(ch - ITX_CH); 2249 dbch = &sc->it[ch - ITX_CH]; 2250 }else { 2251 off = OHCI_IRCTL(ch - IRX_CH); 2252 dbch = &sc->ir[ch - IRX_CH]; 2253 } 2254 cmd = OREAD(sc, off + 0xc); 2255 2256 if( dbch->ndb == 0 ){ 2257 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2258 return; 2259 } 2260 pp = dbch->top; 2261 prev = pp->db; 2262 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2263 if(pp == NULL){ 2264 curr = NULL; 2265 goto outdb; 2266 } 2267 cp = STAILQ_NEXT(pp, link); 2268 if(cp == NULL){ 2269 curr = NULL; 2270 goto outdb; 2271 } 2272 np = STAILQ_NEXT(cp, link); 2273 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2274 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2275 curr = cp->db; 2276 if(np != NULL){ 2277 next = np->db; 2278 }else{ 2279 next = NULL; 2280 } 2281 goto outdb; 2282 } 2283 } 2284 pp = STAILQ_NEXT(pp, link); 2285 prev = pp->db; 2286 } 2287outdb: 2288 if( curr != NULL){ 2289#if 0 2290 printf("Prev DB %d\n", ch); 2291 print_db(pp, prev, ch, dbch->ndesc); 2292#endif 2293 printf("Current DB %d\n", ch); 2294 print_db(cp, curr, ch, dbch->ndesc); 2295#if 0 2296 printf("Next DB %d\n", ch); 2297 print_db(np, next, ch, dbch->ndesc); 2298#endif 2299 }else{ 2300 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2301 } 2302 return; 2303} 2304 2305void 2306print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2307 u_int32_t ch, u_int32_t max) 2308{ 2309 fwohcireg_t stat; 2310 int i, key; 2311 u_int32_t cmd, res; 2312 2313 if(db == NULL){ 2314 printf("No Descriptor is found\n"); 2315 return; 2316 } 2317 2318 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2319 ch, 2320 "Current", 2321 "OP ", 2322 "KEY", 2323 "INT", 2324 "BR ", 2325 "len", 2326 "Addr", 2327 "Depend", 2328 "Stat", 2329 "Cnt"); 2330 for( i = 0 ; i <= max ; i ++){ 2331 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2332 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2333 key = cmd & OHCI_KEY_MASK; 2334 stat = res >> OHCI_STATUS_SHIFT; 2335#if __FreeBSD_version >= 500000 2336 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2337 (uintmax_t)db_tr->bus_addr, 2338#else 2339 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2340 db_tr->bus_addr, 2341#endif 2342 dbcode[(cmd >> 28) & 0xf], 2343 dbkey[(cmd >> 24) & 0x7], 2344 dbcond[(cmd >> 20) & 0x3], 2345 dbcond[(cmd >> 18) & 0x3], 2346 cmd & OHCI_COUNT_MASK, 2347 FWOHCI_DMA_READ(db[i].db.desc.addr), 2348 FWOHCI_DMA_READ(db[i].db.desc.depend), 2349 stat, 2350 res & OHCI_COUNT_MASK); 2351 if(stat & 0xff00){ 2352 printf(" %s%s%s%s%s%s %s(%x)\n", 2353 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2354 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2355 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2356 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2357 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2358 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2359 fwohcicode[stat & 0x1f], 2360 stat & 0x1f 2361 ); 2362 }else{ 2363 printf(" Nostat\n"); 2364 } 2365 if(key == OHCI_KEY_ST2 ){ 2366 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2367 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2368 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2369 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2370 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2371 } 2372 if(key == OHCI_KEY_DEVICE){ 2373 return; 2374 } 2375 if((cmd & OHCI_BRANCH_MASK) 2376 == OHCI_BRANCH_ALWAYS){ 2377 return; 2378 } 2379 if((cmd & OHCI_CMD_MASK) 2380 == OHCI_OUTPUT_LAST){ 2381 return; 2382 } 2383 if((cmd & OHCI_CMD_MASK) 2384 == OHCI_INPUT_LAST){ 2385 return; 2386 } 2387 if(key == OHCI_KEY_ST2 ){ 2388 i++; 2389 } 2390 } 2391 return; 2392} 2393 2394void 2395fwohci_ibr(struct firewire_comm *fc) 2396{ 2397 struct fwohci_softc *sc; 2398 u_int32_t fun; 2399 2400 device_printf(fc->dev, "Initiate bus reset\n"); 2401 sc = (struct fwohci_softc *)fc; 2402 2403 /* 2404 * Set root hold-off bit so that non cyclemaster capable node 2405 * shouldn't became the root node. 2406 */ 2407#if 1 2408 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2409 fun |= FW_PHY_IBR | FW_PHY_RHB; 2410 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2411#else /* Short bus reset */ 2412 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2413 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2414 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2415#endif 2416} 2417 2418void 2419fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2420{ 2421 struct fwohcidb_tr *db_tr, *fdb_tr; 2422 struct fwohci_dbch *dbch; 2423 volatile struct fwohcidb *db; 2424 struct fw_pkt *fp; 2425 volatile struct fwohci_txpkthdr *ohcifp; 2426 unsigned short chtag; 2427 int idb; 2428 2429 dbch = &sc->it[dmach]; 2430 chtag = sc->it[dmach].xferq.flag & 0xff; 2431 2432 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2433 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2434/* 2435device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2436*/ 2437 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2438 db = db_tr->db; 2439 fp = (struct fw_pkt *)db_tr->buf; 2440 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2441 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2442 ohcifp->mode.stream.len = fp->mode.stream.len; 2443 ohcifp->mode.stream.chtag = chtag; 2444 ohcifp->mode.stream.tcode = 0xa; 2445 ohcifp->mode.stream.spd = 0; 2446#if BYTE_ORDER == BIG_ENDIAN 2447 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2448 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2449#endif 2450 2451 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2452 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2453 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2454#if 0 /* if bulkxfer->npackets changes */ 2455 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2456 | OHCI_UPDATE 2457 | OHCI_BRANCH_ALWAYS; 2458 db[0].db.desc.depend = 2459 = db[dbch->ndesc - 1].db.desc.depend 2460 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2461#else 2462 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2463 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2464#endif 2465 bulkxfer->end = (caddr_t)db_tr; 2466 db_tr = STAILQ_NEXT(db_tr, link); 2467 } 2468 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2469 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2470 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2471#if 0 /* if bulkxfer->npackets changes */ 2472 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2473 /* OHCI 1.1 and above */ 2474 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2475#endif 2476/* 2477 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2478 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2479device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2480*/ 2481 return; 2482} 2483 2484static int 2485fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2486 int poffset) 2487{ 2488 volatile struct fwohcidb *db = db_tr->db; 2489 struct fw_xferq *it; 2490 int err = 0; 2491 2492 it = &dbch->xferq; 2493 if(it->buf == 0){ 2494 err = EINVAL; 2495 return err; 2496 } 2497 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2498 db_tr->dbcnt = 3; 2499 2500 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2501 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2502 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2503 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2504 2505 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2506 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2507#if 1 2508 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2509 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2510#endif 2511 return 0; 2512} 2513 2514int 2515fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2516 int poffset, struct fwdma_alloc *dummy_dma) 2517{ 2518 volatile struct fwohcidb *db = db_tr->db; 2519 struct fw_xferq *ir; 2520 int i, ldesc; 2521 bus_addr_t dbuf[2]; 2522 int dsiz[2]; 2523 2524 ir = &dbch->xferq; 2525 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2526 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2527 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2528 if (db_tr->buf == NULL) 2529 return(ENOMEM); 2530 db_tr->dbcnt = 1; 2531 dsiz[0] = ir->psize; 2532 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2533 BUS_DMASYNC_PREREAD); 2534 } else { 2535 db_tr->dbcnt = 0; 2536 if (dummy_dma != NULL) { 2537 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2538 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2539 } 2540 dsiz[db_tr->dbcnt] = ir->psize; 2541 if (ir->buf != NULL) { 2542 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2543 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2544 } 2545 db_tr->dbcnt++; 2546 } 2547 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2548 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2549 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2550 if (ir->flag & FWXFERQ_STREAM) { 2551 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2552 } 2553 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2554 } 2555 ldesc = db_tr->dbcnt - 1; 2556 if (ir->flag & FWXFERQ_STREAM) { 2557 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2558 } 2559 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2560 return 0; 2561} 2562 2563 2564static int 2565fwohci_arcv_swap(struct fw_pkt *fp, int len) 2566{ 2567 struct fw_pkt *fp0; 2568 u_int32_t ld0; 2569 int slen; 2570#if BYTE_ORDER == BIG_ENDIAN 2571 int i; 2572#endif 2573 2574 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2575#if 0 2576 printf("ld0: x%08x\n", ld0); 2577#endif 2578 fp0 = (struct fw_pkt *)&ld0; 2579 switch (fp0->mode.common.tcode) { 2580 case FWTCODE_RREQQ: 2581 case FWTCODE_WRES: 2582 case FWTCODE_WREQQ: 2583 case FWTCODE_RRESQ: 2584 case FWOHCITCODE_PHY: 2585 slen = 12; 2586 break; 2587 case FWTCODE_RREQB: 2588 case FWTCODE_WREQB: 2589 case FWTCODE_LREQ: 2590 case FWTCODE_RRESB: 2591 case FWTCODE_LRES: 2592 slen = 16; 2593 break; 2594 default: 2595 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2596 return(0); 2597 } 2598 if (slen > len) { 2599 if (firewire_debug) 2600 printf("splitted header\n"); 2601 return(-slen); 2602 } 2603#if BYTE_ORDER == BIG_ENDIAN 2604 for(i = 0; i < slen/4; i ++) 2605 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2606#endif 2607 return(slen); 2608} 2609 2610#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2611static int 2612fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2613{ 2614 int r; 2615 2616 switch(fp->mode.common.tcode){ 2617 case FWTCODE_RREQQ: 2618 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2619 break; 2620 case FWTCODE_WRES: 2621 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2622 break; 2623 case FWTCODE_WREQQ: 2624 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2625 break; 2626 case FWTCODE_RREQB: 2627 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2628 break; 2629 case FWTCODE_RRESQ: 2630 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2631 break; 2632 case FWTCODE_WREQB: 2633 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2634 + sizeof(u_int32_t); 2635 break; 2636 case FWTCODE_LREQ: 2637 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2638 + sizeof(u_int32_t); 2639 break; 2640 case FWTCODE_RRESB: 2641 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2642 + sizeof(u_int32_t); 2643 break; 2644 case FWTCODE_LRES: 2645 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2646 + sizeof(u_int32_t); 2647 break; 2648 case FWOHCITCODE_PHY: 2649 r = 16; 2650 break; 2651 default: 2652 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2653 fp->mode.common.tcode); 2654 r = 0; 2655 } 2656 if (r > dbch->xferq.psize) { 2657 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2658 /* panic ? */ 2659 } 2660 return r; 2661} 2662 2663static void 2664fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2665{ 2666 volatile struct fwohcidb *db = &db_tr->db[0]; 2667 2668 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2669 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2670 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2671 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2672 dbch->bottom = db_tr; 2673} 2674 2675static void 2676fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2677{ 2678 struct fwohcidb_tr *db_tr; 2679 struct iovec vec[2]; 2680 struct fw_pkt pktbuf; 2681 int nvec; 2682 struct fw_pkt *fp; 2683 u_int8_t *ld; 2684 u_int32_t stat, off, status; 2685 u_int spd; 2686 int len, plen, hlen, pcnt, offset; 2687 int s; 2688 caddr_t buf; 2689 int resCount; 2690 2691 if(&sc->arrq == dbch){ 2692 off = OHCI_ARQOFF; 2693 }else if(&sc->arrs == dbch){ 2694 off = OHCI_ARSOFF; 2695 }else{ 2696 return; 2697 } 2698 2699 s = splfw(); 2700 db_tr = dbch->top; 2701 pcnt = 0; 2702 /* XXX we cannot handle a packet which lies in more than two buf */ 2703 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2704 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2705 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2706 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2707#if 0 2708 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2709#endif 2710 while (status & OHCI_CNTL_DMA_ACTIVE) { 2711 len = dbch->xferq.psize - resCount; 2712 ld = (u_int8_t *)db_tr->buf; 2713 if (dbch->pdb_tr == NULL) { 2714 len -= dbch->buf_offset; 2715 ld += dbch->buf_offset; 2716 } 2717 if (len > 0) 2718 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2719 BUS_DMASYNC_POSTREAD); 2720 while (len > 0 ) { 2721 if (count >= 0 && count-- == 0) 2722 goto out; 2723 if(dbch->pdb_tr != NULL){ 2724 /* we have a fragment in previous buffer */ 2725 int rlen; 2726 2727 offset = dbch->buf_offset; 2728 if (offset < 0) 2729 offset = - offset; 2730 buf = dbch->pdb_tr->buf + offset; 2731 rlen = dbch->xferq.psize - offset; 2732 if (firewire_debug) 2733 printf("rlen=%d, offset=%d\n", 2734 rlen, dbch->buf_offset); 2735 if (dbch->buf_offset < 0) { 2736 /* splitted in header, pull up */ 2737 char *p; 2738 2739 p = (char *)&pktbuf; 2740 bcopy(buf, p, rlen); 2741 p += rlen; 2742 /* this must be too long but harmless */ 2743 rlen = sizeof(pktbuf) - rlen; 2744 if (rlen < 0) 2745 printf("why rlen < 0\n"); 2746 bcopy(db_tr->buf, p, rlen); 2747 ld += rlen; 2748 len -= rlen; 2749 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2750 if (hlen < 0) { 2751 printf("hlen < 0 shouldn't happen"); 2752 } 2753 offset = sizeof(pktbuf); 2754 vec[0].iov_base = (char *)&pktbuf; 2755 vec[0].iov_len = offset; 2756 } else { 2757 /* splitted in payload */ 2758 offset = rlen; 2759 vec[0].iov_base = buf; 2760 vec[0].iov_len = rlen; 2761 } 2762 fp=(struct fw_pkt *)vec[0].iov_base; 2763 nvec = 1; 2764 } else { 2765 /* no fragment in previous buffer */ 2766 fp=(struct fw_pkt *)ld; 2767 hlen = fwohci_arcv_swap(fp, len); 2768 if (hlen == 0) 2769 /* XXX need reset */ 2770 goto out; 2771 if (hlen < 0) { 2772 dbch->pdb_tr = db_tr; 2773 dbch->buf_offset = - dbch->buf_offset; 2774 /* sanity check */ 2775 if (resCount != 0) 2776 printf("resCount != 0 !?\n"); 2777 goto out; 2778 } 2779 offset = 0; 2780 nvec = 0; 2781 } 2782 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2783 if (plen < 0) { 2784 /* minimum header size + trailer 2785 = sizeof(fw_pkt) so this shouldn't happens */ 2786 printf("plen is negative! offset=%d\n", offset); 2787 goto out; 2788 } 2789 if (plen > 0) { 2790 len -= plen; 2791 if (len < 0) { 2792 dbch->pdb_tr = db_tr; 2793 if (firewire_debug) 2794 printf("splitted payload\n"); 2795 /* sanity check */ 2796 if (resCount != 0) 2797 printf("resCount != 0 !?\n"); 2798 goto out; 2799 } 2800 vec[nvec].iov_base = ld; 2801 vec[nvec].iov_len = plen; 2802 nvec ++; 2803 ld += plen; 2804 } 2805 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2806 if (nvec == 0) 2807 printf("nvec == 0\n"); 2808 2809/* DMA result-code will be written at the tail of packet */ 2810#if BYTE_ORDER == BIG_ENDIAN 2811 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2812#else 2813 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2814#endif 2815#if 0 2816 printf("plen: %d, stat %x\n", plen ,stat); 2817#endif 2818 spd = (stat >> 5) & 0x3; 2819 stat &= 0x1f; 2820 switch(stat){ 2821 case FWOHCIEV_ACKPEND: 2822#if 0 2823 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2824#endif 2825 /* fall through */ 2826 case FWOHCIEV_ACKCOMPL: 2827 if ((vec[nvec-1].iov_len -= 2828 sizeof(struct fwohci_trailer)) == 0) 2829 nvec--; 2830 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2831 break; 2832 case FWOHCIEV_BUSRST: 2833 if (sc->fc.status != FWBUSRESET) 2834 printf("got BUSRST packet!?\n"); 2835 break; 2836 default: 2837 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2838#if 0 /* XXX */ 2839 goto out; 2840#endif 2841 break; 2842 } 2843 pcnt ++; 2844 if (dbch->pdb_tr != NULL) { 2845 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2846 dbch->pdb_tr = NULL; 2847 } 2848 2849 } 2850out: 2851 if (resCount == 0) { 2852 /* done on this buffer */ 2853 if (dbch->pdb_tr == NULL) { 2854 fwohci_arcv_free_buf(dbch, db_tr); 2855 dbch->buf_offset = 0; 2856 } else 2857 if (dbch->pdb_tr != db_tr) 2858 printf("pdb_tr != db_tr\n"); 2859 db_tr = STAILQ_NEXT(db_tr, link); 2860 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2861 >> OHCI_STATUS_SHIFT; 2862 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2863 & OHCI_COUNT_MASK; 2864 /* XXX check buffer overrun */ 2865 dbch->top = db_tr; 2866 } else { 2867 dbch->buf_offset = dbch->xferq.psize - resCount; 2868 break; 2869 } 2870 /* XXX make sure DMA is not dead */ 2871 } 2872#if 0 2873 if (pcnt < 1) 2874 printf("fwohci_arcv: no packets\n"); 2875#endif 2876 splx(s); 2877} 2878