fwohci.c revision 117126
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 117126 2003-07-01 15:52:06Z scottl $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/proc.h> 47#include <sys/systm.h> 48#include <sys/types.h> 49#include <sys/mbuf.h> 50#include <sys/mman.h> 51#include <sys/socket.h> 52#include <sys/socketvar.h> 53#include <sys/signalvar.h> 54#include <sys/malloc.h> 55#include <sys/sockio.h> 56#include <sys/bus.h> 57#include <sys/kernel.h> 58#include <sys/conf.h> 59#include <sys/endian.h> 60 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/rman.h> 64 65#if __FreeBSD_version < 500000 66#include <machine/clock.h> /* for DELAY() */ 67#endif 68 69#include <pci/pcivar.h> 70#include <pci/pcireg.h> 71 72#include <dev/firewire/firewire.h> 73#include <dev/firewire/firewirereg.h> 74#include <dev/firewire/fwdma.h> 75#include <dev/firewire/fwohcireg.h> 76#include <dev/firewire/fwohcivar.h> 77#include <dev/firewire/firewire_phy.h> 78 79#include <dev/firewire/iec68113.h> 80 81#undef OHCI_DEBUG 82 83static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 84 "STOR","LOAD","NOP ","STOP",}; 85 86static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 87 "UNDEF","REG","SYS","DEV"}; 88static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 89char fwohcicode[32][0x20]={ 90 "No stat","Undef","long","miss Ack err", 91 "underrun","overrun","desc err", "data read err", 92 "data write err","bus reset","timeout","tcode err", 93 "Undef","Undef","unknown event","flushed", 94 "Undef","ack complete","ack pend","Undef", 95 "ack busy_X","ack busy_A","ack busy_B","Undef", 96 "Undef","Undef","Undef","ack tardy", 97 "Undef","ack data_err","ack type_err",""}; 98 99#define MAX_SPEED 3 100extern char linkspeed[][0x10]; 101u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 102 103static struct tcode_info tinfo[] = { 104/* hdr_len block flag*/ 105/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 106/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 107/* 2 WRES */ {12, FWTI_RES}, 108/* 3 XXX */ { 0, 0}, 109/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 110/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 111/* 6 RRESQ */ {16, FWTI_RES}, 112/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* 8 CYCS */ { 0, 0}, 114/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 115/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 116/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 117/* c XXX */ { 0, 0}, 118/* d XXX */ { 0, 0}, 119/* e PHY */ {12, FWTI_REQ}, 120/* f XXX */ { 0, 0} 121}; 122 123#define OHCI_WRITE_SIGMASK 0xffff0000 124#define OHCI_READ_SIGMASK 0xffff0000 125 126#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 127#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 128 129static void fwohci_ibr __P((struct firewire_comm *)); 130static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_db_free __P((struct fwohci_dbch *)); 132static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 133static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_start_atq __P((struct firewire_comm *)); 135static void fwohci_start_ats __P((struct firewire_comm *)); 136static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irx_disable __P((struct firewire_comm *, int)); 143#if BYTE_ORDER == BIG_ENDIAN 144static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 145#endif 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_set_intr __P((struct firewire_comm *, int)); 150 151static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 152static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160#if FWOHCI_TASKQUEUE 161static void fwohci_complete(void *, int); 162#endif 163 164/* 165 * memory allocated for DMA programs 166 */ 167#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 168 169/* #define NDB 1024 */ 170#define NDB FWMAXQUEUE 171#define NDVDB (DVBUF * NDB) 172 173#define OHCI_VERSION 0x00 174#define OHCI_ATRETRY 0x08 175#define OHCI_CROMHDR 0x18 176#define OHCI_BUS_OPT 0x20 177#define OHCI_BUSIRMC (1 << 31) 178#define OHCI_BUSCMC (1 << 30) 179#define OHCI_BUSISC (1 << 29) 180#define OHCI_BUSBMC (1 << 28) 181#define OHCI_BUSPMC (1 << 27) 182#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 183 OHCI_BUSBMC | OHCI_BUSPMC 184 185#define OHCI_EUID_HI 0x24 186#define OHCI_EUID_LO 0x28 187 188#define OHCI_CROMPTR 0x34 189#define OHCI_HCCCTL 0x50 190#define OHCI_HCCCTLCLR 0x54 191#define OHCI_AREQHI 0x100 192#define OHCI_AREQHICLR 0x104 193#define OHCI_AREQLO 0x108 194#define OHCI_AREQLOCLR 0x10c 195#define OHCI_PREQHI 0x110 196#define OHCI_PREQHICLR 0x114 197#define OHCI_PREQLO 0x118 198#define OHCI_PREQLOCLR 0x11c 199#define OHCI_PREQUPPER 0x120 200 201#define OHCI_SID_BUF 0x64 202#define OHCI_SID_CNT 0x68 203#define OHCI_SID_ERR (1 << 31) 204#define OHCI_SID_CNT_MASK 0xffc 205 206#define OHCI_IT_STAT 0x90 207#define OHCI_IT_STATCLR 0x94 208#define OHCI_IT_MASK 0x98 209#define OHCI_IT_MASKCLR 0x9c 210 211#define OHCI_IR_STAT 0xa0 212#define OHCI_IR_STATCLR 0xa4 213#define OHCI_IR_MASK 0xa8 214#define OHCI_IR_MASKCLR 0xac 215 216#define OHCI_LNKCTL 0xe0 217#define OHCI_LNKCTLCLR 0xe4 218 219#define OHCI_PHYACCESS 0xec 220#define OHCI_CYCLETIMER 0xf0 221 222#define OHCI_DMACTL(off) (off) 223#define OHCI_DMACTLCLR(off) (off + 4) 224#define OHCI_DMACMD(off) (off + 0xc) 225#define OHCI_DMAMATCH(off) (off + 0x10) 226 227#define OHCI_ATQOFF 0x180 228#define OHCI_ATQCTL OHCI_ATQOFF 229#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 230#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 231#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 232 233#define OHCI_ATSOFF 0x1a0 234#define OHCI_ATSCTL OHCI_ATSOFF 235#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 236#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 237#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 238 239#define OHCI_ARQOFF 0x1c0 240#define OHCI_ARQCTL OHCI_ARQOFF 241#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 242#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 243#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 244 245#define OHCI_ARSOFF 0x1e0 246#define OHCI_ARSCTL OHCI_ARSOFF 247#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 248#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 249#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 250 251#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 252#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 253#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 254#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 255 256#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 257#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 258#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 259#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 260#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 261 262d_ioctl_t fwohci_ioctl; 263 264/* 265 * Communication with PHY device 266 */ 267static u_int32_t 268fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 269{ 270 u_int32_t fun; 271 272 addr &= 0xf; 273 data &= 0xff; 274 275 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 276 OWRITE(sc, OHCI_PHYACCESS, fun); 277 DELAY(100); 278 279 return(fwphy_rddata( sc, addr)); 280} 281 282static u_int32_t 283fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 284{ 285 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 286 int i; 287 u_int32_t bm; 288 289#define OHCI_CSR_DATA 0x0c 290#define OHCI_CSR_COMP 0x10 291#define OHCI_CSR_CONT 0x14 292#define OHCI_BUS_MANAGER_ID 0 293 294 OWRITE(sc, OHCI_CSR_DATA, node); 295 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 296 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 297 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 298 DELAY(10); 299 bm = OREAD(sc, OHCI_CSR_DATA); 300 if((bm & 0x3f) == 0x3f) 301 bm = node; 302 if (bootverbose) 303 device_printf(sc->fc.dev, 304 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 305 306 return(bm); 307} 308 309static u_int32_t 310fwphy_rddata(struct fwohci_softc *sc, u_int addr) 311{ 312 u_int32_t fun, stat; 313 u_int i, retry = 0; 314 315 addr &= 0xf; 316#define MAX_RETRY 100 317again: 318 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 319 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 320 OWRITE(sc, OHCI_PHYACCESS, fun); 321 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 322 fun = OREAD(sc, OHCI_PHYACCESS); 323 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 324 break; 325 DELAY(100); 326 } 327 if(i >= MAX_RETRY) { 328 if (bootverbose) 329 device_printf(sc->fc.dev, "phy read failed(1).\n"); 330 if (++retry < MAX_RETRY) { 331 DELAY(100); 332 goto again; 333 } 334 } 335 /* Make sure that SCLK is started */ 336 stat = OREAD(sc, FWOHCI_INTSTAT); 337 if ((stat & OHCI_INT_REG_FAIL) != 0 || 338 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 339 if (bootverbose) 340 device_printf(sc->fc.dev, "phy read failed(2).\n"); 341 if (++retry < MAX_RETRY) { 342 DELAY(100); 343 goto again; 344 } 345 } 346 if (bootverbose || retry >= MAX_RETRY) 347 device_printf(sc->fc.dev, 348 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 349#undef MAX_RETRY 350 return((fun >> PHYDEV_RDDATA )& 0xff); 351} 352/* Device specific ioctl. */ 353int 354fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 355{ 356 struct firewire_softc *sc; 357 struct fwohci_softc *fc; 358 int unit = DEV2UNIT(dev); 359 int err = 0; 360 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 361 u_int32_t *dmach = (u_int32_t *) data; 362 363 sc = devclass_get_softc(firewire_devclass, unit); 364 if(sc == NULL){ 365 return(EINVAL); 366 } 367 fc = (struct fwohci_softc *)sc->fc; 368 369 if (!data) 370 return(EINVAL); 371 372 switch (cmd) { 373 case FWOHCI_WRREG: 374#define OHCI_MAX_REG 0x800 375 if(reg->addr <= OHCI_MAX_REG){ 376 OWRITE(fc, reg->addr, reg->data); 377 reg->data = OREAD(fc, reg->addr); 378 }else{ 379 err = EINVAL; 380 } 381 break; 382 case FWOHCI_RDREG: 383 if(reg->addr <= OHCI_MAX_REG){ 384 reg->data = OREAD(fc, reg->addr); 385 }else{ 386 err = EINVAL; 387 } 388 break; 389/* Read DMA descriptors for debug */ 390 case DUMPDMA: 391 if(*dmach <= OHCI_MAX_DMA_CH ){ 392 dump_dma(fc, *dmach); 393 dump_db(fc, *dmach); 394 }else{ 395 err = EINVAL; 396 } 397 break; 398 default: 399 break; 400 } 401 return err; 402} 403 404static int 405fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406{ 407 u_int32_t reg, reg2; 408 int e1394a = 1; 409/* 410 * probe PHY parameters 411 * 0. to prove PHY version, whether compliance of 1394a. 412 * 1. to probe maximum speed supported by the PHY and 413 * number of port supported by core-logic. 414 * It is not actually available port on your PC . 415 */ 416 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447#if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449#else /* XXX force to enable 1394a */ 450 if (e1394a) { 451#endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475} 476 477 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 555 /* AT Retries */ 556 OWRITE(sc, FWOHCI_RETRY, 557 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559 560 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562 sc->atrq.bottom = sc->atrq.top; 563 sc->atrs.bottom = sc->atrs.top; 564 565 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567 db_tr->xfer = NULL; 568 } 569 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571 db_tr->xfer = NULL; 572 } 573 574 575 /* Enable interrupt */ 576 OWRITE(sc, FWOHCI_INTMASK, 577 OHCI_INT_ERR | OHCI_INT_PHY_SID 578 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581 fwohci_set_intr(&sc->fc, 1); 582 583} 584 585int 586fwohci_init(struct fwohci_softc *sc, device_t dev) 587{ 588 int i; 589 u_int32_t reg; 590 u_int8_t ui[8]; 591 592#if FWOHCI_TASKQUEUE 593 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594#endif 595 596 reg = OREAD(sc, OHCI_VERSION); 597 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 598 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 599 600/* Available Isochrounous DMA channel probe */ 601 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 602 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 603 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 604 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 605 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 606 for (i = 0; i < 0x20; i++) 607 if ((reg & (1 << i)) == 0) 608 break; 609 sc->fc.nisodma = i; 610 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 611 612 sc->fc.arq = &sc->arrq.xferq; 613 sc->fc.ars = &sc->arrs.xferq; 614 sc->fc.atq = &sc->atrq.xferq; 615 sc->fc.ats = &sc->atrs.xferq; 616 617 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 618 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 619 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 620 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 621 622 sc->arrq.xferq.start = NULL; 623 sc->arrs.xferq.start = NULL; 624 sc->atrq.xferq.start = fwohci_start_atq; 625 sc->atrs.xferq.start = fwohci_start_ats; 626 627 sc->arrq.xferq.buf = NULL; 628 sc->arrs.xferq.buf = NULL; 629 sc->atrq.xferq.buf = NULL; 630 sc->atrs.xferq.buf = NULL; 631 632 sc->arrq.ndesc = 1; 633 sc->arrs.ndesc = 1; 634 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 635 sc->atrs.ndesc = 2; 636 637 sc->arrq.ndb = NDB; 638 sc->arrs.ndb = NDB / 2; 639 sc->atrq.ndb = NDB; 640 sc->atrs.ndb = NDB / 2; 641 642 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 643 sc->fc.it[i] = &sc->it[i].xferq; 644 sc->fc.ir[i] = &sc->ir[i].xferq; 645 sc->it[i].ndb = 0; 646 sc->ir[i].ndb = 0; 647 } 648 649 sc->fc.tcode = tinfo; 650 sc->fc.dev = dev; 651 652 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 653 &sc->crom_dma, BUS_DMA_WAITOK); 654 if(sc->fc.config_rom == NULL){ 655 device_printf(dev, "config_rom alloc failed."); 656 return ENOMEM; 657 } 658 659#if 0 660 bzero(&sc->fc.config_rom[0], CROMSIZE); 661 sc->fc.config_rom[1] = 0x31333934; 662 sc->fc.config_rom[2] = 0xf000a002; 663 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 664 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 665 sc->fc.config_rom[5] = 0; 666 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 667 668 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 669#endif 670 671 672/* SID recieve buffer must allign 2^11 */ 673#define OHCI_SIDSIZE (1 << 11) 674 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 675 &sc->sid_dma, BUS_DMA_WAITOK); 676 if (sc->sid_buf == NULL) { 677 device_printf(dev, "sid_buf alloc failed."); 678 return ENOMEM; 679 } 680 681 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 682 &sc->dummy_dma, BUS_DMA_WAITOK); 683 684 if (sc->dummy_dma.v_addr == NULL) { 685 device_printf(dev, "dummy_dma alloc failed."); 686 return ENOMEM; 687 } 688 689 fwohci_db_init(sc, &sc->arrq); 690 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 691 return ENOMEM; 692 693 fwohci_db_init(sc, &sc->arrs); 694 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 695 return ENOMEM; 696 697 fwohci_db_init(sc, &sc->atrq); 698 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 699 return ENOMEM; 700 701 fwohci_db_init(sc, &sc->atrs); 702 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 703 return ENOMEM; 704 705 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 706 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 707 for( i = 0 ; i < 8 ; i ++) 708 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 709 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 710 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 711 712 sc->fc.ioctl = fwohci_ioctl; 713 sc->fc.cyctimer = fwohci_cyctimer; 714 sc->fc.set_bmr = fwohci_set_bus_manager; 715 sc->fc.ibr = fwohci_ibr; 716 sc->fc.irx_enable = fwohci_irx_enable; 717 sc->fc.irx_disable = fwohci_irx_disable; 718 719 sc->fc.itx_enable = fwohci_itxbuf_enable; 720 sc->fc.itx_disable = fwohci_itx_disable; 721#if BYTE_ORDER == BIG_ENDIAN 722 sc->fc.irx_post = fwohci_irx_post; 723#else 724 sc->fc.irx_post = NULL; 725#endif 726 sc->fc.itx_post = NULL; 727 sc->fc.timeout = fwohci_timeout; 728 sc->fc.poll = fwohci_poll; 729 sc->fc.set_intr = fwohci_set_intr; 730 731 sc->intmask = sc->irstat = sc->itstat = 0; 732 733 fw_init(&sc->fc); 734 fwohci_reset(sc, dev); 735 736 return 0; 737} 738 739void 740fwohci_timeout(void *arg) 741{ 742 struct fwohci_softc *sc; 743 744 sc = (struct fwohci_softc *)arg; 745} 746 747u_int32_t 748fwohci_cyctimer(struct firewire_comm *fc) 749{ 750 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 751 return(OREAD(sc, OHCI_CYCLETIMER)); 752} 753 754int 755fwohci_detach(struct fwohci_softc *sc, device_t dev) 756{ 757 int i; 758 759 if (sc->sid_buf != NULL) 760 fwdma_free(&sc->fc, &sc->sid_dma); 761 if (sc->fc.config_rom != NULL) 762 fwdma_free(&sc->fc, &sc->crom_dma); 763 764 fwohci_db_free(&sc->arrq); 765 fwohci_db_free(&sc->arrs); 766 767 fwohci_db_free(&sc->atrq); 768 fwohci_db_free(&sc->atrs); 769 770 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 771 fwohci_db_free(&sc->it[i]); 772 fwohci_db_free(&sc->ir[i]); 773 } 774 775 return 0; 776} 777 778#define LAST_DB(dbtr, db) do { \ 779 struct fwohcidb_tr *_dbtr = (dbtr); \ 780 int _cnt = _dbtr->dbcnt; \ 781 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 782} while (0) 783 784static void 785fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 786{ 787 struct fwohcidb_tr *db_tr; 788 volatile struct fwohcidb *db; 789 bus_dma_segment_t *s; 790 int i; 791 792 db_tr = (struct fwohcidb_tr *)arg; 793 db = &db_tr->db[db_tr->dbcnt]; 794 if (error) { 795 if (firewire_debug || error != EFBIG) 796 printf("fwohci_execute_db: error=%d\n", error); 797 return; 798 } 799 for (i = 0; i < nseg; i++) { 800 s = &segs[i]; 801 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 802 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 803 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 804 db++; 805 db_tr->dbcnt++; 806 } 807} 808 809static void 810fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 811 bus_size_t size, int error) 812{ 813 fwohci_execute_db(arg, segs, nseg, error); 814} 815 816static void 817fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 818{ 819 int i, s; 820 int tcode, hdr_len, pl_off, pl_len; 821 int fsegment = -1; 822 u_int32_t off; 823 struct fw_xfer *xfer; 824 struct fw_pkt *fp; 825 volatile struct fwohci_txpkthdr *ohcifp; 826 struct fwohcidb_tr *db_tr; 827 volatile struct fwohcidb *db; 828 struct tcode_info *info; 829 static int maxdesc=0; 830 831 if(&sc->atrq == dbch){ 832 off = OHCI_ATQOFF; 833 }else if(&sc->atrs == dbch){ 834 off = OHCI_ATSOFF; 835 }else{ 836 return; 837 } 838 839 if (dbch->flags & FWOHCI_DBCH_FULL) 840 return; 841 842 s = splfw(); 843 db_tr = dbch->top; 844txloop: 845 xfer = STAILQ_FIRST(&dbch->xferq.q); 846 if(xfer == NULL){ 847 goto kick; 848 } 849 if(dbch->xferq.queued == 0 ){ 850 device_printf(sc->fc.dev, "TX queue empty\n"); 851 } 852 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 853 db_tr->xfer = xfer; 854 xfer->state = FWXF_START; 855 856 fp = (struct fw_pkt *)xfer->send.buf; 857 tcode = fp->mode.common.tcode; 858 859 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 860 info = &tinfo[tcode]; 861 hdr_len = pl_off = info->hdr_len; 862 for( i = 0 ; i < pl_off ; i+= 4){ 863 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 864 } 865 ohcifp->mode.common.spd = xfer->spd; 866 if (tcode == FWTCODE_STREAM ){ 867 hdr_len = 8; 868 ohcifp->mode.stream.len = fp->mode.stream.len; 869 } else if (tcode == FWTCODE_PHY) { 870 hdr_len = 12; 871 ohcifp->mode.ld[1] = fp->mode.ld[1]; 872 ohcifp->mode.ld[2] = fp->mode.ld[2]; 873 ohcifp->mode.common.spd = 0; 874 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 875 } else { 876 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 877 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 878 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 879 } 880 db = &db_tr->db[0]; 881 FWOHCI_DMA_WRITE(db->db.desc.cmd, 882 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 883 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 884/* Specify bound timer of asy. responce */ 885 if(&sc->atrs == dbch){ 886 FWOHCI_DMA_WRITE(db->db.desc.res, 887 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 888 } 889#if BYTE_ORDER == BIG_ENDIAN 890 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 891 hdr_len = 12; 892 for (i = 0; i < hdr_len/4; i ++) 893 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 894#endif 895 896again: 897 db_tr->dbcnt = 2; 898 db = &db_tr->db[db_tr->dbcnt]; 899 pl_len = xfer->send.len - pl_off; 900 if (pl_len > 0) { 901 int err; 902 /* handle payload */ 903 if (xfer->mbuf == NULL) { 904 caddr_t pl_addr; 905 906 pl_addr = xfer->send.buf + pl_off; 907 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 908 pl_addr, pl_len, 909 fwohci_execute_db, db_tr, 910 /*flags*/0); 911 } else { 912 /* XXX we can handle only 6 (=8-2) mbuf chains */ 913 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 914 xfer->mbuf, 915 fwohci_execute_db2, db_tr, 916 /* flags */0); 917 if (err == EFBIG) { 918 struct mbuf *m0; 919 920 if (firewire_debug) 921 device_printf(sc->fc.dev, "EFBIG.\n"); 922 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 923 if (m0 != NULL) { 924 m_copydata(xfer->mbuf, 0, 925 xfer->mbuf->m_pkthdr.len, 926 mtod(m0, caddr_t)); 927 m0->m_len = m0->m_pkthdr.len = 928 xfer->mbuf->m_pkthdr.len; 929 m_freem(xfer->mbuf); 930 xfer->mbuf = m0; 931 goto again; 932 } 933 device_printf(sc->fc.dev, "m_getcl failed.\n"); 934 } 935 } 936 if (err) 937 printf("dmamap_load: err=%d\n", err); 938 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 939 BUS_DMASYNC_PREWRITE); 940#if 0 /* OHCI_OUTPUT_MODE == 0 */ 941 for (i = 2; i < db_tr->dbcnt; i++) 942 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 943 OHCI_OUTPUT_MORE); 944#endif 945 } 946 if (maxdesc < db_tr->dbcnt) { 947 maxdesc = db_tr->dbcnt; 948 if (bootverbose) 949 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 950 } 951 /* last db */ 952 LAST_DB(db_tr, db); 953 FWOHCI_DMA_SET(db->db.desc.cmd, 954 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 955 FWOHCI_DMA_WRITE(db->db.desc.depend, 956 STAILQ_NEXT(db_tr, link)->bus_addr); 957 958 if(fsegment == -1 ) 959 fsegment = db_tr->dbcnt; 960 if (dbch->pdb_tr != NULL) { 961 LAST_DB(dbch->pdb_tr, db); 962 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 963 } 964 dbch->pdb_tr = db_tr; 965 db_tr = STAILQ_NEXT(db_tr, link); 966 if(db_tr != dbch->bottom){ 967 goto txloop; 968 } else { 969 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 970 dbch->flags |= FWOHCI_DBCH_FULL; 971 } 972kick: 973 /* kick asy q */ 974 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 975 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 976 977 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 978 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 979 } else { 980 if (bootverbose) 981 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 982 OREAD(sc, OHCI_DMACTL(off))); 983 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 984 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 985 dbch->xferq.flag |= FWXFERQ_RUNNING; 986 } 987 988 dbch->top = db_tr; 989 splx(s); 990 return; 991} 992 993static void 994fwohci_start_atq(struct firewire_comm *fc) 995{ 996 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 997 fwohci_start( sc, &(sc->atrq)); 998 return; 999} 1000 1001static void 1002fwohci_start_ats(struct firewire_comm *fc) 1003{ 1004 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1005 fwohci_start( sc, &(sc->atrs)); 1006 return; 1007} 1008 1009void 1010fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1011{ 1012 int s, ch, err = 0; 1013 struct fwohcidb_tr *tr; 1014 volatile struct fwohcidb *db; 1015 struct fw_xfer *xfer; 1016 u_int32_t off; 1017 u_int stat, status; 1018 int packets; 1019 struct firewire_comm *fc = (struct firewire_comm *)sc; 1020 1021 if(&sc->atrq == dbch){ 1022 off = OHCI_ATQOFF; 1023 ch = ATRQ_CH; 1024 }else if(&sc->atrs == dbch){ 1025 off = OHCI_ATSOFF; 1026 ch = ATRS_CH; 1027 }else{ 1028 return; 1029 } 1030 s = splfw(); 1031 tr = dbch->bottom; 1032 packets = 0; 1033 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1034 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1035 while(dbch->xferq.queued > 0){ 1036 LAST_DB(tr, db); 1037 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1038 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1039 if (fc->status != FWBUSRESET) 1040 /* maybe out of order?? */ 1041 goto out; 1042 } 1043 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1044 BUS_DMASYNC_POSTWRITE); 1045 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1046#if 0 1047 dump_db(sc, ch); 1048#endif 1049 if(status & OHCI_CNTL_DMA_DEAD) { 1050 /* Stop DMA */ 1051 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1052 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1053 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1054 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1055 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1056 } 1057 stat = status & FWOHCIEV_MASK; 1058 switch(stat){ 1059 case FWOHCIEV_ACKPEND: 1060 case FWOHCIEV_ACKCOMPL: 1061 err = 0; 1062 break; 1063 case FWOHCIEV_ACKBSA: 1064 case FWOHCIEV_ACKBSB: 1065 case FWOHCIEV_ACKBSX: 1066 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1067 err = EBUSY; 1068 break; 1069 case FWOHCIEV_FLUSHED: 1070 case FWOHCIEV_ACKTARD: 1071 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1072 err = EAGAIN; 1073 break; 1074 case FWOHCIEV_MISSACK: 1075 case FWOHCIEV_UNDRRUN: 1076 case FWOHCIEV_OVRRUN: 1077 case FWOHCIEV_DESCERR: 1078 case FWOHCIEV_DTRDERR: 1079 case FWOHCIEV_TIMEOUT: 1080 case FWOHCIEV_TCODERR: 1081 case FWOHCIEV_UNKNOWN: 1082 case FWOHCIEV_ACKDERR: 1083 case FWOHCIEV_ACKTERR: 1084 default: 1085 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1086 stat, fwohcicode[stat]); 1087 err = EINVAL; 1088 break; 1089 } 1090 if (tr->xfer != NULL) { 1091 xfer = tr->xfer; 1092 if (xfer->state == FWXF_RCVD) { 1093 if (firewire_debug) 1094 printf("already rcvd\n"); 1095 fw_xfer_done(xfer); 1096 } else { 1097 xfer->state = FWXF_SENT; 1098 if (err == EBUSY && fc->status != FWBUSRESET) { 1099 xfer->state = FWXF_BUSY; 1100 xfer->resp = err; 1101 if (xfer->retry_req != NULL) 1102 xfer->retry_req(xfer); 1103 else { 1104 xfer->recv.len = 0; 1105 fw_xfer_done(xfer); 1106 } 1107 } else if (stat != FWOHCIEV_ACKPEND) { 1108 if (stat != FWOHCIEV_ACKCOMPL) 1109 xfer->state = FWXF_SENTERR; 1110 xfer->resp = err; 1111 xfer->recv.len = 0; 1112 fw_xfer_done(xfer); 1113 } 1114 } 1115 /* 1116 * The watchdog timer takes care of split 1117 * transcation timeout for ACKPEND case. 1118 */ 1119 } else { 1120 printf("this shouldn't happen\n"); 1121 } 1122 dbch->xferq.queued --; 1123 tr->xfer = NULL; 1124 1125 packets ++; 1126 tr = STAILQ_NEXT(tr, link); 1127 dbch->bottom = tr; 1128 if (dbch->bottom == dbch->top) { 1129 /* we reaches the end of context program */ 1130 if (firewire_debug && dbch->xferq.queued > 0) 1131 printf("queued > 0\n"); 1132 break; 1133 } 1134 } 1135out: 1136 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1137 printf("make free slot\n"); 1138 dbch->flags &= ~FWOHCI_DBCH_FULL; 1139 fwohci_start(sc, dbch); 1140 } 1141 splx(s); 1142} 1143 1144static void 1145fwohci_db_free(struct fwohci_dbch *dbch) 1146{ 1147 struct fwohcidb_tr *db_tr; 1148 int idb; 1149 1150 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1151 return; 1152 1153 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1154 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1155 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1156 db_tr->buf != NULL) { 1157 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1158 db_tr->buf, dbch->xferq.psize); 1159 db_tr->buf = NULL; 1160 } else if (db_tr->dma_map != NULL) 1161 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1162 } 1163 dbch->ndb = 0; 1164 db_tr = STAILQ_FIRST(&dbch->db_trq); 1165 fwdma_free_multiseg(dbch->am); 1166 free(db_tr, M_FW); 1167 STAILQ_INIT(&dbch->db_trq); 1168 dbch->flags &= ~FWOHCI_DBCH_INIT; 1169} 1170 1171static void 1172fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1173{ 1174 int idb; 1175 struct fwohcidb_tr *db_tr; 1176 1177 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1178 goto out; 1179 1180 /* create dma_tag for buffers */ 1181#define MAX_REQCOUNT 0xffff 1182 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1183 /*alignment*/ 1, /*boundary*/ 0, 1184 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1185 /*highaddr*/ BUS_SPACE_MAXADDR, 1186 /*filter*/NULL, /*filterarg*/NULL, 1187 /*maxsize*/ dbch->xferq.psize, 1188 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1189 /*maxsegsz*/ MAX_REQCOUNT, 1190 /*flags*/ 0, 1191 /*lockfunc*/busdma_lock_mutex, 1192 /*lockarg*/&Giant, &dbch->dmat)) 1193 return; 1194 1195 /* allocate DB entries and attach one to each DMA channels */ 1196 /* DB entry must start at 16 bytes bounary. */ 1197 STAILQ_INIT(&dbch->db_trq); 1198 db_tr = (struct fwohcidb_tr *) 1199 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1200 M_FW, M_WAITOK | M_ZERO); 1201 if(db_tr == NULL){ 1202 printf("fwohci_db_init: malloc(1) failed\n"); 1203 return; 1204 } 1205 1206#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1207 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1208 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1209 if (dbch->am == NULL) { 1210 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1211 return; 1212 } 1213 /* Attach DB to DMA ch. */ 1214 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1215 db_tr->dbcnt = 0; 1216 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1217 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1218 /* create dmamap for buffers */ 1219 /* XXX do we need 4bytes alignment tag? */ 1220 /* XXX don't alloc dma_map for AR */ 1221 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1222 printf("bus_dmamap_create failed\n"); 1223 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1224 fwohci_db_free(dbch); 1225 return; 1226 } 1227 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1228 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1229 if (idb % dbch->xferq.bnpacket == 0) 1230 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1231 ].start = (caddr_t)db_tr; 1232 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1233 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1234 ].end = (caddr_t)db_tr; 1235 } 1236 db_tr++; 1237 } 1238 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1239 = STAILQ_FIRST(&dbch->db_trq); 1240out: 1241 dbch->xferq.queued = 0; 1242 dbch->pdb_tr = NULL; 1243 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1244 dbch->bottom = dbch->top; 1245 dbch->flags = FWOHCI_DBCH_INIT; 1246} 1247 1248static int 1249fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1250{ 1251 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1252 int sleepch; 1253 1254 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1255 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1256 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1257 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1258 /* XXX we cannot free buffers until the DMA really stops */ 1259 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1260 fwohci_db_free(&sc->it[dmach]); 1261 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1262 return 0; 1263} 1264 1265static int 1266fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1267{ 1268 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1269 int sleepch; 1270 1271 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1272 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1273 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1274 /* XXX we cannot free buffers until the DMA really stops */ 1275 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1276 fwohci_db_free(&sc->ir[dmach]); 1277 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1278 return 0; 1279} 1280 1281#if BYTE_ORDER == BIG_ENDIAN 1282static void 1283fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1284{ 1285 qld[0] = FWOHCI_DMA_READ(qld[0]); 1286 return; 1287} 1288#endif 1289 1290static int 1291fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1292{ 1293 int err = 0; 1294 int idb, z, i, dmach = 0, ldesc; 1295 u_int32_t off = NULL; 1296 struct fwohcidb_tr *db_tr; 1297 volatile struct fwohcidb *db; 1298 1299 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1300 err = EINVAL; 1301 return err; 1302 } 1303 z = dbch->ndesc; 1304 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1305 if( &sc->it[dmach] == dbch){ 1306 off = OHCI_ITOFF(dmach); 1307 break; 1308 } 1309 } 1310 if(off == NULL){ 1311 err = EINVAL; 1312 return err; 1313 } 1314 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1315 return err; 1316 dbch->xferq.flag |= FWXFERQ_RUNNING; 1317 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1318 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1319 } 1320 db_tr = dbch->top; 1321 for (idb = 0; idb < dbch->ndb; idb ++) { 1322 fwohci_add_tx_buf(dbch, db_tr, idb); 1323 if(STAILQ_NEXT(db_tr, link) == NULL){ 1324 break; 1325 } 1326 db = db_tr->db; 1327 ldesc = db_tr->dbcnt - 1; 1328 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1329 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1330 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1331 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1332 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1333 FWOHCI_DMA_SET( 1334 db[ldesc].db.desc.cmd, 1335 OHCI_INTERRUPT_ALWAYS); 1336 /* OHCI 1.1 and above */ 1337 FWOHCI_DMA_SET( 1338 db[0].db.desc.cmd, 1339 OHCI_INTERRUPT_ALWAYS); 1340 } 1341 } 1342 db_tr = STAILQ_NEXT(db_tr, link); 1343 } 1344 FWOHCI_DMA_CLEAR( 1345 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1346 return err; 1347} 1348 1349static int 1350fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1351{ 1352 int err = 0; 1353 int idb, z, i, dmach = 0, ldesc; 1354 u_int32_t off = NULL; 1355 struct fwohcidb_tr *db_tr; 1356 volatile struct fwohcidb *db; 1357 1358 z = dbch->ndesc; 1359 if(&sc->arrq == dbch){ 1360 off = OHCI_ARQOFF; 1361 }else if(&sc->arrs == dbch){ 1362 off = OHCI_ARSOFF; 1363 }else{ 1364 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1365 if( &sc->ir[dmach] == dbch){ 1366 off = OHCI_IROFF(dmach); 1367 break; 1368 } 1369 } 1370 } 1371 if(off == NULL){ 1372 err = EINVAL; 1373 return err; 1374 } 1375 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1376 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1377 return err; 1378 }else{ 1379 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1380 err = EBUSY; 1381 return err; 1382 } 1383 } 1384 dbch->xferq.flag |= FWXFERQ_RUNNING; 1385 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1386 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1387 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1388 } 1389 db_tr = dbch->top; 1390 for (idb = 0; idb < dbch->ndb; idb ++) { 1391 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1392 if (STAILQ_NEXT(db_tr, link) == NULL) 1393 break; 1394 db = db_tr->db; 1395 ldesc = db_tr->dbcnt - 1; 1396 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1397 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1398 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1399 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1400 FWOHCI_DMA_SET( 1401 db[ldesc].db.desc.cmd, 1402 OHCI_INTERRUPT_ALWAYS); 1403 FWOHCI_DMA_CLEAR( 1404 db[ldesc].db.desc.depend, 1405 0xf); 1406 } 1407 } 1408 db_tr = STAILQ_NEXT(db_tr, link); 1409 } 1410 FWOHCI_DMA_CLEAR( 1411 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1412 dbch->buf_offset = 0; 1413 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1414 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1415 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1416 return err; 1417 }else{ 1418 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1419 } 1420 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1421 return err; 1422} 1423 1424static int 1425fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1426{ 1427 int sec, cycle, cycle_match; 1428 1429 cycle = cycle_now & 0x1fff; 1430 sec = cycle_now >> 13; 1431#define CYCLE_MOD 0x10 1432#if 1 1433#define CYCLE_DELAY 8 /* min delay to start DMA */ 1434#else 1435#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1436#endif 1437 cycle = cycle + CYCLE_DELAY; 1438 if (cycle >= 8000) { 1439 sec ++; 1440 cycle -= 8000; 1441 } 1442 cycle = roundup2(cycle, CYCLE_MOD); 1443 if (cycle >= 8000) { 1444 sec ++; 1445 if (cycle == 8000) 1446 cycle = 0; 1447 else 1448 cycle = CYCLE_MOD; 1449 } 1450 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1451 1452 return(cycle_match); 1453} 1454 1455static int 1456fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1457{ 1458 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1459 int err = 0; 1460 unsigned short tag, ich; 1461 struct fwohci_dbch *dbch; 1462 int cycle_match, cycle_now, s, ldesc; 1463 u_int32_t stat; 1464 struct fw_bulkxfer *first, *chunk, *prev; 1465 struct fw_xferq *it; 1466 1467 dbch = &sc->it[dmach]; 1468 it = &dbch->xferq; 1469 1470 tag = (it->flag >> 6) & 3; 1471 ich = it->flag & 0x3f; 1472 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1473 dbch->ndb = it->bnpacket * it->bnchunk; 1474 dbch->ndesc = 3; 1475 fwohci_db_init(sc, dbch); 1476 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1477 return ENOMEM; 1478 err = fwohci_tx_enable(sc, dbch); 1479 } 1480 if(err) 1481 return err; 1482 1483 ldesc = dbch->ndesc - 1; 1484 s = splfw(); 1485 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1486 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1487 volatile struct fwohcidb *db; 1488 1489 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1490 BUS_DMASYNC_PREWRITE); 1491 fwohci_txbufdb(sc, dmach, chunk); 1492 if (prev != NULL) { 1493 db = ((struct fwohcidb_tr *)(prev->end))->db; 1494#if 0 /* XXX necessary? */ 1495 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1496 OHCI_BRANCH_ALWAYS); 1497#endif 1498#if 0 /* if bulkxfer->npacket changes */ 1499 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1500 ((struct fwohcidb_tr *) 1501 (chunk->start))->bus_addr | dbch->ndesc; 1502#else 1503 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1504 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1505#endif 1506 } 1507 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1508 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1509 prev = chunk; 1510 } 1511 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1512 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1513 splx(s); 1514 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1515 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1516 printf("stat 0x%x\n", stat); 1517 1518 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1519 return 0; 1520 1521#if 0 1522 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1523#endif 1524 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1525 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1526 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1527 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1528 1529 first = STAILQ_FIRST(&it->stdma); 1530 OWRITE(sc, OHCI_ITCMD(dmach), 1531 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1532 if (firewire_debug) { 1533 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1534#if 1 1535 dump_dma(sc, ITX_CH + dmach); 1536#endif 1537 } 1538 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1539#if 1 1540 /* Don't start until all chunks are buffered */ 1541 if (STAILQ_FIRST(&it->stfree) != NULL) 1542 goto out; 1543#endif 1544#if 1 1545 /* Clear cycle match counter bits */ 1546 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1547 1548 /* 2bit second + 13bit cycle */ 1549 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1550 cycle_match = fwohci_next_cycle(fc, cycle_now); 1551 1552 OWRITE(sc, OHCI_ITCTL(dmach), 1553 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1554 | OHCI_CNTL_DMA_RUN); 1555#else 1556 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1557#endif 1558 if (firewire_debug) { 1559 printf("cycle_match: 0x%04x->0x%04x\n", 1560 cycle_now, cycle_match); 1561 dump_dma(sc, ITX_CH + dmach); 1562 dump_db(sc, ITX_CH + dmach); 1563 } 1564 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1565 device_printf(sc->fc.dev, 1566 "IT DMA underrun (0x%08x)\n", stat); 1567 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1568 } 1569out: 1570 return err; 1571} 1572 1573static int 1574fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1575{ 1576 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1577 int err = 0, s, ldesc; 1578 unsigned short tag, ich; 1579 u_int32_t stat; 1580 struct fwohci_dbch *dbch; 1581 struct fwohcidb_tr *db_tr; 1582 struct fw_bulkxfer *first, *prev, *chunk; 1583 struct fw_xferq *ir; 1584 1585 dbch = &sc->ir[dmach]; 1586 ir = &dbch->xferq; 1587 1588 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1589 tag = (ir->flag >> 6) & 3; 1590 ich = ir->flag & 0x3f; 1591 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1592 1593 ir->queued = 0; 1594 dbch->ndb = ir->bnpacket * ir->bnchunk; 1595 dbch->ndesc = 2; 1596 fwohci_db_init(sc, dbch); 1597 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1598 return ENOMEM; 1599 err = fwohci_rx_enable(sc, dbch); 1600 } 1601 if(err) 1602 return err; 1603 1604 first = STAILQ_FIRST(&ir->stfree); 1605 if (first == NULL) { 1606 device_printf(fc->dev, "IR DMA no free chunk\n"); 1607 return 0; 1608 } 1609 1610 ldesc = dbch->ndesc - 1; 1611 s = splfw(); 1612 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1613 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1614 volatile struct fwohcidb *db; 1615 1616#if 1 /* XXX for if_fwe */ 1617 if (chunk->mbuf != NULL) { 1618 db_tr = (struct fwohcidb_tr *)(chunk->start); 1619 db_tr->dbcnt = 1; 1620 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1621 chunk->mbuf, fwohci_execute_db2, db_tr, 1622 /* flags */0); 1623 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1624 OHCI_UPDATE | OHCI_INPUT_LAST | 1625 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1626 } 1627#endif 1628 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1629 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1630 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1631 if (prev != NULL) { 1632 db = ((struct fwohcidb_tr *)(prev->end))->db; 1633 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1634 } 1635 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1636 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1637 prev = chunk; 1638 } 1639 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1640 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1641 splx(s); 1642 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1643 if (stat & OHCI_CNTL_DMA_ACTIVE) 1644 return 0; 1645 if (stat & OHCI_CNTL_DMA_RUN) { 1646 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1647 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1648 } 1649 1650 if (firewire_debug) 1651 printf("start IR DMA 0x%x\n", stat); 1652 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1653 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1654 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1655 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1656 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1657 OWRITE(sc, OHCI_IRCMD(dmach), 1658 ((struct fwohcidb_tr *)(first->start))->bus_addr 1659 | dbch->ndesc); 1660 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1661 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1662#if 0 1663 dump_db(sc, IRX_CH + dmach); 1664#endif 1665 return err; 1666} 1667 1668int 1669fwohci_stop(struct fwohci_softc *sc, device_t dev) 1670{ 1671 u_int i; 1672 1673/* Now stopping all DMA channel */ 1674 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1675 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1676 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1677 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1678 1679 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1680 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1681 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1682 } 1683 1684/* FLUSH FIFO and reset Transmitter/Reciever */ 1685 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1686 1687/* Stop interrupt */ 1688 OWRITE(sc, FWOHCI_INTMASKCLR, 1689 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1690 | OHCI_INT_PHY_INT 1691 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1692 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1693 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1694 | OHCI_INT_PHY_BUS_R); 1695 1696 fw_drain_txq(&sc->fc); 1697 1698/* XXX Link down? Bus reset? */ 1699 return 0; 1700} 1701 1702int 1703fwohci_resume(struct fwohci_softc *sc, device_t dev) 1704{ 1705 int i; 1706 struct fw_xferq *ir; 1707 struct fw_bulkxfer *chunk; 1708 1709 fwohci_reset(sc, dev); 1710 /* XXX resume isochronus receive automatically. (how about TX?) */ 1711 for(i = 0; i < sc->fc.nisodma; i ++) { 1712 ir = &sc->ir[i].xferq; 1713 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1714 device_printf(sc->fc.dev, 1715 "resume iso receive ch: %d\n", i); 1716 ir->flag &= ~FWXFERQ_RUNNING; 1717 /* requeue stdma to stfree */ 1718 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1719 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1720 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1721 } 1722 sc->fc.irx_enable(&sc->fc, i); 1723 } 1724 } 1725 1726 bus_generic_resume(dev); 1727 sc->fc.ibr(&sc->fc); 1728 return 0; 1729} 1730 1731#define ACK_ALL 1732static void 1733fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1734{ 1735 u_int32_t irstat, itstat; 1736 u_int i; 1737 struct firewire_comm *fc = (struct firewire_comm *)sc; 1738 1739#ifdef OHCI_DEBUG 1740 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1741 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1742 stat & OHCI_INT_EN ? "DMA_EN ":"", 1743 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1744 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1745 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1746 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1747 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1748 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1749 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1750 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1751 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1752 stat & OHCI_INT_PHY_SID ? "SID ":"", 1753 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1754 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1755 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1756 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1757 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1758 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1759 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1760 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1761 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1762 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1763 stat, OREAD(sc, FWOHCI_INTMASK) 1764 ); 1765#endif 1766/* Bus reset */ 1767 if(stat & OHCI_INT_PHY_BUS_R ){ 1768 if (fc->status == FWBUSRESET) 1769 goto busresetout; 1770 /* Disable bus reset interrupt until sid recv. */ 1771 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1772 1773 device_printf(fc->dev, "BUS reset\n"); 1774 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1775 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1776 1777 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1778 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1779 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1780 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1781 1782#ifndef ACK_ALL 1783 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1784#endif 1785 fw_busreset(fc); 1786 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1787 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1788 } 1789busresetout: 1790 if((stat & OHCI_INT_DMA_IR )){ 1791#ifndef ACK_ALL 1792 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1793#endif 1794#if __FreeBSD_version >= 500000 1795 irstat = atomic_readandclear_int(&sc->irstat); 1796#else 1797 irstat = sc->irstat; 1798 sc->irstat = 0; 1799#endif 1800 for(i = 0; i < fc->nisodma ; i++){ 1801 struct fwohci_dbch *dbch; 1802 1803 if((irstat & (1 << i)) != 0){ 1804 dbch = &sc->ir[i]; 1805 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1806 device_printf(sc->fc.dev, 1807 "dma(%d) not active\n", i); 1808 continue; 1809 } 1810 fwohci_rbuf_update(sc, i); 1811 } 1812 } 1813 } 1814 if((stat & OHCI_INT_DMA_IT )){ 1815#ifndef ACK_ALL 1816 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1817#endif 1818#if __FreeBSD_version >= 500000 1819 itstat = atomic_readandclear_int(&sc->itstat); 1820#else 1821 itstat = sc->itstat; 1822 sc->itstat = 0; 1823#endif 1824 for(i = 0; i < fc->nisodma ; i++){ 1825 if((itstat & (1 << i)) != 0){ 1826 fwohci_tbuf_update(sc, i); 1827 } 1828 } 1829 } 1830 if((stat & OHCI_INT_DMA_PRRS )){ 1831#ifndef ACK_ALL 1832 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1833#endif 1834#if 0 1835 dump_dma(sc, ARRS_CH); 1836 dump_db(sc, ARRS_CH); 1837#endif 1838 fwohci_arcv(sc, &sc->arrs, count); 1839 } 1840 if((stat & OHCI_INT_DMA_PRRQ )){ 1841#ifndef ACK_ALL 1842 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1843#endif 1844#if 0 1845 dump_dma(sc, ARRQ_CH); 1846 dump_db(sc, ARRQ_CH); 1847#endif 1848 fwohci_arcv(sc, &sc->arrq, count); 1849 } 1850 if(stat & OHCI_INT_PHY_SID){ 1851 u_int32_t *buf, node_id; 1852 int plen; 1853 1854#ifndef ACK_ALL 1855 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1856#endif 1857 /* Enable bus reset interrupt */ 1858 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1859 /* Allow async. request to us */ 1860 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1861 /* XXX insecure ?? */ 1862 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1863 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1864 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1865 /* Set ATRetries register */ 1866 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1867/* 1868** Checking whether the node is root or not. If root, turn on 1869** cycle master. 1870*/ 1871 node_id = OREAD(sc, FWOHCI_NODEID); 1872 plen = OREAD(sc, OHCI_SID_CNT); 1873 1874 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1875 node_id, (plen >> 16) & 0xff); 1876 if (!(node_id & OHCI_NODE_VALID)) { 1877 printf("Bus reset failure\n"); 1878 goto sidout; 1879 } 1880 if (node_id & OHCI_NODE_ROOT) { 1881 printf("CYCLEMASTER mode\n"); 1882 OWRITE(sc, OHCI_LNKCTL, 1883 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1884 } else { 1885 printf("non CYCLEMASTER mode\n"); 1886 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1887 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1888 } 1889 fc->nodeid = node_id & 0x3f; 1890 1891 if (plen & OHCI_SID_ERR) { 1892 device_printf(fc->dev, "SID Error\n"); 1893 goto sidout; 1894 } 1895 plen &= OHCI_SID_CNT_MASK; 1896 if (plen < 4 || plen > OHCI_SIDSIZE) { 1897 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1898 goto sidout; 1899 } 1900 plen -= 4; /* chop control info */ 1901 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1902 if (buf == NULL) { 1903 device_printf(fc->dev, "malloc failed\n"); 1904 goto sidout; 1905 } 1906 for (i = 0; i < plen / 4; i ++) 1907 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1908#if 1 1909 /* pending all pre-bus_reset packets */ 1910 fwohci_txd(sc, &sc->atrq); 1911 fwohci_txd(sc, &sc->atrs); 1912 fwohci_arcv(sc, &sc->arrs, -1); 1913 fwohci_arcv(sc, &sc->arrq, -1); 1914 fw_drain_txq(fc); 1915#endif 1916 fw_sidrcv(fc, buf, plen); 1917 free(buf, M_FW); 1918 } 1919sidout: 1920 if((stat & OHCI_INT_DMA_ATRQ )){ 1921#ifndef ACK_ALL 1922 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1923#endif 1924 fwohci_txd(sc, &(sc->atrq)); 1925 } 1926 if((stat & OHCI_INT_DMA_ATRS )){ 1927#ifndef ACK_ALL 1928 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1929#endif 1930 fwohci_txd(sc, &(sc->atrs)); 1931 } 1932 if((stat & OHCI_INT_PW_ERR )){ 1933#ifndef ACK_ALL 1934 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1935#endif 1936 device_printf(fc->dev, "posted write error\n"); 1937 } 1938 if((stat & OHCI_INT_ERR )){ 1939#ifndef ACK_ALL 1940 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1941#endif 1942 device_printf(fc->dev, "unrecoverable error\n"); 1943 } 1944 if((stat & OHCI_INT_PHY_INT)) { 1945#ifndef ACK_ALL 1946 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1947#endif 1948 device_printf(fc->dev, "phy int\n"); 1949 } 1950 1951 return; 1952} 1953 1954#if FWOHCI_TASKQUEUE 1955static void 1956fwohci_complete(void *arg, int pending) 1957{ 1958 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1959 u_int32_t stat; 1960 1961again: 1962 stat = atomic_readandclear_int(&sc->intstat); 1963 if (stat) 1964 fwohci_intr_body(sc, stat, -1); 1965 else 1966 return; 1967 goto again; 1968} 1969#endif 1970 1971static u_int32_t 1972fwochi_check_stat(struct fwohci_softc *sc) 1973{ 1974 u_int32_t stat, irstat, itstat; 1975 1976 stat = OREAD(sc, FWOHCI_INTSTAT); 1977 if (stat == 0xffffffff) { 1978 device_printf(sc->fc.dev, 1979 "device physically ejected?\n"); 1980 return(stat); 1981 } 1982#ifdef ACK_ALL 1983 if (stat) 1984 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1985#endif 1986 if (stat & OHCI_INT_DMA_IR) { 1987 irstat = OREAD(sc, OHCI_IR_STAT); 1988 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1989 atomic_set_int(&sc->irstat, irstat); 1990 } 1991 if (stat & OHCI_INT_DMA_IT) { 1992 itstat = OREAD(sc, OHCI_IT_STAT); 1993 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1994 atomic_set_int(&sc->itstat, itstat); 1995 } 1996 return(stat); 1997} 1998 1999void 2000fwohci_intr(void *arg) 2001{ 2002 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2003 u_int32_t stat; 2004#if !FWOHCI_TASKQUEUE 2005 u_int32_t bus_reset = 0; 2006#endif 2007 2008 if (!(sc->intmask & OHCI_INT_EN)) { 2009 /* polling mode */ 2010 return; 2011 } 2012 2013#if !FWOHCI_TASKQUEUE 2014again: 2015#endif 2016 stat = fwochi_check_stat(sc); 2017 if (stat == 0 || stat == 0xffffffff) 2018 return; 2019#if FWOHCI_TASKQUEUE 2020 atomic_set_int(&sc->intstat, stat); 2021 /* XXX mask bus reset intr. during bus reset phase */ 2022 if (stat) 2023 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2024#else 2025 /* We cannot clear bus reset event during bus reset phase */ 2026 if ((stat & ~bus_reset) == 0) 2027 return; 2028 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2029 fwohci_intr_body(sc, stat, -1); 2030 goto again; 2031#endif 2032} 2033 2034void 2035fwohci_poll(struct firewire_comm *fc, int quick, int count) 2036{ 2037 int s; 2038 u_int32_t stat; 2039 struct fwohci_softc *sc; 2040 2041 2042 sc = (struct fwohci_softc *)fc; 2043 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2044 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2045 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2046#if 0 2047 if (!quick) { 2048#else 2049 if (1) { 2050#endif 2051 stat = fwochi_check_stat(sc); 2052 if (stat == 0 || stat == 0xffffffff) 2053 return; 2054 } 2055 s = splfw(); 2056 fwohci_intr_body(sc, stat, count); 2057 splx(s); 2058} 2059 2060static void 2061fwohci_set_intr(struct firewire_comm *fc, int enable) 2062{ 2063 struct fwohci_softc *sc; 2064 2065 sc = (struct fwohci_softc *)fc; 2066 if (bootverbose) 2067 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2068 if (enable) { 2069 sc->intmask |= OHCI_INT_EN; 2070 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2071 } else { 2072 sc->intmask &= ~OHCI_INT_EN; 2073 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2074 } 2075} 2076 2077static void 2078fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2079{ 2080 struct firewire_comm *fc = &sc->fc; 2081 volatile struct fwohcidb *db; 2082 struct fw_bulkxfer *chunk; 2083 struct fw_xferq *it; 2084 u_int32_t stat, count; 2085 int s, w=0, ldesc; 2086 2087 it = fc->it[dmach]; 2088 ldesc = sc->it[dmach].ndesc - 1; 2089 s = splfw(); /* unnecessary ? */ 2090 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2091 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2092 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2093 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2094 >> OHCI_STATUS_SHIFT; 2095 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2096 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2097 & OHCI_COUNT_MASK; 2098 if (stat == 0) 2099 break; 2100 STAILQ_REMOVE_HEAD(&it->stdma, link); 2101 switch (stat & FWOHCIEV_MASK){ 2102 case FWOHCIEV_ACKCOMPL: 2103#if 0 2104 device_printf(fc->dev, "0x%08x\n", count); 2105#endif 2106 break; 2107 default: 2108 device_printf(fc->dev, 2109 "Isochronous transmit err %02x(%s)\n", 2110 stat, fwohcicode[stat & 0x1f]); 2111 } 2112 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2113 w++; 2114 } 2115 splx(s); 2116 if (w) 2117 wakeup(it); 2118} 2119 2120static void 2121fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2122{ 2123 struct firewire_comm *fc = &sc->fc; 2124 volatile struct fwohcidb_tr *db_tr; 2125 struct fw_bulkxfer *chunk; 2126 struct fw_xferq *ir; 2127 u_int32_t stat; 2128 int s, w=0, ldesc; 2129 2130 ir = fc->ir[dmach]; 2131 ldesc = sc->ir[dmach].ndesc - 1; 2132#if 0 2133 dump_db(sc, dmach); 2134#endif 2135 s = splfw(); 2136 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2137 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2138 db_tr = (struct fwohcidb_tr *)chunk->end; 2139 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2140 >> OHCI_STATUS_SHIFT; 2141 if (stat == 0) 2142 break; 2143 2144 if (chunk->mbuf != NULL) { 2145 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2146 BUS_DMASYNC_POSTREAD); 2147 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2148 } else if (ir->buf != NULL) { 2149 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2150 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2151 } else { 2152 /* XXX */ 2153 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2154 } 2155 2156 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2157 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2158 switch (stat & FWOHCIEV_MASK) { 2159 case FWOHCIEV_ACKCOMPL: 2160 chunk->resp = 0; 2161 break; 2162 default: 2163 chunk->resp = EINVAL; 2164 device_printf(fc->dev, 2165 "Isochronous receive err %02x(%s)\n", 2166 stat, fwohcicode[stat & 0x1f]); 2167 } 2168 w++; 2169 } 2170 splx(s); 2171 if (w) { 2172 if (ir->flag & FWXFERQ_HANDLER) 2173 ir->hand(ir); 2174 else 2175 wakeup(ir); 2176 } 2177} 2178 2179void 2180dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2181{ 2182 u_int32_t off, cntl, stat, cmd, match; 2183 2184 if(ch == 0){ 2185 off = OHCI_ATQOFF; 2186 }else if(ch == 1){ 2187 off = OHCI_ATSOFF; 2188 }else if(ch == 2){ 2189 off = OHCI_ARQOFF; 2190 }else if(ch == 3){ 2191 off = OHCI_ARSOFF; 2192 }else if(ch < IRX_CH){ 2193 off = OHCI_ITCTL(ch - ITX_CH); 2194 }else{ 2195 off = OHCI_IRCTL(ch - IRX_CH); 2196 } 2197 cntl = stat = OREAD(sc, off); 2198 cmd = OREAD(sc, off + 0xc); 2199 match = OREAD(sc, off + 0x10); 2200 2201 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2202 ch, 2203 cntl, 2204 cmd, 2205 match); 2206 stat &= 0xffff ; 2207 if (stat) { 2208 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2209 ch, 2210 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2211 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2212 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2213 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2214 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2215 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2216 fwohcicode[stat & 0x1f], 2217 stat & 0x1f 2218 ); 2219 }else{ 2220 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2221 } 2222} 2223 2224void 2225dump_db(struct fwohci_softc *sc, u_int32_t ch) 2226{ 2227 struct fwohci_dbch *dbch; 2228 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2229 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2230 int idb, jdb; 2231 u_int32_t cmd, off; 2232 if(ch == 0){ 2233 off = OHCI_ATQOFF; 2234 dbch = &sc->atrq; 2235 }else if(ch == 1){ 2236 off = OHCI_ATSOFF; 2237 dbch = &sc->atrs; 2238 }else if(ch == 2){ 2239 off = OHCI_ARQOFF; 2240 dbch = &sc->arrq; 2241 }else if(ch == 3){ 2242 off = OHCI_ARSOFF; 2243 dbch = &sc->arrs; 2244 }else if(ch < IRX_CH){ 2245 off = OHCI_ITCTL(ch - ITX_CH); 2246 dbch = &sc->it[ch - ITX_CH]; 2247 }else { 2248 off = OHCI_IRCTL(ch - IRX_CH); 2249 dbch = &sc->ir[ch - IRX_CH]; 2250 } 2251 cmd = OREAD(sc, off + 0xc); 2252 2253 if( dbch->ndb == 0 ){ 2254 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2255 return; 2256 } 2257 pp = dbch->top; 2258 prev = pp->db; 2259 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2260 if(pp == NULL){ 2261 curr = NULL; 2262 goto outdb; 2263 } 2264 cp = STAILQ_NEXT(pp, link); 2265 if(cp == NULL){ 2266 curr = NULL; 2267 goto outdb; 2268 } 2269 np = STAILQ_NEXT(cp, link); 2270 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2271 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2272 curr = cp->db; 2273 if(np != NULL){ 2274 next = np->db; 2275 }else{ 2276 next = NULL; 2277 } 2278 goto outdb; 2279 } 2280 } 2281 pp = STAILQ_NEXT(pp, link); 2282 prev = pp->db; 2283 } 2284outdb: 2285 if( curr != NULL){ 2286#if 0 2287 printf("Prev DB %d\n", ch); 2288 print_db(pp, prev, ch, dbch->ndesc); 2289#endif 2290 printf("Current DB %d\n", ch); 2291 print_db(cp, curr, ch, dbch->ndesc); 2292#if 0 2293 printf("Next DB %d\n", ch); 2294 print_db(np, next, ch, dbch->ndesc); 2295#endif 2296 }else{ 2297 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2298 } 2299 return; 2300} 2301 2302void 2303print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2304 u_int32_t ch, u_int32_t max) 2305{ 2306 fwohcireg_t stat; 2307 int i, key; 2308 u_int32_t cmd, res; 2309 2310 if(db == NULL){ 2311 printf("No Descriptor is found\n"); 2312 return; 2313 } 2314 2315 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2316 ch, 2317 "Current", 2318 "OP ", 2319 "KEY", 2320 "INT", 2321 "BR ", 2322 "len", 2323 "Addr", 2324 "Depend", 2325 "Stat", 2326 "Cnt"); 2327 for( i = 0 ; i <= max ; i ++){ 2328 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2329 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2330 key = cmd & OHCI_KEY_MASK; 2331 stat = res >> OHCI_STATUS_SHIFT; 2332#if __FreeBSD_version >= 500000 2333 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2334 (uintmax_t)db_tr->bus_addr, 2335#else 2336 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2337 db_tr->bus_addr, 2338#endif 2339 dbcode[(cmd >> 28) & 0xf], 2340 dbkey[(cmd >> 24) & 0x7], 2341 dbcond[(cmd >> 20) & 0x3], 2342 dbcond[(cmd >> 18) & 0x3], 2343 cmd & OHCI_COUNT_MASK, 2344 FWOHCI_DMA_READ(db[i].db.desc.addr), 2345 FWOHCI_DMA_READ(db[i].db.desc.depend), 2346 stat, 2347 res & OHCI_COUNT_MASK); 2348 if(stat & 0xff00){ 2349 printf(" %s%s%s%s%s%s %s(%x)\n", 2350 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2351 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2352 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2353 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2354 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2355 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2356 fwohcicode[stat & 0x1f], 2357 stat & 0x1f 2358 ); 2359 }else{ 2360 printf(" Nostat\n"); 2361 } 2362 if(key == OHCI_KEY_ST2 ){ 2363 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2364 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2365 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2366 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2367 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2368 } 2369 if(key == OHCI_KEY_DEVICE){ 2370 return; 2371 } 2372 if((cmd & OHCI_BRANCH_MASK) 2373 == OHCI_BRANCH_ALWAYS){ 2374 return; 2375 } 2376 if((cmd & OHCI_CMD_MASK) 2377 == OHCI_OUTPUT_LAST){ 2378 return; 2379 } 2380 if((cmd & OHCI_CMD_MASK) 2381 == OHCI_INPUT_LAST){ 2382 return; 2383 } 2384 if(key == OHCI_KEY_ST2 ){ 2385 i++; 2386 } 2387 } 2388 return; 2389} 2390 2391void 2392fwohci_ibr(struct firewire_comm *fc) 2393{ 2394 struct fwohci_softc *sc; 2395 u_int32_t fun; 2396 2397 device_printf(fc->dev, "Initiate bus reset\n"); 2398 sc = (struct fwohci_softc *)fc; 2399 2400 /* 2401 * Set root hold-off bit so that non cyclemaster capable node 2402 * shouldn't became the root node. 2403 */ 2404#if 1 2405 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2406 fun |= FW_PHY_IBR | FW_PHY_RHB; 2407 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2408#else /* Short bus reset */ 2409 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2410 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2411 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2412#endif 2413} 2414 2415void 2416fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2417{ 2418 struct fwohcidb_tr *db_tr, *fdb_tr; 2419 struct fwohci_dbch *dbch; 2420 volatile struct fwohcidb *db; 2421 struct fw_pkt *fp; 2422 volatile struct fwohci_txpkthdr *ohcifp; 2423 unsigned short chtag; 2424 int idb; 2425 2426 dbch = &sc->it[dmach]; 2427 chtag = sc->it[dmach].xferq.flag & 0xff; 2428 2429 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2430 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2431/* 2432device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2433*/ 2434 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2435 db = db_tr->db; 2436 fp = (struct fw_pkt *)db_tr->buf; 2437 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2438 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2439 ohcifp->mode.stream.len = fp->mode.stream.len; 2440 ohcifp->mode.stream.chtag = chtag; 2441 ohcifp->mode.stream.tcode = 0xa; 2442 ohcifp->mode.stream.spd = 0; 2443#if BYTE_ORDER == BIG_ENDIAN 2444 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2445 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2446#endif 2447 2448 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2449 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2450 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2451#if 0 /* if bulkxfer->npackets changes */ 2452 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2453 | OHCI_UPDATE 2454 | OHCI_BRANCH_ALWAYS; 2455 db[0].db.desc.depend = 2456 = db[dbch->ndesc - 1].db.desc.depend 2457 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2458#else 2459 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2460 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2461#endif 2462 bulkxfer->end = (caddr_t)db_tr; 2463 db_tr = STAILQ_NEXT(db_tr, link); 2464 } 2465 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2466 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2467 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2468#if 0 /* if bulkxfer->npackets changes */ 2469 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2470 /* OHCI 1.1 and above */ 2471 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2472#endif 2473/* 2474 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2475 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2476device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2477*/ 2478 return; 2479} 2480 2481static int 2482fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2483 int poffset) 2484{ 2485 volatile struct fwohcidb *db = db_tr->db; 2486 struct fw_xferq *it; 2487 int err = 0; 2488 2489 it = &dbch->xferq; 2490 if(it->buf == 0){ 2491 err = EINVAL; 2492 return err; 2493 } 2494 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2495 db_tr->dbcnt = 3; 2496 2497 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2498 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2499 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2500 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2501 2502 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2503 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2504#if 1 2505 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2506 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2507#endif 2508 return 0; 2509} 2510 2511int 2512fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2513 int poffset, struct fwdma_alloc *dummy_dma) 2514{ 2515 volatile struct fwohcidb *db = db_tr->db; 2516 struct fw_xferq *ir; 2517 int i, ldesc; 2518 bus_addr_t dbuf[2]; 2519 int dsiz[2]; 2520 2521 ir = &dbch->xferq; 2522 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2523 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2524 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2525 if (db_tr->buf == NULL) 2526 return(ENOMEM); 2527 db_tr->dbcnt = 1; 2528 dsiz[0] = ir->psize; 2529 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2530 BUS_DMASYNC_PREREAD); 2531 } else { 2532 db_tr->dbcnt = 0; 2533 if (dummy_dma != NULL) { 2534 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2535 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2536 } 2537 dsiz[db_tr->dbcnt] = ir->psize; 2538 if (ir->buf != NULL) { 2539 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2540 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2541 } 2542 db_tr->dbcnt++; 2543 } 2544 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2545 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2546 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2547 if (ir->flag & FWXFERQ_STREAM) { 2548 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2549 } 2550 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2551 } 2552 ldesc = db_tr->dbcnt - 1; 2553 if (ir->flag & FWXFERQ_STREAM) { 2554 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2555 } 2556 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2557 return 0; 2558} 2559 2560 2561static int 2562fwohci_arcv_swap(struct fw_pkt *fp, int len) 2563{ 2564 struct fw_pkt *fp0; 2565 u_int32_t ld0; 2566 int slen; 2567#if BYTE_ORDER == BIG_ENDIAN 2568 int i; 2569#endif 2570 2571 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2572#if 0 2573 printf("ld0: x%08x\n", ld0); 2574#endif 2575 fp0 = (struct fw_pkt *)&ld0; 2576 switch (fp0->mode.common.tcode) { 2577 case FWTCODE_RREQQ: 2578 case FWTCODE_WRES: 2579 case FWTCODE_WREQQ: 2580 case FWTCODE_RRESQ: 2581 case FWOHCITCODE_PHY: 2582 slen = 12; 2583 break; 2584 case FWTCODE_RREQB: 2585 case FWTCODE_WREQB: 2586 case FWTCODE_LREQ: 2587 case FWTCODE_RRESB: 2588 case FWTCODE_LRES: 2589 slen = 16; 2590 break; 2591 default: 2592 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2593 return(0); 2594 } 2595 if (slen > len) { 2596 if (firewire_debug) 2597 printf("splitted header\n"); 2598 return(-slen); 2599 } 2600#if BYTE_ORDER == BIG_ENDIAN 2601 for(i = 0; i < slen/4; i ++) 2602 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2603#endif 2604 return(slen); 2605} 2606 2607#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2608static int 2609fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2610{ 2611 int r; 2612 2613 switch(fp->mode.common.tcode){ 2614 case FWTCODE_RREQQ: 2615 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2616 break; 2617 case FWTCODE_WRES: 2618 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2619 break; 2620 case FWTCODE_WREQQ: 2621 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2622 break; 2623 case FWTCODE_RREQB: 2624 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2625 break; 2626 case FWTCODE_RRESQ: 2627 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2628 break; 2629 case FWTCODE_WREQB: 2630 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2631 + sizeof(u_int32_t); 2632 break; 2633 case FWTCODE_LREQ: 2634 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2635 + sizeof(u_int32_t); 2636 break; 2637 case FWTCODE_RRESB: 2638 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2639 + sizeof(u_int32_t); 2640 break; 2641 case FWTCODE_LRES: 2642 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2643 + sizeof(u_int32_t); 2644 break; 2645 case FWOHCITCODE_PHY: 2646 r = 16; 2647 break; 2648 default: 2649 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2650 fp->mode.common.tcode); 2651 r = 0; 2652 } 2653 if (r > dbch->xferq.psize) { 2654 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2655 /* panic ? */ 2656 } 2657 return r; 2658} 2659 2660static void 2661fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2662{ 2663 volatile struct fwohcidb *db = &db_tr->db[0]; 2664 2665 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2666 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2667 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2668 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2669 dbch->bottom = db_tr; 2670} 2671 2672static void 2673fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2674{ 2675 struct fwohcidb_tr *db_tr; 2676 struct iovec vec[2]; 2677 struct fw_pkt pktbuf; 2678 int nvec; 2679 struct fw_pkt *fp; 2680 u_int8_t *ld; 2681 u_int32_t stat, off, status; 2682 u_int spd; 2683 int len, plen, hlen, pcnt, offset; 2684 int s; 2685 caddr_t buf; 2686 int resCount; 2687 2688 if(&sc->arrq == dbch){ 2689 off = OHCI_ARQOFF; 2690 }else if(&sc->arrs == dbch){ 2691 off = OHCI_ARSOFF; 2692 }else{ 2693 return; 2694 } 2695 2696 s = splfw(); 2697 db_tr = dbch->top; 2698 pcnt = 0; 2699 /* XXX we cannot handle a packet which lies in more than two buf */ 2700 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2701 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2702 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2703 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2704#if 0 2705 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2706#endif 2707 while (status & OHCI_CNTL_DMA_ACTIVE) { 2708 len = dbch->xferq.psize - resCount; 2709 ld = (u_int8_t *)db_tr->buf; 2710 if (dbch->pdb_tr == NULL) { 2711 len -= dbch->buf_offset; 2712 ld += dbch->buf_offset; 2713 } 2714 if (len > 0) 2715 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2716 BUS_DMASYNC_POSTREAD); 2717 while (len > 0 ) { 2718 if (count >= 0 && count-- == 0) 2719 goto out; 2720 if(dbch->pdb_tr != NULL){ 2721 /* we have a fragment in previous buffer */ 2722 int rlen; 2723 2724 offset = dbch->buf_offset; 2725 if (offset < 0) 2726 offset = - offset; 2727 buf = dbch->pdb_tr->buf + offset; 2728 rlen = dbch->xferq.psize - offset; 2729 if (firewire_debug) 2730 printf("rlen=%d, offset=%d\n", 2731 rlen, dbch->buf_offset); 2732 if (dbch->buf_offset < 0) { 2733 /* splitted in header, pull up */ 2734 char *p; 2735 2736 p = (char *)&pktbuf; 2737 bcopy(buf, p, rlen); 2738 p += rlen; 2739 /* this must be too long but harmless */ 2740 rlen = sizeof(pktbuf) - rlen; 2741 if (rlen < 0) 2742 printf("why rlen < 0\n"); 2743 bcopy(db_tr->buf, p, rlen); 2744 ld += rlen; 2745 len -= rlen; 2746 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2747 if (hlen < 0) { 2748 printf("hlen < 0 shouldn't happen"); 2749 } 2750 offset = sizeof(pktbuf); 2751 vec[0].iov_base = (char *)&pktbuf; 2752 vec[0].iov_len = offset; 2753 } else { 2754 /* splitted in payload */ 2755 offset = rlen; 2756 vec[0].iov_base = buf; 2757 vec[0].iov_len = rlen; 2758 } 2759 fp=(struct fw_pkt *)vec[0].iov_base; 2760 nvec = 1; 2761 } else { 2762 /* no fragment in previous buffer */ 2763 fp=(struct fw_pkt *)ld; 2764 hlen = fwohci_arcv_swap(fp, len); 2765 if (hlen == 0) 2766 /* XXX need reset */ 2767 goto out; 2768 if (hlen < 0) { 2769 dbch->pdb_tr = db_tr; 2770 dbch->buf_offset = - dbch->buf_offset; 2771 /* sanity check */ 2772 if (resCount != 0) 2773 printf("resCount != 0 !?\n"); 2774 goto out; 2775 } 2776 offset = 0; 2777 nvec = 0; 2778 } 2779 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2780 if (plen < 0) { 2781 /* minimum header size + trailer 2782 = sizeof(fw_pkt) so this shouldn't happens */ 2783 printf("plen is negative! offset=%d\n", offset); 2784 goto out; 2785 } 2786 if (plen > 0) { 2787 len -= plen; 2788 if (len < 0) { 2789 dbch->pdb_tr = db_tr; 2790 if (firewire_debug) 2791 printf("splitted payload\n"); 2792 /* sanity check */ 2793 if (resCount != 0) 2794 printf("resCount != 0 !?\n"); 2795 goto out; 2796 } 2797 vec[nvec].iov_base = ld; 2798 vec[nvec].iov_len = plen; 2799 nvec ++; 2800 ld += plen; 2801 } 2802 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2803 if (nvec == 0) 2804 printf("nvec == 0\n"); 2805 2806/* DMA result-code will be written at the tail of packet */ 2807#if BYTE_ORDER == BIG_ENDIAN 2808 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2809#else 2810 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2811#endif 2812#if 0 2813 printf("plen: %d, stat %x\n", plen ,stat); 2814#endif 2815 spd = (stat >> 5) & 0x3; 2816 stat &= 0x1f; 2817 switch(stat){ 2818 case FWOHCIEV_ACKPEND: 2819#if 0 2820 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2821#endif 2822 /* fall through */ 2823 case FWOHCIEV_ACKCOMPL: 2824 if ((vec[nvec-1].iov_len -= 2825 sizeof(struct fwohci_trailer)) == 0) 2826 nvec--; 2827 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2828 break; 2829 case FWOHCIEV_BUSRST: 2830 if (sc->fc.status != FWBUSRESET) 2831 printf("got BUSRST packet!?\n"); 2832 break; 2833 default: 2834 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2835#if 0 /* XXX */ 2836 goto out; 2837#endif 2838 break; 2839 } 2840 pcnt ++; 2841 if (dbch->pdb_tr != NULL) { 2842 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2843 dbch->pdb_tr = NULL; 2844 } 2845 2846 } 2847out: 2848 if (resCount == 0) { 2849 /* done on this buffer */ 2850 if (dbch->pdb_tr == NULL) { 2851 fwohci_arcv_free_buf(dbch, db_tr); 2852 dbch->buf_offset = 0; 2853 } else 2854 if (dbch->pdb_tr != db_tr) 2855 printf("pdb_tr != db_tr\n"); 2856 db_tr = STAILQ_NEXT(db_tr, link); 2857 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2858 >> OHCI_STATUS_SHIFT; 2859 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2860 & OHCI_COUNT_MASK; 2861 /* XXX check buffer overrun */ 2862 dbch->top = db_tr; 2863 } else { 2864 dbch->buf_offset = dbch->xferq.psize - resCount; 2865 break; 2866 } 2867 /* XXX make sure DMA is not dead */ 2868 } 2869#if 0 2870 if (pcnt < 1) 2871 printf("fwohci_arcv: no packets\n"); 2872#endif 2873 splx(s); 2874} 2875