fwohci.c revision 110273
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 110273 2003-02-03 09:41:42Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/proc.h> 46#include <sys/systm.h> 47#include <sys/types.h> 48#include <sys/mbuf.h> 49#include <sys/mman.h> 50#include <sys/socket.h> 51#include <sys/socketvar.h> 52#include <sys/signalvar.h> 53#include <sys/malloc.h> 54#include <sys/uio.h> 55#include <sys/sockio.h> 56#include <sys/bus.h> 57#include <sys/kernel.h> 58#include <sys/conf.h> 59 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/rman.h> 63 64#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65#include <machine/clock.h> 66#include <pci/pcivar.h> 67#include <pci/pcireg.h> 68#include <vm/vm.h> 69#include <vm/vm_extern.h> 70#include <vm/pmap.h> /* for vtophys proto */ 71 72#include <dev/firewire/firewire.h> 73#include <dev/firewire/firewirereg.h> 74#include <dev/firewire/fwohcireg.h> 75#include <dev/firewire/fwohcivar.h> 76#include <dev/firewire/firewire_phy.h> 77 78#include <dev/firewire/iec68113.h> 79 80#undef OHCI_DEBUG 81 82static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83 "STOR","LOAD","NOP ","STOP",}; 84static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85 "UNDEF","REG","SYS","DEV"}; 86char fwohcicode[32][0x20]={ 87 "No stat","Undef","long","miss Ack err", 88 "underrun","overrun","desc err", "data read err", 89 "data write err","bus reset","timeout","tcode err", 90 "Undef","Undef","unknown event","flushed", 91 "Undef","ack complete","ack pend","Undef", 92 "ack busy_X","ack busy_A","ack busy_B","Undef", 93 "Undef","Undef","Undef","ack tardy", 94 "Undef","ack data_err","ack type_err",""}; 95#define MAX_SPEED 2 96extern char linkspeed[MAX_SPEED+1][0x10]; 97static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99 100static struct tcode_info tinfo[] = { 101/* hdr_len block flag*/ 102/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104/* 2 WRES */ {12, FWTI_RES}, 105/* 3 XXX */ { 0, 0}, 106/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108/* 6 RRESQ */ {16, FWTI_RES}, 109/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110/* 8 CYCS */ { 0, 0}, 111/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114/* c XXX */ { 0, 0}, 115/* d XXX */ { 0, 0}, 116/* e PHY */ {12, FWTI_REQ}, 117/* f XXX */ { 0, 0} 118}; 119 120#define OHCI_WRITE_SIGMASK 0xffff0000 121#define OHCI_READ_SIGMASK 0xffff0000 122 123#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125 126static void fwohci_ibr __P((struct firewire_comm *)); 127static void fwohci_db_init __P((struct fwohci_dbch *)); 128static void fwohci_db_free __P((struct fwohci_dbch *)); 129static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132static void fwohci_start_atq __P((struct firewire_comm *)); 133static void fwohci_start_ats __P((struct firewire_comm *)); 134static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142static int fwohci_irx_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145static int fwohci_irx_disable __P((struct firewire_comm *, int)); 146static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148static int fwohci_itx_disable __P((struct firewire_comm *, int)); 149static void fwohci_timeout __P((void *)); 150static void fwohci_poll __P((struct firewire_comm *, int, int)); 151static void fwohci_set_intr __P((struct firewire_comm *, int)); 152static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154static void dump_db __P((struct fwohci_softc *, u_int32_t)); 155static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161 162/* 163 * memory allocated for DMA programs 164 */ 165#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166 167/* #define NDB 1024 */ 168#define NDB FWMAXQUEUE 169#define NDVDB (DVBUF * NDB) 170 171#define OHCI_VERSION 0x00 172#define OHCI_CROMHDR 0x18 173#define OHCI_BUS_OPT 0x20 174#define OHCI_BUSIRMC (1 << 31) 175#define OHCI_BUSCMC (1 << 30) 176#define OHCI_BUSISC (1 << 29) 177#define OHCI_BUSBMC (1 << 28) 178#define OHCI_BUSPMC (1 << 27) 179#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180 OHCI_BUSBMC | OHCI_BUSPMC 181 182#define OHCI_EUID_HI 0x24 183#define OHCI_EUID_LO 0x28 184 185#define OHCI_CROMPTR 0x34 186#define OHCI_HCCCTL 0x50 187#define OHCI_HCCCTLCLR 0x54 188#define OHCI_AREQHI 0x100 189#define OHCI_AREQHICLR 0x104 190#define OHCI_AREQLO 0x108 191#define OHCI_AREQLOCLR 0x10c 192#define OHCI_PREQHI 0x110 193#define OHCI_PREQHICLR 0x114 194#define OHCI_PREQLO 0x118 195#define OHCI_PREQLOCLR 0x11c 196#define OHCI_PREQUPPER 0x120 197 198#define OHCI_SID_BUF 0x64 199#define OHCI_SID_CNT 0x68 200#define OHCI_SID_CNT_MASK 0xffc 201 202#define OHCI_IT_STAT 0x90 203#define OHCI_IT_STATCLR 0x94 204#define OHCI_IT_MASK 0x98 205#define OHCI_IT_MASKCLR 0x9c 206 207#define OHCI_IR_STAT 0xa0 208#define OHCI_IR_STATCLR 0xa4 209#define OHCI_IR_MASK 0xa8 210#define OHCI_IR_MASKCLR 0xac 211 212#define OHCI_LNKCTL 0xe0 213#define OHCI_LNKCTLCLR 0xe4 214 215#define OHCI_PHYACCESS 0xec 216#define OHCI_CYCLETIMER 0xf0 217 218#define OHCI_DMACTL(off) (off) 219#define OHCI_DMACTLCLR(off) (off + 4) 220#define OHCI_DMACMD(off) (off + 0xc) 221#define OHCI_DMAMATCH(off) (off + 0x10) 222 223#define OHCI_ATQOFF 0x180 224#define OHCI_ATQCTL OHCI_ATQOFF 225#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228 229#define OHCI_ATSOFF 0x1a0 230#define OHCI_ATSCTL OHCI_ATSOFF 231#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234 235#define OHCI_ARQOFF 0x1c0 236#define OHCI_ARQCTL OHCI_ARQOFF 237#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240 241#define OHCI_ARSOFF 0x1e0 242#define OHCI_ARSCTL OHCI_ARSOFF 243#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246 247#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251 252#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257 258d_ioctl_t fwohci_ioctl; 259 260/* 261 * Communication with PHY device 262 */ 263static u_int32_t 264fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265{ 266 u_int32_t fun; 267 268 addr &= 0xf; 269 data &= 0xff; 270 271 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272 OWRITE(sc, OHCI_PHYACCESS, fun); 273 DELAY(100); 274 275 return(fwphy_rddata( sc, addr)); 276} 277 278static u_int32_t 279fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280{ 281 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282 int i; 283 u_int32_t bm; 284 285#define OHCI_CSR_DATA 0x0c 286#define OHCI_CSR_COMP 0x10 287#define OHCI_CSR_CONT 0x14 288#define OHCI_BUS_MANAGER_ID 0 289 290 OWRITE(sc, OHCI_CSR_DATA, node); 291 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294 DELAY(10); 295 bm = OREAD(sc, OHCI_CSR_DATA); 296 if((bm & 0x3f) == 0x3f) 297 bm = node; 298 if (bootverbose) 299 device_printf(sc->fc.dev, 300 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301 302 return(bm); 303} 304 305static u_int32_t 306fwphy_rddata(struct fwohci_softc *sc, u_int addr) 307{ 308 u_int32_t fun, stat; 309 u_int i, retry = 0; 310 311 addr &= 0xf; 312#define MAX_RETRY 100 313again: 314 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316 OWRITE(sc, OHCI_PHYACCESS, fun); 317 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318 fun = OREAD(sc, OHCI_PHYACCESS); 319 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320 break; 321 DELAY(100); 322 } 323 if(i >= MAX_RETRY) { 324 if (bootverbose) 325 device_printf(sc->fc.dev, "phy read failed(1).\n"); 326 if (++retry < MAX_RETRY) { 327 DELAY(100); 328 goto again; 329 } 330 } 331 /* Make sure that SCLK is started */ 332 stat = OREAD(sc, FWOHCI_INTSTAT); 333 if ((stat & OHCI_INT_REG_FAIL) != 0 || 334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335 if (bootverbose) 336 device_printf(sc->fc.dev, "phy read failed(2).\n"); 337 if (++retry < MAX_RETRY) { 338 DELAY(100); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345#undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347} 348/* Device specific ioctl. */ 349int 350fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351{ 352 struct firewire_softc *sc; 353 struct fwohci_softc *fc; 354 int unit = DEV2UNIT(dev); 355 int err = 0; 356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357 u_int32_t *dmach = (u_int32_t *) data; 358 359 sc = devclass_get_softc(firewire_devclass, unit); 360 if(sc == NULL){ 361 return(EINVAL); 362 } 363 fc = (struct fwohci_softc *)sc->fc; 364 365 if (!data) 366 return(EINVAL); 367 368 switch (cmd) { 369 case FWOHCI_WRREG: 370#define OHCI_MAX_REG 0x800 371 if(reg->addr <= OHCI_MAX_REG){ 372 OWRITE(fc, reg->addr, reg->data); 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378 case FWOHCI_RDREG: 379 if(reg->addr <= OHCI_MAX_REG){ 380 reg->data = OREAD(fc, reg->addr); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385/* Read DMA descriptors for debug */ 386 case DUMPDMA: 387 if(*dmach <= OHCI_MAX_DMA_CH ){ 388 dump_dma(fc, *dmach); 389 dump_db(fc, *dmach); 390 }else{ 391 err = EINVAL; 392 } 393 break; 394 default: 395 break; 396 } 397 return err; 398} 399 400static int 401fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402{ 403 u_int32_t reg, reg2; 404 int e1394a = 1; 405/* 406 * probe PHY parameters 407 * 0. to prove PHY version, whether compliance of 1394a. 408 * 1. to probe maximum speed supported by the PHY and 409 * number of port supported by core-logic. 410 * It is not actually available port on your PC . 411 */ 412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413#if 0 414 /* XXX wait for SCLK. */ 415 DELAY(100000); 416#endif 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447#if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449#else /* XXX force to enable 1394a */ 450 if (e1394a) { 451#endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475} 476 477 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 /* AT Retries */ 555 OWRITE(sc, FWOHCI_RETRY, 556 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560 db_tr->xfer = NULL; 561 } 562 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564 db_tr->xfer = NULL; 565 } 566 567 568 /* Enable interrupt */ 569 OWRITE(sc, FWOHCI_INTMASK, 570 OHCI_INT_ERR | OHCI_INT_PHY_SID 571 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574 fwohci_set_intr(&sc->fc, 1); 575 576} 577 578int 579fwohci_init(struct fwohci_softc *sc, device_t dev) 580{ 581 int i; 582 u_int32_t reg; 583 u_int8_t ui[8]; 584 585 reg = OREAD(sc, OHCI_VERSION); 586 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588 589/* Available Isochrounous DMA channel probe */ 590 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 591 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 592 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 593 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 595 for (i = 0; i < 0x20; i++) 596 if ((reg & (1 << i)) == 0) 597 break; 598 sc->fc.nisodma = i; 599 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600 601 sc->fc.arq = &sc->arrq.xferq; 602 sc->fc.ars = &sc->arrs.xferq; 603 sc->fc.atq = &sc->atrq.xferq; 604 sc->fc.ats = &sc->atrs.xferq; 605 606 sc->arrq.xferq.start = NULL; 607 sc->arrs.xferq.start = NULL; 608 sc->atrq.xferq.start = fwohci_start_atq; 609 sc->atrs.xferq.start = fwohci_start_ats; 610 611 sc->arrq.xferq.drain = NULL; 612 sc->arrs.xferq.drain = NULL; 613 sc->atrq.xferq.drain = fwohci_drain_atq; 614 sc->atrs.xferq.drain = fwohci_drain_ats; 615 616 sc->arrq.ndesc = 1; 617 sc->arrs.ndesc = 1; 618 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 619 sc->atrs.ndesc = 6 / 2; 620 621 sc->arrq.ndb = NDB; 622 sc->arrs.ndb = NDB / 2; 623 sc->atrq.ndb = NDB; 624 sc->atrs.ndb = NDB / 2; 625 626 sc->arrq.dummy = NULL; 627 sc->arrs.dummy = NULL; 628 sc->atrq.dummy = NULL; 629 sc->atrs.dummy = NULL; 630 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631 sc->fc.it[i] = &sc->it[i].xferq; 632 sc->fc.ir[i] = &sc->ir[i].xferq; 633 sc->it[i].ndb = 0; 634 sc->ir[i].ndb = 0; 635 } 636 637 sc->fc.tcode = tinfo; 638 639 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 640 641 if(sc->cromptr == NULL){ 642 device_printf(dev, "cromptr alloc failed."); 643 return ENOMEM; 644 } 645 sc->fc.dev = dev; 646 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 657 658/* SID recieve buffer must allign 2^11 */ 659#define OHCI_SIDSIZE (1 << 11) 660 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 661 if (sc->fc.sid_buf == NULL) { 662 device_printf(dev, "sid_buf alloc failed.\n"); 663 return ENOMEM; 664 } 665 if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666 device_printf(dev, "sid_buf(%p) not aligned.\n", 667 sc->fc.sid_buf); 668 return ENOMEM; 669 } 670 671 fwohci_db_init(&sc->arrq); 672 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673 return ENOMEM; 674 675 fwohci_db_init(&sc->arrs); 676 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677 return ENOMEM; 678 679 fwohci_db_init(&sc->atrq); 680 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681 return ENOMEM; 682 683 fwohci_db_init(&sc->atrs); 684 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685 return ENOMEM; 686 687 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689 for( i = 0 ; i < 8 ; i ++) 690 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693 694 sc->fc.ioctl = fwohci_ioctl; 695 sc->fc.cyctimer = fwohci_cyctimer; 696 sc->fc.set_bmr = fwohci_set_bus_manager; 697 sc->fc.ibr = fwohci_ibr; 698 sc->fc.irx_enable = fwohci_irx_enable; 699 sc->fc.irx_disable = fwohci_irx_disable; 700 701 sc->fc.itx_enable = fwohci_itxbuf_enable; 702 sc->fc.itx_disable = fwohci_itx_disable; 703 sc->fc.irx_post = fwohci_irx_post; 704 sc->fc.itx_post = NULL; 705 sc->fc.timeout = fwohci_timeout; 706 sc->fc.poll = fwohci_poll; 707 sc->fc.set_intr = fwohci_set_intr; 708 709 fw_init(&sc->fc); 710 fwohci_reset(sc, dev); 711 712 return 0; 713} 714 715void 716fwohci_timeout(void *arg) 717{ 718 struct fwohci_softc *sc; 719 720 sc = (struct fwohci_softc *)arg; 721 callout_reset(&sc->fc.timeout_callout, FW_XFERTIMEOUT * hz * 10, 722 (void *)fwohci_timeout, (void *)sc); 723} 724 725u_int32_t 726fwohci_cyctimer(struct firewire_comm *fc) 727{ 728 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 729 return(OREAD(sc, OHCI_CYCLETIMER)); 730} 731 732int 733fwohci_detach(struct fwohci_softc *sc, device_t dev) 734{ 735 int i; 736 737 if (sc->fc.sid_buf != NULL) 738 free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 739 if (sc->cromptr != NULL) 740 free((void *)sc->cromptr, M_FW); 741 742 fwohci_db_free(&sc->arrq); 743 fwohci_db_free(&sc->arrs); 744 745 fwohci_db_free(&sc->atrq); 746 fwohci_db_free(&sc->atrs); 747 748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749 fwohci_db_free(&sc->it[i]); 750 fwohci_db_free(&sc->ir[i]); 751 } 752 753 return 0; 754} 755 756#define LAST_DB(dbtr, db) do { \ 757 struct fwohcidb_tr *_dbtr = (dbtr); \ 758 int _cnt = _dbtr->dbcnt; \ 759 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 760} while (0) 761 762static void 763fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 764{ 765 int i, s; 766 int tcode, hdr_len, hdr_off, len; 767 int fsegment = -1; 768 u_int32_t off; 769 struct fw_xfer *xfer; 770 struct fw_pkt *fp; 771 volatile struct fwohci_txpkthdr *ohcifp; 772 struct fwohcidb_tr *db_tr; 773 volatile struct fwohcidb *db; 774 struct mbuf *m; 775 struct tcode_info *info; 776 static int maxdesc=0; 777 778 if(&sc->atrq == dbch){ 779 off = OHCI_ATQOFF; 780 }else if(&sc->atrs == dbch){ 781 off = OHCI_ATSOFF; 782 }else{ 783 return; 784 } 785 786 if (dbch->flags & FWOHCI_DBCH_FULL) 787 return; 788 789 s = splfw(); 790 db_tr = dbch->top; 791txloop: 792 xfer = STAILQ_FIRST(&dbch->xferq.q); 793 if(xfer == NULL){ 794 goto kick; 795 } 796 if(dbch->xferq.queued == 0 ){ 797 device_printf(sc->fc.dev, "TX queue empty\n"); 798 } 799 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 800 db_tr->xfer = xfer; 801 xfer->state = FWXF_START; 802 dbch->xferq.packets++; 803 804 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 805 tcode = fp->mode.common.tcode; 806 807 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 808 info = &tinfo[tcode]; 809 hdr_len = hdr_off = info->hdr_len; 810 /* fw_asyreq must pass valid send.len */ 811 len = xfer->send.len; 812 for( i = 0 ; i < hdr_off ; i+= 4){ 813 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 814 } 815 ohcifp->mode.common.spd = xfer->spd; 816 if (tcode == FWTCODE_STREAM ){ 817 hdr_len = 8; 818 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 819 } else if (tcode == FWTCODE_PHY) { 820 hdr_len = 12; 821 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 822 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 823 ohcifp->mode.common.spd = 0; 824 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 825 } else { 826 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 827 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 828 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 829 } 830 db = &db_tr->db[0]; 831 db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 832 db->db.desc.reqcount = hdr_len; 833 db->db.desc.status = 0; 834/* Specify bound timer of asy. responce */ 835 if(&sc->atrs == dbch){ 836 db->db.desc.count 837 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 838 } 839 840 db_tr->dbcnt = 2; 841 db = &db_tr->db[db_tr->dbcnt]; 842 if(len > hdr_off){ 843 if (xfer->mbuf == NULL) { 844 db->db.desc.addr 845 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 846 db->db.desc.control = OHCI_OUTPUT_MORE; 847 db->db.desc.reqcount = len - hdr_off; 848 db->db.desc.status = 0; 849 850 db_tr->dbcnt++; 851 } else { 852 int mchain=0; 853 /* XXX we assume mbuf chain is shorter than ndesc */ 854 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 855 if (m->m_len == 0) 856 /* unrecoverable error could occur. */ 857 continue; 858 mchain++; 859 if (db_tr->dbcnt >= dbch->ndesc) 860 continue; 861 db->db.desc.addr 862 = vtophys(mtod(m, caddr_t)); 863 db->db.desc.control = OHCI_OUTPUT_MORE; 864 db->db.desc.reqcount = m->m_len; 865 db->db.desc.status = 0; 866 db++; 867 db_tr->dbcnt++; 868 } 869 if (mchain > dbch->ndesc - 2) 870 device_printf(sc->fc.dev, 871 "dbch->ndesc(%d) is too small for" 872 " mbuf chain(%d), trancated.\n", 873 dbch->ndesc, mchain); 874 } 875 } 876 if (maxdesc < db_tr->dbcnt) { 877 maxdesc = db_tr->dbcnt; 878 if (bootverbose) 879 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 880 } 881 /* last db */ 882 LAST_DB(db_tr, db); 883 db->db.desc.control |= OHCI_OUTPUT_LAST 884 | OHCI_INTERRUPT_ALWAYS 885 | OHCI_BRANCH_ALWAYS; 886 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 887 888 if(fsegment == -1 ) 889 fsegment = db_tr->dbcnt; 890 if (dbch->pdb_tr != NULL) { 891 LAST_DB(dbch->pdb_tr, db); 892 db->db.desc.depend |= db_tr->dbcnt; 893 } 894 dbch->pdb_tr = db_tr; 895 db_tr = STAILQ_NEXT(db_tr, link); 896 if(db_tr != dbch->bottom){ 897 goto txloop; 898 } else { 899 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 900 dbch->flags |= FWOHCI_DBCH_FULL; 901 } 902kick: 903 if (firewire_debug) printf("kick\n"); 904 /* kick asy q */ 905 906 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 907 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 908 } else { 909 if (bootverbose) 910 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 911 OREAD(sc, OHCI_DMACTL(off))); 912 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 913 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 914 dbch->xferq.flag |= FWXFERQ_RUNNING; 915 } 916 917 dbch->top = db_tr; 918 splx(s); 919 return; 920} 921 922static void 923fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 924{ 925 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 926 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 927 return; 928} 929 930static void 931fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 932{ 933 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 934 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 935 return; 936} 937 938static void 939fwohci_start_atq(struct firewire_comm *fc) 940{ 941 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 942 fwohci_start( sc, &(sc->atrq)); 943 return; 944} 945 946static void 947fwohci_start_ats(struct firewire_comm *fc) 948{ 949 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 950 fwohci_start( sc, &(sc->atrs)); 951 return; 952} 953 954void 955fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 956{ 957 int s, err = 0; 958 struct fwohcidb_tr *tr; 959 volatile struct fwohcidb *db; 960 struct fw_xfer *xfer; 961 u_int32_t off; 962 u_int stat; 963 int packets; 964 struct firewire_comm *fc = (struct firewire_comm *)sc; 965 if(&sc->atrq == dbch){ 966 off = OHCI_ATQOFF; 967 }else if(&sc->atrs == dbch){ 968 off = OHCI_ATSOFF; 969 }else{ 970 return; 971 } 972 s = splfw(); 973 tr = dbch->bottom; 974 packets = 0; 975 while(dbch->xferq.queued > 0){ 976 LAST_DB(tr, db); 977 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 978 if (fc->status != FWBUSRESET) 979 /* maybe out of order?? */ 980 goto out; 981 } 982 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 983#ifdef OHCI_DEBUG 984 dump_dma(sc, ch); 985 dump_db(sc, ch); 986#endif 987/* Stop DMA */ 988 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 989 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 990 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 991 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 992 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 993 } 994 stat = db->db.desc.status & FWOHCIEV_MASK; 995 switch(stat){ 996 case FWOHCIEV_ACKCOMPL: 997 case FWOHCIEV_ACKPEND: 998 err = 0; 999 break; 1000 case FWOHCIEV_ACKBSA: 1001 case FWOHCIEV_ACKBSB: 1002 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1003 case FWOHCIEV_ACKBSX: 1004 err = EBUSY; 1005 break; 1006 case FWOHCIEV_FLUSHED: 1007 case FWOHCIEV_ACKTARD: 1008 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1009 err = EAGAIN; 1010 break; 1011 case FWOHCIEV_MISSACK: 1012 case FWOHCIEV_UNDRRUN: 1013 case FWOHCIEV_OVRRUN: 1014 case FWOHCIEV_DESCERR: 1015 case FWOHCIEV_DTRDERR: 1016 case FWOHCIEV_TIMEOUT: 1017 case FWOHCIEV_TCODERR: 1018 case FWOHCIEV_UNKNOWN: 1019 case FWOHCIEV_ACKDERR: 1020 case FWOHCIEV_ACKTERR: 1021 default: 1022 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1023 stat, fwohcicode[stat]); 1024 err = EINVAL; 1025 break; 1026 } 1027 if(tr->xfer != NULL){ 1028 xfer = tr->xfer; 1029 xfer->state = FWXF_SENT; 1030 if(err == EBUSY && fc->status != FWBUSRESET){ 1031 xfer->state = FWXF_BUSY; 1032 switch(xfer->act_type){ 1033 case FWACT_XFER: 1034 xfer->resp = err; 1035 if(xfer->retry_req != NULL){ 1036 xfer->retry_req(xfer); 1037 } 1038 break; 1039 default: 1040 break; 1041 } 1042 } else if( stat != FWOHCIEV_ACKPEND){ 1043 if (stat != FWOHCIEV_ACKCOMPL) 1044 xfer->state = FWXF_SENTERR; 1045 xfer->resp = err; 1046 switch(xfer->act_type){ 1047 case FWACT_XFER: 1048 fw_xfer_done(xfer); 1049 break; 1050 default: 1051 break; 1052 } 1053 } 1054 } 1055 dbch->xferq.queued --; 1056 tr->xfer = NULL; 1057 1058 packets ++; 1059 tr = STAILQ_NEXT(tr, link); 1060 dbch->bottom = tr; 1061 } 1062out: 1063 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1064 printf("make free slot\n"); 1065 dbch->flags &= ~FWOHCI_DBCH_FULL; 1066 fwohci_start(sc, dbch); 1067 } 1068 splx(s); 1069} 1070 1071static void 1072fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1073{ 1074 int i, s, found=0; 1075 struct fwohcidb_tr *tr; 1076 1077 if(xfer->state != FWXF_START) return; 1078 1079 s = splfw(); 1080 tr = dbch->bottom; 1081 for (i = 0; i < dbch->xferq.queued; i ++) { 1082 if(tr->xfer == xfer){ 1083 tr->xfer = NULL; 1084#if 0 1085 dbch->xferq.queued --; 1086 /* XXX */ 1087 if (tr == dbch->bottom) 1088 dbch->bottom = STAILQ_NEXT(tr, link); 1089 if (dbch->flags & FWOHCI_DBCH_FULL) { 1090 printf("fwohci_drain: make slot\n"); 1091 dbch->flags &= ~FWOHCI_DBCH_FULL; 1092 fwohci_start((struct fwohci_softc *)fc, dbch); 1093 } 1094#endif 1095 found ++; 1096 break; 1097 } 1098 tr = STAILQ_NEXT(tr, link); 1099 } 1100 splx(s); 1101 if (!found) 1102 device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1103 return; 1104} 1105 1106static void 1107fwohci_db_free(struct fwohci_dbch *dbch) 1108{ 1109 struct fwohcidb_tr *db_tr; 1110 int idb, i; 1111 1112 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1113 return; 1114 1115 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1116 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1117 idb < dbch->ndb; 1118 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1119 if (db_tr->buf != NULL) { 1120 free(db_tr->buf, M_FW); 1121 db_tr->buf = NULL; 1122 } 1123 } 1124 } 1125 dbch->ndb = 0; 1126 db_tr = STAILQ_FIRST(&dbch->db_trq); 1127 for (i = 0; i < dbch->npages; i++) 1128 free(dbch->pages[i], M_FW); 1129 free(db_tr, M_FW); 1130 STAILQ_INIT(&dbch->db_trq); 1131 dbch->flags &= ~FWOHCI_DBCH_INIT; 1132} 1133 1134static void 1135fwohci_db_init(struct fwohci_dbch *dbch) 1136{ 1137 int idb; 1138 struct fwohcidb_tr *db_tr; 1139 int ndbpp, i, j; 1140 1141 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1142 goto out; 1143 1144 /* allocate DB entries and attach one to each DMA channels */ 1145 /* DB entry must start at 16 bytes bounary. */ 1146 STAILQ_INIT(&dbch->db_trq); 1147 db_tr = (struct fwohcidb_tr *) 1148 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1149 M_FW, M_ZERO); 1150 if(db_tr == NULL){ 1151 printf("fwohci_db_init: malloc(1) failed\n"); 1152 return; 1153 } 1154 1155 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1156 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1157 if (firewire_debug) 1158 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1159 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1160 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1161 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1162 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1163 return; 1164 } 1165 for (i = 0; i < dbch->npages; i++) { 1166 dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1167 if (dbch->pages[i] == NULL) { 1168 printf("fwohci_db_init: malloc(2) failed\n"); 1169 for (j = 0; j < i; j ++) 1170 free(dbch->pages[j], M_FW); 1171 free(db_tr, M_FW); 1172 return; 1173 } 1174 } 1175 /* Attach DB to DMA ch. */ 1176 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1177 db_tr->dbcnt = 0; 1178 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1179 + dbch->ndesc * (idb % ndbpp); 1180 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1181 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1182 dbch->xferq.bnpacket != 0) { 1183 if (idb % dbch->xferq.bnpacket == 0) 1184 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1185 ].start = (caddr_t)db_tr; 1186 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1187 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1188 ].end = (caddr_t)db_tr; 1189 } 1190 db_tr++; 1191 } 1192 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1193 = STAILQ_FIRST(&dbch->db_trq); 1194out: 1195 dbch->frag.buf = NULL; 1196 dbch->frag.len = 0; 1197 dbch->frag.plen = 0; 1198 dbch->xferq.queued = 0; 1199 dbch->pdb_tr = NULL; 1200 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1201 dbch->bottom = dbch->top; 1202 dbch->flags = FWOHCI_DBCH_INIT; 1203} 1204 1205static int 1206fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1207{ 1208 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1209 int dummy; 1210 1211 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1212 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1213 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1214 /* XXX we cannot free buffers until the DMA really stops */ 1215 tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1216 fwohci_db_free(&sc->it[dmach]); 1217 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1218 return 0; 1219} 1220 1221static int 1222fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1223{ 1224 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1225 int dummy; 1226 1227 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1228 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1229 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1230 /* XXX we cannot free buffers until the DMA really stops */ 1231 tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1232 if(sc->ir[dmach].dummy != NULL){ 1233 free(sc->ir[dmach].dummy, M_FW); 1234 } 1235 sc->ir[dmach].dummy = NULL; 1236 fwohci_db_free(&sc->ir[dmach]); 1237 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1238 return 0; 1239} 1240 1241static void 1242fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1243{ 1244 qld[0] = ntohl(qld[0]); 1245 return; 1246} 1247 1248static int 1249fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1250{ 1251 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1252 int err = 0; 1253 unsigned short tag, ich; 1254 1255 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1256 ich = sc->ir[dmach].xferq.flag & 0x3f; 1257 1258#if 0 1259 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1260 wakeup(fc->ir[dmach]); 1261 return err; 1262 } 1263#endif 1264 1265 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1266 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1267 sc->ir[dmach].xferq.queued = 0; 1268 sc->ir[dmach].ndb = NDB; 1269 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1270 sc->ir[dmach].ndesc = 1; 1271 fwohci_db_init(&sc->ir[dmach]); 1272 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1273 return ENOMEM; 1274 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1275 } 1276 if(err){ 1277 device_printf(sc->fc.dev, "err in IRX setting\n"); 1278 return err; 1279 } 1280 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1281 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1282 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1283 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1284 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1285 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1286 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1287 OWRITE(sc, OHCI_IRCMD(dmach), 1288 vtophys(sc->ir[dmach].top->db) | 1); 1289 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1290 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1291 } 1292 return err; 1293} 1294 1295static int 1296fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1297{ 1298 int err = 0; 1299 int idb, z, i, dmach = 0; 1300 u_int32_t off = NULL; 1301 struct fwohcidb_tr *db_tr; 1302 volatile struct fwohcidb *db; 1303 1304 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1305 err = EINVAL; 1306 return err; 1307 } 1308 z = dbch->ndesc; 1309 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1310 if( &sc->it[dmach] == dbch){ 1311 off = OHCI_ITOFF(dmach); 1312 break; 1313 } 1314 } 1315 if(off == NULL){ 1316 err = EINVAL; 1317 return err; 1318 } 1319 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1320 return err; 1321 dbch->xferq.flag |= FWXFERQ_RUNNING; 1322 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1323 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1324 } 1325 db_tr = dbch->top; 1326 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1327 fwohci_add_tx_buf(db_tr, 1328 dbch->xferq.psize, dbch->xferq.flag, 1329 dbch->xferq.buf + dbch->xferq.psize * idb); 1330 if(STAILQ_NEXT(db_tr, link) == NULL){ 1331 break; 1332 } 1333 db = db_tr->db; 1334 db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1335 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1336 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1337 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1338 db[db_tr->dbcnt - 1].db.desc.control 1339 |= OHCI_INTERRUPT_ALWAYS; 1340 /* OHCI 1.1 and above */ 1341 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1342#if 0 1343 db[0].db.desc.depend &= ~0xf; 1344 db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1345#endif 1346 } 1347 } 1348 db_tr = STAILQ_NEXT(db_tr, link); 1349 } 1350 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1351 return err; 1352} 1353 1354static int 1355fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1356{ 1357 int err = 0; 1358 int idb, z, i, dmach = 0, ldesc; 1359 u_int32_t off = NULL; 1360 struct fwohcidb_tr *db_tr; 1361 volatile struct fwohcidb *db; 1362 1363 z = dbch->ndesc; 1364 if(&sc->arrq == dbch){ 1365 off = OHCI_ARQOFF; 1366 }else if(&sc->arrs == dbch){ 1367 off = OHCI_ARSOFF; 1368 }else{ 1369 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1370 if( &sc->ir[dmach] == dbch){ 1371 off = OHCI_IROFF(dmach); 1372 break; 1373 } 1374 } 1375 } 1376 if(off == NULL){ 1377 err = EINVAL; 1378 return err; 1379 } 1380 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1381 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1382 return err; 1383 }else{ 1384 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1385 err = EBUSY; 1386 return err; 1387 } 1388 } 1389 dbch->xferq.flag |= FWXFERQ_RUNNING; 1390 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1391 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1392 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1393 } 1394 db_tr = dbch->top; 1395 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1396 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1397 fwohci_add_rx_buf(db_tr, 1398 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1399 }else{ 1400 fwohci_add_rx_buf(db_tr, 1401 dbch->xferq.psize, dbch->xferq.flag, 1402 dbch->xferq.buf + dbch->xferq.psize * idb, 1403 dbch->dummy + sizeof(u_int32_t) * idb); 1404 } 1405 if(STAILQ_NEXT(db_tr, link) == NULL){ 1406 break; 1407 } 1408 db = db_tr->db; 1409 ldesc = db_tr->dbcnt - 1; 1410 db[ldesc].db.desc.depend 1411 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1412 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1413 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1414 db[ldesc].db.desc.control 1415 |= OHCI_INTERRUPT_ALWAYS; 1416 db[ldesc].db.desc.depend &= ~0xf; 1417 } 1418 } 1419 db_tr = STAILQ_NEXT(db_tr, link); 1420 } 1421 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1422 dbch->buf_offset = 0; 1423 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1424 return err; 1425 }else{ 1426 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1427 } 1428 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1429 return err; 1430} 1431 1432static int 1433fwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1434{ 1435 int sec, cycle, cycle_match; 1436 1437 cycle = cycle_now & 0x1fff; 1438 sec = cycle_now >> 13; 1439#define CYCLE_MOD 0x10 1440#define CYCLE_DELAY 8 /* min delay to start DMA */ 1441 cycle = cycle + CYCLE_DELAY; 1442 if (cycle >= 8000) { 1443 sec ++; 1444 cycle -= 8000; 1445 } 1446 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1447 if (cycle >= 8000) { 1448 sec ++; 1449 if (cycle == 8000) 1450 cycle = 0; 1451 else 1452 cycle = CYCLE_MOD; 1453 } 1454 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1455 1456 return(cycle_match); 1457} 1458 1459static int 1460fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1461{ 1462 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1463 int err = 0; 1464 unsigned short tag, ich; 1465 struct fwohci_dbch *dbch; 1466 int cycle_match, cycle_now, s, ldesc; 1467 u_int32_t stat; 1468 struct fw_bulkxfer *first, *chunk, *prev; 1469 struct fw_xferq *it; 1470 1471 dbch = &sc->it[dmach]; 1472 it = &dbch->xferq; 1473 1474 tag = (it->flag >> 6) & 3; 1475 ich = it->flag & 0x3f; 1476 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1477 dbch->ndb = it->bnpacket * it->bnchunk; 1478 dbch->ndesc = 3; 1479 fwohci_db_init(dbch); 1480 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1481 return ENOMEM; 1482 err = fwohci_tx_enable(sc, dbch); 1483 } 1484 if(err) 1485 return err; 1486 1487 ldesc = dbch->ndesc - 1; 1488 s = splfw(); 1489 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1490 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1491 volatile struct fwohcidb *db; 1492 1493 fwohci_txbufdb(sc, dmach, chunk); 1494#if 0 1495 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1496 db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1497 db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1498 db[ldesc].db.desc.depend &= ~0xf; 1499 db[0].db.desc.depend &= ~0xf; 1500#endif 1501 if (prev != NULL) { 1502 db = ((struct fwohcidb_tr *)(prev->end))->db; 1503 db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1504#if 0 /* if bulkxfer->npacket changes */ 1505 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1506 vtophys(((struct fwohcidb_tr *) 1507 (chunk->start))->db) | dbch->ndesc; 1508#else 1509 db[0].db.desc.depend |= dbch->ndesc; 1510 db[ldesc].db.desc.depend |= dbch->ndesc; 1511#endif 1512 } 1513 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1514 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1515 prev = chunk; 1516 } 1517 splx(s); 1518 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1519 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1520 return 0; 1521 1522 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1523 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1524 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1525 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1526 1527 first = STAILQ_FIRST(&it->stdma); 1528 OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1529 (first->start))->db) | dbch->ndesc); 1530 if (firewire_debug) 1531 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1532 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1533#if 1 1534 /* Don't start until all chunks are buffered */ 1535 if (STAILQ_FIRST(&it->stfree) != NULL) 1536 goto out; 1537#endif 1538#ifdef FWXFERQ_DV 1539#define CYCLE_OFFSET 1 1540 if(dbch->xferq.flag & FWXFERQ_DV){ 1541 struct fw_pkt *fp; 1542 struct fwohcidb_tr *db_tr; 1543 1544 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1545 fp = (struct fw_pkt *)db_tr->buf; 1546 dbch->xferq.dvoffset = CYCLE_OFFSET; 1547 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1548 } 1549#endif 1550 /* Clear cycle match counter bits */ 1551 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1552 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1553 1554 /* 2bit second + 13bit cycle */ 1555 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1556 cycle_match = fwochi_next_cycle(fc, cycle_now); 1557 1558 OWRITE(sc, OHCI_ITCTL(dmach), 1559 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1560 | OHCI_CNTL_DMA_RUN); 1561 if (firewire_debug) 1562 printf("cycle_match: 0x%04x->0x%04x\n", 1563 cycle_now, cycle_match); 1564 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1565 device_printf(sc->fc.dev, 1566 "IT DMA underrun (0x%08x)\n", stat); 1567 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1568 } 1569out: 1570 return err; 1571} 1572 1573static int 1574fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1575{ 1576 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1577 int err = 0, s, ldesc; 1578 unsigned short tag, ich; 1579 u_int32_t stat; 1580 struct fwohci_dbch *dbch; 1581 struct fw_bulkxfer *first, *prev, *chunk; 1582 struct fw_xferq *ir; 1583 1584 dbch = &sc->ir[dmach]; 1585 ir = &dbch->xferq; 1586 ldesc = dbch->ndesc - 1; 1587 1588 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1589 tag = (ir->flag >> 6) & 3; 1590 ich = ir->flag & 0x3f; 1591 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1592 1593 ir->queued = 0; 1594 dbch->ndb = ir->bnpacket * ir->bnchunk; 1595 dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1596 M_FW, 0); 1597 if (dbch->dummy == NULL) { 1598 err = ENOMEM; 1599 return err; 1600 } 1601 dbch->ndesc = 2; 1602 fwohci_db_init(dbch); 1603 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1604 return ENOMEM; 1605 err = fwohci_rx_enable(sc, dbch); 1606 } 1607 if(err) 1608 return err; 1609 1610 s = splfw(); 1611 1612 first = STAILQ_FIRST(&ir->stfree); 1613 if (first == NULL) { 1614 device_printf(fc->dev, "IR DMA no free chunk\n"); 1615 splx(s); 1616 return 0; 1617 } 1618 1619 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1620 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1621 volatile struct fwohcidb *db; 1622 1623 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1624 db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1625 db[ldesc].db.desc.depend &= ~0xf; 1626 if (prev != NULL) { 1627 db = ((struct fwohcidb_tr *)(prev->end))->db; 1628#if 0 1629 db[ldesc].db.desc.depend = 1630 vtophys(((struct fwohcidb_tr *) 1631 (chunk->start))->db) | dbch->ndesc; 1632#else 1633 db[ldesc].db.desc.depend |= dbch->ndesc; 1634#endif 1635 } 1636 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1637 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1638 prev = chunk; 1639 } 1640 splx(s); 1641 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1642 if (stat & OHCI_CNTL_DMA_ACTIVE) 1643 return 0; 1644 if (stat & OHCI_CNTL_DMA_RUN) { 1645 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1646 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1647 } 1648 1649 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1650 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1651 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1652 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1653 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1654 OWRITE(sc, OHCI_IRCMD(dmach), 1655 vtophys(((struct fwohcidb_tr *)(first->start))->db) 1656 | dbch->ndesc); 1657 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1658 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1659 return err; 1660} 1661 1662static int 1663fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1664{ 1665 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1666 int err = 0; 1667 1668 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1669 err = fwohci_irxpp_enable(fc, dmach); 1670 return err; 1671 }else{ 1672 err = fwohci_irxbuf_enable(fc, dmach); 1673 return err; 1674 } 1675} 1676 1677int 1678fwohci_stop(struct fwohci_softc *sc, device_t dev) 1679{ 1680 u_int i; 1681 1682/* Now stopping all DMA channel */ 1683 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1684 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1685 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1686 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1687 1688 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1689 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1690 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1691 } 1692 1693/* FLUSH FIFO and reset Transmitter/Reciever */ 1694 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1695 1696/* Stop interrupt */ 1697 OWRITE(sc, FWOHCI_INTMASKCLR, 1698 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1699 | OHCI_INT_PHY_INT 1700 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1701 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1702 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1703 | OHCI_INT_PHY_BUS_R); 1704/* XXX Link down? Bus reset? */ 1705 return 0; 1706} 1707 1708int 1709fwohci_resume(struct fwohci_softc *sc, device_t dev) 1710{ 1711 int i; 1712 1713 fwohci_reset(sc, dev); 1714 /* XXX resume isochronus receive automatically. (how about TX?) */ 1715 for(i = 0; i < sc->fc.nisodma; i ++) { 1716 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1717 device_printf(sc->fc.dev, 1718 "resume iso receive ch: %d\n", i); 1719 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1720 sc->fc.irx_enable(&sc->fc, i); 1721 } 1722 } 1723 1724 bus_generic_resume(dev); 1725 sc->fc.ibr(&sc->fc); 1726 return 0; 1727} 1728 1729#define ACK_ALL 1730static void 1731fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1732{ 1733 u_int32_t irstat, itstat; 1734 u_int i; 1735 struct firewire_comm *fc = (struct firewire_comm *)sc; 1736 1737#ifdef OHCI_DEBUG 1738 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1739 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1740 stat & OHCI_INT_EN ? "DMA_EN ":"", 1741 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1742 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1743 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1744 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1745 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1746 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1747 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1748 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1749 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1750 stat & OHCI_INT_PHY_SID ? "SID ":"", 1751 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1752 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1753 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1754 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1755 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1756 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1757 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1758 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1759 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1760 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1761 stat, OREAD(sc, FWOHCI_INTMASK) 1762 ); 1763#endif 1764/* Bus reset */ 1765 if(stat & OHCI_INT_PHY_BUS_R ){ 1766 device_printf(fc->dev, "BUS reset\n"); 1767 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1768 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1769 1770 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1771 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1772 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1773 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1774 1775#if 0 1776 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1777 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1778 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1779 } 1780 1781#endif 1782 fw_busreset(fc); 1783 1784 /* XXX need to wait DMA to stop */ 1785#ifndef ACK_ALL 1786 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1787#endif 1788#if 0 1789 /* pending all pre-bus_reset packets */ 1790 fwohci_txd(sc, &sc->atrq); 1791 fwohci_txd(sc, &sc->atrs); 1792 fwohci_arcv(sc, &sc->arrs, -1); 1793 fwohci_arcv(sc, &sc->arrq, -1); 1794#endif 1795 1796 1797 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1798 /* XXX insecure ?? */ 1799 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1800 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1801 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1802 1803 } 1804 if((stat & OHCI_INT_DMA_IR )){ 1805#ifndef ACK_ALL 1806 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1807#endif 1808 irstat = OREAD(sc, OHCI_IR_STAT); 1809 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1810 for(i = 0; i < fc->nisodma ; i++){ 1811 struct fwohci_dbch *dbch; 1812 1813 if((irstat & (1 << i)) != 0){ 1814 dbch = &sc->ir[i]; 1815 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1816 device_printf(sc->fc.dev, 1817 "dma(%d) not active\n", i); 1818 continue; 1819 } 1820 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1821 fwohci_ircv(sc, dbch, count); 1822 } else { 1823 fwohci_rbuf_update(sc, i); 1824 } 1825 } 1826 } 1827 } 1828 if((stat & OHCI_INT_DMA_IT )){ 1829#ifndef ACK_ALL 1830 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1831#endif 1832 itstat = OREAD(sc, OHCI_IT_STAT); 1833 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1834 for(i = 0; i < fc->nisodma ; i++){ 1835 if((itstat & (1 << i)) != 0){ 1836 fwohci_tbuf_update(sc, i); 1837 } 1838 } 1839 } 1840 if((stat & OHCI_INT_DMA_PRRS )){ 1841#ifndef ACK_ALL 1842 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1843#endif 1844#if 0 1845 dump_dma(sc, ARRS_CH); 1846 dump_db(sc, ARRS_CH); 1847#endif 1848 fwohci_arcv(sc, &sc->arrs, count); 1849 } 1850 if((stat & OHCI_INT_DMA_PRRQ )){ 1851#ifndef ACK_ALL 1852 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1853#endif 1854#if 0 1855 dump_dma(sc, ARRQ_CH); 1856 dump_db(sc, ARRQ_CH); 1857#endif 1858 fwohci_arcv(sc, &sc->arrq, count); 1859 } 1860 if(stat & OHCI_INT_PHY_SID){ 1861 caddr_t buf; 1862 int plen; 1863 1864#ifndef ACK_ALL 1865 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1866#endif 1867/* 1868** Checking whether the node is root or not. If root, turn on 1869** cycle master. 1870*/ 1871 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1872 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1873 printf("Bus reset failure\n"); 1874 goto sidout; 1875 } 1876 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1877 printf("CYCLEMASTER mode\n"); 1878 OWRITE(sc, OHCI_LNKCTL, 1879 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1880 }else{ 1881 printf("non CYCLEMASTER mode\n"); 1882 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1883 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1884 } 1885 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1886 1887 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1888 if (plen < 4 || plen > OHCI_SIDSIZE) { 1889 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1890 goto sidout; 1891 } 1892 plen -= 4; /* chop control info */ 1893 buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1894 if(buf == NULL) goto sidout; 1895 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1896 buf, plen); 1897#if 1 1898 /* pending all pre-bus_reset packets */ 1899 fwohci_txd(sc, &sc->atrq); 1900 fwohci_txd(sc, &sc->atrs); 1901 fwohci_arcv(sc, &sc->arrs, -1); 1902 fwohci_arcv(sc, &sc->arrq, -1); 1903#endif 1904 fw_sidrcv(fc, buf, plen, 0); 1905 } 1906sidout: 1907 if((stat & OHCI_INT_DMA_ATRQ )){ 1908#ifndef ACK_ALL 1909 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1910#endif 1911 fwohci_txd(sc, &(sc->atrq)); 1912 } 1913 if((stat & OHCI_INT_DMA_ATRS )){ 1914#ifndef ACK_ALL 1915 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1916#endif 1917 fwohci_txd(sc, &(sc->atrs)); 1918 } 1919 if((stat & OHCI_INT_PW_ERR )){ 1920#ifndef ACK_ALL 1921 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1922#endif 1923 device_printf(fc->dev, "posted write error\n"); 1924 } 1925 if((stat & OHCI_INT_ERR )){ 1926#ifndef ACK_ALL 1927 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1928#endif 1929 device_printf(fc->dev, "unrecoverable error\n"); 1930 } 1931 if((stat & OHCI_INT_PHY_INT)) { 1932#ifndef ACK_ALL 1933 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1934#endif 1935 device_printf(fc->dev, "phy int\n"); 1936 } 1937 1938 return; 1939} 1940 1941void 1942fwohci_intr(void *arg) 1943{ 1944 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1945 u_int32_t stat; 1946 1947 if (!(sc->intmask & OHCI_INT_EN)) { 1948 /* polling mode */ 1949 return; 1950 } 1951 1952 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1953 if (stat == 0xffffffff) { 1954 device_printf(sc->fc.dev, 1955 "device physically ejected?\n"); 1956 return; 1957 } 1958#ifdef ACK_ALL 1959 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1960#endif 1961 fwohci_intr_body(sc, stat, -1); 1962 } 1963} 1964 1965static void 1966fwohci_poll(struct firewire_comm *fc, int quick, int count) 1967{ 1968 int s; 1969 u_int32_t stat; 1970 struct fwohci_softc *sc; 1971 1972 1973 sc = (struct fwohci_softc *)fc; 1974 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1975 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1976 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1977#if 0 1978 if (!quick) { 1979#else 1980 if (1) { 1981#endif 1982 stat = OREAD(sc, FWOHCI_INTSTAT); 1983 if (stat == 0) 1984 return; 1985 if (stat == 0xffffffff) { 1986 device_printf(sc->fc.dev, 1987 "device physically ejected?\n"); 1988 return; 1989 } 1990#ifdef ACK_ALL 1991 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1992#endif 1993 } 1994 s = splfw(); 1995 fwohci_intr_body(sc, stat, count); 1996 splx(s); 1997} 1998 1999static void 2000fwohci_set_intr(struct firewire_comm *fc, int enable) 2001{ 2002 struct fwohci_softc *sc; 2003 2004 sc = (struct fwohci_softc *)fc; 2005 if (bootverbose) 2006 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2007 if (enable) { 2008 sc->intmask |= OHCI_INT_EN; 2009 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2010 } else { 2011 sc->intmask &= ~OHCI_INT_EN; 2012 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2013 } 2014} 2015 2016static void 2017fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2018{ 2019 struct firewire_comm *fc = &sc->fc; 2020 volatile struct fwohcidb *db; 2021 struct fw_bulkxfer *chunk; 2022 struct fw_xferq *it; 2023 u_int32_t stat, count; 2024 int s, w=0; 2025 2026 it = fc->it[dmach]; 2027 s = splfw(); /* unnecessary ? */ 2028 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2029 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2030 stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2031 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2032 count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2033 if (stat == 0) 2034 break; 2035 STAILQ_REMOVE_HEAD(&it->stdma, link); 2036 switch (stat & FWOHCIEV_MASK){ 2037 case FWOHCIEV_ACKCOMPL: 2038#if 0 2039 device_printf(fc->dev, "0x%08x\n", count); 2040#endif 2041 break; 2042 default: 2043 device_printf(fc->dev, 2044 "Isochronous transmit err %02x\n", stat); 2045 } 2046 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2047 w++; 2048 } 2049 splx(s); 2050 if (w) 2051 wakeup(it); 2052} 2053 2054static void 2055fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2056{ 2057 struct firewire_comm *fc = &sc->fc; 2058 volatile struct fwohcidb *db; 2059 struct fw_bulkxfer *chunk; 2060 struct fw_xferq *ir; 2061 u_int32_t stat; 2062 int s, w=0; 2063 2064 ir = fc->ir[dmach]; 2065 s = splfw(); 2066 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2067 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2068 stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2069 if (stat == 0) 2070 break; 2071 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2072 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2073 switch (stat & FWOHCIEV_MASK) { 2074 case FWOHCIEV_ACKCOMPL: 2075 break; 2076 default: 2077 device_printf(fc->dev, 2078 "Isochronous receive err %02x\n", stat); 2079 } 2080 w++; 2081 } 2082 splx(s); 2083 if (w) 2084 wakeup(ir); 2085} 2086 2087void 2088dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2089{ 2090 u_int32_t off, cntl, stat, cmd, match; 2091 2092 if(ch == 0){ 2093 off = OHCI_ATQOFF; 2094 }else if(ch == 1){ 2095 off = OHCI_ATSOFF; 2096 }else if(ch == 2){ 2097 off = OHCI_ARQOFF; 2098 }else if(ch == 3){ 2099 off = OHCI_ARSOFF; 2100 }else if(ch < IRX_CH){ 2101 off = OHCI_ITCTL(ch - ITX_CH); 2102 }else{ 2103 off = OHCI_IRCTL(ch - IRX_CH); 2104 } 2105 cntl = stat = OREAD(sc, off); 2106 cmd = OREAD(sc, off + 0xc); 2107 match = OREAD(sc, off + 0x10); 2108 2109 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2110 ch, 2111 cntl, 2112 stat, 2113 cmd, 2114 match); 2115 stat &= 0xffff ; 2116 if(stat & 0xff00){ 2117 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2118 ch, 2119 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2120 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2121 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2122 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2123 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2124 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2125 fwohcicode[stat & 0x1f], 2126 stat & 0x1f 2127 ); 2128 }else{ 2129 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2130 } 2131} 2132 2133void 2134dump_db(struct fwohci_softc *sc, u_int32_t ch) 2135{ 2136 struct fwohci_dbch *dbch; 2137 struct fwohcidb_tr *cp = NULL, *pp, *np; 2138 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2139 int idb, jdb; 2140 u_int32_t cmd, off; 2141 if(ch == 0){ 2142 off = OHCI_ATQOFF; 2143 dbch = &sc->atrq; 2144 }else if(ch == 1){ 2145 off = OHCI_ATSOFF; 2146 dbch = &sc->atrs; 2147 }else if(ch == 2){ 2148 off = OHCI_ARQOFF; 2149 dbch = &sc->arrq; 2150 }else if(ch == 3){ 2151 off = OHCI_ARSOFF; 2152 dbch = &sc->arrs; 2153 }else if(ch < IRX_CH){ 2154 off = OHCI_ITCTL(ch - ITX_CH); 2155 dbch = &sc->it[ch - ITX_CH]; 2156 }else { 2157 off = OHCI_IRCTL(ch - IRX_CH); 2158 dbch = &sc->ir[ch - IRX_CH]; 2159 } 2160 cmd = OREAD(sc, off + 0xc); 2161 2162 if( dbch->ndb == 0 ){ 2163 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2164 return; 2165 } 2166 pp = dbch->top; 2167 prev = pp->db; 2168 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2169 if(pp == NULL){ 2170 curr = NULL; 2171 goto outdb; 2172 } 2173 cp = STAILQ_NEXT(pp, link); 2174 if(cp == NULL){ 2175 curr = NULL; 2176 goto outdb; 2177 } 2178 np = STAILQ_NEXT(cp, link); 2179 if(cp == NULL) break; 2180 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2181 if((cmd & 0xfffffff0) 2182 == vtophys(&(cp->db[jdb]))){ 2183 curr = cp->db; 2184 if(np != NULL){ 2185 next = np->db; 2186 }else{ 2187 next = NULL; 2188 } 2189 goto outdb; 2190 } 2191 } 2192 pp = STAILQ_NEXT(pp, link); 2193 prev = pp->db; 2194 } 2195outdb: 2196 if( curr != NULL){ 2197 printf("Prev DB %d\n", ch); 2198 print_db(prev, ch, dbch->ndesc); 2199 printf("Current DB %d\n", ch); 2200 print_db(curr, ch, dbch->ndesc); 2201 printf("Next DB %d\n", ch); 2202 print_db(next, ch, dbch->ndesc); 2203 }else{ 2204 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2205 } 2206 return; 2207} 2208 2209void 2210print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2211{ 2212 fwohcireg_t stat; 2213 int i, key; 2214 2215 if(db == NULL){ 2216 printf("No Descriptor is found\n"); 2217 return; 2218 } 2219 2220 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2221 ch, 2222 "Current", 2223 "OP ", 2224 "KEY", 2225 "INT", 2226 "BR ", 2227 "len", 2228 "Addr", 2229 "Depend", 2230 "Stat", 2231 "Cnt"); 2232 for( i = 0 ; i <= max ; i ++){ 2233 key = db[i].db.desc.control & OHCI_KEY_MASK; 2234#if __FreeBSD_version >= 500000 2235 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2236#else 2237 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2238#endif 2239 vtophys(&db[i]), 2240 dbcode[(db[i].db.desc.control >> 12) & 0xf], 2241 dbkey[(db[i].db.desc.control >> 8) & 0x7], 2242 dbcond[(db[i].db.desc.control >> 4) & 0x3], 2243 dbcond[(db[i].db.desc.control >> 2) & 0x3], 2244 db[i].db.desc.reqcount, 2245 db[i].db.desc.addr, 2246 db[i].db.desc.depend, 2247 db[i].db.desc.status, 2248 db[i].db.desc.count); 2249 stat = db[i].db.desc.status; 2250 if(stat & 0xff00){ 2251 printf(" %s%s%s%s%s%s %s(%x)\n", 2252 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2253 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2254 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2255 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2256 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2257 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2258 fwohcicode[stat & 0x1f], 2259 stat & 0x1f 2260 ); 2261 }else{ 2262 printf(" Nostat\n"); 2263 } 2264 if(key == OHCI_KEY_ST2 ){ 2265 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2266 db[i+1].db.immed[0], 2267 db[i+1].db.immed[1], 2268 db[i+1].db.immed[2], 2269 db[i+1].db.immed[3]); 2270 } 2271 if(key == OHCI_KEY_DEVICE){ 2272 return; 2273 } 2274 if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2275 == OHCI_BRANCH_ALWAYS){ 2276 return; 2277 } 2278 if((db[i].db.desc.control & OHCI_CMD_MASK) 2279 == OHCI_OUTPUT_LAST){ 2280 return; 2281 } 2282 if((db[i].db.desc.control & OHCI_CMD_MASK) 2283 == OHCI_INPUT_LAST){ 2284 return; 2285 } 2286 if(key == OHCI_KEY_ST2 ){ 2287 i++; 2288 } 2289 } 2290 return; 2291} 2292 2293void 2294fwohci_ibr(struct firewire_comm *fc) 2295{ 2296 struct fwohci_softc *sc; 2297 u_int32_t fun; 2298 2299 sc = (struct fwohci_softc *)fc; 2300 2301 /* 2302 * Set root hold-off bit so that non cyclemaster capable node 2303 * shouldn't became the root node. 2304 */ 2305#if 1 2306 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2307 fun |= FW_PHY_IBR | FW_PHY_RHB; 2308 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2309#else /* Short bus reset */ 2310 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2311 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2312 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2313#endif 2314} 2315 2316void 2317fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2318{ 2319 struct fwohcidb_tr *db_tr, *fdb_tr; 2320 struct fwohci_dbch *dbch; 2321 volatile struct fwohcidb *db; 2322 struct fw_pkt *fp; 2323 volatile struct fwohci_txpkthdr *ohcifp; 2324 unsigned short chtag; 2325 int idb; 2326 2327 dbch = &sc->it[dmach]; 2328 chtag = sc->it[dmach].xferq.flag & 0xff; 2329 2330 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2331 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2332/* 2333device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2334*/ 2335 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2336 db = db_tr->db; 2337#if 0 2338 db[0].db.desc.control 2339 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2340 db[0].db.desc.reqcount = 8; 2341#endif 2342 fp = (struct fw_pkt *)db_tr->buf; 2343 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2344 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2345 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2346 ohcifp->mode.stream.chtag = chtag; 2347 ohcifp->mode.stream.tcode = 0xa; 2348 ohcifp->mode.stream.spd = 0; 2349 2350 db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2351 db[2].db.desc.status = 0; 2352 db[2].db.desc.count = 0; 2353#if 0 /* if bulkxfer->npackets changes */ 2354 db[2].db.desc.control = OHCI_OUTPUT_LAST 2355 | OHCI_UPDATE 2356 | OHCI_BRANCH_ALWAYS; 2357 db[0].db.desc.depend = 2358 = db[dbch->ndesc - 1].db.desc.depend 2359 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2360#else 2361 db[0].db.desc.depend |= dbch->ndesc; 2362 db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2363#endif 2364 bulkxfer->end = (caddr_t)db_tr; 2365 db_tr = STAILQ_NEXT(db_tr, link); 2366 } 2367 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2368 db[0].db.desc.depend &= ~0xf; 2369 db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2370#if 0 /* if bulkxfer->npackets changes */ 2371 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2372 /* OHCI 1.1 and above */ 2373 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2374#endif 2375/* 2376 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2377 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2378device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2379*/ 2380 return; 2381} 2382 2383static int 2384fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2385 int mode, void *buf) 2386{ 2387 volatile struct fwohcidb *db = db_tr->db; 2388 int err = 0; 2389 if(buf == 0){ 2390 err = EINVAL; 2391 return err; 2392 } 2393 db_tr->buf = buf; 2394 db_tr->dbcnt = 3; 2395 db_tr->dummy = NULL; 2396 2397 db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2398 db[0].db.desc.reqcount = 8; 2399 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2400 db[2].db.desc.control = 2401 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2402#if 1 2403 db[0].db.desc.status = 0; 2404 db[0].db.desc.count = 0; 2405 db[2].db.desc.status = 0; 2406 db[2].db.desc.count = 0; 2407#endif 2408 if( mode & FWXFERQ_STREAM ){ 2409 if(mode & FWXFERQ_PACKET ){ 2410 db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2411 } 2412 } else { 2413 printf("fwohci_add_tx_buf: who calls me?"); 2414 } 2415 return 1; 2416} 2417 2418int 2419fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2420 void *buf, void *dummy) 2421{ 2422 volatile struct fwohcidb *db = db_tr->db; 2423 int i; 2424 void *dbuf[2]; 2425 int dsiz[2]; 2426 2427 if(buf == 0){ 2428 buf = malloc(size, M_FW, M_NOWAIT); 2429 if(buf == NULL) return 0; 2430 db_tr->buf = buf; 2431 db_tr->dbcnt = 1; 2432 db_tr->dummy = NULL; 2433 dsiz[0] = size; 2434 dbuf[0] = buf; 2435 }else if(dummy == NULL){ 2436 db_tr->buf = buf; 2437 db_tr->dbcnt = 1; 2438 db_tr->dummy = NULL; 2439 dsiz[0] = size; 2440 dbuf[0] = buf; 2441 }else{ 2442 db_tr->buf = buf; 2443 db_tr->dbcnt = 2; 2444 db_tr->dummy = dummy; 2445 dsiz[0] = sizeof(u_int32_t); 2446 dsiz[1] = size; 2447 dbuf[0] = dummy; 2448 dbuf[1] = buf; 2449 } 2450 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2451 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2452 db[i].db.desc.control = OHCI_INPUT_MORE; 2453 db[i].db.desc.reqcount = dsiz[i]; 2454 if( mode & FWXFERQ_STREAM ){ 2455 db[i].db.desc.control |= OHCI_UPDATE; 2456 } 2457 db[i].db.desc.status = 0; 2458 db[i].db.desc.count = dsiz[i]; 2459 } 2460 if( mode & FWXFERQ_STREAM ){ 2461 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2462 if(mode & FWXFERQ_PACKET ){ 2463 db[db_tr->dbcnt - 1].db.desc.control 2464 |= OHCI_INTERRUPT_ALWAYS; 2465 } 2466 } 2467 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2468 return 1; 2469} 2470 2471static void 2472fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2473{ 2474 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2475 struct firewire_comm *fc = (struct firewire_comm *)sc; 2476 int z = 1; 2477 struct fw_pkt *fp; 2478 u_int8_t *ld; 2479 u_int32_t off = NULL; 2480 u_int32_t stat; 2481 u_int32_t *qld; 2482 u_int32_t reg; 2483 u_int spd; 2484 u_int dmach; 2485 int len, i, plen; 2486 caddr_t buf; 2487 2488 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2489 if( &sc->ir[dmach] == dbch){ 2490 off = OHCI_IROFF(dmach); 2491 break; 2492 } 2493 } 2494 if(off == NULL){ 2495 return; 2496 } 2497 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2498 fwohci_irx_disable(&sc->fc, dmach); 2499 return; 2500 } 2501 2502 odb_tr = NULL; 2503 db_tr = dbch->top; 2504 i = 0; 2505 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2506 if (count >= 0 && count-- == 0) 2507 break; 2508 ld = (u_int8_t *)db_tr->buf; 2509 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2510 /* skip timeStamp */ 2511 ld += sizeof(struct fwohci_trailer); 2512 } 2513 qld = (u_int32_t *)ld; 2514 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2515/* 2516{ 2517device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2518 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2519} 2520*/ 2521 fp=(struct fw_pkt *)ld; 2522 qld[0] = htonl(qld[0]); 2523 plen = sizeof(struct fw_isohdr) 2524 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2525 ld += plen; 2526 len -= plen; 2527 buf = db_tr->buf; 2528 db_tr->buf = NULL; 2529 stat = reg & 0x1f; 2530 spd = reg & 0x3; 2531 switch(stat){ 2532 case FWOHCIEV_ACKCOMPL: 2533 case FWOHCIEV_ACKPEND: 2534 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2535 break; 2536 default: 2537 free(buf, M_FW); 2538 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2539 break; 2540 } 2541 i++; 2542 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2543 dbch->xferq.flag, 0, NULL); 2544 db_tr->db[0].db.desc.depend &= ~0xf; 2545 if(dbch->pdb_tr != NULL){ 2546 dbch->pdb_tr->db[0].db.desc.depend |= z; 2547 } else { 2548 /* XXX should be rewritten in better way */ 2549 dbch->bottom->db[0].db.desc.depend |= z; 2550 } 2551 dbch->pdb_tr = db_tr; 2552 db_tr = STAILQ_NEXT(db_tr, link); 2553 } 2554 dbch->top = db_tr; 2555 reg = OREAD(sc, OHCI_DMACTL(off)); 2556 if (reg & OHCI_CNTL_DMA_ACTIVE) 2557 return; 2558 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2559 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2560 dbch->top = db_tr; 2561 fwohci_irx_enable(fc, dmach); 2562} 2563 2564#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2565static int 2566fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2567{ 2568 int i; 2569 2570 for( i = 4; i < hlen ; i+=4){ 2571 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2572 } 2573 2574 switch(fp->mode.common.tcode){ 2575 case FWTCODE_RREQQ: 2576 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2577 case FWTCODE_WRES: 2578 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2579 case FWTCODE_WREQQ: 2580 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2581 case FWTCODE_RREQB: 2582 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2583 case FWTCODE_RRESQ: 2584 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2585 case FWTCODE_WREQB: 2586 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2587 + sizeof(u_int32_t); 2588 case FWTCODE_LREQ: 2589 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2590 + sizeof(u_int32_t); 2591 case FWTCODE_RRESB: 2592 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2593 + sizeof(u_int32_t); 2594 case FWTCODE_LRES: 2595 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2596 + sizeof(u_int32_t); 2597 case FWOHCITCODE_PHY: 2598 return 16; 2599 } 2600 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2601 return 0; 2602} 2603 2604static void 2605fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2606{ 2607 struct fwohcidb_tr *db_tr; 2608 int z = 1; 2609 struct fw_pkt *fp; 2610 u_int8_t *ld; 2611 u_int32_t stat, off; 2612 u_int spd; 2613 int len, plen, hlen, pcnt, poff = 0, rlen; 2614 int s; 2615 caddr_t buf; 2616 int resCount; 2617 2618 if(&sc->arrq == dbch){ 2619 off = OHCI_ARQOFF; 2620 }else if(&sc->arrs == dbch){ 2621 off = OHCI_ARSOFF; 2622 }else{ 2623 return; 2624 } 2625 2626 s = splfw(); 2627 db_tr = dbch->top; 2628 pcnt = 0; 2629 /* XXX we cannot handle a packet which lies in more than two buf */ 2630 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2631 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2632 resCount = db_tr->db[0].db.desc.count; 2633 len = dbch->xferq.psize - resCount 2634 - dbch->buf_offset; 2635 while (len > 0 ) { 2636 if (count >= 0 && count-- == 0) 2637 goto out; 2638 if(dbch->frag.buf != NULL){ 2639 buf = dbch->frag.buf; 2640 if (dbch->frag.plen < 0) { 2641 /* incomplete header */ 2642 int hlen; 2643 2644 hlen = - dbch->frag.plen; 2645 rlen = hlen - dbch->frag.len; 2646 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2647 ld += rlen; 2648 len -= rlen; 2649 dbch->frag.len += rlen; 2650#if 0 2651 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2652#endif 2653 fp=(struct fw_pkt *)dbch->frag.buf; 2654 dbch->frag.plen 2655 = fwohci_get_plen(sc, fp, hlen); 2656 if (dbch->frag.plen == 0) 2657 goto out; 2658 } 2659 rlen = dbch->frag.plen - dbch->frag.len; 2660#if 0 2661 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2662#endif 2663 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2664 rlen); 2665 ld += rlen; 2666 len -= rlen; 2667 plen = dbch->frag.plen; 2668 dbch->frag.buf = NULL; 2669 dbch->frag.plen = 0; 2670 dbch->frag.len = 0; 2671 poff = 0; 2672 }else{ 2673 fp=(struct fw_pkt *)ld; 2674 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2675 switch(fp->mode.common.tcode){ 2676 case FWTCODE_RREQQ: 2677 case FWTCODE_WRES: 2678 case FWTCODE_WREQQ: 2679 case FWTCODE_RRESQ: 2680 case FWOHCITCODE_PHY: 2681 hlen = 12; 2682 break; 2683 case FWTCODE_RREQB: 2684 case FWTCODE_WREQB: 2685 case FWTCODE_LREQ: 2686 case FWTCODE_RRESB: 2687 case FWTCODE_LRES: 2688 hlen = 16; 2689 break; 2690 default: 2691 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2692 goto out; 2693 } 2694 if (len >= hlen) { 2695 plen = fwohci_get_plen(sc, fp, hlen); 2696 if (plen == 0) 2697 goto out; 2698 plen = (plen + 3) & ~3; 2699 len -= plen; 2700 } else { 2701 plen = -hlen; 2702 len -= hlen; 2703 } 2704 if(resCount > 0 || len > 0){ 2705 buf = malloc( dbch->xferq.psize, 2706 M_FW, M_NOWAIT); 2707 if(buf == NULL){ 2708 printf("cannot malloc!\n"); 2709 free(db_tr->buf, M_FW); 2710 goto out; 2711 } 2712 bcopy(ld, buf, plen); 2713 poff = 0; 2714 dbch->frag.buf = NULL; 2715 dbch->frag.plen = 0; 2716 dbch->frag.len = 0; 2717 }else if(len < 0){ 2718 dbch->frag.buf = db_tr->buf; 2719 if (plen < 0) { 2720#if 0 2721 printf("plen < 0:" 2722 "hlen: %d len: %d\n", 2723 hlen, len); 2724#endif 2725 dbch->frag.len = hlen + len; 2726 dbch->frag.plen = -hlen; 2727 } else { 2728 dbch->frag.len = plen + len; 2729 dbch->frag.plen = plen; 2730 } 2731 bcopy(ld, db_tr->buf, dbch->frag.len); 2732 buf = NULL; 2733 }else{ 2734 buf = db_tr->buf; 2735 poff = ld - (u_int8_t *)buf; 2736 dbch->frag.buf = NULL; 2737 dbch->frag.plen = 0; 2738 dbch->frag.len = 0; 2739 } 2740 ld += plen; 2741 } 2742 if( buf != NULL){ 2743/* DMA result-code will be written at the tail of packet */ 2744 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2745 spd = (stat >> 5) & 0x3; 2746 stat &= 0x1f; 2747 switch(stat){ 2748 case FWOHCIEV_ACKPEND: 2749#if 1 2750 printf("fwohci_arcv: ack pending..\n"); 2751#endif 2752 /* fall through */ 2753 case FWOHCIEV_ACKCOMPL: 2754 if( poff != 0 ) 2755 bcopy(buf+poff, buf, plen - 4); 2756 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2757 break; 2758 case FWOHCIEV_BUSRST: 2759 free(buf, M_FW); 2760 if (sc->fc.status != FWBUSRESET) 2761 printf("got BUSRST packet!?\n"); 2762 break; 2763 default: 2764 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2765#if 0 /* XXX */ 2766 goto out; 2767#endif 2768 break; 2769 } 2770 } 2771 pcnt ++; 2772 }; 2773out: 2774 if (resCount == 0) { 2775 /* done on this buffer */ 2776 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2777 dbch->xferq.flag, 0, NULL); 2778 dbch->bottom->db[0].db.desc.depend |= z; 2779 dbch->bottom = db_tr; 2780 db_tr = STAILQ_NEXT(db_tr, link); 2781 dbch->top = db_tr; 2782 dbch->buf_offset = 0; 2783 } else { 2784 dbch->buf_offset = dbch->xferq.psize - resCount; 2785 break; 2786 } 2787 /* XXX make sure DMA is not dead */ 2788 } 2789#if 0 2790 if (pcnt < 1) 2791 printf("fwohci_arcv: no packets\n"); 2792#endif 2793 splx(s); 2794} 2795