fwohci.c revision 109890
1265533Sdelphij/* 2202719Sgabor * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3202719Sgabor * All rights reserved. 4202719Sgabor * 5202719Sgabor * Redistribution and use in source and binary forms, with or without 6202719Sgabor * modification, are permitted provided that the following conditions 7202719Sgabor * are met: 8202719Sgabor * 1. Redistributions of source code must retain the above copyright 9202719Sgabor * notice, this list of conditions and the following disclaimer. 10202719Sgabor * 2. Redistributions in binary form must reproduce the above copyright 11202719Sgabor * notice, this list of conditions and the following disclaimer in the 12202719Sgabor * documentation and/or other materials provided with the distribution. 13202719Sgabor * 3. All advertising materials mentioning features or use of this software 14202719Sgabor * must display the acknowledgement as bellow: 15202719Sgabor * 16202719Sgabor * This product includes software developed by K. Kobayashi and H. Shimokawa 17202719Sgabor * 18202719Sgabor * 4. The name of the author may not be used to endorse or promote products 19202719Sgabor * derived from this software without specific prior written permission. 20202719Sgabor * 21202719Sgabor * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22202719Sgabor * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23202719Sgabor * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24202719Sgabor * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25202719Sgabor * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26202719Sgabor * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27202719Sgabor * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28202719Sgabor * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29202719Sgabor * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30202719Sgabor * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31202719Sgabor * POSSIBILITY OF SUCH DAMAGE. 32202719Sgabor * 33202719Sgabor * $FreeBSD: head/sys/dev/firewire/fwohci.c 109890 2003-01-26 15:39:04Z simokawa $ 34202719Sgabor * 35202719Sgabor */ 36202719Sgabor 37202719Sgabor#define ATRQ_CH 0 38202719Sgabor#define ATRS_CH 1 39202719Sgabor#define ARRQ_CH 2 40202719Sgabor#define ARRS_CH 3 41202719Sgabor#define ITX_CH 4 42202719Sgabor#define IRX_CH 0x24 43202719Sgabor 44202719Sgabor#include <sys/param.h> 45202719Sgabor#include <sys/proc.h> 46202719Sgabor#include <sys/systm.h> 47202719Sgabor#include <sys/types.h> 48202719Sgabor#include <sys/mbuf.h> 49202719Sgabor#include <sys/mman.h> 50202719Sgabor#include <sys/socket.h> 51202719Sgabor#include <sys/socketvar.h> 52202719Sgabor#include <sys/signalvar.h> 53202719Sgabor#include <sys/malloc.h> 54202719Sgabor#include <sys/uio.h> 55202719Sgabor#include <sys/sockio.h> 56202719Sgabor#include <sys/bus.h> 57202719Sgabor#include <sys/kernel.h> 58202719Sgabor#include <sys/conf.h> 59202719Sgabor 60202719Sgabor#include <machine/bus.h> 61202719Sgabor#include <machine/resource.h> 62202719Sgabor#include <sys/rman.h> 63202719Sgabor 64202719Sgabor#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65202719Sgabor#include <machine/clock.h> 66202719Sgabor#include <pci/pcivar.h> 67202719Sgabor#include <pci/pcireg.h> 68202719Sgabor#include <vm/vm.h> 69202719Sgabor#include <vm/vm_extern.h> 70202719Sgabor#include <vm/pmap.h> /* for vtophys proto */ 71202719Sgabor 72202719Sgabor#include <dev/firewire/firewire.h> 73202719Sgabor#include <dev/firewire/firewirereg.h> 74202719Sgabor#include <dev/firewire/fwohcireg.h> 75202719Sgabor#include <dev/firewire/fwohcivar.h> 76202719Sgabor#include <dev/firewire/firewire_phy.h> 77202719Sgabor 78202719Sgabor#include <dev/firewire/iec68113.h> 79202719Sgabor 80202719Sgabor#undef OHCI_DEBUG 81202719Sgabor 82202719Sgaborstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83202719Sgabor "STOR","LOAD","NOP ","STOP",}; 84202719Sgaborstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85202719Sgabor "UNDEF","REG","SYS","DEV"}; 86202719Sgaborchar fwohcicode[32][0x20]={ 87202719Sgabor "No stat","Undef","long","miss Ack err", 88202719Sgabor "underrun","overrun","desc err", "data read err", 89202719Sgabor "data write err","bus reset","timeout","tcode err", 90202719Sgabor "Undef","Undef","unknown event","flushed", 91202719Sgabor "Undef","ack complete","ack pend","Undef", 92202719Sgabor "ack busy_X","ack busy_A","ack busy_B","Undef", 93202719Sgabor "Undef","Undef","Undef","ack tardy", 94203443Sgabor "Undef","ack data_err","ack type_err",""}; 95202719Sgabor#define MAX_SPEED 2 96202719Sgaborextern char linkspeed[MAX_SPEED+1][0x10]; 97202719Sgaborstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98202719Sgaboru_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99202719Sgabor 100202719Sgaborstatic struct tcode_info tinfo[] = { 101202719Sgabor/* hdr_len block flag*/ 102202719Sgabor/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103202719Sgabor/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104202719Sgabor/* 2 WRES */ {12, FWTI_RES}, 105202719Sgabor/* 3 XXX */ { 0, 0}, 106202719Sgabor/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107202719Sgabor/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108202719Sgabor/* 6 RRESQ */ {16, FWTI_RES}, 109202719Sgabor/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110202719Sgabor/* 8 CYCS */ { 0, 0}, 111202719Sgabor/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112202719Sgabor/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113202719Sgabor/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114202719Sgabor/* c XXX */ { 0, 0}, 115202719Sgabor/* d XXX */ { 0, 0}, 116202719Sgabor/* e PHY */ {12, FWTI_REQ}, 117202719Sgabor/* f XXX */ { 0, 0} 118202719Sgabor}; 119202719Sgabor 120202719Sgabor#define OHCI_WRITE_SIGMASK 0xffff0000 121202719Sgabor#define OHCI_READ_SIGMASK 0xffff0000 122202719Sgabor 123202719Sgabor#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124202719Sgabor#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125202719Sgabor 126202719Sgaborstatic void fwohci_ibr __P((struct firewire_comm *)); 127203443Sgaborstatic void fwohci_db_init __P((struct fwohci_dbch *)); 128203443Sgaborstatic void fwohci_db_free __P((struct fwohci_dbch *)); 129202719Sgaborstatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130202719Sgaborstatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131202719Sgaborstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132202719Sgaborstatic void fwohci_start_atq __P((struct firewire_comm *)); 133202719Sgaborstatic void fwohci_start_ats __P((struct firewire_comm *)); 134202719Sgaborstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135202719Sgaborstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136202719Sgaborstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137202719Sgaborstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138202719Sgaborstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139202719Sgaborstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140202719Sgaborstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141202719Sgaborstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142202719Sgaborstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 143202719Sgaborstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144202719Sgaborstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145202719Sgaborstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 146202719Sgaborstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147202719Sgaborstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148202719Sgaborstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 149202719Sgaborstatic void fwohci_timeout __P((void *)); 150202719Sgaborstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 151202719Sgaborstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 152202719Sgaborstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153202719Sgaborstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154202719Sgaborstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 155202719Sgaborstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156202719Sgaborstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157202719Sgaborstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158202719Sgaborstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159202719Sgaborstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160202719Sgaborvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161202719Sgabor 162202719Sgabor/* 163202719Sgabor * memory allocated for DMA programs 164202719Sgabor */ 165202719Sgabor#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166202719Sgabor 167202719Sgabor/* #define NDB 1024 */ 168202719Sgabor#define NDB FWMAXQUEUE 169202719Sgabor#define NDVDB (DVBUF * NDB) 170202719Sgabor 171202719Sgabor#define OHCI_VERSION 0x00 172202719Sgabor#define OHCI_CROMHDR 0x18 173202719Sgabor#define OHCI_BUS_OPT 0x20 174202719Sgabor#define OHCI_BUSIRMC (1 << 31) 175202719Sgabor#define OHCI_BUSCMC (1 << 30) 176203443Sgabor#define OHCI_BUSISC (1 << 29) 177203443Sgabor#define OHCI_BUSBMC (1 << 28) 178202719Sgabor#define OHCI_BUSPMC (1 << 27) 179203443Sgabor#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180202719Sgabor OHCI_BUSBMC | OHCI_BUSPMC 181202719Sgabor 182202719Sgabor#define OHCI_EUID_HI 0x24 183202719Sgabor#define OHCI_EUID_LO 0x28 184202719Sgabor 185202719Sgabor#define OHCI_CROMPTR 0x34 186202719Sgabor#define OHCI_HCCCTL 0x50 187202719Sgabor#define OHCI_HCCCTLCLR 0x54 188203443Sgabor#define OHCI_AREQHI 0x100 189203443Sgabor#define OHCI_AREQHICLR 0x104 190203443Sgabor#define OHCI_AREQLO 0x108 191203443Sgabor#define OHCI_AREQLOCLR 0x10c 192203443Sgabor#define OHCI_PREQHI 0x110 193202719Sgabor#define OHCI_PREQHICLR 0x114 194202719Sgabor#define OHCI_PREQLO 0x118 195202719Sgabor#define OHCI_PREQLOCLR 0x11c 196202719Sgabor#define OHCI_PREQUPPER 0x120 197202719Sgabor 198202719Sgabor#define OHCI_SID_BUF 0x64 199202719Sgabor#define OHCI_SID_CNT 0x68 200202719Sgabor#define OHCI_SID_CNT_MASK 0xffc 201202719Sgabor 202202719Sgabor#define OHCI_IT_STAT 0x90 203202719Sgabor#define OHCI_IT_STATCLR 0x94 204202719Sgabor#define OHCI_IT_MASK 0x98 205202719Sgabor#define OHCI_IT_MASKCLR 0x9c 206202719Sgabor 207202719Sgabor#define OHCI_IR_STAT 0xa0 208202719Sgabor#define OHCI_IR_STATCLR 0xa4 209202719Sgabor#define OHCI_IR_MASK 0xa8 210202719Sgabor#define OHCI_IR_MASKCLR 0xac 211202719Sgabor 212202719Sgabor#define OHCI_LNKCTL 0xe0 213202719Sgabor#define OHCI_LNKCTLCLR 0xe4 214202719Sgabor 215202719Sgabor#define OHCI_PHYACCESS 0xec 216202719Sgabor#define OHCI_CYCLETIMER 0xf0 217202719Sgabor 218202719Sgabor#define OHCI_DMACTL(off) (off) 219202719Sgabor#define OHCI_DMACTLCLR(off) (off + 4) 220202719Sgabor#define OHCI_DMACMD(off) (off + 0xc) 221202719Sgabor#define OHCI_DMAMATCH(off) (off + 0x10) 222202719Sgabor 223202719Sgabor#define OHCI_ATQOFF 0x180 224202719Sgabor#define OHCI_ATQCTL OHCI_ATQOFF 225202719Sgabor#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226202719Sgabor#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227202719Sgabor#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228202719Sgabor 229202719Sgabor#define OHCI_ATSOFF 0x1a0 230202719Sgabor#define OHCI_ATSCTL OHCI_ATSOFF 231202719Sgabor#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232202719Sgabor#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233202719Sgabor#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234202719Sgabor 235202719Sgabor#define OHCI_ARQOFF 0x1c0 236202719Sgabor#define OHCI_ARQCTL OHCI_ARQOFF 237202719Sgabor#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238202719Sgabor#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239203443Sgabor#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240203443Sgabor 241203443Sgabor#define OHCI_ARSOFF 0x1e0 242202719Sgabor#define OHCI_ARSCTL OHCI_ARSOFF 243202719Sgabor#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244202719Sgabor#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245202719Sgabor#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246202719Sgabor 247202719Sgabor#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248202719Sgabor#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249202719Sgabor#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250202719Sgabor#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251202719Sgabor 252202719Sgabor#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253202719Sgabor#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254202719Sgabor#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255202719Sgabor#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256202719Sgabor#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257202719Sgabor 258202719Sgabord_ioctl_t fwohci_ioctl; 259202719Sgabor 260202719Sgabor/* 261202719Sgabor * Communication with PHY device 262202719Sgabor */ 263202719Sgaborstatic u_int32_t 264202719Sgaborfwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265202719Sgabor{ 266202719Sgabor u_int32_t fun; 267202719Sgabor 268202719Sgabor addr &= 0xf; 269202719Sgabor data &= 0xff; 270202719Sgabor 271202719Sgabor fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272202719Sgabor OWRITE(sc, OHCI_PHYACCESS, fun); 273202719Sgabor DELAY(100); 274202719Sgabor 275202719Sgabor return(fwphy_rddata( sc, addr)); 276202719Sgabor} 277203443Sgabor 278202719Sgaborstatic u_int32_t 279202719Sgaborfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280202719Sgabor{ 281202719Sgabor struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282202719Sgabor int i; 283202719Sgabor u_int32_t bm; 284202719Sgabor 285202719Sgabor#define OHCI_CSR_DATA 0x0c 286202719Sgabor#define OHCI_CSR_COMP 0x10 287202719Sgabor#define OHCI_CSR_CONT 0x14 288202719Sgabor#define OHCI_BUS_MANAGER_ID 0 289202719Sgabor 290202719Sgabor OWRITE(sc, OHCI_CSR_DATA, node); 291202719Sgabor OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292202719Sgabor OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293203443Sgabor for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294203443Sgabor DELAY(10); 295203443Sgabor bm = OREAD(sc, OHCI_CSR_DATA); 296203443Sgabor if((bm & 0x3f) == 0x3f) 297203443Sgabor bm = node; 298203443Sgabor if (bootverbose) 299203443Sgabor device_printf(sc->fc.dev, 300202719Sgabor "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301202719Sgabor 302202719Sgabor return(bm); 303202719Sgabor} 304202719Sgabor 305202719Sgaborstatic u_int32_t 306202719Sgaborfwphy_rddata(struct fwohci_softc *sc, u_int addr) 307202719Sgabor{ 308202719Sgabor u_int32_t fun, stat; 309202719Sgabor u_int i, retry = 0; 310202719Sgabor 311202719Sgabor addr &= 0xf; 312202719Sgabor#define MAX_RETRY 100 313202719Sgaboragain: 314202719Sgabor OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315202719Sgabor fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316202719Sgabor OWRITE(sc, OHCI_PHYACCESS, fun); 317202719Sgabor for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318202719Sgabor fun = OREAD(sc, OHCI_PHYACCESS); 319202719Sgabor if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320202719Sgabor break; 321202719Sgabor DELAY(100); 322202719Sgabor } 323202719Sgabor if(i >= MAX_RETRY) { 324202719Sgabor if (bootverbose) 325244861Skevlo device_printf(sc->fc.dev, "phy read failed(1).\n"); 326202719Sgabor if (++retry < MAX_RETRY) { 327202719Sgabor DELAY(100); 328202719Sgabor goto again; 329202719Sgabor } 330202719Sgabor } 331202719Sgabor /* Make sure that SCLK is started */ 332202719Sgabor stat = OREAD(sc, FWOHCI_INTSTAT); 333202719Sgabor if ((stat & OHCI_INT_REG_FAIL) != 0 || 334202719Sgabor ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335202719Sgabor if (bootverbose) 336203443Sgabor device_printf(sc->fc.dev, "phy read failed(2).\n"); 337203443Sgabor if (++retry < MAX_RETRY) { 338202719Sgabor DELAY(100); 339202719Sgabor goto again; 340202719Sgabor } 341202719Sgabor } 342202719Sgabor if (bootverbose || retry >= MAX_RETRY) 343202719Sgabor device_printf(sc->fc.dev, 344202719Sgabor "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345202719Sgabor#undef MAX_RETRY 346202719Sgabor return((fun >> PHYDEV_RDDATA )& 0xff); 347202719Sgabor} 348202719Sgabor/* Device specific ioctl. */ 349202719Sgaborint 350203443Sgaborfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351202719Sgabor{ 352202719Sgabor struct firewire_softc *sc; 353202719Sgabor struct fwohci_softc *fc; 354202719Sgabor int unit = DEV2UNIT(dev); 355202719Sgabor int err = 0; 356244861Skevlo struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357244861Skevlo u_int32_t *dmach = (u_int32_t *) data; 358202719Sgabor 359202719Sgabor sc = devclass_get_softc(firewire_devclass, unit); 360202719Sgabor if(sc == NULL){ 361202719Sgabor return(EINVAL); 362202719Sgabor } 363202719Sgabor fc = (struct fwohci_softc *)sc->fc; 364202719Sgabor 365202719Sgabor if (!data) 366202719Sgabor return(EINVAL); 367202719Sgabor 368202719Sgabor switch (cmd) { 369202719Sgabor case FWOHCI_WRREG: 370202719Sgabor#define OHCI_MAX_REG 0x800 371202719Sgabor if(reg->addr <= OHCI_MAX_REG){ 372202719Sgabor OWRITE(fc, reg->addr, reg->data); 373202719Sgabor reg->data = OREAD(fc, reg->addr); 374202719Sgabor }else{ 375202719Sgabor err = EINVAL; 376202719Sgabor } 377202719Sgabor break; 378202719Sgabor case FWOHCI_RDREG: 379202719Sgabor if(reg->addr <= OHCI_MAX_REG){ 380202719Sgabor reg->data = OREAD(fc, reg->addr); 381202719Sgabor }else{ 382202719Sgabor err = EINVAL; 383202719Sgabor } 384202719Sgabor break; 385202719Sgabor/* Read DMA descriptors for debug */ 386202719Sgabor case DUMPDMA: 387202719Sgabor if(*dmach <= OHCI_MAX_DMA_CH ){ 388202719Sgabor dump_dma(fc, *dmach); 389202719Sgabor dump_db(fc, *dmach); 390202719Sgabor }else{ 391202719Sgabor err = EINVAL; 392202719Sgabor } 393202719Sgabor break; 394202719Sgabor default: 395202719Sgabor break; 396202719Sgabor } 397202719Sgabor return err; 398202719Sgabor} 399202719Sgabor 400203443Sgaborstatic int 401203443Sgaborfwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402202719Sgabor{ 403202719Sgabor u_int32_t reg, reg2; 404202719Sgabor int e1394a = 1; 405202719Sgabor/* 406244861Skevlo * probe PHY parameters 407244861Skevlo * 0. to prove PHY version, whether compliance of 1394a. 408202719Sgabor * 1. to probe maximum speed supported by the PHY and 409202719Sgabor * number of port supported by core-logic. 410202719Sgabor * It is not actually available port on your PC . 411202719Sgabor */ 412202719Sgabor OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413202719Sgabor#if 0 414202719Sgabor /* XXX wait for SCLK. */ 415202719Sgabor DELAY(100000); 416202719Sgabor#endif 417202719Sgabor reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418202719Sgabor 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447#if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449#else /* XXX force to enable 1394a */ 450 if (e1394a) { 451#endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475} 476 477 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 /* AT Retries */ 555 OWRITE(sc, FWOHCI_RETRY, 556 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560 db_tr->xfer = NULL; 561 } 562 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564 db_tr->xfer = NULL; 565 } 566 567 568 /* Enable interrupt */ 569 OWRITE(sc, FWOHCI_INTMASK, 570 OHCI_INT_ERR | OHCI_INT_PHY_SID 571 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574 fwohci_set_intr(&sc->fc, 1); 575 576} 577 578int 579fwohci_init(struct fwohci_softc *sc, device_t dev) 580{ 581 int i; 582 u_int32_t reg; 583 u_int8_t ui[8]; 584 585 reg = OREAD(sc, OHCI_VERSION); 586 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588 589/* XXX: Available Isochrounous DMA channel probe */ 590 for( i = 0 ; i < 0x20 ; i ++ ){ 591 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 592 reg = OREAD(sc, OHCI_IRCTL(i)); 593 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 594 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 595 reg = OREAD(sc, OHCI_ITCTL(i)); 596 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 597 } 598 sc->fc.nisodma = i; 599 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600 601 sc->fc.arq = &sc->arrq.xferq; 602 sc->fc.ars = &sc->arrs.xferq; 603 sc->fc.atq = &sc->atrq.xferq; 604 sc->fc.ats = &sc->atrs.xferq; 605 606 sc->arrq.xferq.start = NULL; 607 sc->arrs.xferq.start = NULL; 608 sc->atrq.xferq.start = fwohci_start_atq; 609 sc->atrs.xferq.start = fwohci_start_ats; 610 611 sc->arrq.xferq.drain = NULL; 612 sc->arrs.xferq.drain = NULL; 613 sc->atrq.xferq.drain = fwohci_drain_atq; 614 sc->atrs.xferq.drain = fwohci_drain_ats; 615 616 sc->arrq.ndesc = 1; 617 sc->arrs.ndesc = 1; 618 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 619 sc->atrs.ndesc = 6 / 2; 620 621 sc->arrq.ndb = NDB; 622 sc->arrs.ndb = NDB / 2; 623 sc->atrq.ndb = NDB; 624 sc->atrs.ndb = NDB / 2; 625 626 sc->arrq.dummy = NULL; 627 sc->arrs.dummy = NULL; 628 sc->atrq.dummy = NULL; 629 sc->atrs.dummy = NULL; 630 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631 sc->fc.it[i] = &sc->it[i].xferq; 632 sc->fc.ir[i] = &sc->ir[i].xferq; 633 sc->it[i].ndb = 0; 634 sc->ir[i].ndb = 0; 635 } 636 637 sc->fc.tcode = tinfo; 638 639 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT); 640 641 if(sc->cromptr == NULL){ 642 device_printf(dev, "cromptr alloc failed."); 643 return ENOMEM; 644 } 645 sc->fc.dev = dev; 646 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 657 658/* SID recieve buffer must allign 2^11 */ 659#define OHCI_SIDSIZE (1 << 11) 660 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 661 if (sc->fc.sid_buf == NULL) { 662 device_printf(dev, "sid_buf alloc failed.\n"); 663 return ENOMEM; 664 } 665 if (((u_int32_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666 device_printf(dev, "sid_buf(%p) not aligned.\n", 667 sc->fc.sid_buf); 668 return ENOMEM; 669 } 670 671 fwohci_db_init(&sc->arrq); 672 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673 return ENOMEM; 674 675 fwohci_db_init(&sc->arrs); 676 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677 return ENOMEM; 678 679 fwohci_db_init(&sc->atrq); 680 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681 return ENOMEM; 682 683 fwohci_db_init(&sc->atrs); 684 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685 return ENOMEM; 686 687 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689 for( i = 0 ; i < 8 ; i ++) 690 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693 694 sc->fc.ioctl = fwohci_ioctl; 695 sc->fc.cyctimer = fwohci_cyctimer; 696 sc->fc.set_bmr = fwohci_set_bus_manager; 697 sc->fc.ibr = fwohci_ibr; 698 sc->fc.irx_enable = fwohci_irx_enable; 699 sc->fc.irx_disable = fwohci_irx_disable; 700 701 sc->fc.itx_enable = fwohci_itxbuf_enable; 702 sc->fc.itx_disable = fwohci_itx_disable; 703 sc->fc.irx_post = fwohci_irx_post; 704 sc->fc.itx_post = NULL; 705 sc->fc.timeout = fwohci_timeout; 706 sc->fc.poll = fwohci_poll; 707 sc->fc.set_intr = fwohci_set_intr; 708 709 fw_init(&sc->fc); 710 fwohci_reset(sc, dev); 711 712 return 0; 713} 714 715void 716fwohci_timeout(void *arg) 717{ 718 struct fwohci_softc *sc; 719 720 sc = (struct fwohci_softc *)arg; 721 sc->fc.timeouthandle = timeout(fwohci_timeout, 722 (void *)sc, FW_XFERTIMEOUT * hz * 10); 723} 724 725u_int32_t 726fwohci_cyctimer(struct firewire_comm *fc) 727{ 728 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 729 return(OREAD(sc, OHCI_CYCLETIMER)); 730} 731 732int 733fwohci_detach(struct fwohci_softc *sc, device_t dev) 734{ 735 int i; 736 737 if (sc->fc.sid_buf != NULL) 738 free((void *)(uintptr_t)sc->fc.sid_buf, M_DEVBUF); 739 if (sc->cromptr != NULL) 740 free((void *)sc->cromptr, M_DEVBUF); 741 742 fwohci_db_free(&sc->arrq); 743 fwohci_db_free(&sc->arrs); 744 745 fwohci_db_free(&sc->atrq); 746 fwohci_db_free(&sc->atrs); 747 748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749 fwohci_db_free(&sc->it[i]); 750 fwohci_db_free(&sc->ir[i]); 751 } 752 753 return 0; 754} 755 756#define LAST_DB(dbtr, db) do { \ 757 struct fwohcidb_tr *_dbtr = (dbtr); \ 758 int _cnt = _dbtr->dbcnt; \ 759 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 760} while (0) 761 762static void 763fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 764{ 765 int i, s; 766 int tcode, hdr_len, hdr_off, len; 767 int fsegment = -1; 768 u_int32_t off; 769 struct fw_xfer *xfer; 770 struct fw_pkt *fp; 771 volatile struct fwohci_txpkthdr *ohcifp; 772 struct fwohcidb_tr *db_tr; 773 volatile struct fwohcidb *db; 774 struct mbuf *m; 775 struct tcode_info *info; 776 static int maxdesc=0; 777 778 if(&sc->atrq == dbch){ 779 off = OHCI_ATQOFF; 780 }else if(&sc->atrs == dbch){ 781 off = OHCI_ATSOFF; 782 }else{ 783 return; 784 } 785 786 if (dbch->flags & FWOHCI_DBCH_FULL) 787 return; 788 789 s = splfw(); 790 db_tr = dbch->top; 791txloop: 792 xfer = STAILQ_FIRST(&dbch->xferq.q); 793 if(xfer == NULL){ 794 goto kick; 795 } 796 if(dbch->xferq.queued == 0 ){ 797 device_printf(sc->fc.dev, "TX queue empty\n"); 798 } 799 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 800 db_tr->xfer = xfer; 801 xfer->state = FWXF_START; 802 dbch->xferq.packets++; 803 804 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 805 tcode = fp->mode.common.tcode; 806 807 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 808 info = &tinfo[tcode]; 809 hdr_len = hdr_off = info->hdr_len; 810 /* fw_asyreq must pass valid send.len */ 811 len = xfer->send.len; 812 for( i = 0 ; i < hdr_off ; i+= 4){ 813 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 814 } 815 ohcifp->mode.common.spd = xfer->spd; 816 if (tcode == FWTCODE_STREAM ){ 817 hdr_len = 8; 818 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 819 } else if (tcode == FWTCODE_PHY) { 820 hdr_len = 12; 821 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 822 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 823 ohcifp->mode.common.spd = 0; 824 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 825 } else { 826 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 827 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 828 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 829 } 830 db = &db_tr->db[0]; 831 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 832 db->db.desc.status = 0; 833/* Specify bound timer of asy. responce */ 834 if(&sc->atrs == dbch){ 835 db->db.desc.count 836 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 837 } 838 839 db_tr->dbcnt = 2; 840 db = &db_tr->db[db_tr->dbcnt]; 841 if(len > hdr_off){ 842 if (xfer->mbuf == NULL) { 843 db->db.desc.addr 844 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 845 db->db.desc.cmd 846 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 847 db->db.desc.status = 0; 848 849 db_tr->dbcnt++; 850 } else { 851 int mchain=0; 852 /* XXX we assume mbuf chain is shorter than ndesc */ 853 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 854 if (m->m_len == 0) 855 /* unrecoverable error could occur. */ 856 continue; 857 mchain++; 858 if (db_tr->dbcnt >= dbch->ndesc) 859 continue; 860 db->db.desc.addr 861 = vtophys(mtod(m, caddr_t)); 862 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 863 db->db.desc.status = 0; 864 db++; 865 db_tr->dbcnt++; 866 } 867 if (mchain > dbch->ndesc - 2) 868 device_printf(sc->fc.dev, 869 "dbch->ndesc(%d) is too small for" 870 " mbuf chain(%d), trancated.\n", 871 dbch->ndesc, mchain); 872 } 873 } 874 if (maxdesc < db_tr->dbcnt) { 875 maxdesc = db_tr->dbcnt; 876 if (bootverbose) 877 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 878 } 879 /* last db */ 880 LAST_DB(db_tr, db); 881 db->db.desc.cmd |= OHCI_OUTPUT_LAST 882 | OHCI_INTERRUPT_ALWAYS 883 | OHCI_BRANCH_ALWAYS; 884 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 885 886 if(fsegment == -1 ) 887 fsegment = db_tr->dbcnt; 888 if (dbch->pdb_tr != NULL) { 889 LAST_DB(dbch->pdb_tr, db); 890 db->db.desc.depend |= db_tr->dbcnt; 891 } 892 dbch->pdb_tr = db_tr; 893 db_tr = STAILQ_NEXT(db_tr, link); 894 if(db_tr != dbch->bottom){ 895 goto txloop; 896 } else { 897 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 898 dbch->flags |= FWOHCI_DBCH_FULL; 899 } 900kick: 901 if (firewire_debug) printf("kick\n"); 902 /* kick asy q */ 903 904 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 905 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 906 } else { 907 if (bootverbose) 908 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 909 OREAD(sc, OHCI_DMACTL(off))); 910 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 911 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 912 dbch->xferq.flag |= FWXFERQ_RUNNING; 913 } 914 915 dbch->top = db_tr; 916 splx(s); 917 return; 918} 919 920static void 921fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 922{ 923 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 924 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 925 return; 926} 927 928static void 929fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 930{ 931 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 932 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 933 return; 934} 935 936static void 937fwohci_start_atq(struct firewire_comm *fc) 938{ 939 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 940 fwohci_start( sc, &(sc->atrq)); 941 return; 942} 943 944static void 945fwohci_start_ats(struct firewire_comm *fc) 946{ 947 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 948 fwohci_start( sc, &(sc->atrs)); 949 return; 950} 951 952void 953fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 954{ 955 int s, err = 0; 956 struct fwohcidb_tr *tr; 957 volatile struct fwohcidb *db; 958 struct fw_xfer *xfer; 959 u_int32_t off; 960 u_int stat; 961 int packets; 962 struct firewire_comm *fc = (struct firewire_comm *)sc; 963 if(&sc->atrq == dbch){ 964 off = OHCI_ATQOFF; 965 }else if(&sc->atrs == dbch){ 966 off = OHCI_ATSOFF; 967 }else{ 968 return; 969 } 970 s = splfw(); 971 tr = dbch->bottom; 972 packets = 0; 973 while(dbch->xferq.queued > 0){ 974 LAST_DB(tr, db); 975 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 976 if (fc->status != FWBUSRESET) 977 /* maybe out of order?? */ 978 goto out; 979 } 980 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 981#ifdef OHCI_DEBUG 982 dump_dma(sc, ch); 983 dump_db(sc, ch); 984#endif 985/* Stop DMA */ 986 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 987 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 988 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 989 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 990 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 991 } 992 stat = db->db.desc.status & FWOHCIEV_MASK; 993 switch(stat){ 994 case FWOHCIEV_ACKCOMPL: 995 case FWOHCIEV_ACKPEND: 996 err = 0; 997 break; 998 case FWOHCIEV_ACKBSA: 999 case FWOHCIEV_ACKBSB: 1000 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1001 case FWOHCIEV_ACKBSX: 1002 err = EBUSY; 1003 break; 1004 case FWOHCIEV_FLUSHED: 1005 case FWOHCIEV_ACKTARD: 1006 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1007 err = EAGAIN; 1008 break; 1009 case FWOHCIEV_MISSACK: 1010 case FWOHCIEV_UNDRRUN: 1011 case FWOHCIEV_OVRRUN: 1012 case FWOHCIEV_DESCERR: 1013 case FWOHCIEV_DTRDERR: 1014 case FWOHCIEV_TIMEOUT: 1015 case FWOHCIEV_TCODERR: 1016 case FWOHCIEV_UNKNOWN: 1017 case FWOHCIEV_ACKDERR: 1018 case FWOHCIEV_ACKTERR: 1019 default: 1020 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1021 stat, fwohcicode[stat]); 1022 err = EINVAL; 1023 break; 1024 } 1025 if(tr->xfer != NULL){ 1026 xfer = tr->xfer; 1027 xfer->state = FWXF_SENT; 1028 if(err == EBUSY && fc->status != FWBUSRESET){ 1029 xfer->state = FWXF_BUSY; 1030 switch(xfer->act_type){ 1031 case FWACT_XFER: 1032 xfer->resp = err; 1033 if(xfer->retry_req != NULL){ 1034 xfer->retry_req(xfer); 1035 } 1036 break; 1037 default: 1038 break; 1039 } 1040 } else if( stat != FWOHCIEV_ACKPEND){ 1041 if (stat != FWOHCIEV_ACKCOMPL) 1042 xfer->state = FWXF_SENTERR; 1043 xfer->resp = err; 1044 switch(xfer->act_type){ 1045 case FWACT_XFER: 1046 fw_xfer_done(xfer); 1047 break; 1048 default: 1049 break; 1050 } 1051 } 1052 dbch->xferq.queued --; 1053 } 1054 tr->xfer = NULL; 1055 1056 packets ++; 1057 tr = STAILQ_NEXT(tr, link); 1058 dbch->bottom = tr; 1059 } 1060out: 1061 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1062 printf("make free slot\n"); 1063 dbch->flags &= ~FWOHCI_DBCH_FULL; 1064 fwohci_start(sc, dbch); 1065 } 1066 splx(s); 1067} 1068 1069static void 1070fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1071{ 1072 int i, s; 1073 struct fwohcidb_tr *tr; 1074 1075 if(xfer->state != FWXF_START) return; 1076 1077 s = splfw(); 1078 tr = dbch->bottom; 1079 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1080 if(tr->xfer == xfer){ 1081 s = splfw(); 1082 tr->xfer = NULL; 1083 dbch->xferq.queued --; 1084#if 1 1085 /* XXX */ 1086 if (tr == dbch->bottom) 1087 dbch->bottom = STAILQ_NEXT(tr, link); 1088#endif 1089 if (dbch->flags & FWOHCI_DBCH_FULL) { 1090 printf("fwohci_drain: make slot\n"); 1091 dbch->flags &= ~FWOHCI_DBCH_FULL; 1092 fwohci_start((struct fwohci_softc *)fc, dbch); 1093 } 1094 1095 splx(s); 1096 break; 1097 } 1098 tr = STAILQ_NEXT(tr, link); 1099 } 1100 splx(s); 1101 return; 1102} 1103 1104static void 1105fwohci_db_free(struct fwohci_dbch *dbch) 1106{ 1107 struct fwohcidb_tr *db_tr; 1108 int idb, i; 1109 1110 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1111 return; 1112 1113 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1114 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1115 idb < dbch->ndb; 1116 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1117 if (db_tr->buf != NULL) { 1118 free(db_tr->buf, M_DEVBUF); 1119 db_tr->buf = NULL; 1120 } 1121 } 1122 } 1123 dbch->ndb = 0; 1124 db_tr = STAILQ_FIRST(&dbch->db_trq); 1125 for (i = 0; i < dbch->npages; i++) 1126 free(dbch->pages[i], M_DEVBUF); 1127 free(db_tr, M_DEVBUF); 1128 STAILQ_INIT(&dbch->db_trq); 1129 dbch->flags &= ~FWOHCI_DBCH_INIT; 1130} 1131 1132static void 1133fwohci_db_init(struct fwohci_dbch *dbch) 1134{ 1135 int idb; 1136 struct fwohcidb_tr *db_tr; 1137 int ndbpp, i, j; 1138 1139 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1140 goto out; 1141 1142 /* allocate DB entries and attach one to each DMA channels */ 1143 /* DB entry must start at 16 bytes bounary. */ 1144 STAILQ_INIT(&dbch->db_trq); 1145 db_tr = (struct fwohcidb_tr *) 1146 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1147 M_DEVBUF, M_NOWAIT | M_ZERO); 1148 if(db_tr == NULL){ 1149 printf("fwohci_db_init: malloc(1) failed\n"); 1150 return; 1151 } 1152 1153 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1154 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1155 if (firewire_debug) 1156 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1157 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1158 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1159 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1160 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1161 return; 1162 } 1163 for (i = 0; i < dbch->npages; i++) { 1164 dbch->pages[i] = malloc(PAGE_SIZE, M_DEVBUF, 1165 M_NOWAIT | M_ZERO); 1166 if (dbch->pages[i] == NULL) { 1167 printf("fwohci_db_init: malloc(2) failed\n"); 1168 for (j = 0; j < i; j ++) 1169 free(dbch->pages[j], M_DEVBUF); 1170 free(db_tr, M_DEVBUF); 1171 return; 1172 } 1173 } 1174 /* Attach DB to DMA ch. */ 1175 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1176 db_tr->dbcnt = 0; 1177 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1178 + dbch->ndesc * (idb % ndbpp); 1179 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1180 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1181 dbch->xferq.bnpacket != 0) { 1182 if (idb % dbch->xferq.bnpacket == 0) 1183 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1184 ].start = (caddr_t)db_tr; 1185 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1186 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1187 ].end = (caddr_t)db_tr; 1188 } 1189 db_tr++; 1190 } 1191 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1192 = STAILQ_FIRST(&dbch->db_trq); 1193out: 1194 dbch->frag.buf = NULL; 1195 dbch->frag.len = 0; 1196 dbch->frag.plen = 0; 1197 dbch->xferq.queued = 0; 1198 dbch->pdb_tr = NULL; 1199 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1200 dbch->bottom = dbch->top; 1201 dbch->flags = FWOHCI_DBCH_INIT; 1202} 1203 1204static int 1205fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1206{ 1207 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1208 int dummy; 1209 1210 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1211 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1212 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1213 /* XXX we cannot free buffers until the DMA really stops */ 1214 tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1215 fwohci_db_free(&sc->it[dmach]); 1216 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1217 return 0; 1218} 1219 1220static int 1221fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1222{ 1223 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1224 int dummy; 1225 1226 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1227 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1228 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1229 /* XXX we cannot free buffers until the DMA really stops */ 1230 tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1231 if(sc->ir[dmach].dummy != NULL){ 1232 free(sc->ir[dmach].dummy, M_DEVBUF); 1233 } 1234 sc->ir[dmach].dummy = NULL; 1235 fwohci_db_free(&sc->ir[dmach]); 1236 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1237 return 0; 1238} 1239 1240static void 1241fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1242{ 1243 qld[0] = ntohl(qld[0]); 1244 return; 1245} 1246 1247static int 1248fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1249{ 1250 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1251 int err = 0; 1252 unsigned short tag, ich; 1253 1254 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1255 ich = sc->ir[dmach].xferq.flag & 0x3f; 1256 1257#if 0 1258 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1259 wakeup(fc->ir[dmach]); 1260 return err; 1261 } 1262#endif 1263 1264 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1265 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1266 sc->ir[dmach].xferq.queued = 0; 1267 sc->ir[dmach].ndb = NDB; 1268 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1269 sc->ir[dmach].ndesc = 1; 1270 fwohci_db_init(&sc->ir[dmach]); 1271 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1272 return ENOMEM; 1273 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1274 } 1275 if(err){ 1276 device_printf(sc->fc.dev, "err in IRX setting\n"); 1277 return err; 1278 } 1279 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1280 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1281 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1282 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1283 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1284 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1285 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1286 OWRITE(sc, OHCI_IRCMD(dmach), 1287 vtophys(sc->ir[dmach].top->db) | 1); 1288 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1289 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1290 } 1291 return err; 1292} 1293 1294static int 1295fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1296{ 1297 int err = 0; 1298 int idb, z, i, dmach = 0; 1299 u_int32_t off = NULL; 1300 struct fwohcidb_tr *db_tr; 1301 1302 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1303 err = EINVAL; 1304 return err; 1305 } 1306 z = dbch->ndesc; 1307 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1308 if( &sc->it[dmach] == dbch){ 1309 off = OHCI_ITOFF(dmach); 1310 break; 1311 } 1312 } 1313 if(off == NULL){ 1314 err = EINVAL; 1315 return err; 1316 } 1317 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1318 return err; 1319 dbch->xferq.flag |= FWXFERQ_RUNNING; 1320 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1321 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1322 } 1323 db_tr = dbch->top; 1324 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1325 fwohci_add_tx_buf(db_tr, 1326 dbch->xferq.psize, dbch->xferq.flag, 1327 dbch->xferq.buf + dbch->xferq.psize * idb); 1328 if(STAILQ_NEXT(db_tr, link) == NULL){ 1329 break; 1330 } 1331 db_tr->db[0].db.desc.depend 1332 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1333 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1334 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1335 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1336 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1337 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1338 |= OHCI_INTERRUPT_ALWAYS; 1339 db_tr->db[0].db.desc.depend &= ~0xf; 1340 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1341 ~0xf; 1342 /* OHCI 1.1 and above */ 1343 db_tr->db[0].db.desc.cmd 1344 |= OHCI_INTERRUPT_ALWAYS; 1345 } 1346 } 1347 db_tr = STAILQ_NEXT(db_tr, link); 1348 } 1349 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1350 return err; 1351} 1352 1353static int 1354fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1355{ 1356 int err = 0; 1357 int idb, z, i, dmach = 0; 1358 u_int32_t off = NULL; 1359 struct fwohcidb_tr *db_tr; 1360 1361 z = dbch->ndesc; 1362 if(&sc->arrq == dbch){ 1363 off = OHCI_ARQOFF; 1364 }else if(&sc->arrs == dbch){ 1365 off = OHCI_ARSOFF; 1366 }else{ 1367 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1368 if( &sc->ir[dmach] == dbch){ 1369 off = OHCI_IROFF(dmach); 1370 break; 1371 } 1372 } 1373 } 1374 if(off == NULL){ 1375 err = EINVAL; 1376 return err; 1377 } 1378 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1379 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1380 return err; 1381 }else{ 1382 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1383 err = EBUSY; 1384 return err; 1385 } 1386 } 1387 dbch->xferq.flag |= FWXFERQ_RUNNING; 1388 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1389 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1390 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1391 } 1392 db_tr = dbch->top; 1393 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1394 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1395 fwohci_add_rx_buf(db_tr, 1396 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1397 }else{ 1398 fwohci_add_rx_buf(db_tr, 1399 dbch->xferq.psize, dbch->xferq.flag, 1400 dbch->xferq.buf + dbch->xferq.psize * idb, 1401 dbch->dummy + sizeof(u_int32_t) * idb); 1402 } 1403 if(STAILQ_NEXT(db_tr, link) == NULL){ 1404 break; 1405 } 1406 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1407 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1408 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1409 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1410 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1411 |= OHCI_INTERRUPT_ALWAYS; 1412 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1413 ~0xf; 1414 } 1415 } 1416 db_tr = STAILQ_NEXT(db_tr, link); 1417 } 1418 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1419 dbch->buf_offset = 0; 1420 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1421 return err; 1422 }else{ 1423 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1424 } 1425 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1426 return err; 1427} 1428 1429static int 1430fwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1431{ 1432 int sec, cycle, cycle_match; 1433 1434 cycle = cycle_now & 0x1fff; 1435 sec = cycle_now >> 13; 1436#define CYCLE_MOD 0x10 1437#define CYCLE_DELAY 8 /* min delay to start DMA */ 1438 cycle = cycle + CYCLE_DELAY; 1439 if (cycle >= 8000) { 1440 sec ++; 1441 cycle -= 8000; 1442 } 1443 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1444 if (cycle >= 8000) { 1445 sec ++; 1446 if (cycle == 8000) 1447 cycle = 0; 1448 else 1449 cycle = CYCLE_MOD; 1450 } 1451 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1452 1453 return(cycle_match); 1454} 1455 1456static int 1457fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1458{ 1459 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1460 int err = 0; 1461 unsigned short tag, ich; 1462 struct fwohci_dbch *dbch; 1463 int cycle_match, cycle_now, s, ldesc; 1464 u_int32_t stat; 1465 struct fw_bulkxfer *first, *chunk, *prev; 1466 struct fw_xferq *it; 1467 1468 dbch = &sc->it[dmach]; 1469 it = &dbch->xferq; 1470 1471 tag = (it->flag >> 6) & 3; 1472 ich = it->flag & 0x3f; 1473 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1474 dbch->ndb = it->bnpacket * it->bnchunk; 1475 dbch->ndesc = 3; 1476 fwohci_db_init(dbch); 1477 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1478 return ENOMEM; 1479 err = fwohci_tx_enable(sc, dbch); 1480 } 1481 if(err) 1482 return err; 1483 1484 s = splfw(); 1485 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1486 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1487 volatile struct fwohcidb *db; 1488 1489 fwohci_txbufdb(sc, dmach, chunk); 1490 ldesc = dbch->ndesc - 1; 1491 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1492 db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1493 db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1494 db[ldesc].db.desc.depend &= ~0xf; 1495 db[0].db.desc.depend &= ~0xf; 1496 if (prev != NULL) { 1497 db = ((struct fwohcidb_tr *)(prev->end))->db; 1498 db[ldesc].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 1499 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1500 vtophys(((struct fwohcidb_tr *) 1501 (chunk->start))->db) | dbch->ndesc; 1502 } 1503 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1504 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1505 prev = chunk; 1506 } 1507 splx(s); 1508 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1509 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1510 return 0; 1511 1512 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1513 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1514 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1515 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1516 1517 first = STAILQ_FIRST(&it->stdma); 1518 OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1519 (first->start))->db) | dbch->ndesc); 1520 if (firewire_debug) 1521 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1522 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1523#if 1 1524 /* Don't start until all chunks are buffered */ 1525 if (STAILQ_FIRST(&it->stfree) != NULL) 1526 goto out; 1527#endif 1528#ifdef FWXFERQ_DV 1529#define CYCLE_OFFSET 1 1530 if(dbch->xferq.flag & FWXFERQ_DV){ 1531 struct fw_pkt *fp; 1532 struct fwohcidb_tr *db_tr; 1533 1534 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1535 fp = (struct fw_pkt *)db_tr->buf; 1536 dbch->xferq.dvoffset = CYCLE_OFFSET; 1537 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1538 } 1539#endif 1540 /* Clear cycle match counter bits */ 1541 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1542 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1543 1544 /* 2bit second + 13bit cycle */ 1545 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1546 cycle_match = fwochi_next_cycle(fc, cycle_now); 1547 1548 OWRITE(sc, OHCI_ITCTL(dmach), 1549 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1550 | OHCI_CNTL_DMA_RUN); 1551 if (firewire_debug) 1552 printf("cycle_match: 0x%04x->0x%04x\n", 1553 cycle_now, cycle_match); 1554 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1555 device_printf(sc->fc.dev, 1556 "IT DMA underrun (0x%08x)\n", stat); 1557 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1558 } 1559out: 1560 return err; 1561} 1562 1563static int 1564fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1565{ 1566 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1567 int err = 0, s, ldesc; 1568 unsigned short tag, ich; 1569 u_int32_t stat; 1570 struct fwohci_dbch *dbch; 1571 struct fw_bulkxfer *first, *prev, *chunk; 1572 struct fw_xferq *ir; 1573 1574 dbch = &sc->ir[dmach]; 1575 ir = &dbch->xferq; 1576 ldesc = dbch->ndesc - 1; 1577 1578 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1579 tag = (ir->flag >> 6) & 3; 1580 ich = ir->flag & 0x3f; 1581 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1582 1583 ir->queued = 0; 1584 dbch->ndb = ir->bnpacket * ir->bnchunk; 1585 dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1586 M_DEVBUF, M_NOWAIT); 1587 if (dbch->dummy == NULL) { 1588 err = ENOMEM; 1589 return err; 1590 } 1591 dbch->ndesc = 2; 1592 fwohci_db_init(dbch); 1593 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1594 return ENOMEM; 1595 err = fwohci_rx_enable(sc, dbch); 1596 } 1597 if(err) 1598 return err; 1599 1600 s = splfw(); 1601 1602 first = STAILQ_FIRST(&ir->stfree); 1603 if (first == NULL) { 1604 device_printf(fc->dev, "IR DMA no free chunk\n"); 1605 splx(s); 1606 return 0; 1607 } 1608 1609 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1610 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1611 volatile struct fwohcidb *db; 1612 1613 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1614 db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1615 db[ldesc].db.desc.depend &= ~0xf; 1616 if (prev != NULL) { 1617 db = ((struct fwohcidb_tr *)(prev->end))->db; 1618 db[ldesc].db.desc.depend = 1619 vtophys(((struct fwohcidb_tr *) 1620 (chunk->start))->db) | dbch->ndesc; 1621 } 1622 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1623 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1624 prev = chunk; 1625 } 1626 splx(s); 1627 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1628 if (stat & OHCI_CNTL_DMA_ACTIVE) 1629 return 0; 1630 if (stat & OHCI_CNTL_DMA_RUN) { 1631 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1632 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1633 } 1634 1635 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1636 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1637 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1638 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1639 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1640 OWRITE(sc, OHCI_IRCMD(dmach), 1641 vtophys(((struct fwohcidb_tr *)(first->start))->db) 1642 | dbch->ndesc); 1643 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1644 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1645 return err; 1646} 1647 1648static int 1649fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1650{ 1651 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1652 int err = 0; 1653 1654 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1655 err = fwohci_irxpp_enable(fc, dmach); 1656 return err; 1657 }else{ 1658 err = fwohci_irxbuf_enable(fc, dmach); 1659 return err; 1660 } 1661} 1662 1663int 1664fwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1665{ 1666 u_int i; 1667 1668/* Now stopping all DMA channel */ 1669 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1670 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1671 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1672 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1673 1674 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1675 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1676 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1677 } 1678 1679/* FLUSH FIFO and reset Transmitter/Reciever */ 1680 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1681 1682/* Stop interrupt */ 1683 OWRITE(sc, FWOHCI_INTMASKCLR, 1684 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1685 | OHCI_INT_PHY_INT 1686 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1687 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1688 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1689 | OHCI_INT_PHY_BUS_R); 1690/* XXX Link down? Bus reset? */ 1691 return 0; 1692} 1693 1694int 1695fwohci_resume(struct fwohci_softc *sc, device_t dev) 1696{ 1697 int i; 1698 1699 fwohci_reset(sc, dev); 1700 /* XXX resume isochronus receive automatically. (how about TX?) */ 1701 for(i = 0; i < sc->fc.nisodma; i ++) { 1702 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1703 device_printf(sc->fc.dev, 1704 "resume iso receive ch: %d\n", i); 1705 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1706 sc->fc.irx_enable(&sc->fc, i); 1707 } 1708 } 1709 1710 bus_generic_resume(dev); 1711 sc->fc.ibr(&sc->fc); 1712 return 0; 1713} 1714 1715#define ACK_ALL 1716static void 1717fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1718{ 1719 u_int32_t irstat, itstat; 1720 u_int i; 1721 struct firewire_comm *fc = (struct firewire_comm *)sc; 1722 1723#ifdef OHCI_DEBUG 1724 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1725 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1726 stat & OHCI_INT_EN ? "DMA_EN ":"", 1727 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1728 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1729 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1730 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1731 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1732 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1733 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1734 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1735 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1736 stat & OHCI_INT_PHY_SID ? "SID ":"", 1737 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1738 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1739 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1740 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1741 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1742 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1743 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1744 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1745 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1746 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1747 stat, OREAD(sc, FWOHCI_INTMASK) 1748 ); 1749#endif 1750/* Bus reset */ 1751 if(stat & OHCI_INT_PHY_BUS_R ){ 1752 device_printf(fc->dev, "BUS reset\n"); 1753 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1754 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1755 1756 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1757 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1758 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1759 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1760 1761#if 0 1762 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1763 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1764 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1765 } 1766 1767#endif 1768 fw_busreset(fc); 1769 1770 /* XXX need to wait DMA to stop */ 1771#ifndef ACK_ALL 1772 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1773#endif 1774#if 1 1775 /* pending all pre-bus_reset packets */ 1776 fwohci_txd(sc, &sc->atrq); 1777 fwohci_txd(sc, &sc->atrs); 1778 fwohci_arcv(sc, &sc->arrs, -1); 1779 fwohci_arcv(sc, &sc->arrq, -1); 1780#endif 1781 1782 1783 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1784 /* XXX insecure ?? */ 1785 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1786 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1787 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1788 1789 } 1790 if((stat & OHCI_INT_DMA_IR )){ 1791#ifndef ACK_ALL 1792 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1793#endif 1794 irstat = OREAD(sc, OHCI_IR_STAT); 1795 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1796 for(i = 0; i < fc->nisodma ; i++){ 1797 struct fwohci_dbch *dbch; 1798 1799 if((irstat & (1 << i)) != 0){ 1800 dbch = &sc->ir[i]; 1801 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1802 device_printf(sc->fc.dev, 1803 "dma(%d) not active\n", i); 1804 continue; 1805 } 1806 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1807 fwohci_ircv(sc, dbch, count); 1808 } else { 1809 fwohci_rbuf_update(sc, i); 1810 } 1811 } 1812 } 1813 } 1814 if((stat & OHCI_INT_DMA_IT )){ 1815#ifndef ACK_ALL 1816 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1817#endif 1818 itstat = OREAD(sc, OHCI_IT_STAT); 1819 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1820 for(i = 0; i < fc->nisodma ; i++){ 1821 if((itstat & (1 << i)) != 0){ 1822 fwohci_tbuf_update(sc, i); 1823 } 1824 } 1825 } 1826 if((stat & OHCI_INT_DMA_PRRS )){ 1827#ifndef ACK_ALL 1828 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1829#endif 1830#if 0 1831 dump_dma(sc, ARRS_CH); 1832 dump_db(sc, ARRS_CH); 1833#endif 1834 fwohci_arcv(sc, &sc->arrs, count); 1835 } 1836 if((stat & OHCI_INT_DMA_PRRQ )){ 1837#ifndef ACK_ALL 1838 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1839#endif 1840#if 0 1841 dump_dma(sc, ARRQ_CH); 1842 dump_db(sc, ARRQ_CH); 1843#endif 1844 fwohci_arcv(sc, &sc->arrq, count); 1845 } 1846 if(stat & OHCI_INT_PHY_SID){ 1847 caddr_t buf; 1848 int plen; 1849 1850#ifndef ACK_ALL 1851 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1852#endif 1853/* 1854** Checking whether the node is root or not. If root, turn on 1855** cycle master. 1856*/ 1857 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1858 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1859 printf("Bus reset failure\n"); 1860 goto sidout; 1861 } 1862 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1863 printf("CYCLEMASTER mode\n"); 1864 OWRITE(sc, OHCI_LNKCTL, 1865 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1866 }else{ 1867 printf("non CYCLEMASTER mode\n"); 1868 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1869 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1870 } 1871 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1872 1873 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1874 if (plen < 4 || plen > OHCI_SIDSIZE) { 1875 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1876 goto sidout; 1877 } 1878 plen -= 4; /* chop control info */ 1879 buf = malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 1880 if(buf == NULL) goto sidout; 1881 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1882 buf, plen); 1883 fw_sidrcv(fc, buf, plen, 0); 1884 } 1885sidout: 1886 if((stat & OHCI_INT_DMA_ATRQ )){ 1887#ifndef ACK_ALL 1888 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1889#endif 1890 fwohci_txd(sc, &(sc->atrq)); 1891 } 1892 if((stat & OHCI_INT_DMA_ATRS )){ 1893#ifndef ACK_ALL 1894 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1895#endif 1896 fwohci_txd(sc, &(sc->atrs)); 1897 } 1898 if((stat & OHCI_INT_PW_ERR )){ 1899#ifndef ACK_ALL 1900 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1901#endif 1902 device_printf(fc->dev, "posted write error\n"); 1903 } 1904 if((stat & OHCI_INT_ERR )){ 1905#ifndef ACK_ALL 1906 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1907#endif 1908 device_printf(fc->dev, "unrecoverable error\n"); 1909 } 1910 if((stat & OHCI_INT_PHY_INT)) { 1911#ifndef ACK_ALL 1912 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1913#endif 1914 device_printf(fc->dev, "phy int\n"); 1915 } 1916 1917 return; 1918} 1919 1920void 1921fwohci_intr(void *arg) 1922{ 1923 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1924 u_int32_t stat; 1925 1926 if (!(sc->intmask & OHCI_INT_EN)) { 1927 /* polling mode */ 1928 return; 1929 } 1930 1931 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1932 if (stat == 0xffffffff) { 1933 device_printf(sc->fc.dev, 1934 "device physically ejected?\n"); 1935 return; 1936 } 1937#ifdef ACK_ALL 1938 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1939#endif 1940 fwohci_intr_body(sc, stat, -1); 1941 } 1942} 1943 1944static void 1945fwohci_poll(struct firewire_comm *fc, int quick, int count) 1946{ 1947 int s; 1948 u_int32_t stat; 1949 struct fwohci_softc *sc; 1950 1951 1952 sc = (struct fwohci_softc *)fc; 1953 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1954 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1955 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1956#if 0 1957 if (!quick) { 1958#else 1959 if (1) { 1960#endif 1961 stat = OREAD(sc, FWOHCI_INTSTAT); 1962 if (stat == 0) 1963 return; 1964 if (stat == 0xffffffff) { 1965 device_printf(sc->fc.dev, 1966 "device physically ejected?\n"); 1967 return; 1968 } 1969#ifdef ACK_ALL 1970 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1971#endif 1972 } 1973 s = splfw(); 1974 fwohci_intr_body(sc, stat, count); 1975 splx(s); 1976} 1977 1978static void 1979fwohci_set_intr(struct firewire_comm *fc, int enable) 1980{ 1981 struct fwohci_softc *sc; 1982 1983 sc = (struct fwohci_softc *)fc; 1984 if (bootverbose) 1985 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1986 if (enable) { 1987 sc->intmask |= OHCI_INT_EN; 1988 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1989 } else { 1990 sc->intmask &= ~OHCI_INT_EN; 1991 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1992 } 1993} 1994 1995static void 1996fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1997{ 1998 struct firewire_comm *fc = &sc->fc; 1999 volatile struct fwohcidb *db; 2000 struct fw_bulkxfer *chunk; 2001 struct fw_xferq *it; 2002 u_int32_t stat, count; 2003 int s, w=0; 2004 2005 it = fc->it[dmach]; 2006 s = splfw(); /* unnecessary ? */ 2007 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2008 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2009 stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2010 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2011 count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2012 if (stat == 0) 2013 break; 2014 STAILQ_REMOVE_HEAD(&it->stdma, link); 2015 switch (stat & FWOHCIEV_MASK){ 2016 case FWOHCIEV_ACKCOMPL: 2017#if 0 2018 device_printf(fc->dev, "0x%08x\n", count); 2019#endif 2020 break; 2021 default: 2022 device_printf(fc->dev, 2023 "Isochronous transmit err %02x\n", stat); 2024 } 2025 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2026 w++; 2027 } 2028 splx(s); 2029 if (w) 2030 wakeup(it); 2031} 2032 2033static void 2034fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2035{ 2036 struct firewire_comm *fc = &sc->fc; 2037 volatile struct fwohcidb *db; 2038 struct fw_bulkxfer *chunk; 2039 struct fw_xferq *ir; 2040 u_int32_t stat; 2041 int s, w=0; 2042 2043 ir = fc->ir[dmach]; 2044 s = splfw(); 2045 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2046 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2047 stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2048 if (stat == 0) 2049 break; 2050 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2051 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2052 switch (stat & FWOHCIEV_MASK) { 2053 case FWOHCIEV_ACKCOMPL: 2054 break; 2055 default: 2056 device_printf(fc->dev, 2057 "Isochronous receive err %02x\n", stat); 2058 } 2059 w++; 2060 } 2061 splx(s); 2062 if (w) 2063 wakeup(ir); 2064} 2065 2066void 2067dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2068{ 2069 u_int32_t off, cntl, stat, cmd, match; 2070 2071 if(ch == 0){ 2072 off = OHCI_ATQOFF; 2073 }else if(ch == 1){ 2074 off = OHCI_ATSOFF; 2075 }else if(ch == 2){ 2076 off = OHCI_ARQOFF; 2077 }else if(ch == 3){ 2078 off = OHCI_ARSOFF; 2079 }else if(ch < IRX_CH){ 2080 off = OHCI_ITCTL(ch - ITX_CH); 2081 }else{ 2082 off = OHCI_IRCTL(ch - IRX_CH); 2083 } 2084 cntl = stat = OREAD(sc, off); 2085 cmd = OREAD(sc, off + 0xc); 2086 match = OREAD(sc, off + 0x10); 2087 2088 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2089 ch, 2090 cntl, 2091 stat, 2092 cmd, 2093 match); 2094 stat &= 0xffff ; 2095 if(stat & 0xff00){ 2096 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2097 ch, 2098 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2099 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2100 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2101 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2102 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2103 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2104 fwohcicode[stat & 0x1f], 2105 stat & 0x1f 2106 ); 2107 }else{ 2108 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2109 } 2110} 2111 2112void 2113dump_db(struct fwohci_softc *sc, u_int32_t ch) 2114{ 2115 struct fwohci_dbch *dbch; 2116 struct fwohcidb_tr *cp = NULL, *pp, *np; 2117 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2118 int idb, jdb; 2119 u_int32_t cmd, off; 2120 if(ch == 0){ 2121 off = OHCI_ATQOFF; 2122 dbch = &sc->atrq; 2123 }else if(ch == 1){ 2124 off = OHCI_ATSOFF; 2125 dbch = &sc->atrs; 2126 }else if(ch == 2){ 2127 off = OHCI_ARQOFF; 2128 dbch = &sc->arrq; 2129 }else if(ch == 3){ 2130 off = OHCI_ARSOFF; 2131 dbch = &sc->arrs; 2132 }else if(ch < IRX_CH){ 2133 off = OHCI_ITCTL(ch - ITX_CH); 2134 dbch = &sc->it[ch - ITX_CH]; 2135 }else { 2136 off = OHCI_IRCTL(ch - IRX_CH); 2137 dbch = &sc->ir[ch - IRX_CH]; 2138 } 2139 cmd = OREAD(sc, off + 0xc); 2140 2141 if( dbch->ndb == 0 ){ 2142 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2143 return; 2144 } 2145 pp = dbch->top; 2146 prev = pp->db; 2147 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2148 if(pp == NULL){ 2149 curr = NULL; 2150 goto outdb; 2151 } 2152 cp = STAILQ_NEXT(pp, link); 2153 if(cp == NULL){ 2154 curr = NULL; 2155 goto outdb; 2156 } 2157 np = STAILQ_NEXT(cp, link); 2158 if(cp == NULL) break; 2159 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2160 if((cmd & 0xfffffff0) 2161 == vtophys(&(cp->db[jdb]))){ 2162 curr = cp->db; 2163 if(np != NULL){ 2164 next = np->db; 2165 }else{ 2166 next = NULL; 2167 } 2168 goto outdb; 2169 } 2170 } 2171 pp = STAILQ_NEXT(pp, link); 2172 prev = pp->db; 2173 } 2174outdb: 2175 if( curr != NULL){ 2176 printf("Prev DB %d\n", ch); 2177 print_db(prev, ch, dbch->ndesc); 2178 printf("Current DB %d\n", ch); 2179 print_db(curr, ch, dbch->ndesc); 2180 printf("Next DB %d\n", ch); 2181 print_db(next, ch, dbch->ndesc); 2182 }else{ 2183 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2184 } 2185 return; 2186} 2187 2188void 2189print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2190{ 2191 fwohcireg_t stat; 2192 int i, key; 2193 2194 if(db == NULL){ 2195 printf("No Descriptor is found\n"); 2196 return; 2197 } 2198 2199 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2200 ch, 2201 "Current", 2202 "OP ", 2203 "KEY", 2204 "INT", 2205 "BR ", 2206 "len", 2207 "Addr", 2208 "Depend", 2209 "Stat", 2210 "Cnt"); 2211 for( i = 0 ; i <= max ; i ++){ 2212 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2213#if __FreeBSD_version >= 500000 2214 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2215#else 2216 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2217#endif 2218 vtophys(&db[i]), 2219 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2220 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2221 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2222 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2223 db[i].db.desc.cmd & 0xffff, 2224 db[i].db.desc.addr, 2225 db[i].db.desc.depend, 2226 db[i].db.desc.status, 2227 db[i].db.desc.count); 2228 stat = db[i].db.desc.status; 2229 if(stat & 0xff00){ 2230 printf(" %s%s%s%s%s%s %s(%x)\n", 2231 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2232 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2233 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2234 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2235 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2236 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2237 fwohcicode[stat & 0x1f], 2238 stat & 0x1f 2239 ); 2240 }else{ 2241 printf(" Nostat\n"); 2242 } 2243 if(key == OHCI_KEY_ST2 ){ 2244 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2245 db[i+1].db.immed[0], 2246 db[i+1].db.immed[1], 2247 db[i+1].db.immed[2], 2248 db[i+1].db.immed[3]); 2249 } 2250 if(key == OHCI_KEY_DEVICE){ 2251 return; 2252 } 2253 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2254 == OHCI_BRANCH_ALWAYS){ 2255 return; 2256 } 2257 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2258 == OHCI_OUTPUT_LAST){ 2259 return; 2260 } 2261 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2262 == OHCI_INPUT_LAST){ 2263 return; 2264 } 2265 if(key == OHCI_KEY_ST2 ){ 2266 i++; 2267 } 2268 } 2269 return; 2270} 2271 2272void 2273fwohci_ibr(struct firewire_comm *fc) 2274{ 2275 struct fwohci_softc *sc; 2276 u_int32_t fun; 2277 2278 sc = (struct fwohci_softc *)fc; 2279 2280 /* 2281 * Set root hold-off bit so that non cyclemaster capable node 2282 * shouldn't became the root node. 2283 */ 2284#if 1 2285 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2286 fun |= FW_PHY_IBR | FW_PHY_RHB; 2287 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2288#else /* Short bus reset */ 2289 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2290 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2291 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2292#endif 2293} 2294 2295void 2296fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2297{ 2298 struct fwohcidb_tr *db_tr, *fdb_tr; 2299 struct fwohci_dbch *dbch; 2300 struct fw_pkt *fp; 2301 volatile struct fwohci_txpkthdr *ohcifp; 2302 unsigned short chtag; 2303 int idb; 2304 2305 dbch = &sc->it[dmach]; 2306 chtag = sc->it[dmach].xferq.flag & 0xff; 2307 2308 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2309 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2310/* 2311device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2312*/ 2313 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2314 db_tr->db[0].db.desc.cmd 2315 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2316 fp = (struct fw_pkt *)db_tr->buf; 2317 ohcifp = (volatile struct fwohci_txpkthdr *) 2318 db_tr->db[1].db.immed; 2319 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2320 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2321 ohcifp->mode.stream.chtag = chtag; 2322 ohcifp->mode.stream.tcode = 0xa; 2323 ohcifp->mode.stream.spd = 0; 2324 2325 db_tr->db[2].db.desc.cmd 2326 = OHCI_OUTPUT_LAST 2327 | OHCI_UPDATE 2328 | OHCI_BRANCH_ALWAYS 2329 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2330 db_tr->db[2].db.desc.status = 0; 2331 db_tr->db[2].db.desc.count = 0; 2332 db_tr->db[0].db.desc.depend 2333 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2334 db_tr->db[dbch->ndesc - 1].db.desc.depend 2335 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2336 bulkxfer->end = (caddr_t)db_tr; 2337 db_tr = STAILQ_NEXT(db_tr, link); 2338 } 2339 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2340 db_tr->db[0].db.desc.depend &= ~0xf; 2341 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2342 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2343 /* OHCI 1.1 and above */ 2344 db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2345 2346 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2347 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2348/* 2349device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2350*/ 2351 return; 2352} 2353 2354static int 2355fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2356 int mode, void *buf) 2357{ 2358 volatile struct fwohcidb *db = db_tr->db; 2359 int err = 0; 2360 if(buf == 0){ 2361 err = EINVAL; 2362 return err; 2363 } 2364 db_tr->buf = buf; 2365 db_tr->dbcnt = 3; 2366 db_tr->dummy = NULL; 2367 2368 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2369 2370 db[2].db.desc.depend = 0; 2371 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2372 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2373 2374 db[0].db.desc.status = 0; 2375 db[0].db.desc.count = 0; 2376 2377 db[2].db.desc.status = 0; 2378 db[2].db.desc.count = 0; 2379 if( mode & FWXFERQ_STREAM ){ 2380 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2381 if(mode & FWXFERQ_PACKET ){ 2382 db[2].db.desc.cmd 2383 |= OHCI_INTERRUPT_ALWAYS; 2384 } 2385 } 2386 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2387 return 1; 2388} 2389 2390int 2391fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2392 void *buf, void *dummy) 2393{ 2394 volatile struct fwohcidb *db = db_tr->db; 2395 int i; 2396 void *dbuf[2]; 2397 int dsiz[2]; 2398 2399 if(buf == 0){ 2400 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2401 if(buf == NULL) return 0; 2402 db_tr->buf = buf; 2403 db_tr->dbcnt = 1; 2404 db_tr->dummy = NULL; 2405 dsiz[0] = size; 2406 dbuf[0] = buf; 2407 }else if(dummy == NULL){ 2408 db_tr->buf = buf; 2409 db_tr->dbcnt = 1; 2410 db_tr->dummy = NULL; 2411 dsiz[0] = size; 2412 dbuf[0] = buf; 2413 }else{ 2414 db_tr->buf = buf; 2415 db_tr->dbcnt = 2; 2416 db_tr->dummy = dummy; 2417 dsiz[0] = sizeof(u_int32_t); 2418 dsiz[1] = size; 2419 dbuf[0] = dummy; 2420 dbuf[1] = buf; 2421 } 2422 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2423 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2424 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2425 if( mode & FWXFERQ_STREAM ){ 2426 db[i].db.desc.cmd |= OHCI_UPDATE; 2427 } 2428 db[i].db.desc.status = 0; 2429 db[i].db.desc.count = dsiz[i]; 2430 } 2431 if( mode & FWXFERQ_STREAM ){ 2432 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2433 if(mode & FWXFERQ_PACKET ){ 2434 db[db_tr->dbcnt - 1].db.desc.cmd 2435 |= OHCI_INTERRUPT_ALWAYS; 2436 } 2437 } 2438 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2439 return 1; 2440} 2441 2442static void 2443fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2444{ 2445 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2446 struct firewire_comm *fc = (struct firewire_comm *)sc; 2447 int z = 1; 2448 struct fw_pkt *fp; 2449 u_int8_t *ld; 2450 u_int32_t off = NULL; 2451 u_int32_t stat; 2452 u_int32_t *qld; 2453 u_int32_t reg; 2454 u_int spd; 2455 u_int dmach; 2456 int len, i, plen; 2457 caddr_t buf; 2458 2459 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2460 if( &sc->ir[dmach] == dbch){ 2461 off = OHCI_IROFF(dmach); 2462 break; 2463 } 2464 } 2465 if(off == NULL){ 2466 return; 2467 } 2468 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2469 fwohci_irx_disable(&sc->fc, dmach); 2470 return; 2471 } 2472 2473 odb_tr = NULL; 2474 db_tr = dbch->top; 2475 i = 0; 2476 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2477 if (count >= 0 && count-- == 0) 2478 break; 2479 ld = (u_int8_t *)db_tr->buf; 2480 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2481 /* skip timeStamp */ 2482 ld += sizeof(struct fwohci_trailer); 2483 } 2484 qld = (u_int32_t *)ld; 2485 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2486/* 2487{ 2488device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2489 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2490} 2491*/ 2492 fp=(struct fw_pkt *)ld; 2493 qld[0] = htonl(qld[0]); 2494 plen = sizeof(struct fw_isohdr) 2495 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2496 ld += plen; 2497 len -= plen; 2498 buf = db_tr->buf; 2499 db_tr->buf = NULL; 2500 stat = reg & 0x1f; 2501 spd = reg & 0x3; 2502 switch(stat){ 2503 case FWOHCIEV_ACKCOMPL: 2504 case FWOHCIEV_ACKPEND: 2505 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2506 break; 2507 default: 2508 free(buf, M_DEVBUF); 2509 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2510 break; 2511 } 2512 i++; 2513 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2514 dbch->xferq.flag, 0, NULL); 2515 db_tr->db[0].db.desc.depend &= ~0xf; 2516 if(dbch->pdb_tr != NULL){ 2517 dbch->pdb_tr->db[0].db.desc.depend |= z; 2518 } else { 2519 /* XXX should be rewritten in better way */ 2520 dbch->bottom->db[0].db.desc.depend |= z; 2521 } 2522 dbch->pdb_tr = db_tr; 2523 db_tr = STAILQ_NEXT(db_tr, link); 2524 } 2525 dbch->top = db_tr; 2526 reg = OREAD(sc, OHCI_DMACTL(off)); 2527 if (reg & OHCI_CNTL_DMA_ACTIVE) 2528 return; 2529 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2530 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2531 dbch->top = db_tr; 2532 fwohci_irx_enable(fc, dmach); 2533} 2534 2535#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2536static int 2537fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2538{ 2539 int i; 2540 2541 for( i = 4; i < hlen ; i+=4){ 2542 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2543 } 2544 2545 switch(fp->mode.common.tcode){ 2546 case FWTCODE_RREQQ: 2547 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2548 case FWTCODE_WRES: 2549 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2550 case FWTCODE_WREQQ: 2551 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2552 case FWTCODE_RREQB: 2553 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2554 case FWTCODE_RRESQ: 2555 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2556 case FWTCODE_WREQB: 2557 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2558 + sizeof(u_int32_t); 2559 case FWTCODE_LREQ: 2560 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2561 + sizeof(u_int32_t); 2562 case FWTCODE_RRESB: 2563 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2564 + sizeof(u_int32_t); 2565 case FWTCODE_LRES: 2566 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2567 + sizeof(u_int32_t); 2568 case FWOHCITCODE_PHY: 2569 return 16; 2570 } 2571 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2572 return 0; 2573} 2574 2575static void 2576fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2577{ 2578 struct fwohcidb_tr *db_tr; 2579 int z = 1; 2580 struct fw_pkt *fp; 2581 u_int8_t *ld; 2582 u_int32_t stat, off; 2583 u_int spd; 2584 int len, plen, hlen, pcnt, poff = 0, rlen; 2585 int s; 2586 caddr_t buf; 2587 int resCount; 2588 2589 if(&sc->arrq == dbch){ 2590 off = OHCI_ARQOFF; 2591 }else if(&sc->arrs == dbch){ 2592 off = OHCI_ARSOFF; 2593 }else{ 2594 return; 2595 } 2596 2597 s = splfw(); 2598 db_tr = dbch->top; 2599 pcnt = 0; 2600 /* XXX we cannot handle a packet which lies in more than two buf */ 2601 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2602 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2603 resCount = db_tr->db[0].db.desc.count; 2604 len = dbch->xferq.psize - resCount 2605 - dbch->buf_offset; 2606 while (len > 0 ) { 2607 if (count >= 0 && count-- == 0) 2608 goto out; 2609 if(dbch->frag.buf != NULL){ 2610 buf = dbch->frag.buf; 2611 if (dbch->frag.plen < 0) { 2612 /* incomplete header */ 2613 int hlen; 2614 2615 hlen = - dbch->frag.plen; 2616 rlen = hlen - dbch->frag.len; 2617 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2618 ld += rlen; 2619 len -= rlen; 2620 dbch->frag.len += rlen; 2621#if 0 2622 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2623#endif 2624 fp=(struct fw_pkt *)dbch->frag.buf; 2625 dbch->frag.plen 2626 = fwohci_get_plen(sc, fp, hlen); 2627 if (dbch->frag.plen == 0) 2628 goto out; 2629 } 2630 rlen = dbch->frag.plen - dbch->frag.len; 2631#if 0 2632 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2633#endif 2634 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2635 rlen); 2636 ld += rlen; 2637 len -= rlen; 2638 plen = dbch->frag.plen; 2639 dbch->frag.buf = NULL; 2640 dbch->frag.plen = 0; 2641 dbch->frag.len = 0; 2642 poff = 0; 2643 }else{ 2644 fp=(struct fw_pkt *)ld; 2645 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2646 switch(fp->mode.common.tcode){ 2647 case FWTCODE_RREQQ: 2648 case FWTCODE_WRES: 2649 case FWTCODE_WREQQ: 2650 case FWTCODE_RRESQ: 2651 case FWOHCITCODE_PHY: 2652 hlen = 12; 2653 break; 2654 case FWTCODE_RREQB: 2655 case FWTCODE_WREQB: 2656 case FWTCODE_LREQ: 2657 case FWTCODE_RRESB: 2658 case FWTCODE_LRES: 2659 hlen = 16; 2660 break; 2661 default: 2662 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2663 goto out; 2664 } 2665 if (len >= hlen) { 2666 plen = fwohci_get_plen(sc, fp, hlen); 2667 if (plen == 0) 2668 goto out; 2669 plen = (plen + 3) & ~3; 2670 len -= plen; 2671 } else { 2672 plen = -hlen; 2673 len -= hlen; 2674 } 2675 if(resCount > 0 || len > 0){ 2676 buf = malloc( dbch->xferq.psize, 2677 M_DEVBUF, M_NOWAIT); 2678 if(buf == NULL){ 2679 printf("cannot malloc!\n"); 2680 free(db_tr->buf, M_DEVBUF); 2681 goto out; 2682 } 2683 bcopy(ld, buf, plen); 2684 poff = 0; 2685 dbch->frag.buf = NULL; 2686 dbch->frag.plen = 0; 2687 dbch->frag.len = 0; 2688 }else if(len < 0){ 2689 dbch->frag.buf = db_tr->buf; 2690 if (plen < 0) { 2691#if 0 2692 printf("plen < 0:" 2693 "hlen: %d len: %d\n", 2694 hlen, len); 2695#endif 2696 dbch->frag.len = hlen + len; 2697 dbch->frag.plen = -hlen; 2698 } else { 2699 dbch->frag.len = plen + len; 2700 dbch->frag.plen = plen; 2701 } 2702 bcopy(ld, db_tr->buf, dbch->frag.len); 2703 buf = NULL; 2704 }else{ 2705 buf = db_tr->buf; 2706 poff = ld - (u_int8_t *)buf; 2707 dbch->frag.buf = NULL; 2708 dbch->frag.plen = 0; 2709 dbch->frag.len = 0; 2710 } 2711 ld += plen; 2712 } 2713 if( buf != NULL){ 2714/* DMA result-code will be written at the tail of packet */ 2715 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2716 spd = (stat >> 5) & 0x3; 2717 stat &= 0x1f; 2718 switch(stat){ 2719 case FWOHCIEV_ACKPEND: 2720#if 0 2721 printf("fwohci_arcv: ack pending..\n"); 2722#endif 2723 /* fall through */ 2724 case FWOHCIEV_ACKCOMPL: 2725 if( poff != 0 ) 2726 bcopy(buf+poff, buf, plen - 4); 2727 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2728 break; 2729 case FWOHCIEV_BUSRST: 2730 free(buf, M_DEVBUF); 2731 if (sc->fc.status != FWBUSRESET) 2732 printf("got BUSRST packet!?\n"); 2733 break; 2734 default: 2735 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2736#if 0 /* XXX */ 2737 goto out; 2738#endif 2739 break; 2740 } 2741 } 2742 pcnt ++; 2743 }; 2744out: 2745 if (resCount == 0) { 2746 /* done on this buffer */ 2747 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2748 dbch->xferq.flag, 0, NULL); 2749 dbch->bottom->db[0].db.desc.depend |= z; 2750 dbch->bottom = db_tr; 2751 db_tr = STAILQ_NEXT(db_tr, link); 2752 dbch->top = db_tr; 2753 dbch->buf_offset = 0; 2754 } else { 2755 dbch->buf_offset = dbch->xferq.psize - resCount; 2756 break; 2757 } 2758 /* XXX make sure DMA is not dead */ 2759 } 2760#if 0 2761 if (pcnt < 1) 2762 printf("fwohci_arcv: no packets\n"); 2763#endif 2764 splx(s); 2765} 2766