fwohci.c revision 109814
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109814 2003-01-25 14:47:33Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirereg.h> 73#include <dev/firewire/fwohcireg.h> 74#include <dev/firewire/fwohcivar.h> 75#include <dev/firewire/firewire_phy.h> 76 77#include <dev/firewire/iec68113.h> 78 79#undef OHCI_DEBUG 80 81static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82 "STOR","LOAD","NOP ","STOP",}; 83static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84 "UNDEF","REG","SYS","DEV"}; 85char fwohcicode[32][0x20]={ 86 "No stat","Undef","long","miss Ack err", 87 "underrun","overrun","desc err", "data read err", 88 "data write err","bus reset","timeout","tcode err", 89 "Undef","Undef","unknown event","flushed", 90 "Undef","ack complete","ack pend","Undef", 91 "ack busy_X","ack busy_A","ack busy_B","Undef", 92 "Undef","Undef","Undef","ack tardy", 93 "Undef","ack data_err","ack type_err",""}; 94#define MAX_SPEED 2 95extern char linkspeed[MAX_SPEED+1][0x10]; 96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr __P((struct firewire_comm *)); 126static void fwohci_db_init __P((struct fwohci_dbch *)); 127static void fwohci_db_free __P((struct fwohci_dbch *)); 128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_start_atq __P((struct firewire_comm *)); 132static void fwohci_start_ats __P((struct firewire_comm *)); 133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144static int fwohci_irx_disable __P((struct firewire_comm *, int)); 145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_poll __P((struct firewire_comm *, int, int)); 150static void fwohci_set_intr __P((struct firewire_comm *, int)); 151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160 161/* 162 * memory allocated for DMA programs 163 */ 164#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166/* #define NDB 1024 */ 167#define NDB FWMAXQUEUE 168#define NDVDB (DVBUF * NDB) 169 170#define OHCI_VERSION 0x00 171#define OHCI_CROMHDR 0x18 172#define OHCI_BUS_OPT 0x20 173#define OHCI_BUSIRMC (1 << 31) 174#define OHCI_BUSCMC (1 << 30) 175#define OHCI_BUSISC (1 << 29) 176#define OHCI_BUSBMC (1 << 28) 177#define OHCI_BUSPMC (1 << 27) 178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181#define OHCI_EUID_HI 0x24 182#define OHCI_EUID_LO 0x28 183 184#define OHCI_CROMPTR 0x34 185#define OHCI_HCCCTL 0x50 186#define OHCI_HCCCTLCLR 0x54 187#define OHCI_AREQHI 0x100 188#define OHCI_AREQHICLR 0x104 189#define OHCI_AREQLO 0x108 190#define OHCI_AREQLOCLR 0x10c 191#define OHCI_PREQHI 0x110 192#define OHCI_PREQHICLR 0x114 193#define OHCI_PREQLO 0x118 194#define OHCI_PREQLOCLR 0x11c 195#define OHCI_PREQUPPER 0x120 196 197#define OHCI_SID_BUF 0x64 198#define OHCI_SID_CNT 0x68 199#define OHCI_SID_CNT_MASK 0xffc 200 201#define OHCI_IT_STAT 0x90 202#define OHCI_IT_STATCLR 0x94 203#define OHCI_IT_MASK 0x98 204#define OHCI_IT_MASKCLR 0x9c 205 206#define OHCI_IR_STAT 0xa0 207#define OHCI_IR_STATCLR 0xa4 208#define OHCI_IR_MASK 0xa8 209#define OHCI_IR_MASKCLR 0xac 210 211#define OHCI_LNKCTL 0xe0 212#define OHCI_LNKCTLCLR 0xe4 213 214#define OHCI_PHYACCESS 0xec 215#define OHCI_CYCLETIMER 0xf0 216 217#define OHCI_DMACTL(off) (off) 218#define OHCI_DMACTLCLR(off) (off + 4) 219#define OHCI_DMACMD(off) (off + 0xc) 220#define OHCI_DMAMATCH(off) (off + 0x10) 221 222#define OHCI_ATQOFF 0x180 223#define OHCI_ATQCTL OHCI_ATQOFF 224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228#define OHCI_ATSOFF 0x1a0 229#define OHCI_ATSCTL OHCI_ATSOFF 230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234#define OHCI_ARQOFF 0x1c0 235#define OHCI_ARQCTL OHCI_ARQOFF 236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240#define OHCI_ARSOFF 0x1e0 241#define OHCI_ARSCTL OHCI_ARSOFF 242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257d_ioctl_t fwohci_ioctl; 258 259/* 260 * Communication with PHY device 261 */ 262static u_int32_t 263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264{ 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275} 276 277static u_int32_t 278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279{ 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284#define OHCI_CSR_DATA 0x0c 285#define OHCI_CSR_COMP 0x10 286#define OHCI_CSR_CONT 0x14 287#define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(10); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302} 303 304static u_int32_t 305fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306{ 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311#define MAX_RETRY 100 312again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(100); 321 } 322 if(i >= MAX_RETRY) { 323 if (bootverbose) 324 device_printf(sc->fc.dev, "phy read failed(1).\n"); 325 if (++retry < MAX_RETRY) { 326 DELAY(100); 327 goto again; 328 } 329 } 330 /* Make sure that SCLK is started */ 331 stat = OREAD(sc, FWOHCI_INTSTAT); 332 if ((stat & OHCI_INT_REG_FAIL) != 0 || 333 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 334 if (bootverbose) 335 device_printf(sc->fc.dev, "phy read failed(2).\n"); 336 if (++retry < MAX_RETRY) { 337 DELAY(100); 338 goto again; 339 } 340 } 341 if (bootverbose || retry >= MAX_RETRY) 342 device_printf(sc->fc.dev, 343 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 344#undef MAX_RETRY 345 return((fun >> PHYDEV_RDDATA )& 0xff); 346} 347/* Device specific ioctl. */ 348int 349fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350{ 351 struct firewire_softc *sc; 352 struct fwohci_softc *fc; 353 int unit = DEV2UNIT(dev); 354 int err = 0; 355 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356 u_int32_t *dmach = (u_int32_t *) data; 357 358 sc = devclass_get_softc(firewire_devclass, unit); 359 if(sc == NULL){ 360 return(EINVAL); 361 } 362 fc = (struct fwohci_softc *)sc->fc; 363 364 if (!data) 365 return(EINVAL); 366 367 switch (cmd) { 368 case FWOHCI_WRREG: 369#define OHCI_MAX_REG 0x800 370 if(reg->addr <= OHCI_MAX_REG){ 371 OWRITE(fc, reg->addr, reg->data); 372 reg->data = OREAD(fc, reg->addr); 373 }else{ 374 err = EINVAL; 375 } 376 break; 377 case FWOHCI_RDREG: 378 if(reg->addr <= OHCI_MAX_REG){ 379 reg->data = OREAD(fc, reg->addr); 380 }else{ 381 err = EINVAL; 382 } 383 break; 384/* Read DMA descriptors for debug */ 385 case DUMPDMA: 386 if(*dmach <= OHCI_MAX_DMA_CH ){ 387 dump_dma(fc, *dmach); 388 dump_db(fc, *dmach); 389 }else{ 390 err = EINVAL; 391 } 392 break; 393 default: 394 break; 395 } 396 return err; 397} 398 399static int 400fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 401{ 402 u_int32_t reg, reg2; 403 int e1394a = 1; 404/* 405 * probe PHY parameters 406 * 0. to prove PHY version, whether compliance of 1394a. 407 * 1. to probe maximum speed supported by the PHY and 408 * number of port supported by core-logic. 409 * It is not actually available port on your PC . 410 */ 411 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 412#if 0 413 /* XXX wait for SCLK. */ 414 DELAY(100000); 415#endif 416 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417 418 if((reg >> 5) != 7 ){ 419 sc->fc.mode &= ~FWPHYASYST; 420 sc->fc.nport = reg & FW_PHY_NP; 421 sc->fc.speed = reg & FW_PHY_SPD >> 6; 422 if (sc->fc.speed > MAX_SPEED) { 423 device_printf(dev, "invalid speed %d (fixed to %d).\n", 424 sc->fc.speed, MAX_SPEED); 425 sc->fc.speed = MAX_SPEED; 426 } 427 device_printf(dev, 428 "Phy 1394 only %s, %d ports.\n", 429 linkspeed[sc->fc.speed], sc->fc.nport); 430 }else{ 431 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432 sc->fc.mode |= FWPHYASYST; 433 sc->fc.nport = reg & FW_PHY_NP; 434 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435 if (sc->fc.speed > MAX_SPEED) { 436 device_printf(dev, "invalid speed %d (fixed to %d).\n", 437 sc->fc.speed, MAX_SPEED); 438 sc->fc.speed = MAX_SPEED; 439 } 440 device_printf(dev, 441 "Phy 1394a available %s, %d ports.\n", 442 linkspeed[sc->fc.speed], sc->fc.nport); 443 444 /* check programPhyEnable */ 445 reg2 = fwphy_rddata(sc, 5); 446#if 0 447 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448#else /* XXX force to enable 1394a */ 449 if (e1394a) { 450#endif 451 if (bootverbose) 452 device_printf(dev, 453 "Enable 1394a Enhancements\n"); 454 /* enable EAA EMC */ 455 reg2 |= 0x03; 456 /* set aPhyEnhanceEnable */ 457 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459 } else { 460 /* for safe */ 461 reg2 &= ~0x83; 462 } 463 reg2 = fwphy_wrdata(sc, 5, reg2); 464 } 465 466 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467 if((reg >> 5) == 7 ){ 468 reg = fwphy_rddata(sc, 4); 469 reg |= 1 << 6; 470 fwphy_wrdata(sc, 4, reg); 471 reg = fwphy_rddata(sc, 4); 472 } 473 return 0; 474} 475 476 477void 478fwohci_reset(struct fwohci_softc *sc, device_t dev) 479{ 480 int i, max_rec, speed; 481 u_int32_t reg, reg2; 482 struct fwohcidb_tr *db_tr; 483 484 /* Disable interrupt */ 485 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486 487 /* Now stopping all DMA channel */ 488 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492 493 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 } 498 499 /* FLUSH FIFO and reset Transmitter/Reciever */ 500 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501 if (bootverbose) 502 device_printf(dev, "resetting OHCI..."); 503 i = 0; 504 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505 if (i++ > 100) break; 506 DELAY(1000); 507 } 508 if (bootverbose) 509 printf("done (loop=%d)\n", i); 510 511 /* Probe phy */ 512 fwohci_probe_phy(sc, dev); 513 514 /* Probe link */ 515 reg = OREAD(sc, OHCI_BUS_OPT); 516 reg2 = reg | OHCI_BUSFNC; 517 max_rec = (reg & 0x0000f000) >> 12; 518 speed = (reg & 0x00000007); 519 device_printf(dev, "Link %s, max_rec %d bytes.\n", 520 linkspeed[speed], MAXREC(max_rec)); 521 /* XXX fix max_rec */ 522 sc->fc.maxrec = sc->fc.speed + 8; 523 if (max_rec != sc->fc.maxrec) { 524 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525 device_printf(dev, "max_rec %d -> %d\n", 526 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527 } 528 if (bootverbose) 529 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530 OWRITE(sc, OHCI_BUS_OPT, reg2); 531 532 /* Initialize registers */ 533 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 535 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 538 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539 fw_busreset(&sc->fc); 540 541 /* Enable link */ 542 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543 544 /* Force to start async RX DMA */ 545 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547 fwohci_rx_enable(sc, &sc->arrq); 548 fwohci_rx_enable(sc, &sc->arrs); 549 550 /* Initialize async TX */ 551 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 /* AT Retries */ 554 OWRITE(sc, FWOHCI_RETRY, 555 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559 db_tr->xfer = NULL; 560 } 561 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563 db_tr->xfer = NULL; 564 } 565 566 567 /* Enable interrupt */ 568 OWRITE(sc, FWOHCI_INTMASK, 569 OHCI_INT_ERR | OHCI_INT_PHY_SID 570 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573 fwohci_set_intr(&sc->fc, 1); 574 575} 576 577int 578fwohci_init(struct fwohci_softc *sc, device_t dev) 579{ 580 int i; 581 u_int32_t reg; 582 u_int8_t ui[8]; 583 584 reg = OREAD(sc, OHCI_VERSION); 585 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 586 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 587 588/* XXX: Available Isochrounous DMA channel probe */ 589 for( i = 0 ; i < 0x20 ; i ++ ){ 590 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 591 reg = OREAD(sc, OHCI_IRCTL(i)); 592 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 593 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 594 reg = OREAD(sc, OHCI_ITCTL(i)); 595 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 596 } 597 sc->fc.nisodma = i; 598 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 599 600 sc->fc.arq = &sc->arrq.xferq; 601 sc->fc.ars = &sc->arrs.xferq; 602 sc->fc.atq = &sc->atrq.xferq; 603 sc->fc.ats = &sc->atrs.xferq; 604 605 sc->arrq.xferq.start = NULL; 606 sc->arrs.xferq.start = NULL; 607 sc->atrq.xferq.start = fwohci_start_atq; 608 sc->atrs.xferq.start = fwohci_start_ats; 609 610 sc->arrq.xferq.drain = NULL; 611 sc->arrs.xferq.drain = NULL; 612 sc->atrq.xferq.drain = fwohci_drain_atq; 613 sc->atrs.xferq.drain = fwohci_drain_ats; 614 615 sc->arrq.ndesc = 1; 616 sc->arrs.ndesc = 1; 617 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 618 sc->atrs.ndesc = 6 / 2; 619 620 sc->arrq.ndb = NDB; 621 sc->arrs.ndb = NDB / 2; 622 sc->atrq.ndb = NDB; 623 sc->atrs.ndb = NDB / 2; 624 625 sc->arrq.dummy = NULL; 626 sc->arrs.dummy = NULL; 627 sc->atrq.dummy = NULL; 628 sc->atrs.dummy = NULL; 629 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 630 sc->fc.it[i] = &sc->it[i].xferq; 631 sc->fc.ir[i] = &sc->ir[i].xferq; 632 sc->it[i].ndb = 0; 633 sc->ir[i].ndb = 0; 634 } 635 636 sc->fc.tcode = tinfo; 637 638 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT); 639 640 if(sc->cromptr == NULL){ 641 device_printf(dev, "cromptr alloc failed."); 642 return ENOMEM; 643 } 644 sc->fc.dev = dev; 645 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 646 647 sc->fc.config_rom[1] = 0x31333934; 648 sc->fc.config_rom[2] = 0xf000a002; 649 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 650 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 651 sc->fc.config_rom[5] = 0; 652 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 653 654 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 655 656 657/* SID recieve buffer must allign 2^11 */ 658#define OHCI_SIDSIZE (1 << 11) 659 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 660 if (sc->fc.sid_buf == NULL) { 661 device_printf(dev, "sid_buf alloc failed.\n"); 662 return ENOMEM; 663 } 664 if (((u_int32_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 665 device_printf(dev, "sid_buf(%p) not aligned.\n", 666 sc->fc.sid_buf); 667 return ENOMEM; 668 } 669 670 fwohci_db_init(&sc->arrq); 671 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 672 return ENOMEM; 673 674 fwohci_db_init(&sc->arrs); 675 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 676 return ENOMEM; 677 678 fwohci_db_init(&sc->atrq); 679 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 680 return ENOMEM; 681 682 fwohci_db_init(&sc->atrs); 683 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 684 return ENOMEM; 685 686 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 687 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 688 for( i = 0 ; i < 8 ; i ++) 689 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 690 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 691 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 692 693 sc->fc.ioctl = fwohci_ioctl; 694 sc->fc.cyctimer = fwohci_cyctimer; 695 sc->fc.set_bmr = fwohci_set_bus_manager; 696 sc->fc.ibr = fwohci_ibr; 697 sc->fc.irx_enable = fwohci_irx_enable; 698 sc->fc.irx_disable = fwohci_irx_disable; 699 700 sc->fc.itx_enable = fwohci_itxbuf_enable; 701 sc->fc.itx_disable = fwohci_itx_disable; 702 sc->fc.irx_post = fwohci_irx_post; 703 sc->fc.itx_post = NULL; 704 sc->fc.timeout = fwohci_timeout; 705 sc->fc.poll = fwohci_poll; 706 sc->fc.set_intr = fwohci_set_intr; 707 708 fw_init(&sc->fc); 709 fwohci_reset(sc, dev); 710 711 return 0; 712} 713 714void 715fwohci_timeout(void *arg) 716{ 717 struct fwohci_softc *sc; 718 719 sc = (struct fwohci_softc *)arg; 720 sc->fc.timeouthandle = timeout(fwohci_timeout, 721 (void *)sc, FW_XFERTIMEOUT * hz * 10); 722} 723 724u_int32_t 725fwohci_cyctimer(struct firewire_comm *fc) 726{ 727 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 728 return(OREAD(sc, OHCI_CYCLETIMER)); 729} 730 731int 732fwohci_detach(struct fwohci_softc *sc, device_t dev) 733{ 734 int i; 735 736 if (sc->fc.sid_buf != NULL) 737 free((void *)(uintptr_t)sc->fc.sid_buf, M_DEVBUF); 738 if (sc->cromptr != NULL) 739 free((void *)sc->cromptr, M_DEVBUF); 740 741 fwohci_db_free(&sc->arrq); 742 fwohci_db_free(&sc->arrs); 743 744 fwohci_db_free(&sc->atrq); 745 fwohci_db_free(&sc->atrs); 746 747 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 748 fwohci_db_free(&sc->it[i]); 749 fwohci_db_free(&sc->ir[i]); 750 } 751 752 return 0; 753} 754 755#define LAST_DB(dbtr, db) do { \ 756 struct fwohcidb_tr *_dbtr = (dbtr); \ 757 int _cnt = _dbtr->dbcnt; \ 758 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 759} while (0) 760 761static void 762fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 763{ 764 int i, s; 765 int tcode, hdr_len, hdr_off, len; 766 int fsegment = -1; 767 u_int32_t off; 768 struct fw_xfer *xfer; 769 struct fw_pkt *fp; 770 volatile struct fwohci_txpkthdr *ohcifp; 771 struct fwohcidb_tr *db_tr; 772 volatile struct fwohcidb *db; 773 struct mbuf *m; 774 struct tcode_info *info; 775 static int maxdesc=0; 776 777 if(&sc->atrq == dbch){ 778 off = OHCI_ATQOFF; 779 }else if(&sc->atrs == dbch){ 780 off = OHCI_ATSOFF; 781 }else{ 782 return; 783 } 784 785 if (dbch->flags & FWOHCI_DBCH_FULL) 786 return; 787 788 s = splfw(); 789 db_tr = dbch->top; 790txloop: 791 xfer = STAILQ_FIRST(&dbch->xferq.q); 792 if(xfer == NULL){ 793 goto kick; 794 } 795 if(dbch->xferq.queued == 0 ){ 796 device_printf(sc->fc.dev, "TX queue empty\n"); 797 } 798 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 799 db_tr->xfer = xfer; 800 xfer->state = FWXF_START; 801 dbch->xferq.packets++; 802 803 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 804 tcode = fp->mode.common.tcode; 805 806 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 807 info = &tinfo[tcode]; 808 hdr_len = hdr_off = info->hdr_len; 809 /* fw_asyreq must pass valid send.len */ 810 len = xfer->send.len; 811 for( i = 0 ; i < hdr_off ; i+= 4){ 812 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 813 } 814 ohcifp->mode.common.spd = xfer->spd; 815 if (tcode == FWTCODE_STREAM ){ 816 hdr_len = 8; 817 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 818 } else if (tcode == FWTCODE_PHY) { 819 hdr_len = 12; 820 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 821 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 822 ohcifp->mode.common.spd = 0; 823 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 824 } else { 825 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 826 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 827 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 828 } 829 db = &db_tr->db[0]; 830 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 831 db->db.desc.status = 0; 832/* Specify bound timer of asy. responce */ 833 if(&sc->atrs == dbch){ 834 db->db.desc.count 835 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 836 } 837 838 db_tr->dbcnt = 2; 839 db = &db_tr->db[db_tr->dbcnt]; 840 if(len > hdr_off){ 841 if (xfer->mbuf == NULL) { 842 db->db.desc.addr 843 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 844 db->db.desc.cmd 845 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 846 db->db.desc.status = 0; 847 848 db_tr->dbcnt++; 849 } else { 850 /* XXX we assume mbuf chain is shorter than ndesc */ 851 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 852 if (m->m_len == 0) 853 /* unrecoverable error could ocurre. */ 854 continue; 855 if (db_tr->dbcnt >= dbch->ndesc) { 856 device_printf(sc->fc.dev, 857 "dbch->ndesc is too small" 858 ", trancated.\n"); 859 break; 860 } 861 db->db.desc.addr 862 = vtophys(mtod(m, caddr_t)); 863 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 864 db->db.desc.status = 0; 865 db++; 866 db_tr->dbcnt++; 867 } 868 } 869 } 870 if (maxdesc < db_tr->dbcnt) { 871 maxdesc = db_tr->dbcnt; 872 if (bootverbose) 873 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 874 } 875 /* last db */ 876 LAST_DB(db_tr, db); 877 db->db.desc.cmd |= OHCI_OUTPUT_LAST 878 | OHCI_INTERRUPT_ALWAYS 879 | OHCI_BRANCH_ALWAYS; 880 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 881 882 if(fsegment == -1 ) 883 fsegment = db_tr->dbcnt; 884 if (dbch->pdb_tr != NULL) { 885 LAST_DB(dbch->pdb_tr, db); 886 db->db.desc.depend |= db_tr->dbcnt; 887 } 888 dbch->pdb_tr = db_tr; 889 db_tr = STAILQ_NEXT(db_tr, link); 890 if(db_tr != dbch->bottom){ 891 goto txloop; 892 } else { 893 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 894 dbch->flags |= FWOHCI_DBCH_FULL; 895 } 896kick: 897 if (firewire_debug) printf("kick\n"); 898 /* kick asy q */ 899 900 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 901 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 902 } else { 903 if (bootverbose) 904 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 905 OREAD(sc, OHCI_DMACTL(off))); 906 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 907 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 908 dbch->xferq.flag |= FWXFERQ_RUNNING; 909 } 910 911 dbch->top = db_tr; 912 splx(s); 913 return; 914} 915 916static void 917fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 918{ 919 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 920 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 921 return; 922} 923 924static void 925fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 926{ 927 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 928 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 929 return; 930} 931 932static void 933fwohci_start_atq(struct firewire_comm *fc) 934{ 935 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 936 fwohci_start( sc, &(sc->atrq)); 937 return; 938} 939 940static void 941fwohci_start_ats(struct firewire_comm *fc) 942{ 943 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 944 fwohci_start( sc, &(sc->atrs)); 945 return; 946} 947 948void 949fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 950{ 951 int s, err = 0; 952 struct fwohcidb_tr *tr; 953 volatile struct fwohcidb *db; 954 struct fw_xfer *xfer; 955 u_int32_t off; 956 u_int stat; 957 int packets; 958 struct firewire_comm *fc = (struct firewire_comm *)sc; 959 if(&sc->atrq == dbch){ 960 off = OHCI_ATQOFF; 961 }else if(&sc->atrs == dbch){ 962 off = OHCI_ATSOFF; 963 }else{ 964 return; 965 } 966 s = splfw(); 967 tr = dbch->bottom; 968 packets = 0; 969 while(dbch->xferq.queued > 0){ 970 LAST_DB(tr, db); 971 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 972 if (fc->status != FWBUSRESET) 973 /* maybe out of order?? */ 974 goto out; 975 } 976 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 977#ifdef OHCI_DEBUG 978 dump_dma(sc, ch); 979 dump_db(sc, ch); 980#endif 981/* Stop DMA */ 982 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 983 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 984 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 985 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 986 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 987 } 988 stat = db->db.desc.status & FWOHCIEV_MASK; 989 switch(stat){ 990 case FWOHCIEV_ACKCOMPL: 991 case FWOHCIEV_ACKPEND: 992 err = 0; 993 break; 994 case FWOHCIEV_ACKBSA: 995 case FWOHCIEV_ACKBSB: 996 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 997 case FWOHCIEV_ACKBSX: 998 err = EBUSY; 999 break; 1000 case FWOHCIEV_FLUSHED: 1001 case FWOHCIEV_ACKTARD: 1002 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1003 err = EAGAIN; 1004 break; 1005 case FWOHCIEV_MISSACK: 1006 case FWOHCIEV_UNDRRUN: 1007 case FWOHCIEV_OVRRUN: 1008 case FWOHCIEV_DESCERR: 1009 case FWOHCIEV_DTRDERR: 1010 case FWOHCIEV_TIMEOUT: 1011 case FWOHCIEV_TCODERR: 1012 case FWOHCIEV_UNKNOWN: 1013 case FWOHCIEV_ACKDERR: 1014 case FWOHCIEV_ACKTERR: 1015 default: 1016 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1017 stat, fwohcicode[stat]); 1018 err = EINVAL; 1019 break; 1020 } 1021 if(tr->xfer != NULL){ 1022 xfer = tr->xfer; 1023 xfer->state = FWXF_SENT; 1024 if(err == EBUSY && fc->status != FWBUSRESET){ 1025 xfer->state = FWXF_BUSY; 1026 switch(xfer->act_type){ 1027 case FWACT_XFER: 1028 xfer->resp = err; 1029 if(xfer->retry_req != NULL){ 1030 xfer->retry_req(xfer); 1031 } 1032 break; 1033 default: 1034 break; 1035 } 1036 } else if( stat != FWOHCIEV_ACKPEND){ 1037 if (stat != FWOHCIEV_ACKCOMPL) 1038 xfer->state = FWXF_SENTERR; 1039 xfer->resp = err; 1040 switch(xfer->act_type){ 1041 case FWACT_XFER: 1042 fw_xfer_done(xfer); 1043 break; 1044 default: 1045 break; 1046 } 1047 } 1048 dbch->xferq.queued --; 1049 } 1050 tr->xfer = NULL; 1051 1052 packets ++; 1053 tr = STAILQ_NEXT(tr, link); 1054 dbch->bottom = tr; 1055 } 1056out: 1057 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1058 printf("make free slot\n"); 1059 dbch->flags &= ~FWOHCI_DBCH_FULL; 1060 fwohci_start(sc, dbch); 1061 } 1062 splx(s); 1063} 1064 1065static void 1066fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1067{ 1068 int i, s; 1069 struct fwohcidb_tr *tr; 1070 1071 if(xfer->state != FWXF_START) return; 1072 1073 s = splfw(); 1074 tr = dbch->bottom; 1075 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1076 if(tr->xfer == xfer){ 1077 s = splfw(); 1078 tr->xfer = NULL; 1079 dbch->xferq.queued --; 1080#if 1 1081 /* XXX */ 1082 if (tr == dbch->bottom) 1083 dbch->bottom = STAILQ_NEXT(tr, link); 1084#endif 1085 if (dbch->flags & FWOHCI_DBCH_FULL) { 1086 printf("fwohci_drain: make slot\n"); 1087 dbch->flags &= ~FWOHCI_DBCH_FULL; 1088 fwohci_start((struct fwohci_softc *)fc, dbch); 1089 } 1090 1091 splx(s); 1092 break; 1093 } 1094 tr = STAILQ_NEXT(tr, link); 1095 } 1096 splx(s); 1097 return; 1098} 1099 1100static void 1101fwohci_db_free(struct fwohci_dbch *dbch) 1102{ 1103 struct fwohcidb_tr *db_tr; 1104 int idb, i; 1105 1106 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1107 return; 1108 1109 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1110 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1111 idb < dbch->ndb; 1112 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1113 if (db_tr->buf != NULL) { 1114 free(db_tr->buf, M_DEVBUF); 1115 db_tr->buf = NULL; 1116 } 1117 } 1118 } 1119 dbch->ndb = 0; 1120 db_tr = STAILQ_FIRST(&dbch->db_trq); 1121 for (i = 0; i < dbch->npages; i++) 1122 free(dbch->pages[i], M_DEVBUF); 1123 free(db_tr, M_DEVBUF); 1124 STAILQ_INIT(&dbch->db_trq); 1125 dbch->flags &= ~FWOHCI_DBCH_INIT; 1126} 1127 1128static void 1129fwohci_db_init(struct fwohci_dbch *dbch) 1130{ 1131 int idb; 1132 struct fwohcidb_tr *db_tr; 1133 int ndbpp, i, j; 1134 1135 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1136 goto out; 1137 1138 /* allocate DB entries and attach one to each DMA channels */ 1139 /* DB entry must start at 16 bytes bounary. */ 1140 STAILQ_INIT(&dbch->db_trq); 1141 db_tr = (struct fwohcidb_tr *) 1142 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1143 M_DEVBUF, M_NOWAIT | M_ZERO); 1144 if(db_tr == NULL){ 1145 printf("fwohci_db_init: malloc(1) failed\n"); 1146 return; 1147 } 1148 1149 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1150 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1151 if (firewire_debug) 1152 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1153 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1154 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1155 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1156 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1157 return; 1158 } 1159 for (i = 0; i < dbch->npages; i++) { 1160 dbch->pages[i] = malloc(PAGE_SIZE, M_DEVBUF, 1161 M_NOWAIT | M_ZERO); 1162 if (dbch->pages[i] == NULL) { 1163 printf("fwohci_db_init: malloc(2) failed\n"); 1164 for (j = 0; j < i; j ++) 1165 free(dbch->pages[j], M_DEVBUF); 1166 free(db_tr, M_DEVBUF); 1167 return; 1168 } 1169 } 1170 /* Attach DB to DMA ch. */ 1171 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1172 db_tr->dbcnt = 0; 1173 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1174 + dbch->ndesc * (idb % ndbpp); 1175 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1176 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1177 dbch->xferq.bnpacket != 0) { 1178 if (idb % dbch->xferq.bnpacket == 0) 1179 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1180 ].start = (caddr_t)db_tr; 1181 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1182 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1183 ].end = (caddr_t)db_tr; 1184 } 1185 db_tr++; 1186 } 1187 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1188 = STAILQ_FIRST(&dbch->db_trq); 1189out: 1190 dbch->frag.buf = NULL; 1191 dbch->frag.len = 0; 1192 dbch->frag.plen = 0; 1193 dbch->xferq.queued = 0; 1194 dbch->pdb_tr = NULL; 1195 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1196 dbch->bottom = dbch->top; 1197 dbch->flags = FWOHCI_DBCH_INIT; 1198} 1199 1200static int 1201fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1202{ 1203 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1204 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1205 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1206 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1207 fwohci_db_free(&sc->it[dmach]); 1208 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1209 return 0; 1210} 1211 1212static int 1213fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1214{ 1215 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1216 1217 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1218 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1219 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1220 if(sc->ir[dmach].dummy != NULL){ 1221 free(sc->ir[dmach].dummy, M_DEVBUF); 1222 } 1223 sc->ir[dmach].dummy = NULL; 1224 fwohci_db_free(&sc->ir[dmach]); 1225 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1226 return 0; 1227} 1228 1229static void 1230fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1231{ 1232 qld[0] = ntohl(qld[0]); 1233 return; 1234} 1235 1236static int 1237fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1238{ 1239 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1240 int err = 0; 1241 unsigned short tag, ich; 1242 1243 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1244 ich = sc->ir[dmach].xferq.flag & 0x3f; 1245 1246#if 0 1247 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1248 wakeup(fc->ir[dmach]); 1249 return err; 1250 } 1251#endif 1252 1253 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1254 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1255 sc->ir[dmach].xferq.queued = 0; 1256 sc->ir[dmach].ndb = NDB; 1257 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1258 sc->ir[dmach].ndesc = 1; 1259 fwohci_db_init(&sc->ir[dmach]); 1260 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1261 return ENOMEM; 1262 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1263 } 1264 if(err){ 1265 device_printf(sc->fc.dev, "err in IRX setting\n"); 1266 return err; 1267 } 1268 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1269 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1270 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1271 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1272 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1273 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1274 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1275 OWRITE(sc, OHCI_IRCMD(dmach), 1276 vtophys(sc->ir[dmach].top->db) | 1); 1277 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1278 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1279 } 1280 return err; 1281} 1282 1283static int 1284fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1285{ 1286 int err = 0; 1287 int idb, z, i, dmach = 0; 1288 u_int32_t off = NULL; 1289 struct fwohcidb_tr *db_tr; 1290 1291 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1292 err = EINVAL; 1293 return err; 1294 } 1295 z = dbch->ndesc; 1296 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1297 if( &sc->it[dmach] == dbch){ 1298 off = OHCI_ITOFF(dmach); 1299 break; 1300 } 1301 } 1302 if(off == NULL){ 1303 err = EINVAL; 1304 return err; 1305 } 1306 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1307 return err; 1308 dbch->xferq.flag |= FWXFERQ_RUNNING; 1309 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1310 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1311 } 1312 db_tr = dbch->top; 1313 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1314 fwohci_add_tx_buf(db_tr, 1315 dbch->xferq.psize, dbch->xferq.flag, 1316 dbch->xferq.buf + dbch->xferq.psize * idb); 1317 if(STAILQ_NEXT(db_tr, link) == NULL){ 1318 break; 1319 } 1320 db_tr->db[0].db.desc.depend 1321 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1322 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1323 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1324 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1325 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1326 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1327 |= OHCI_INTERRUPT_ALWAYS; 1328 db_tr->db[0].db.desc.depend &= ~0xf; 1329 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1330 ~0xf; 1331 /* OHCI 1.1 and above */ 1332 db_tr->db[0].db.desc.cmd 1333 |= OHCI_INTERRUPT_ALWAYS; 1334 } 1335 } 1336 db_tr = STAILQ_NEXT(db_tr, link); 1337 } 1338 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1339 return err; 1340} 1341 1342static int 1343fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1344{ 1345 int err = 0; 1346 int idb, z, i, dmach = 0; 1347 u_int32_t off = NULL; 1348 struct fwohcidb_tr *db_tr; 1349 1350 z = dbch->ndesc; 1351 if(&sc->arrq == dbch){ 1352 off = OHCI_ARQOFF; 1353 }else if(&sc->arrs == dbch){ 1354 off = OHCI_ARSOFF; 1355 }else{ 1356 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1357 if( &sc->ir[dmach] == dbch){ 1358 off = OHCI_IROFF(dmach); 1359 break; 1360 } 1361 } 1362 } 1363 if(off == NULL){ 1364 err = EINVAL; 1365 return err; 1366 } 1367 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1368 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1369 return err; 1370 }else{ 1371 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1372 err = EBUSY; 1373 return err; 1374 } 1375 } 1376 dbch->xferq.flag |= FWXFERQ_RUNNING; 1377 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1378 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1379 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1380 } 1381 db_tr = dbch->top; 1382 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1383 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1384 fwohci_add_rx_buf(db_tr, 1385 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1386 }else{ 1387 fwohci_add_rx_buf(db_tr, 1388 dbch->xferq.psize, dbch->xferq.flag, 1389 dbch->xferq.buf + dbch->xferq.psize * idb, 1390 dbch->dummy + sizeof(u_int32_t) * idb); 1391 } 1392 if(STAILQ_NEXT(db_tr, link) == NULL){ 1393 break; 1394 } 1395 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1396 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1397 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1398 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1399 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1400 |= OHCI_INTERRUPT_ALWAYS; 1401 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1402 ~0xf; 1403 } 1404 } 1405 db_tr = STAILQ_NEXT(db_tr, link); 1406 } 1407 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1408 dbch->buf_offset = 0; 1409 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1410 return err; 1411 }else{ 1412 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1413 } 1414 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1415 return err; 1416} 1417 1418static int 1419fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1420{ 1421 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1422 int err = 0; 1423 unsigned short tag, ich; 1424 struct fwohci_dbch *dbch; 1425 int cycle_now, sec, cycle, cycle_match; 1426 u_int32_t stat; 1427 1428 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1429 ich = sc->it[dmach].xferq.flag & 0x3f; 1430 dbch = &sc->it[dmach]; 1431 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1432 dbch->xferq.queued = 0; 1433 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1434 dbch->ndesc = 3; 1435 fwohci_db_init(dbch); 1436 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1437 return ENOMEM; 1438 err = fwohci_tx_enable(sc, dbch); 1439 } 1440 if(err) 1441 return err; 1442 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1443 if (stat & OHCI_CNTL_DMA_ACTIVE) { 1444 if(dbch->xferq.stdma2 != NULL){ 1445 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1446 ((struct fwohcidb_tr *) 1447 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1448 |= OHCI_BRANCH_ALWAYS; 1449 ((struct fwohcidb_tr *) 1450 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1451 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1452 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1453 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1454 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1455 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1456 } else { 1457 device_printf(fc->dev, 1458 "fwohci_itxbuf_enable: queue underrun\n"); 1459 } 1460 return err; 1461 } 1462 if (firewire_debug) 1463 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1464 fw_tbuf_update(&sc->fc, dmach, 0); 1465 if(dbch->xferq.stdma == NULL){ 1466 return err; 1467 } 1468 if(dbch->xferq.stdma2 == NULL){ 1469 /* wait until 2 chunks buffered */ 1470 return err; 1471 } 1472 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1473 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1474 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1475 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1476 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1477 ((struct fwohcidb_tr *) 1478 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1479 |= OHCI_BRANCH_ALWAYS; 1480 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1481 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1482 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1483 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1484 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1485 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1486 OWRITE(sc, OHCI_ITCMD(dmach), 1487 vtophys(((struct fwohcidb_tr *) 1488 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1489#define CYCLE_OFFSET 1 1490 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1491#ifdef FWXFERQ_DV 1492 if(dbch->xferq.flag & FWXFERQ_DV){ 1493 struct fw_pkt *fp; 1494 struct fwohcidb_tr *db_tr; 1495 1496 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1497 fp = (struct fw_pkt *)db_tr->buf; 1498 dbch->xferq.dvoffset = CYCLE_OFFSET; 1499 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1500 } 1501#endif 1502 /* 2bit second + 13bit cycle */ 1503 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1504 cycle = cycle_now & 0x1fff; 1505 sec = cycle_now >> 13; 1506#define CYCLE_MOD 0x10 1507#define CYCLE_DELAY 8 /* min delay to start DMA */ 1508 cycle = cycle + CYCLE_DELAY; 1509 if (cycle >= 8000) { 1510 sec ++; 1511 cycle -= 8000; 1512 } 1513 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1514 if (cycle >= 8000) { 1515 sec ++; 1516 if (cycle == 8000) 1517 cycle = 0; 1518 else 1519 cycle = CYCLE_MOD; 1520 } 1521 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1522 /* Clear cycle match counter bits */ 1523 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1524 OWRITE(sc, OHCI_ITCTL(dmach), 1525 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1526 | OHCI_CNTL_DMA_RUN); 1527 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1528 if (firewire_debug) 1529 printf("cycle_match: 0x%04x->0x%04x\n", 1530 cycle_now, cycle_match); 1531 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1532 if (firewire_debug) 1533 printf("fwohci_itxbuf_enable: restart 0x%08x\n", stat); 1534 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1535 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1536 } 1537 return err; 1538} 1539 1540static int 1541fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1542{ 1543 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1544 int err = 0; 1545 unsigned short tag, ich; 1546 u_int32_t stat; 1547 1548 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1549 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1550 ich = sc->ir[dmach].xferq.flag & 0x3f; 1551 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1552 1553 sc->ir[dmach].xferq.queued = 0; 1554 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1555 sc->ir[dmach].xferq.bnchunk; 1556 sc->ir[dmach].dummy = 1557 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1558 M_DEVBUF, M_NOWAIT); 1559 if(sc->ir[dmach].dummy == NULL){ 1560 err = ENOMEM; 1561 return err; 1562 } 1563 sc->ir[dmach].ndesc = 2; 1564 fwohci_db_init(&sc->ir[dmach]); 1565 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1566 return ENOMEM; 1567 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1568 } 1569 if(err) 1570 return err; 1571 1572 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1573 if (stat & OHCI_CNTL_DMA_ACTIVE) { 1574 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1575 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1576 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1577 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1578 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1579 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1580 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1581 } 1582 } else if (!(stat & OHCI_CNTL_DMA_ACTIVE) 1583 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)) { 1584 if (firewire_debug) 1585 device_printf(sc->fc.dev, "IR DMA stat %x\n", stat); 1586 fw_rbuf_update(&sc->fc, dmach, 0); 1587 1588 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1589 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1590 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1591 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1592 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1593 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1594 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1595 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1596 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1597 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1598 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1599 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1600 }else{ 1601 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1602 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1603 } 1604 OWRITE(sc, OHCI_IRCMD(dmach), 1605 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1606 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1607 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1608 } 1609 return err; 1610} 1611 1612static int 1613fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1614{ 1615 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1616 int err = 0; 1617 1618 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1619 err = fwohci_irxpp_enable(fc, dmach); 1620 return err; 1621 }else{ 1622 err = fwohci_irxbuf_enable(fc, dmach); 1623 return err; 1624 } 1625} 1626 1627int 1628fwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1629{ 1630 u_int i; 1631 1632/* Now stopping all DMA channel */ 1633 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1634 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1635 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1636 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1637 1638 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1639 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1640 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1641 } 1642 1643/* FLUSH FIFO and reset Transmitter/Reciever */ 1644 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1645 1646/* Stop interrupt */ 1647 OWRITE(sc, FWOHCI_INTMASKCLR, 1648 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1649 | OHCI_INT_PHY_INT 1650 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1651 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1652 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1653 | OHCI_INT_PHY_BUS_R); 1654/* XXX Link down? Bus reset? */ 1655 return 0; 1656} 1657 1658int 1659fwohci_resume(struct fwohci_softc *sc, device_t dev) 1660{ 1661 int i; 1662 1663 fwohci_reset(sc, dev); 1664 /* XXX resume isochronus receive automatically. (how about TX?) */ 1665 for(i = 0; i < sc->fc.nisodma; i ++) { 1666 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1667 device_printf(sc->fc.dev, 1668 "resume iso receive ch: %d\n", i); 1669 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1670 sc->fc.irx_enable(&sc->fc, i); 1671 } 1672 } 1673 1674 bus_generic_resume(dev); 1675 sc->fc.ibr(&sc->fc); 1676 return 0; 1677} 1678 1679#define ACK_ALL 1680static void 1681fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1682{ 1683 u_int32_t irstat, itstat; 1684 u_int i; 1685 struct firewire_comm *fc = (struct firewire_comm *)sc; 1686 1687#ifdef OHCI_DEBUG 1688 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1689 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1690 stat & OHCI_INT_EN ? "DMA_EN ":"", 1691 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1692 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1693 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1694 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1695 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1696 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1697 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1698 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1699 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1700 stat & OHCI_INT_PHY_SID ? "SID ":"", 1701 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1702 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1703 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1704 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1705 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1706 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1707 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1708 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1709 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1710 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1711 stat, OREAD(sc, FWOHCI_INTMASK) 1712 ); 1713#endif 1714/* Bus reset */ 1715 if(stat & OHCI_INT_PHY_BUS_R ){ 1716 device_printf(fc->dev, "BUS reset\n"); 1717 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1718 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1719 1720 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1721 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1722 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1723 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1724 1725#if 0 1726 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1727 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1728 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1729 } 1730 1731#endif 1732 fw_busreset(fc); 1733 1734 /* XXX need to wait DMA to stop */ 1735#ifndef ACK_ALL 1736 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1737#endif 1738#if 1 1739 /* pending all pre-bus_reset packets */ 1740 fwohci_txd(sc, &sc->atrq); 1741 fwohci_txd(sc, &sc->atrs); 1742 fwohci_arcv(sc, &sc->arrs, -1); 1743 fwohci_arcv(sc, &sc->arrq, -1); 1744#endif 1745 1746 1747 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1748 /* XXX insecure ?? */ 1749 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1750 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1751 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1752 1753 } 1754 if((stat & OHCI_INT_DMA_IR )){ 1755#ifndef ACK_ALL 1756 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1757#endif 1758 irstat = OREAD(sc, OHCI_IR_STAT); 1759 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1760 for(i = 0; i < fc->nisodma ; i++){ 1761 struct fwohci_dbch *dbch; 1762 1763 if((irstat & (1 << i)) != 0){ 1764 dbch = &sc->ir[i]; 1765 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1766 device_printf(sc->fc.dev, 1767 "dma(%d) not active\n", i); 1768 continue; 1769 } 1770 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1771 fwohci_ircv(sc, dbch, count); 1772 } else { 1773 fwohci_rbuf_update(sc, i); 1774 } 1775 } 1776 } 1777 } 1778 if((stat & OHCI_INT_DMA_IT )){ 1779#ifndef ACK_ALL 1780 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1781#endif 1782 itstat = OREAD(sc, OHCI_IT_STAT); 1783 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1784 for(i = 0; i < fc->nisodma ; i++){ 1785 if((itstat & (1 << i)) != 0){ 1786 fwohci_tbuf_update(sc, i); 1787 } 1788 } 1789 } 1790 if((stat & OHCI_INT_DMA_PRRS )){ 1791#ifndef ACK_ALL 1792 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1793#endif 1794#if 0 1795 dump_dma(sc, ARRS_CH); 1796 dump_db(sc, ARRS_CH); 1797#endif 1798 fwohci_arcv(sc, &sc->arrs, count); 1799 } 1800 if((stat & OHCI_INT_DMA_PRRQ )){ 1801#ifndef ACK_ALL 1802 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1803#endif 1804#if 0 1805 dump_dma(sc, ARRQ_CH); 1806 dump_db(sc, ARRQ_CH); 1807#endif 1808 fwohci_arcv(sc, &sc->arrq, count); 1809 } 1810 if(stat & OHCI_INT_PHY_SID){ 1811 caddr_t buf; 1812 int plen; 1813 1814#ifndef ACK_ALL 1815 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1816#endif 1817/* 1818** Checking whether the node is root or not. If root, turn on 1819** cycle master. 1820*/ 1821 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1822 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1823 printf("Bus reset failure\n"); 1824 goto sidout; 1825 } 1826 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1827 printf("CYCLEMASTER mode\n"); 1828 OWRITE(sc, OHCI_LNKCTL, 1829 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1830 }else{ 1831 printf("non CYCLEMASTER mode\n"); 1832 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1833 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1834 } 1835 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1836 1837 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1838 if (plen < 4 || plen > OHCI_SIDSIZE) { 1839 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1840 goto sidout; 1841 } 1842 plen -= 4; /* chop control info */ 1843 buf = malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 1844 if(buf == NULL) goto sidout; 1845 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1846 buf, plen); 1847 fw_sidrcv(fc, buf, plen, 0); 1848 } 1849sidout: 1850 if((stat & OHCI_INT_DMA_ATRQ )){ 1851#ifndef ACK_ALL 1852 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1853#endif 1854 fwohci_txd(sc, &(sc->atrq)); 1855 } 1856 if((stat & OHCI_INT_DMA_ATRS )){ 1857#ifndef ACK_ALL 1858 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1859#endif 1860 fwohci_txd(sc, &(sc->atrs)); 1861 } 1862 if((stat & OHCI_INT_PW_ERR )){ 1863#ifndef ACK_ALL 1864 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1865#endif 1866 device_printf(fc->dev, "posted write error\n"); 1867 } 1868 if((stat & OHCI_INT_ERR )){ 1869#ifndef ACK_ALL 1870 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1871#endif 1872 device_printf(fc->dev, "unrecoverable error\n"); 1873 } 1874 if((stat & OHCI_INT_PHY_INT)) { 1875#ifndef ACK_ALL 1876 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1877#endif 1878 device_printf(fc->dev, "phy int\n"); 1879 } 1880 1881 return; 1882} 1883 1884void 1885fwohci_intr(void *arg) 1886{ 1887 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1888 u_int32_t stat; 1889 1890 if (!(sc->intmask & OHCI_INT_EN)) { 1891 /* polling mode */ 1892 return; 1893 } 1894 1895 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1896 if (stat == 0xffffffff) { 1897 device_printf(sc->fc.dev, 1898 "device physically ejected?\n"); 1899 return; 1900 } 1901#ifdef ACK_ALL 1902 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1903#endif 1904 fwohci_intr_body(sc, stat, -1); 1905 } 1906} 1907 1908static void 1909fwohci_poll(struct firewire_comm *fc, int quick, int count) 1910{ 1911 int s; 1912 u_int32_t stat; 1913 struct fwohci_softc *sc; 1914 1915 1916 sc = (struct fwohci_softc *)fc; 1917 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1918 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1919 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1920#if 0 1921 if (!quick) { 1922#else 1923 if (1) { 1924#endif 1925 stat = OREAD(sc, FWOHCI_INTSTAT); 1926 if (stat == 0) 1927 return; 1928 if (stat == 0xffffffff) { 1929 device_printf(sc->fc.dev, 1930 "device physically ejected?\n"); 1931 return; 1932 } 1933#ifdef ACK_ALL 1934 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1935#endif 1936 } 1937 s = splfw(); 1938 fwohci_intr_body(sc, stat, count); 1939 splx(s); 1940} 1941 1942static void 1943fwohci_set_intr(struct firewire_comm *fc, int enable) 1944{ 1945 struct fwohci_softc *sc; 1946 1947 sc = (struct fwohci_softc *)fc; 1948 if (bootverbose) 1949 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1950 if (enable) { 1951 sc->intmask |= OHCI_INT_EN; 1952 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1953 } else { 1954 sc->intmask &= ~OHCI_INT_EN; 1955 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1956 } 1957} 1958 1959static void 1960fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1961{ 1962 int stat; 1963 struct firewire_comm *fc = &sc->fc; 1964 struct fwohci_dbch *dbch; 1965 struct fwohcidb_tr *db_tr; 1966 1967 dbch = &sc->it[dmach]; 1968#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1969 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1970 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1971/* 1972 * Overwrite highest significant 4 bits timestamp information 1973 */ 1974 fp = (struct fw_pkt *)db_tr->buf; 1975 fp->mode.ld[2] &= htonl(0xffff0fff); 1976 fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1977 } 1978#endif 1979 /* 1980 * XXX interrupt could be missed. 1981 * We have to check more than one buffer/chunk 1982 */ 1983 if (firewire_debug && dbch->xferq.stdma2 != NULL) { 1984 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->end; 1985 stat = db_tr->db[2].db.desc.status; 1986 if (stat) 1987 device_printf(fc->dev, 1988 "stdma2 already done stat:0x%x\n", stat); 1989 } 1990 1991 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1992 switch(stat){ 1993 case FWOHCIEV_ACKCOMPL: 1994#ifdef FWXFERQ_DV 1995 if (dbch->xferq.flag & FWXFERQ_DV) { 1996 struct ciphdr *ciph; 1997 int timer, timestamp, cycl, diff; 1998 static int last_timer=0; 1999 struct fw_pkt *fp; 2000 2001 timer = (fc->cyctimer(fc) >> 12) & 0xffff; 2002 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 2003 fp = (struct fw_pkt *)db_tr->buf; 2004 ciph = (struct ciphdr *) &fp->mode.ld[1]; 2005 timestamp = db_tr->db[2].db.desc.count & 0xffff; 2006 cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 2007 diff = cycl - (timestamp & 0xf) - CYCLE_OFFSET; 2008 if (diff < 0) 2009 diff += 16; 2010 if (diff > 8) 2011 diff -= 16; 2012 if (firewire_debug || diff != 0) 2013 printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 2014 " cyc: 0x%x diff: %+1d\n", 2015 ciph->dbc, last_timer, timestamp, cycl, diff); 2016 last_timer = timer; 2017 /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 2018 } 2019#endif 2020 fw_tbuf_update(fc, dmach, 1); 2021 break; 2022 default: 2023 device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 2024 fw_tbuf_update(fc, dmach, 0); 2025 break; 2026 } 2027 fwohci_itxbuf_enable(fc, dmach); 2028} 2029 2030static void 2031fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2032{ 2033 struct firewire_comm *fc = &sc->fc; 2034 int stat; 2035 2036 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 2037 switch(stat){ 2038 case FWOHCIEV_ACKCOMPL: 2039 fw_rbuf_update(fc, dmach, 1); 2040 wakeup(fc->ir[dmach]); 2041 fwohci_irx_enable(fc, dmach); 2042 break; 2043 default: 2044 device_printf(fc->dev, "Isochronous receive err %02x\n", 2045 stat); 2046 break; 2047 } 2048} 2049 2050void 2051dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2052{ 2053 u_int32_t off, cntl, stat, cmd, match; 2054 2055 if(ch == 0){ 2056 off = OHCI_ATQOFF; 2057 }else if(ch == 1){ 2058 off = OHCI_ATSOFF; 2059 }else if(ch == 2){ 2060 off = OHCI_ARQOFF; 2061 }else if(ch == 3){ 2062 off = OHCI_ARSOFF; 2063 }else if(ch < IRX_CH){ 2064 off = OHCI_ITCTL(ch - ITX_CH); 2065 }else{ 2066 off = OHCI_IRCTL(ch - IRX_CH); 2067 } 2068 cntl = stat = OREAD(sc, off); 2069 cmd = OREAD(sc, off + 0xc); 2070 match = OREAD(sc, off + 0x10); 2071 2072 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2073 ch, 2074 cntl, 2075 stat, 2076 cmd, 2077 match); 2078 stat &= 0xffff ; 2079 if(stat & 0xff00){ 2080 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2081 ch, 2082 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2083 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2084 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2085 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2086 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2087 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2088 fwohcicode[stat & 0x1f], 2089 stat & 0x1f 2090 ); 2091 }else{ 2092 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2093 } 2094} 2095 2096void 2097dump_db(struct fwohci_softc *sc, u_int32_t ch) 2098{ 2099 struct fwohci_dbch *dbch; 2100 struct fwohcidb_tr *cp = NULL, *pp, *np; 2101 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2102 int idb, jdb; 2103 u_int32_t cmd, off; 2104 if(ch == 0){ 2105 off = OHCI_ATQOFF; 2106 dbch = &sc->atrq; 2107 }else if(ch == 1){ 2108 off = OHCI_ATSOFF; 2109 dbch = &sc->atrs; 2110 }else if(ch == 2){ 2111 off = OHCI_ARQOFF; 2112 dbch = &sc->arrq; 2113 }else if(ch == 3){ 2114 off = OHCI_ARSOFF; 2115 dbch = &sc->arrs; 2116 }else if(ch < IRX_CH){ 2117 off = OHCI_ITCTL(ch - ITX_CH); 2118 dbch = &sc->it[ch - ITX_CH]; 2119 }else { 2120 off = OHCI_IRCTL(ch - IRX_CH); 2121 dbch = &sc->ir[ch - IRX_CH]; 2122 } 2123 cmd = OREAD(sc, off + 0xc); 2124 2125 if( dbch->ndb == 0 ){ 2126 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2127 return; 2128 } 2129 pp = dbch->top; 2130 prev = pp->db; 2131 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2132 if(pp == NULL){ 2133 curr = NULL; 2134 goto outdb; 2135 } 2136 cp = STAILQ_NEXT(pp, link); 2137 if(cp == NULL){ 2138 curr = NULL; 2139 goto outdb; 2140 } 2141 np = STAILQ_NEXT(cp, link); 2142 if(cp == NULL) break; 2143 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2144 if((cmd & 0xfffffff0) 2145 == vtophys(&(cp->db[jdb]))){ 2146 curr = cp->db; 2147 if(np != NULL){ 2148 next = np->db; 2149 }else{ 2150 next = NULL; 2151 } 2152 goto outdb; 2153 } 2154 } 2155 pp = STAILQ_NEXT(pp, link); 2156 prev = pp->db; 2157 } 2158outdb: 2159 if( curr != NULL){ 2160 printf("Prev DB %d\n", ch); 2161 print_db(prev, ch, dbch->ndesc); 2162 printf("Current DB %d\n", ch); 2163 print_db(curr, ch, dbch->ndesc); 2164 printf("Next DB %d\n", ch); 2165 print_db(next, ch, dbch->ndesc); 2166 }else{ 2167 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2168 } 2169 return; 2170} 2171 2172void 2173print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2174{ 2175 fwohcireg_t stat; 2176 int i, key; 2177 2178 if(db == NULL){ 2179 printf("No Descriptor is found\n"); 2180 return; 2181 } 2182 2183 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2184 ch, 2185 "Current", 2186 "OP ", 2187 "KEY", 2188 "INT", 2189 "BR ", 2190 "len", 2191 "Addr", 2192 "Depend", 2193 "Stat", 2194 "Cnt"); 2195 for( i = 0 ; i <= max ; i ++){ 2196 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2197#if __FreeBSD_version >= 500000 2198 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2199#else 2200 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2201#endif 2202 vtophys(&db[i]), 2203 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2204 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2205 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2206 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2207 db[i].db.desc.cmd & 0xffff, 2208 db[i].db.desc.addr, 2209 db[i].db.desc.depend, 2210 db[i].db.desc.status, 2211 db[i].db.desc.count); 2212 stat = db[i].db.desc.status; 2213 if(stat & 0xff00){ 2214 printf(" %s%s%s%s%s%s %s(%x)\n", 2215 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2216 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2217 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2218 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2219 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2220 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2221 fwohcicode[stat & 0x1f], 2222 stat & 0x1f 2223 ); 2224 }else{ 2225 printf(" Nostat\n"); 2226 } 2227 if(key == OHCI_KEY_ST2 ){ 2228 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2229 db[i+1].db.immed[0], 2230 db[i+1].db.immed[1], 2231 db[i+1].db.immed[2], 2232 db[i+1].db.immed[3]); 2233 } 2234 if(key == OHCI_KEY_DEVICE){ 2235 return; 2236 } 2237 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2238 == OHCI_BRANCH_ALWAYS){ 2239 return; 2240 } 2241 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2242 == OHCI_OUTPUT_LAST){ 2243 return; 2244 } 2245 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2246 == OHCI_INPUT_LAST){ 2247 return; 2248 } 2249 if(key == OHCI_KEY_ST2 ){ 2250 i++; 2251 } 2252 } 2253 return; 2254} 2255 2256void 2257fwohci_ibr(struct firewire_comm *fc) 2258{ 2259 struct fwohci_softc *sc; 2260 u_int32_t fun; 2261 2262 sc = (struct fwohci_softc *)fc; 2263 2264 /* 2265 * Set root hold-off bit so that non cyclemaster capable node 2266 * shouldn't became the root node. 2267 */ 2268#if 1 2269 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2270 fun |= FW_PHY_IBR | FW_PHY_RHB; 2271 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2272#else /* Short bus reset */ 2273 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2274 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2275 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2276#endif 2277} 2278 2279void 2280fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2281{ 2282 struct fwohcidb_tr *db_tr, *fdb_tr; 2283 struct fwohci_dbch *dbch; 2284 struct fw_pkt *fp; 2285 volatile struct fwohci_txpkthdr *ohcifp; 2286 unsigned short chtag; 2287 int idb; 2288 2289 dbch = &sc->it[dmach]; 2290 chtag = sc->it[dmach].xferq.flag & 0xff; 2291 2292 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2293 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2294/* 2295device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2296*/ 2297 if(bulkxfer->flag != 0){ 2298 return; 2299 } 2300 bulkxfer->flag = 1; 2301 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2302 db_tr->db[0].db.desc.cmd 2303 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2304 fp = (struct fw_pkt *)db_tr->buf; 2305 ohcifp = (volatile struct fwohci_txpkthdr *) 2306 db_tr->db[1].db.immed; 2307 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2308 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2309 ohcifp->mode.stream.chtag = chtag; 2310 ohcifp->mode.stream.tcode = 0xa; 2311 ohcifp->mode.stream.spd = 4; 2312 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2313 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2314 2315 db_tr->db[2].db.desc.cmd 2316 = OHCI_OUTPUT_LAST 2317 | OHCI_UPDATE 2318 | OHCI_BRANCH_ALWAYS 2319 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2320 db_tr->db[2].db.desc.status = 0; 2321 db_tr->db[2].db.desc.count = 0; 2322 db_tr->db[0].db.desc.depend 2323 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2324 db_tr->db[dbch->ndesc - 1].db.desc.depend 2325 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2326 bulkxfer->end = (caddr_t)db_tr; 2327 db_tr = STAILQ_NEXT(db_tr, link); 2328 } 2329 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2330 db_tr->db[0].db.desc.depend &= ~0xf; 2331 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2332#if 0 2333/**/ 2334 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2335 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2336/**/ 2337#endif 2338 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2339 /* OHCI 1.1 and above */ 2340 db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2341 2342 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2343 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2344/* 2345device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2346*/ 2347 return; 2348} 2349 2350static int 2351fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2352 int mode, void *buf) 2353{ 2354 volatile struct fwohcidb *db = db_tr->db; 2355 int err = 0; 2356 if(buf == 0){ 2357 err = EINVAL; 2358 return err; 2359 } 2360 db_tr->buf = buf; 2361 db_tr->dbcnt = 3; 2362 db_tr->dummy = NULL; 2363 2364 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2365 2366 db[2].db.desc.depend = 0; 2367 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2368 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2369 2370 db[0].db.desc.status = 0; 2371 db[0].db.desc.count = 0; 2372 2373 db[2].db.desc.status = 0; 2374 db[2].db.desc.count = 0; 2375 if( mode & FWXFERQ_STREAM ){ 2376 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2377 if(mode & FWXFERQ_PACKET ){ 2378 db[2].db.desc.cmd 2379 |= OHCI_INTERRUPT_ALWAYS; 2380 } 2381 } 2382 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2383 return 1; 2384} 2385 2386int 2387fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2388 void *buf, void *dummy) 2389{ 2390 volatile struct fwohcidb *db = db_tr->db; 2391 int i; 2392 void *dbuf[2]; 2393 int dsiz[2]; 2394 2395 if(buf == 0){ 2396 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2397 if(buf == NULL) return 0; 2398 db_tr->buf = buf; 2399 db_tr->dbcnt = 1; 2400 db_tr->dummy = NULL; 2401 dsiz[0] = size; 2402 dbuf[0] = buf; 2403 }else if(dummy == NULL){ 2404 db_tr->buf = buf; 2405 db_tr->dbcnt = 1; 2406 db_tr->dummy = NULL; 2407 dsiz[0] = size; 2408 dbuf[0] = buf; 2409 }else{ 2410 db_tr->buf = buf; 2411 db_tr->dbcnt = 2; 2412 db_tr->dummy = dummy; 2413 dsiz[0] = sizeof(u_int32_t); 2414 dsiz[1] = size; 2415 dbuf[0] = dummy; 2416 dbuf[1] = buf; 2417 } 2418 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2419 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2420 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2421 if( mode & FWXFERQ_STREAM ){ 2422 db[i].db.desc.cmd |= OHCI_UPDATE; 2423 } 2424 db[i].db.desc.status = 0; 2425 db[i].db.desc.count = dsiz[i]; 2426 } 2427 if( mode & FWXFERQ_STREAM ){ 2428 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2429 if(mode & FWXFERQ_PACKET ){ 2430 db[db_tr->dbcnt - 1].db.desc.cmd 2431 |= OHCI_INTERRUPT_ALWAYS; 2432 } 2433 } 2434 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2435 return 1; 2436} 2437 2438static void 2439fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2440{ 2441 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2442 struct firewire_comm *fc = (struct firewire_comm *)sc; 2443 int z = 1; 2444 struct fw_pkt *fp; 2445 u_int8_t *ld; 2446 u_int32_t off = NULL; 2447 u_int32_t stat; 2448 u_int32_t *qld; 2449 u_int32_t reg; 2450 u_int spd; 2451 u_int dmach; 2452 int len, i, plen; 2453 caddr_t buf; 2454 2455 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2456 if( &sc->ir[dmach] == dbch){ 2457 off = OHCI_IROFF(dmach); 2458 break; 2459 } 2460 } 2461 if(off == NULL){ 2462 return; 2463 } 2464 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2465 fwohci_irx_disable(&sc->fc, dmach); 2466 return; 2467 } 2468 2469 odb_tr = NULL; 2470 db_tr = dbch->top; 2471 i = 0; 2472 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2473 if (count >= 0 && count-- == 0) 2474 break; 2475 ld = (u_int8_t *)db_tr->buf; 2476 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2477 /* skip timeStamp */ 2478 ld += sizeof(struct fwohci_trailer); 2479 } 2480 qld = (u_int32_t *)ld; 2481 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2482/* 2483{ 2484device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2485 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2486} 2487*/ 2488 fp=(struct fw_pkt *)ld; 2489 qld[0] = htonl(qld[0]); 2490 plen = sizeof(struct fw_isohdr) 2491 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2492 ld += plen; 2493 len -= plen; 2494 buf = db_tr->buf; 2495 db_tr->buf = NULL; 2496 stat = reg & 0x1f; 2497 spd = reg & 0x3; 2498 switch(stat){ 2499 case FWOHCIEV_ACKCOMPL: 2500 case FWOHCIEV_ACKPEND: 2501 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2502 break; 2503 default: 2504 free(buf, M_DEVBUF); 2505 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2506 break; 2507 } 2508 i++; 2509 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2510 dbch->xferq.flag, 0, NULL); 2511 db_tr->db[0].db.desc.depend &= ~0xf; 2512 if(dbch->pdb_tr != NULL){ 2513 dbch->pdb_tr->db[0].db.desc.depend |= z; 2514 } else { 2515 /* XXX should be rewritten in better way */ 2516 dbch->bottom->db[0].db.desc.depend |= z; 2517 } 2518 dbch->pdb_tr = db_tr; 2519 db_tr = STAILQ_NEXT(db_tr, link); 2520 } 2521 dbch->top = db_tr; 2522 reg = OREAD(sc, OHCI_DMACTL(off)); 2523 if (reg & OHCI_CNTL_DMA_ACTIVE) 2524 return; 2525 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2526 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2527 dbch->top = db_tr; 2528 fwohci_irx_enable(fc, dmach); 2529} 2530 2531#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2532static int 2533fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2534{ 2535 int i; 2536 2537 for( i = 4; i < hlen ; i+=4){ 2538 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2539 } 2540 2541 switch(fp->mode.common.tcode){ 2542 case FWTCODE_RREQQ: 2543 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2544 case FWTCODE_WRES: 2545 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2546 case FWTCODE_WREQQ: 2547 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2548 case FWTCODE_RREQB: 2549 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2550 case FWTCODE_RRESQ: 2551 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2552 case FWTCODE_WREQB: 2553 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2554 + sizeof(u_int32_t); 2555 case FWTCODE_LREQ: 2556 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2557 + sizeof(u_int32_t); 2558 case FWTCODE_RRESB: 2559 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2560 + sizeof(u_int32_t); 2561 case FWTCODE_LRES: 2562 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2563 + sizeof(u_int32_t); 2564 case FWOHCITCODE_PHY: 2565 return 16; 2566 } 2567 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2568 return 0; 2569} 2570 2571static void 2572fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2573{ 2574 struct fwohcidb_tr *db_tr; 2575 int z = 1; 2576 struct fw_pkt *fp; 2577 u_int8_t *ld; 2578 u_int32_t stat, off; 2579 u_int spd; 2580 int len, plen, hlen, pcnt, poff = 0, rlen; 2581 int s; 2582 caddr_t buf; 2583 int resCount; 2584 2585 if(&sc->arrq == dbch){ 2586 off = OHCI_ARQOFF; 2587 }else if(&sc->arrs == dbch){ 2588 off = OHCI_ARSOFF; 2589 }else{ 2590 return; 2591 } 2592 2593 s = splfw(); 2594 db_tr = dbch->top; 2595 pcnt = 0; 2596 /* XXX we cannot handle a packet which lies in more than two buf */ 2597 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2598 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2599 resCount = db_tr->db[0].db.desc.count; 2600 len = dbch->xferq.psize - resCount 2601 - dbch->buf_offset; 2602 while (len > 0 ) { 2603 if (count >= 0 && count-- == 0) 2604 goto out; 2605 if(dbch->frag.buf != NULL){ 2606 buf = dbch->frag.buf; 2607 if (dbch->frag.plen < 0) { 2608 /* incomplete header */ 2609 int hlen; 2610 2611 hlen = - dbch->frag.plen; 2612 rlen = hlen - dbch->frag.len; 2613 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2614 ld += rlen; 2615 len -= rlen; 2616 dbch->frag.len += rlen; 2617#if 0 2618 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2619#endif 2620 fp=(struct fw_pkt *)dbch->frag.buf; 2621 dbch->frag.plen 2622 = fwohci_get_plen(sc, fp, hlen); 2623 if (dbch->frag.plen == 0) 2624 goto out; 2625 } 2626 rlen = dbch->frag.plen - dbch->frag.len; 2627#if 0 2628 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2629#endif 2630 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2631 rlen); 2632 ld += rlen; 2633 len -= rlen; 2634 plen = dbch->frag.plen; 2635 dbch->frag.buf = NULL; 2636 dbch->frag.plen = 0; 2637 dbch->frag.len = 0; 2638 poff = 0; 2639 }else{ 2640 fp=(struct fw_pkt *)ld; 2641 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2642 switch(fp->mode.common.tcode){ 2643 case FWTCODE_RREQQ: 2644 case FWTCODE_WRES: 2645 case FWTCODE_WREQQ: 2646 case FWTCODE_RRESQ: 2647 case FWOHCITCODE_PHY: 2648 hlen = 12; 2649 break; 2650 case FWTCODE_RREQB: 2651 case FWTCODE_WREQB: 2652 case FWTCODE_LREQ: 2653 case FWTCODE_RRESB: 2654 case FWTCODE_LRES: 2655 hlen = 16; 2656 break; 2657 default: 2658 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2659 goto out; 2660 } 2661 if (len >= hlen) { 2662 plen = fwohci_get_plen(sc, fp, hlen); 2663 if (plen == 0) 2664 goto out; 2665 plen = (plen + 3) & ~3; 2666 len -= plen; 2667 } else { 2668 plen = -hlen; 2669 len -= hlen; 2670 } 2671 if(resCount > 0 || len > 0){ 2672 buf = malloc( dbch->xferq.psize, 2673 M_DEVBUF, M_NOWAIT); 2674 if(buf == NULL){ 2675 printf("cannot malloc!\n"); 2676 free(db_tr->buf, M_DEVBUF); 2677 goto out; 2678 } 2679 bcopy(ld, buf, plen); 2680 poff = 0; 2681 dbch->frag.buf = NULL; 2682 dbch->frag.plen = 0; 2683 dbch->frag.len = 0; 2684 }else if(len < 0){ 2685 dbch->frag.buf = db_tr->buf; 2686 if (plen < 0) { 2687#if 0 2688 printf("plen < 0:" 2689 "hlen: %d len: %d\n", 2690 hlen, len); 2691#endif 2692 dbch->frag.len = hlen + len; 2693 dbch->frag.plen = -hlen; 2694 } else { 2695 dbch->frag.len = plen + len; 2696 dbch->frag.plen = plen; 2697 } 2698 bcopy(ld, db_tr->buf, dbch->frag.len); 2699 buf = NULL; 2700 }else{ 2701 buf = db_tr->buf; 2702 poff = ld - (u_int8_t *)buf; 2703 dbch->frag.buf = NULL; 2704 dbch->frag.plen = 0; 2705 dbch->frag.len = 0; 2706 } 2707 ld += plen; 2708 } 2709 if( buf != NULL){ 2710/* DMA result-code will be written at the tail of packet */ 2711 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2712 spd = (stat >> 5) & 0x3; 2713 stat &= 0x1f; 2714 switch(stat){ 2715 case FWOHCIEV_ACKPEND: 2716#if 0 2717 printf("fwohci_arcv: ack pending..\n"); 2718#endif 2719 /* fall through */ 2720 case FWOHCIEV_ACKCOMPL: 2721 if( poff != 0 ) 2722 bcopy(buf+poff, buf, plen - 4); 2723 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2724 break; 2725 case FWOHCIEV_BUSRST: 2726 free(buf, M_DEVBUF); 2727 if (sc->fc.status != FWBUSRESET) 2728 printf("got BUSRST packet!?\n"); 2729 break; 2730 default: 2731 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2732#if 0 /* XXX */ 2733 goto out; 2734#endif 2735 break; 2736 } 2737 } 2738 pcnt ++; 2739 }; 2740out: 2741 if (resCount == 0) { 2742 /* done on this buffer */ 2743 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2744 dbch->xferq.flag, 0, NULL); 2745 dbch->bottom->db[0].db.desc.depend |= z; 2746 dbch->bottom = db_tr; 2747 db_tr = STAILQ_NEXT(db_tr, link); 2748 dbch->top = db_tr; 2749 dbch->buf_offset = 0; 2750 } else { 2751 dbch->buf_offset = dbch->xferq.psize - resCount; 2752 break; 2753 } 2754 /* XXX make sure DMA is not dead */ 2755 } 2756#if 0 2757 if (pcnt < 1) 2758 printf("fwohci_arcv: no packets\n"); 2759#endif 2760 splx(s); 2761} 2762