fwohci.c revision 109736
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109736 2003-01-23 13:34:40Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirereg.h> 73#include <dev/firewire/fwohcireg.h> 74#include <dev/firewire/fwohcivar.h> 75#include <dev/firewire/firewire_phy.h> 76 77#include <dev/firewire/iec68113.h> 78 79#undef OHCI_DEBUG 80 81static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82 "STOR","LOAD","NOP ","STOP",}; 83static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84 "UNDEF","REG","SYS","DEV"}; 85char fwohcicode[32][0x20]={ 86 "No stat","Undef","long","miss Ack err", 87 "underrun","overrun","desc err", "data read err", 88 "data write err","bus reset","timeout","tcode err", 89 "Undef","Undef","unknown event","flushed", 90 "Undef","ack complete","ack pend","Undef", 91 "ack busy_X","ack busy_A","ack busy_B","Undef", 92 "Undef","Undef","Undef","ack tardy", 93 "Undef","ack data_err","ack type_err",""}; 94#define MAX_SPEED 2 95extern char linkspeed[MAX_SPEED+1][0x10]; 96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr __P((struct firewire_comm *)); 126static void fwohci_db_init __P((struct fwohci_dbch *)); 127static void fwohci_db_free __P((struct fwohci_dbch *)); 128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_start_atq __P((struct firewire_comm *)); 132static void fwohci_start_ats __P((struct firewire_comm *)); 133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144static int fwohci_irx_disable __P((struct firewire_comm *, int)); 145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_poll __P((struct firewire_comm *, int, int)); 150static void fwohci_set_intr __P((struct firewire_comm *, int)); 151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160 161/* 162 * memory allocated for DMA programs 163 */ 164#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166/* #define NDB 1024 */ 167#define NDB FWMAXQUEUE 168#define NDVDB (DVBUF * NDB) 169 170#define OHCI_VERSION 0x00 171#define OHCI_CROMHDR 0x18 172#define OHCI_BUS_OPT 0x20 173#define OHCI_BUSIRMC (1 << 31) 174#define OHCI_BUSCMC (1 << 30) 175#define OHCI_BUSISC (1 << 29) 176#define OHCI_BUSBMC (1 << 28) 177#define OHCI_BUSPMC (1 << 27) 178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181#define OHCI_EUID_HI 0x24 182#define OHCI_EUID_LO 0x28 183 184#define OHCI_CROMPTR 0x34 185#define OHCI_HCCCTL 0x50 186#define OHCI_HCCCTLCLR 0x54 187#define OHCI_AREQHI 0x100 188#define OHCI_AREQHICLR 0x104 189#define OHCI_AREQLO 0x108 190#define OHCI_AREQLOCLR 0x10c 191#define OHCI_PREQHI 0x110 192#define OHCI_PREQHICLR 0x114 193#define OHCI_PREQLO 0x118 194#define OHCI_PREQLOCLR 0x11c 195#define OHCI_PREQUPPER 0x120 196 197#define OHCI_SID_BUF 0x64 198#define OHCI_SID_CNT 0x68 199#define OHCI_SID_CNT_MASK 0xffc 200 201#define OHCI_IT_STAT 0x90 202#define OHCI_IT_STATCLR 0x94 203#define OHCI_IT_MASK 0x98 204#define OHCI_IT_MASKCLR 0x9c 205 206#define OHCI_IR_STAT 0xa0 207#define OHCI_IR_STATCLR 0xa4 208#define OHCI_IR_MASK 0xa8 209#define OHCI_IR_MASKCLR 0xac 210 211#define OHCI_LNKCTL 0xe0 212#define OHCI_LNKCTLCLR 0xe4 213 214#define OHCI_PHYACCESS 0xec 215#define OHCI_CYCLETIMER 0xf0 216 217#define OHCI_DMACTL(off) (off) 218#define OHCI_DMACTLCLR(off) (off + 4) 219#define OHCI_DMACMD(off) (off + 0xc) 220#define OHCI_DMAMATCH(off) (off + 0x10) 221 222#define OHCI_ATQOFF 0x180 223#define OHCI_ATQCTL OHCI_ATQOFF 224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228#define OHCI_ATSOFF 0x1a0 229#define OHCI_ATSCTL OHCI_ATSOFF 230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234#define OHCI_ARQOFF 0x1c0 235#define OHCI_ARQCTL OHCI_ARQOFF 236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240#define OHCI_ARSOFF 0x1e0 241#define OHCI_ARSCTL OHCI_ARSOFF 242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257d_ioctl_t fwohci_ioctl; 258 259/* 260 * Communication with PHY device 261 */ 262static u_int32_t 263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264{ 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275} 276 277static u_int32_t 278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279{ 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284#define OHCI_CSR_DATA 0x0c 285#define OHCI_CSR_COMP 0x10 286#define OHCI_CSR_CONT 0x14 287#define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(10); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302} 303 304static u_int32_t 305fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306{ 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311#define MAX_RETRY 100 312again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(100); 321 } 322 if(i >= MAX_RETRY) { 323 if (bootverbose) 324 device_printf(sc->fc.dev, "phy read failed(1).\n"); 325 if (++retry < MAX_RETRY) { 326 DELAY(100); 327 goto again; 328 } 329 } 330 /* Make sure that SCLK is started */ 331 stat = OREAD(sc, FWOHCI_INTSTAT); 332 if ((stat & OHCI_INT_REG_FAIL) != 0 || 333 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 334 if (bootverbose) 335 device_printf(sc->fc.dev, "phy read failed(2).\n"); 336 if (++retry < MAX_RETRY) { 337 DELAY(100); 338 goto again; 339 } 340 } 341 if (bootverbose || retry >= MAX_RETRY) 342 device_printf(sc->fc.dev, 343 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 344#undef MAX_RETRY 345 return((fun >> PHYDEV_RDDATA )& 0xff); 346} 347/* Device specific ioctl. */ 348int 349fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350{ 351 struct firewire_softc *sc; 352 struct fwohci_softc *fc; 353 int unit = DEV2UNIT(dev); 354 int err = 0; 355 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356 u_int32_t *dmach = (u_int32_t *) data; 357 358 sc = devclass_get_softc(firewire_devclass, unit); 359 if(sc == NULL){ 360 return(EINVAL); 361 } 362 fc = (struct fwohci_softc *)sc->fc; 363 364 if (!data) 365 return(EINVAL); 366 367 switch (cmd) { 368 case FWOHCI_WRREG: 369#define OHCI_MAX_REG 0x800 370 if(reg->addr <= OHCI_MAX_REG){ 371 OWRITE(fc, reg->addr, reg->data); 372 reg->data = OREAD(fc, reg->addr); 373 }else{ 374 err = EINVAL; 375 } 376 break; 377 case FWOHCI_RDREG: 378 if(reg->addr <= OHCI_MAX_REG){ 379 reg->data = OREAD(fc, reg->addr); 380 }else{ 381 err = EINVAL; 382 } 383 break; 384/* Read DMA descriptors for debug */ 385 case DUMPDMA: 386 if(*dmach <= OHCI_MAX_DMA_CH ){ 387 dump_dma(fc, *dmach); 388 dump_db(fc, *dmach); 389 }else{ 390 err = EINVAL; 391 } 392 break; 393 default: 394 break; 395 } 396 return err; 397} 398 399static int 400fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 401{ 402 u_int32_t reg, reg2; 403 int e1394a = 1; 404/* 405 * probe PHY parameters 406 * 0. to prove PHY version, whether compliance of 1394a. 407 * 1. to probe maximum speed supported by the PHY and 408 * number of port supported by core-logic. 409 * It is not actually available port on your PC . 410 */ 411 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 412#if 0 413 /* XXX wait for SCLK. */ 414 DELAY(100000); 415#endif 416 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417 418 if((reg >> 5) != 7 ){ 419 sc->fc.mode &= ~FWPHYASYST; 420 sc->fc.nport = reg & FW_PHY_NP; 421 sc->fc.speed = reg & FW_PHY_SPD >> 6; 422 if (sc->fc.speed > MAX_SPEED) { 423 device_printf(dev, "invalid speed %d (fixed to %d).\n", 424 sc->fc.speed, MAX_SPEED); 425 sc->fc.speed = MAX_SPEED; 426 } 427 device_printf(dev, 428 "Phy 1394 only %s, %d ports.\n", 429 linkspeed[sc->fc.speed], sc->fc.nport); 430 }else{ 431 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432 sc->fc.mode |= FWPHYASYST; 433 sc->fc.nport = reg & FW_PHY_NP; 434 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435 if (sc->fc.speed > MAX_SPEED) { 436 device_printf(dev, "invalid speed %d (fixed to %d).\n", 437 sc->fc.speed, MAX_SPEED); 438 sc->fc.speed = MAX_SPEED; 439 } 440 device_printf(dev, 441 "Phy 1394a available %s, %d ports.\n", 442 linkspeed[sc->fc.speed], sc->fc.nport); 443 444 /* check programPhyEnable */ 445 reg2 = fwphy_rddata(sc, 5); 446#if 0 447 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448#else /* XXX force to enable 1394a */ 449 if (e1394a) { 450#endif 451 if (bootverbose) 452 device_printf(dev, 453 "Enable 1394a Enhancements\n"); 454 /* enable EAA EMC */ 455 reg2 |= 0x03; 456 /* set aPhyEnhanceEnable */ 457 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459 } else { 460 /* for safe */ 461 reg2 &= ~0x83; 462 } 463 reg2 = fwphy_wrdata(sc, 5, reg2); 464 } 465 466 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467 if((reg >> 5) == 7 ){ 468 reg = fwphy_rddata(sc, 4); 469 reg |= 1 << 6; 470 fwphy_wrdata(sc, 4, reg); 471 reg = fwphy_rddata(sc, 4); 472 } 473 return 0; 474} 475 476 477void 478fwohci_reset(struct fwohci_softc *sc, device_t dev) 479{ 480 int i, max_rec, speed; 481 u_int32_t reg, reg2; 482 struct fwohcidb_tr *db_tr; 483 484 /* Disable interrupt */ 485 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486 487 /* Now stopping all DMA channel */ 488 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492 493 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 } 498 499 /* FLUSH FIFO and reset Transmitter/Reciever */ 500 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501 if (bootverbose) 502 device_printf(dev, "resetting OHCI..."); 503 i = 0; 504 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505 if (i++ > 100) break; 506 DELAY(1000); 507 } 508 if (bootverbose) 509 printf("done (loop=%d)\n", i); 510 511 /* Probe phy */ 512 fwohci_probe_phy(sc, dev); 513 514 /* Probe link */ 515 reg = OREAD(sc, OHCI_BUS_OPT); 516 reg2 = reg | OHCI_BUSFNC; 517 max_rec = (reg & 0x0000f000) >> 12; 518 speed = (reg & 0x00000007); 519 device_printf(dev, "Link %s, max_rec %d bytes.\n", 520 linkspeed[speed], MAXREC(max_rec)); 521 /* XXX fix max_rec */ 522 sc->fc.maxrec = sc->fc.speed + 8; 523 if (max_rec != sc->fc.maxrec) { 524 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525 device_printf(dev, "max_rec %d -> %d\n", 526 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527 } 528 if (bootverbose) 529 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530 OWRITE(sc, OHCI_BUS_OPT, reg2); 531 532 /* Initialize registers */ 533 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 535 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 538 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539 fw_busreset(&sc->fc); 540 541 /* Enable link */ 542 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543 544 /* Force to start async RX DMA */ 545 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547 fwohci_rx_enable(sc, &sc->arrq); 548 fwohci_rx_enable(sc, &sc->arrs); 549 550 /* Initialize async TX */ 551 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 /* AT Retries */ 554 OWRITE(sc, FWOHCI_RETRY, 555 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559 db_tr->xfer = NULL; 560 } 561 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563 db_tr->xfer = NULL; 564 } 565 566 567 /* Enable interrupt */ 568 OWRITE(sc, FWOHCI_INTMASK, 569 OHCI_INT_ERR | OHCI_INT_PHY_SID 570 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573 fwohci_set_intr(&sc->fc, 1); 574 575} 576 577int 578fwohci_init(struct fwohci_softc *sc, device_t dev) 579{ 580 int i; 581 u_int32_t reg; 582 583 reg = OREAD(sc, OHCI_VERSION); 584 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586 587/* XXX: Available Isochrounous DMA channel probe */ 588 for( i = 0 ; i < 0x20 ; i ++ ){ 589 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 590 reg = OREAD(sc, OHCI_IRCTL(i)); 591 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 592 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 593 reg = OREAD(sc, OHCI_ITCTL(i)); 594 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 595 } 596 sc->fc.nisodma = i; 597 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 598 599 sc->fc.arq = &sc->arrq.xferq; 600 sc->fc.ars = &sc->arrs.xferq; 601 sc->fc.atq = &sc->atrq.xferq; 602 sc->fc.ats = &sc->atrs.xferq; 603 604 sc->arrq.xferq.start = NULL; 605 sc->arrs.xferq.start = NULL; 606 sc->atrq.xferq.start = fwohci_start_atq; 607 sc->atrs.xferq.start = fwohci_start_ats; 608 609 sc->arrq.xferq.drain = NULL; 610 sc->arrs.xferq.drain = NULL; 611 sc->atrq.xferq.drain = fwohci_drain_atq; 612 sc->atrs.xferq.drain = fwohci_drain_ats; 613 614 sc->arrq.ndesc = 1; 615 sc->arrs.ndesc = 1; 616 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 617 sc->atrs.ndesc = 6 / 2; 618 619 sc->arrq.ndb = NDB; 620 sc->arrs.ndb = NDB / 2; 621 sc->atrq.ndb = NDB; 622 sc->atrs.ndb = NDB / 2; 623 624 sc->arrq.dummy = NULL; 625 sc->arrs.dummy = NULL; 626 sc->atrq.dummy = NULL; 627 sc->atrs.dummy = NULL; 628 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 629 sc->fc.it[i] = &sc->it[i].xferq; 630 sc->fc.ir[i] = &sc->ir[i].xferq; 631 sc->it[i].ndb = 0; 632 sc->ir[i].ndb = 0; 633 } 634 635 sc->fc.tcode = tinfo; 636 637 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT); 638 639 if(sc->cromptr == NULL){ 640 device_printf(dev, "cromptr alloc failed."); 641 return ENOMEM; 642 } 643 sc->fc.dev = dev; 644 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 645 646 sc->fc.config_rom[1] = 0x31333934; 647 sc->fc.config_rom[2] = 0xf000a002; 648 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 649 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 650 sc->fc.config_rom[5] = 0; 651 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 652 653 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 654 655 656/* SID recieve buffer must allign 2^11 */ 657#define OHCI_SIDSIZE (1 << 11) 658 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 659 if (sc->fc.sid_buf == NULL) { 660 device_printf(dev, "sid_buf alloc failed.\n"); 661 return ENOMEM; 662 } 663 if (((u_int32_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 664 device_printf(dev, "sid_buf(%p) not aligned.\n", 665 sc->fc.sid_buf); 666 return ENOMEM; 667 } 668 669 fwohci_db_init(&sc->arrq); 670 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 671 return ENOMEM; 672 673 fwohci_db_init(&sc->arrs); 674 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 675 return ENOMEM; 676 677 fwohci_db_init(&sc->atrq); 678 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 679 return ENOMEM; 680 681 fwohci_db_init(&sc->atrs); 682 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 683 return ENOMEM; 684 685 reg = OREAD(sc, FWOHCIGUID_H); 686 for( i = 0 ; i < 4 ; i ++){ 687 sc->fc.eui[3 - i] = reg & 0xff; 688 reg = reg >> 8; 689 } 690 reg = OREAD(sc, FWOHCIGUID_L); 691 for( i = 0 ; i < 4 ; i ++){ 692 sc->fc.eui[7 - i] = reg & 0xff; 693 reg = reg >> 8; 694 } 695 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 696 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 697 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 698 sc->fc.ioctl = fwohci_ioctl; 699 sc->fc.cyctimer = fwohci_cyctimer; 700 sc->fc.set_bmr = fwohci_set_bus_manager; 701 sc->fc.ibr = fwohci_ibr; 702 sc->fc.irx_enable = fwohci_irx_enable; 703 sc->fc.irx_disable = fwohci_irx_disable; 704 705 sc->fc.itx_enable = fwohci_itxbuf_enable; 706 sc->fc.itx_disable = fwohci_itx_disable; 707 sc->fc.irx_post = fwohci_irx_post; 708 sc->fc.itx_post = NULL; 709 sc->fc.timeout = fwohci_timeout; 710 sc->fc.poll = fwohci_poll; 711 sc->fc.set_intr = fwohci_set_intr; 712 713 fw_init(&sc->fc); 714 fwohci_reset(sc, dev); 715 716 return 0; 717} 718 719void 720fwohci_timeout(void *arg) 721{ 722 struct fwohci_softc *sc; 723 724 sc = (struct fwohci_softc *)arg; 725 sc->fc.timeouthandle = timeout(fwohci_timeout, 726 (void *)sc, FW_XFERTIMEOUT * hz * 10); 727} 728 729u_int32_t 730fwohci_cyctimer(struct firewire_comm *fc) 731{ 732 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 733 return(OREAD(sc, OHCI_CYCLETIMER)); 734} 735 736int 737fwohci_detach(struct fwohci_softc *sc, device_t dev) 738{ 739 int i; 740 741 if (sc->fc.sid_buf != NULL) 742 free((void *)(uintptr_t)sc->fc.sid_buf, M_DEVBUF); 743 if (sc->cromptr != NULL) 744 free((void *)sc->cromptr, M_DEVBUF); 745 746 fwohci_db_free(&sc->arrq); 747 fwohci_db_free(&sc->arrs); 748 749 fwohci_db_free(&sc->atrq); 750 fwohci_db_free(&sc->atrs); 751 752 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 753 fwohci_db_free(&sc->it[i]); 754 fwohci_db_free(&sc->ir[i]); 755 } 756 757 return 0; 758} 759 760#define LAST_DB(dbtr, db) do { \ 761 struct fwohcidb_tr *_dbtr = (dbtr); \ 762 int _cnt = _dbtr->dbcnt; \ 763 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 764} while (0) 765 766static void 767fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 768{ 769 int i, s; 770 int tcode, hdr_len, hdr_off, len; 771 int fsegment = -1; 772 u_int32_t off; 773 struct fw_xfer *xfer; 774 struct fw_pkt *fp; 775 volatile struct fwohci_txpkthdr *ohcifp; 776 struct fwohcidb_tr *db_tr; 777 volatile struct fwohcidb *db; 778 struct mbuf *m; 779 struct tcode_info *info; 780 static int maxdesc=0; 781 782 if(&sc->atrq == dbch){ 783 off = OHCI_ATQOFF; 784 }else if(&sc->atrs == dbch){ 785 off = OHCI_ATSOFF; 786 }else{ 787 return; 788 } 789 790 if (dbch->flags & FWOHCI_DBCH_FULL) 791 return; 792 793 s = splfw(); 794 db_tr = dbch->top; 795txloop: 796 xfer = STAILQ_FIRST(&dbch->xferq.q); 797 if(xfer == NULL){ 798 goto kick; 799 } 800 if(dbch->xferq.queued == 0 ){ 801 device_printf(sc->fc.dev, "TX queue empty\n"); 802 } 803 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 804 db_tr->xfer = xfer; 805 xfer->state = FWXF_START; 806 dbch->xferq.packets++; 807 808 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 809 tcode = fp->mode.common.tcode; 810 811 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 812 info = &tinfo[tcode]; 813 hdr_len = hdr_off = info->hdr_len; 814 /* fw_asyreq must pass valid send.len */ 815 len = xfer->send.len; 816 for( i = 0 ; i < hdr_off ; i+= 4){ 817 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 818 } 819 ohcifp->mode.common.spd = xfer->spd; 820 if (tcode == FWTCODE_STREAM ){ 821 hdr_len = 8; 822 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 823 } else if (tcode == FWTCODE_PHY) { 824 hdr_len = 12; 825 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 826 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 827 ohcifp->mode.common.spd = 0; 828 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 829 } else { 830 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 831 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 832 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 833 } 834 db = &db_tr->db[0]; 835 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 836 db->db.desc.status = 0; 837/* Specify bound timer of asy. responce */ 838 if(&sc->atrs == dbch){ 839 db->db.desc.count 840 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 841 } 842 843 db_tr->dbcnt = 2; 844 db = &db_tr->db[db_tr->dbcnt]; 845 if(len > hdr_off){ 846 if (xfer->mbuf == NULL) { 847 db->db.desc.addr 848 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 849 db->db.desc.cmd 850 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 851 db->db.desc.status = 0; 852 853 db_tr->dbcnt++; 854 } else { 855 /* XXX we assume mbuf chain is shorter than ndesc */ 856 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 857 if (m->m_len == 0) 858 /* unrecoverable error could ocurre. */ 859 continue; 860 if (db_tr->dbcnt >= dbch->ndesc) { 861 device_printf(sc->fc.dev, 862 "dbch->ndesc is too small" 863 ", trancated.\n"); 864 break; 865 } 866 db->db.desc.addr 867 = vtophys(mtod(m, caddr_t)); 868 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 869 db->db.desc.status = 0; 870 db++; 871 db_tr->dbcnt++; 872 } 873 } 874 } 875 if (maxdesc < db_tr->dbcnt) { 876 maxdesc = db_tr->dbcnt; 877 if (bootverbose) 878 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 879 } 880 /* last db */ 881 LAST_DB(db_tr, db); 882 db->db.desc.cmd |= OHCI_OUTPUT_LAST 883 | OHCI_INTERRUPT_ALWAYS 884 | OHCI_BRANCH_ALWAYS; 885 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 886 887 if(fsegment == -1 ) 888 fsegment = db_tr->dbcnt; 889 if (dbch->pdb_tr != NULL) { 890 LAST_DB(dbch->pdb_tr, db); 891 db->db.desc.depend |= db_tr->dbcnt; 892 } 893 dbch->pdb_tr = db_tr; 894 db_tr = STAILQ_NEXT(db_tr, link); 895 if(db_tr != dbch->bottom){ 896 goto txloop; 897 } else { 898 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 899 dbch->flags |= FWOHCI_DBCH_FULL; 900 } 901kick: 902 if (firewire_debug) printf("kick\n"); 903 /* kick asy q */ 904 905 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 906 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 907 } else { 908 if (bootverbose) 909 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 910 OREAD(sc, OHCI_DMACTL(off))); 911 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 912 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 913 dbch->xferq.flag |= FWXFERQ_RUNNING; 914 } 915 916 dbch->top = db_tr; 917 splx(s); 918 return; 919} 920 921static void 922fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 923{ 924 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 925 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 926 return; 927} 928 929static void 930fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 931{ 932 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 933 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 934 return; 935} 936 937static void 938fwohci_start_atq(struct firewire_comm *fc) 939{ 940 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 941 fwohci_start( sc, &(sc->atrq)); 942 return; 943} 944 945static void 946fwohci_start_ats(struct firewire_comm *fc) 947{ 948 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 949 fwohci_start( sc, &(sc->atrs)); 950 return; 951} 952 953void 954fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 955{ 956 int s, err = 0; 957 struct fwohcidb_tr *tr; 958 volatile struct fwohcidb *db; 959 struct fw_xfer *xfer; 960 u_int32_t off; 961 u_int stat; 962 int packets; 963 struct firewire_comm *fc = (struct firewire_comm *)sc; 964 if(&sc->atrq == dbch){ 965 off = OHCI_ATQOFF; 966 }else if(&sc->atrs == dbch){ 967 off = OHCI_ATSOFF; 968 }else{ 969 return; 970 } 971 s = splfw(); 972 tr = dbch->bottom; 973 packets = 0; 974 while(dbch->xferq.queued > 0){ 975 LAST_DB(tr, db); 976 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 977 if (fc->status != FWBUSRESET) 978 /* maybe out of order?? */ 979 goto out; 980 } 981 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 982#ifdef OHCI_DEBUG 983 dump_dma(sc, ch); 984 dump_db(sc, ch); 985#endif 986/* Stop DMA */ 987 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 988 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 989 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 990 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 991 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 992 } 993 stat = db->db.desc.status & FWOHCIEV_MASK; 994 switch(stat){ 995 case FWOHCIEV_ACKCOMPL: 996 case FWOHCIEV_ACKPEND: 997 err = 0; 998 break; 999 case FWOHCIEV_ACKBSA: 1000 case FWOHCIEV_ACKBSB: 1001 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1002 case FWOHCIEV_ACKBSX: 1003 err = EBUSY; 1004 break; 1005 case FWOHCIEV_FLUSHED: 1006 case FWOHCIEV_ACKTARD: 1007 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1008 err = EAGAIN; 1009 break; 1010 case FWOHCIEV_MISSACK: 1011 case FWOHCIEV_UNDRRUN: 1012 case FWOHCIEV_OVRRUN: 1013 case FWOHCIEV_DESCERR: 1014 case FWOHCIEV_DTRDERR: 1015 case FWOHCIEV_TIMEOUT: 1016 case FWOHCIEV_TCODERR: 1017 case FWOHCIEV_UNKNOWN: 1018 case FWOHCIEV_ACKDERR: 1019 case FWOHCIEV_ACKTERR: 1020 default: 1021 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1022 stat, fwohcicode[stat]); 1023 err = EINVAL; 1024 break; 1025 } 1026 if(tr->xfer != NULL){ 1027 xfer = tr->xfer; 1028 xfer->state = FWXF_SENT; 1029 if(err == EBUSY && fc->status != FWBUSRESET){ 1030 xfer->state = FWXF_BUSY; 1031 switch(xfer->act_type){ 1032 case FWACT_XFER: 1033 xfer->resp = err; 1034 if(xfer->retry_req != NULL){ 1035 xfer->retry_req(xfer); 1036 } 1037 break; 1038 default: 1039 break; 1040 } 1041 } else if( stat != FWOHCIEV_ACKPEND){ 1042 if (stat != FWOHCIEV_ACKCOMPL) 1043 xfer->state = FWXF_SENTERR; 1044 xfer->resp = err; 1045 switch(xfer->act_type){ 1046 case FWACT_XFER: 1047 fw_xfer_done(xfer); 1048 break; 1049 default: 1050 break; 1051 } 1052 } 1053 dbch->xferq.queued --; 1054 } 1055 tr->xfer = NULL; 1056 1057 packets ++; 1058 tr = STAILQ_NEXT(tr, link); 1059 dbch->bottom = tr; 1060 } 1061out: 1062 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1063 printf("make free slot\n"); 1064 dbch->flags &= ~FWOHCI_DBCH_FULL; 1065 fwohci_start(sc, dbch); 1066 } 1067 splx(s); 1068} 1069 1070static void 1071fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1072{ 1073 int i, s; 1074 struct fwohcidb_tr *tr; 1075 1076 if(xfer->state != FWXF_START) return; 1077 1078 s = splfw(); 1079 tr = dbch->bottom; 1080 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1081 if(tr->xfer == xfer){ 1082 s = splfw(); 1083 tr->xfer = NULL; 1084 dbch->xferq.queued --; 1085#if 1 1086 /* XXX */ 1087 if (tr == dbch->bottom) 1088 dbch->bottom = STAILQ_NEXT(tr, link); 1089#endif 1090 if (dbch->flags & FWOHCI_DBCH_FULL) { 1091 printf("fwohci_drain: make slot\n"); 1092 dbch->flags &= ~FWOHCI_DBCH_FULL; 1093 fwohci_start((struct fwohci_softc *)fc, dbch); 1094 } 1095 1096 splx(s); 1097 break; 1098 } 1099 tr = STAILQ_NEXT(tr, link); 1100 } 1101 splx(s); 1102 return; 1103} 1104 1105static void 1106fwohci_db_free(struct fwohci_dbch *dbch) 1107{ 1108 struct fwohcidb_tr *db_tr; 1109 int idb, i; 1110 1111 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1112 return; 1113 1114 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1115 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1116 idb < dbch->ndb; 1117 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1118 if (db_tr->buf != NULL) { 1119 free(db_tr->buf, M_DEVBUF); 1120 db_tr->buf = NULL; 1121 } 1122 } 1123 } 1124 dbch->ndb = 0; 1125 db_tr = STAILQ_FIRST(&dbch->db_trq); 1126 for (i = 0; i < dbch->npages; i++) 1127 free(dbch->pages[i], M_DEVBUF); 1128 free(db_tr, M_DEVBUF); 1129 STAILQ_INIT(&dbch->db_trq); 1130 dbch->flags &= ~FWOHCI_DBCH_INIT; 1131} 1132 1133static void 1134fwohci_db_init(struct fwohci_dbch *dbch) 1135{ 1136 int idb; 1137 struct fwohcidb_tr *db_tr; 1138 int ndbpp, i, j; 1139 1140 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1141 goto out; 1142 1143 /* allocate DB entries and attach one to each DMA channels */ 1144 /* DB entry must start at 16 bytes bounary. */ 1145 STAILQ_INIT(&dbch->db_trq); 1146 db_tr = (struct fwohcidb_tr *) 1147 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1148 M_DEVBUF, M_NOWAIT | M_ZERO); 1149 if(db_tr == NULL){ 1150 printf("fwohci_db_init: malloc(1) failed\n"); 1151 return; 1152 } 1153 1154 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1155 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1156 if (firewire_debug) 1157 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1158 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1159 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1160 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1161 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1162 return; 1163 } 1164 for (i = 0; i < dbch->npages; i++) { 1165 dbch->pages[i] = malloc(PAGE_SIZE, M_DEVBUF, 1166 M_NOWAIT | M_ZERO); 1167 if (dbch->pages[i] == NULL) { 1168 printf("fwohci_db_init: malloc(2) failed\n"); 1169 for (j = 0; j < i; j ++) 1170 free(dbch->pages[j], M_DEVBUF); 1171 free(db_tr, M_DEVBUF); 1172 return; 1173 } 1174 } 1175 /* Attach DB to DMA ch. */ 1176 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1177 db_tr->dbcnt = 0; 1178 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1179 + dbch->ndesc * (idb % ndbpp); 1180 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1181 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1182 dbch->xferq.bnpacket != 0) { 1183 if (idb % dbch->xferq.bnpacket == 0) 1184 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1185 ].start = (caddr_t)db_tr; 1186 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1187 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1188 ].end = (caddr_t)db_tr; 1189 } 1190 db_tr++; 1191 } 1192 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1193 = STAILQ_FIRST(&dbch->db_trq); 1194out: 1195 dbch->frag.buf = NULL; 1196 dbch->frag.len = 0; 1197 dbch->frag.plen = 0; 1198 dbch->xferq.queued = 0; 1199 dbch->pdb_tr = NULL; 1200 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1201 dbch->bottom = dbch->top; 1202 dbch->flags = FWOHCI_DBCH_INIT; 1203} 1204 1205static int 1206fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1207{ 1208 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1209 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1210 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1211 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1212 fwohci_db_free(&sc->it[dmach]); 1213 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1214 return 0; 1215} 1216 1217static int 1218fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1219{ 1220 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1221 1222 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1223 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1224 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1225 if(sc->ir[dmach].dummy != NULL){ 1226 free(sc->ir[dmach].dummy, M_DEVBUF); 1227 } 1228 sc->ir[dmach].dummy = NULL; 1229 fwohci_db_free(&sc->ir[dmach]); 1230 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1231 return 0; 1232} 1233 1234static void 1235fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1236{ 1237 qld[0] = ntohl(qld[0]); 1238 return; 1239} 1240 1241static int 1242fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1243{ 1244 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1245 int err = 0; 1246 unsigned short tag, ich; 1247 1248 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1249 ich = sc->ir[dmach].xferq.flag & 0x3f; 1250 1251#if 0 1252 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1253 wakeup(fc->ir[dmach]); 1254 return err; 1255 } 1256#endif 1257 1258 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1259 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1260 sc->ir[dmach].xferq.queued = 0; 1261 sc->ir[dmach].ndb = NDB; 1262 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1263 sc->ir[dmach].ndesc = 1; 1264 fwohci_db_init(&sc->ir[dmach]); 1265 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1266 return ENOMEM; 1267 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1268 } 1269 if(err){ 1270 device_printf(sc->fc.dev, "err in IRX setting\n"); 1271 return err; 1272 } 1273 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1274 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1275 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1276 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1277 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1278 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1279 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1280 OWRITE(sc, OHCI_IRCMD(dmach), 1281 vtophys(sc->ir[dmach].top->db) | 1); 1282 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1283 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1284 } 1285 return err; 1286} 1287 1288static int 1289fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1290{ 1291 int err = 0; 1292 int idb, z, i, dmach = 0; 1293 u_int32_t off = NULL; 1294 struct fwohcidb_tr *db_tr; 1295 1296 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1297 err = EINVAL; 1298 return err; 1299 } 1300 z = dbch->ndesc; 1301 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1302 if( &sc->it[dmach] == dbch){ 1303 off = OHCI_ITOFF(dmach); 1304 break; 1305 } 1306 } 1307 if(off == NULL){ 1308 err = EINVAL; 1309 return err; 1310 } 1311 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1312 return err; 1313 dbch->xferq.flag |= FWXFERQ_RUNNING; 1314 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1315 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1316 } 1317 db_tr = dbch->top; 1318 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1319 fwohci_add_tx_buf(db_tr, 1320 dbch->xferq.psize, dbch->xferq.flag, 1321 dbch->xferq.buf + dbch->xferq.psize * idb); 1322 if(STAILQ_NEXT(db_tr, link) == NULL){ 1323 break; 1324 } 1325 db_tr->db[0].db.desc.depend 1326 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1327 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1328 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1329 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1330 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1331 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1332 |= OHCI_INTERRUPT_ALWAYS; 1333 db_tr->db[0].db.desc.depend &= ~0xf; 1334 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1335 ~0xf; 1336 /* OHCI 1.1 and above */ 1337 db_tr->db[0].db.desc.cmd 1338 |= OHCI_INTERRUPT_ALWAYS; 1339 } 1340 } 1341 db_tr = STAILQ_NEXT(db_tr, link); 1342 } 1343 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1344 return err; 1345} 1346 1347static int 1348fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1349{ 1350 int err = 0; 1351 int idb, z, i, dmach = 0; 1352 u_int32_t off = NULL; 1353 struct fwohcidb_tr *db_tr; 1354 1355 z = dbch->ndesc; 1356 if(&sc->arrq == dbch){ 1357 off = OHCI_ARQOFF; 1358 }else if(&sc->arrs == dbch){ 1359 off = OHCI_ARSOFF; 1360 }else{ 1361 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1362 if( &sc->ir[dmach] == dbch){ 1363 off = OHCI_IROFF(dmach); 1364 break; 1365 } 1366 } 1367 } 1368 if(off == NULL){ 1369 err = EINVAL; 1370 return err; 1371 } 1372 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1373 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1374 return err; 1375 }else{ 1376 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1377 err = EBUSY; 1378 return err; 1379 } 1380 } 1381 dbch->xferq.flag |= FWXFERQ_RUNNING; 1382 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1383 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1384 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1385 } 1386 db_tr = dbch->top; 1387 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1388 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1389 fwohci_add_rx_buf(db_tr, 1390 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1391 }else{ 1392 fwohci_add_rx_buf(db_tr, 1393 dbch->xferq.psize, dbch->xferq.flag, 1394 dbch->xferq.buf + dbch->xferq.psize * idb, 1395 dbch->dummy + sizeof(u_int32_t) * idb); 1396 } 1397 if(STAILQ_NEXT(db_tr, link) == NULL){ 1398 break; 1399 } 1400 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1401 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1402 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1403 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1404 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1405 |= OHCI_INTERRUPT_ALWAYS; 1406 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1407 ~0xf; 1408 } 1409 } 1410 db_tr = STAILQ_NEXT(db_tr, link); 1411 } 1412 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1413 dbch->buf_offset = 0; 1414 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1415 return err; 1416 }else{ 1417 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1418 } 1419 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1420 return err; 1421} 1422 1423static int 1424fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1425{ 1426 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1427 int err = 0; 1428 unsigned short tag, ich; 1429 struct fwohci_dbch *dbch; 1430 struct fw_pkt *fp; 1431 struct fwohcidb_tr *db_tr; 1432 int cycle_now, sec, cycle, cycle_match; 1433 u_int32_t stat; 1434 1435 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1436 ich = sc->it[dmach].xferq.flag & 0x3f; 1437 dbch = &sc->it[dmach]; 1438 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1439 dbch->xferq.queued = 0; 1440 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1441 dbch->ndesc = 3; 1442 fwohci_db_init(dbch); 1443 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1444 return ENOMEM; 1445 err = fwohci_tx_enable(sc, dbch); 1446 } 1447 if(err) 1448 return err; 1449 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1450 if (stat & OHCI_CNTL_DMA_ACTIVE) { 1451 if(dbch->xferq.stdma2 != NULL){ 1452 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1453 ((struct fwohcidb_tr *) 1454 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1455 |= OHCI_BRANCH_ALWAYS; 1456 ((struct fwohcidb_tr *) 1457 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1458 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1459 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1460 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1461 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1462 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1463 } else { 1464 device_printf(fc->dev, 1465 "fwohci_itxbuf_enable: queue underrun\n"); 1466 } 1467 return err; 1468 } 1469 if (firewire_debug) 1470 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1471 fw_tbuf_update(&sc->fc, dmach, 0); 1472 if(dbch->xferq.stdma == NULL){ 1473 return err; 1474 } 1475 if(dbch->xferq.stdma2 == NULL){ 1476 /* wait until 2 chunks buffered */ 1477 return err; 1478 } 1479 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1480 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1481 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1482 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1483 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1484 ((struct fwohcidb_tr *) 1485 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1486 |= OHCI_BRANCH_ALWAYS; 1487 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1488 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1489 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1490 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1491 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1492 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1493 OWRITE(sc, OHCI_ITCMD(dmach), 1494 vtophys(((struct fwohcidb_tr *) 1495 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1496#define CYCLE_OFFSET 1 1497 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1498 if(dbch->xferq.flag & FWXFERQ_DV){ 1499 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1500 fp = (struct fw_pkt *)db_tr->buf; 1501 dbch->xferq.dvoffset = CYCLE_OFFSET; 1502 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1503 } 1504 /* 2bit second + 13bit cycle */ 1505 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1506 cycle = cycle_now & 0x1fff; 1507 sec = cycle_now >> 13; 1508#define CYCLE_MOD 0x10 1509#define CYCLE_DELAY 8 /* min delay to start DMA */ 1510 cycle = cycle + CYCLE_DELAY; 1511 if (cycle >= 8000) { 1512 sec ++; 1513 cycle -= 8000; 1514 } 1515 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1516 if (cycle >= 8000) { 1517 sec ++; 1518 if (cycle == 8000) 1519 cycle = 0; 1520 else 1521 cycle = CYCLE_MOD; 1522 } 1523 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1524 /* Clear cycle match counter bits */ 1525 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1526 OWRITE(sc, OHCI_ITCTL(dmach), 1527 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1528 | OHCI_CNTL_DMA_RUN); 1529 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1530 if (firewire_debug) 1531 printf("cycle_match: 0x%04x->0x%04x\n", 1532 cycle_now, cycle_match); 1533 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1534 if (firewire_debug) 1535 printf("fwohci_itxbuf_enable: restart 0x%08x\n", stat); 1536 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1537 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1538 } 1539 return err; 1540} 1541 1542static int 1543fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1544{ 1545 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1546 int err = 0; 1547 unsigned short tag, ich; 1548 u_int32_t stat; 1549 1550 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1551 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1552 ich = sc->ir[dmach].xferq.flag & 0x3f; 1553 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1554 1555 sc->ir[dmach].xferq.queued = 0; 1556 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1557 sc->ir[dmach].xferq.bnchunk; 1558 sc->ir[dmach].dummy = 1559 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1560 M_DEVBUF, M_NOWAIT); 1561 if(sc->ir[dmach].dummy == NULL){ 1562 err = ENOMEM; 1563 return err; 1564 } 1565 sc->ir[dmach].ndesc = 2; 1566 fwohci_db_init(&sc->ir[dmach]); 1567 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1568 return ENOMEM; 1569 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1570 } 1571 if(err) 1572 return err; 1573 1574 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1575 if (stat & OHCI_CNTL_DMA_ACTIVE) { 1576 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1577 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1578 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1579 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1580 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1581 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1582 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1583 } 1584 } else if (!(stat & OHCI_CNTL_DMA_ACTIVE) 1585 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)) { 1586 if (firewire_debug) 1587 device_printf(sc->fc.dev, "IR DMA stat %x\n", stat); 1588 fw_rbuf_update(&sc->fc, dmach, 0); 1589 1590 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1591 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1592 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1593 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1594 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1595 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1596 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1597 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1598 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1599 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1600 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1601 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1602 }else{ 1603 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1604 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1605 } 1606 OWRITE(sc, OHCI_IRCMD(dmach), 1607 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1608 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1609 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1610 } 1611 return err; 1612} 1613 1614static int 1615fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1616{ 1617 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1618 int err = 0; 1619 1620 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1621 err = fwohci_irxpp_enable(fc, dmach); 1622 return err; 1623 }else{ 1624 err = fwohci_irxbuf_enable(fc, dmach); 1625 return err; 1626 } 1627} 1628 1629int 1630fwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1631{ 1632 u_int i; 1633 1634/* Now stopping all DMA channel */ 1635 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1636 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1637 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1638 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1639 1640 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1641 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1642 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1643 } 1644 1645/* FLUSH FIFO and reset Transmitter/Reciever */ 1646 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1647 1648/* Stop interrupt */ 1649 OWRITE(sc, FWOHCI_INTMASKCLR, 1650 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1651 | OHCI_INT_PHY_INT 1652 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1653 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1654 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1655 | OHCI_INT_PHY_BUS_R); 1656/* XXX Link down? Bus reset? */ 1657 return 0; 1658} 1659 1660int 1661fwohci_resume(struct fwohci_softc *sc, device_t dev) 1662{ 1663 int i; 1664 1665 fwohci_reset(sc, dev); 1666 /* XXX resume isochronus receive automatically. (how about TX?) */ 1667 for(i = 0; i < sc->fc.nisodma; i ++) { 1668 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1669 device_printf(sc->fc.dev, 1670 "resume iso receive ch: %d\n", i); 1671 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1672 sc->fc.irx_enable(&sc->fc, i); 1673 } 1674 } 1675 1676 bus_generic_resume(dev); 1677 sc->fc.ibr(&sc->fc); 1678 return 0; 1679} 1680 1681#define ACK_ALL 1682static void 1683fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1684{ 1685 u_int32_t irstat, itstat; 1686 u_int i; 1687 struct firewire_comm *fc = (struct firewire_comm *)sc; 1688 1689#ifdef OHCI_DEBUG 1690 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1691 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1692 stat & OHCI_INT_EN ? "DMA_EN ":"", 1693 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1694 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1695 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1696 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1697 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1698 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1699 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1700 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1701 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1702 stat & OHCI_INT_PHY_SID ? "SID ":"", 1703 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1704 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1705 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1706 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1707 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1708 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1709 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1710 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1711 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1712 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1713 stat, OREAD(sc, FWOHCI_INTMASK) 1714 ); 1715#endif 1716/* Bus reset */ 1717 if(stat & OHCI_INT_PHY_BUS_R ){ 1718 device_printf(fc->dev, "BUS reset\n"); 1719 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1720 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1721 1722 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1723 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1724 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1725 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1726 1727#if 0 1728 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1729 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1730 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1731 } 1732 1733#endif 1734 fw_busreset(fc); 1735 1736 /* XXX need to wait DMA to stop */ 1737#ifndef ACK_ALL 1738 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1739#endif 1740#if 1 1741 /* pending all pre-bus_reset packets */ 1742 fwohci_txd(sc, &sc->atrq); 1743 fwohci_txd(sc, &sc->atrs); 1744 fwohci_arcv(sc, &sc->arrs, -1); 1745 fwohci_arcv(sc, &sc->arrq, -1); 1746#endif 1747 1748 1749 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1750 /* XXX insecure ?? */ 1751 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1752 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1753 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1754 1755 } 1756 if((stat & OHCI_INT_DMA_IR )){ 1757#ifndef ACK_ALL 1758 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1759#endif 1760 irstat = OREAD(sc, OHCI_IR_STAT); 1761 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1762 for(i = 0; i < fc->nisodma ; i++){ 1763 struct fwohci_dbch *dbch; 1764 1765 if((irstat & (1 << i)) != 0){ 1766 dbch = &sc->ir[i]; 1767 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1768 device_printf(sc->fc.dev, 1769 "dma(%d) not active\n", i); 1770 continue; 1771 } 1772 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1773 fwohci_ircv(sc, dbch, count); 1774 } else { 1775 fwohci_rbuf_update(sc, i); 1776 } 1777 } 1778 } 1779 } 1780 if((stat & OHCI_INT_DMA_IT )){ 1781#ifndef ACK_ALL 1782 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1783#endif 1784 itstat = OREAD(sc, OHCI_IT_STAT); 1785 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1786 for(i = 0; i < fc->nisodma ; i++){ 1787 if((itstat & (1 << i)) != 0){ 1788 fwohci_tbuf_update(sc, i); 1789 } 1790 } 1791 } 1792 if((stat & OHCI_INT_DMA_PRRS )){ 1793#ifndef ACK_ALL 1794 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1795#endif 1796#if 0 1797 dump_dma(sc, ARRS_CH); 1798 dump_db(sc, ARRS_CH); 1799#endif 1800 fwohci_arcv(sc, &sc->arrs, count); 1801 } 1802 if((stat & OHCI_INT_DMA_PRRQ )){ 1803#ifndef ACK_ALL 1804 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1805#endif 1806#if 0 1807 dump_dma(sc, ARRQ_CH); 1808 dump_db(sc, ARRQ_CH); 1809#endif 1810 fwohci_arcv(sc, &sc->arrq, count); 1811 } 1812 if(stat & OHCI_INT_PHY_SID){ 1813 caddr_t buf; 1814 int plen; 1815 1816#ifndef ACK_ALL 1817 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1818#endif 1819/* 1820** Checking whether the node is root or not. If root, turn on 1821** cycle master. 1822*/ 1823 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1824 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1825 printf("Bus reset failure\n"); 1826 goto sidout; 1827 } 1828 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1829 printf("CYCLEMASTER mode\n"); 1830 OWRITE(sc, OHCI_LNKCTL, 1831 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1832 }else{ 1833 printf("non CYCLEMASTER mode\n"); 1834 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1835 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1836 } 1837 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1838 1839 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1840 if (plen < 4 || plen > OHCI_SIDSIZE) { 1841 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1842 goto sidout; 1843 } 1844 plen -= 4; /* chop control info */ 1845 buf = malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 1846 if(buf == NULL) goto sidout; 1847 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1848 buf, plen); 1849 fw_sidrcv(fc, buf, plen, 0); 1850 } 1851sidout: 1852 if((stat & OHCI_INT_DMA_ATRQ )){ 1853#ifndef ACK_ALL 1854 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1855#endif 1856 fwohci_txd(sc, &(sc->atrq)); 1857 } 1858 if((stat & OHCI_INT_DMA_ATRS )){ 1859#ifndef ACK_ALL 1860 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1861#endif 1862 fwohci_txd(sc, &(sc->atrs)); 1863 } 1864 if((stat & OHCI_INT_PW_ERR )){ 1865#ifndef ACK_ALL 1866 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1867#endif 1868 device_printf(fc->dev, "posted write error\n"); 1869 } 1870 if((stat & OHCI_INT_ERR )){ 1871#ifndef ACK_ALL 1872 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1873#endif 1874 device_printf(fc->dev, "unrecoverable error\n"); 1875 } 1876 if((stat & OHCI_INT_PHY_INT)) { 1877#ifndef ACK_ALL 1878 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1879#endif 1880 device_printf(fc->dev, "phy int\n"); 1881 } 1882 1883 return; 1884} 1885 1886void 1887fwohci_intr(void *arg) 1888{ 1889 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1890 u_int32_t stat; 1891 1892 if (!(sc->intmask & OHCI_INT_EN)) { 1893 /* polling mode */ 1894 return; 1895 } 1896 1897 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1898 if (stat == 0xffffffff) { 1899 device_printf(sc->fc.dev, 1900 "device physically ejected?\n"); 1901 return; 1902 } 1903#ifdef ACK_ALL 1904 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1905#endif 1906 fwohci_intr_body(sc, stat, -1); 1907 } 1908} 1909 1910static void 1911fwohci_poll(struct firewire_comm *fc, int quick, int count) 1912{ 1913 int s; 1914 u_int32_t stat; 1915 struct fwohci_softc *sc; 1916 1917 1918 sc = (struct fwohci_softc *)fc; 1919 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1920 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1921 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1922#if 0 1923 if (!quick) { 1924#else 1925 if (1) { 1926#endif 1927 stat = OREAD(sc, FWOHCI_INTSTAT); 1928 if (stat == 0) 1929 return; 1930 if (stat == 0xffffffff) { 1931 device_printf(sc->fc.dev, 1932 "device physically ejected?\n"); 1933 return; 1934 } 1935#ifdef ACK_ALL 1936 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1937#endif 1938 } 1939 s = splfw(); 1940 fwohci_intr_body(sc, stat, count); 1941 splx(s); 1942} 1943 1944static void 1945fwohci_set_intr(struct firewire_comm *fc, int enable) 1946{ 1947 struct fwohci_softc *sc; 1948 1949 sc = (struct fwohci_softc *)fc; 1950 if (bootverbose) 1951 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1952 if (enable) { 1953 sc->intmask |= OHCI_INT_EN; 1954 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1955 } else { 1956 sc->intmask &= ~OHCI_INT_EN; 1957 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1958 } 1959} 1960 1961static void 1962fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1963{ 1964 int stat; 1965 struct firewire_comm *fc = &sc->fc; 1966 struct fw_pkt *fp; 1967 struct fwohci_dbch *dbch; 1968 struct fwohcidb_tr *db_tr; 1969 1970 dbch = &sc->it[dmach]; 1971#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1972 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1973 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1974/* 1975 * Overwrite highest significant 4 bits timestamp information 1976 */ 1977 fp = (struct fw_pkt *)db_tr->buf; 1978 fp->mode.ld[2] &= htonl(0xffff0fff); 1979 fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1980 } 1981#endif 1982 /* 1983 * XXX interrupt could be missed. 1984 * We have to check more than one buffer/chunk 1985 */ 1986 if (firewire_debug && dbch->xferq.stdma2 != NULL) { 1987 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->end; 1988 stat = db_tr->db[2].db.desc.status; 1989 if (stat) 1990 device_printf(fc->dev, 1991 "stdma2 already done stat:0x%x\n", stat); 1992 } 1993 1994 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1995 switch(stat){ 1996 case FWOHCIEV_ACKCOMPL: 1997#if 1 1998 if (dbch->xferq.flag & FWXFERQ_DV) { 1999 struct ciphdr *ciph; 2000 int timer, timestamp, cycl, diff; 2001 static int last_timer=0; 2002 2003 timer = (fc->cyctimer(fc) >> 12) & 0xffff; 2004 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 2005 fp = (struct fw_pkt *)db_tr->buf; 2006 ciph = (struct ciphdr *) &fp->mode.ld[1]; 2007 timestamp = db_tr->db[2].db.desc.count & 0xffff; 2008 cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 2009 diff = cycl - (timestamp & 0xf) - CYCLE_OFFSET; 2010 if (diff < 0) 2011 diff += 16; 2012 if (diff > 8) 2013 diff -= 16; 2014 if (firewire_debug || diff != 0) 2015 printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 2016 " cyc: 0x%x diff: %+1d\n", 2017 ciph->dbc, last_timer, timestamp, cycl, diff); 2018 last_timer = timer; 2019 /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 2020 } 2021#endif 2022 fw_tbuf_update(fc, dmach, 1); 2023 break; 2024 default: 2025 device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 2026 fw_tbuf_update(fc, dmach, 0); 2027 break; 2028 } 2029 fwohci_itxbuf_enable(fc, dmach); 2030} 2031 2032static void 2033fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2034{ 2035 struct firewire_comm *fc = &sc->fc; 2036 int stat; 2037 2038 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 2039 switch(stat){ 2040 case FWOHCIEV_ACKCOMPL: 2041 fw_rbuf_update(fc, dmach, 1); 2042 wakeup(fc->ir[dmach]); 2043 fwohci_irx_enable(fc, dmach); 2044 break; 2045 default: 2046 device_printf(fc->dev, "Isochronous receive err %02x\n", 2047 stat); 2048 break; 2049 } 2050} 2051 2052void 2053dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2054{ 2055 u_int32_t off, cntl, stat, cmd, match; 2056 2057 if(ch == 0){ 2058 off = OHCI_ATQOFF; 2059 }else if(ch == 1){ 2060 off = OHCI_ATSOFF; 2061 }else if(ch == 2){ 2062 off = OHCI_ARQOFF; 2063 }else if(ch == 3){ 2064 off = OHCI_ARSOFF; 2065 }else if(ch < IRX_CH){ 2066 off = OHCI_ITCTL(ch - ITX_CH); 2067 }else{ 2068 off = OHCI_IRCTL(ch - IRX_CH); 2069 } 2070 cntl = stat = OREAD(sc, off); 2071 cmd = OREAD(sc, off + 0xc); 2072 match = OREAD(sc, off + 0x10); 2073 2074 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2075 ch, 2076 cntl, 2077 stat, 2078 cmd, 2079 match); 2080 stat &= 0xffff ; 2081 if(stat & 0xff00){ 2082 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2083 ch, 2084 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2085 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2086 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2087 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2088 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2089 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2090 fwohcicode[stat & 0x1f], 2091 stat & 0x1f 2092 ); 2093 }else{ 2094 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2095 } 2096} 2097 2098void 2099dump_db(struct fwohci_softc *sc, u_int32_t ch) 2100{ 2101 struct fwohci_dbch *dbch; 2102 struct fwohcidb_tr *cp = NULL, *pp, *np; 2103 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2104 int idb, jdb; 2105 u_int32_t cmd, off; 2106 if(ch == 0){ 2107 off = OHCI_ATQOFF; 2108 dbch = &sc->atrq; 2109 }else if(ch == 1){ 2110 off = OHCI_ATSOFF; 2111 dbch = &sc->atrs; 2112 }else if(ch == 2){ 2113 off = OHCI_ARQOFF; 2114 dbch = &sc->arrq; 2115 }else if(ch == 3){ 2116 off = OHCI_ARSOFF; 2117 dbch = &sc->arrs; 2118 }else if(ch < IRX_CH){ 2119 off = OHCI_ITCTL(ch - ITX_CH); 2120 dbch = &sc->it[ch - ITX_CH]; 2121 }else { 2122 off = OHCI_IRCTL(ch - IRX_CH); 2123 dbch = &sc->ir[ch - IRX_CH]; 2124 } 2125 cmd = OREAD(sc, off + 0xc); 2126 2127 if( dbch->ndb == 0 ){ 2128 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2129 return; 2130 } 2131 pp = dbch->top; 2132 prev = pp->db; 2133 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2134 if(pp == NULL){ 2135 curr = NULL; 2136 goto outdb; 2137 } 2138 cp = STAILQ_NEXT(pp, link); 2139 if(cp == NULL){ 2140 curr = NULL; 2141 goto outdb; 2142 } 2143 np = STAILQ_NEXT(cp, link); 2144 if(cp == NULL) break; 2145 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2146 if((cmd & 0xfffffff0) 2147 == vtophys(&(cp->db[jdb]))){ 2148 curr = cp->db; 2149 if(np != NULL){ 2150 next = np->db; 2151 }else{ 2152 next = NULL; 2153 } 2154 goto outdb; 2155 } 2156 } 2157 pp = STAILQ_NEXT(pp, link); 2158 prev = pp->db; 2159 } 2160outdb: 2161 if( curr != NULL){ 2162 printf("Prev DB %d\n", ch); 2163 print_db(prev, ch, dbch->ndesc); 2164 printf("Current DB %d\n", ch); 2165 print_db(curr, ch, dbch->ndesc); 2166 printf("Next DB %d\n", ch); 2167 print_db(next, ch, dbch->ndesc); 2168 }else{ 2169 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2170 } 2171 return; 2172} 2173 2174void 2175print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2176{ 2177 fwohcireg_t stat; 2178 int i, key; 2179 2180 if(db == NULL){ 2181 printf("No Descriptor is found\n"); 2182 return; 2183 } 2184 2185 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2186 ch, 2187 "Current", 2188 "OP ", 2189 "KEY", 2190 "INT", 2191 "BR ", 2192 "len", 2193 "Addr", 2194 "Depend", 2195 "Stat", 2196 "Cnt"); 2197 for( i = 0 ; i <= max ; i ++){ 2198 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2199#if __FreeBSD_version >= 500000 2200 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2201#else 2202 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2203#endif 2204 vtophys(&db[i]), 2205 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2206 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2207 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2208 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2209 db[i].db.desc.cmd & 0xffff, 2210 db[i].db.desc.addr, 2211 db[i].db.desc.depend, 2212 db[i].db.desc.status, 2213 db[i].db.desc.count); 2214 stat = db[i].db.desc.status; 2215 if(stat & 0xff00){ 2216 printf(" %s%s%s%s%s%s %s(%x)\n", 2217 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2218 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2219 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2220 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2221 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2222 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2223 fwohcicode[stat & 0x1f], 2224 stat & 0x1f 2225 ); 2226 }else{ 2227 printf(" Nostat\n"); 2228 } 2229 if(key == OHCI_KEY_ST2 ){ 2230 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2231 db[i+1].db.immed[0], 2232 db[i+1].db.immed[1], 2233 db[i+1].db.immed[2], 2234 db[i+1].db.immed[3]); 2235 } 2236 if(key == OHCI_KEY_DEVICE){ 2237 return; 2238 } 2239 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2240 == OHCI_BRANCH_ALWAYS){ 2241 return; 2242 } 2243 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2244 == OHCI_OUTPUT_LAST){ 2245 return; 2246 } 2247 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2248 == OHCI_INPUT_LAST){ 2249 return; 2250 } 2251 if(key == OHCI_KEY_ST2 ){ 2252 i++; 2253 } 2254 } 2255 return; 2256} 2257 2258void 2259fwohci_ibr(struct firewire_comm *fc) 2260{ 2261 struct fwohci_softc *sc; 2262 u_int32_t fun; 2263 2264 sc = (struct fwohci_softc *)fc; 2265 2266 /* 2267 * Set root hold-off bit so that non cyclemaster capable node 2268 * shouldn't became the root node. 2269 */ 2270#if 1 2271 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2272 fun |= FW_PHY_IBR | FW_PHY_RHB; 2273 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2274#else /* Short bus reset */ 2275 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2276 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2277 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2278#endif 2279} 2280 2281void 2282fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2283{ 2284 struct fwohcidb_tr *db_tr, *fdb_tr; 2285 struct fwohci_dbch *dbch; 2286 struct fw_pkt *fp; 2287 volatile struct fwohci_txpkthdr *ohcifp; 2288 unsigned short chtag; 2289 int idb; 2290 2291 dbch = &sc->it[dmach]; 2292 chtag = sc->it[dmach].xferq.flag & 0xff; 2293 2294 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2295 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2296/* 2297device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2298*/ 2299 if(bulkxfer->flag != 0){ 2300 return; 2301 } 2302 bulkxfer->flag = 1; 2303 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2304 db_tr->db[0].db.desc.cmd 2305 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2306 fp = (struct fw_pkt *)db_tr->buf; 2307 ohcifp = (volatile struct fwohci_txpkthdr *) 2308 db_tr->db[1].db.immed; 2309 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2310 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2311 ohcifp->mode.stream.chtag = chtag; 2312 ohcifp->mode.stream.tcode = 0xa; 2313 ohcifp->mode.stream.spd = 4; 2314 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2315 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2316 2317 db_tr->db[2].db.desc.cmd 2318 = OHCI_OUTPUT_LAST 2319 | OHCI_UPDATE 2320 | OHCI_BRANCH_ALWAYS 2321 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2322 db_tr->db[2].db.desc.status = 0; 2323 db_tr->db[2].db.desc.count = 0; 2324 db_tr->db[0].db.desc.depend 2325 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2326 db_tr->db[dbch->ndesc - 1].db.desc.depend 2327 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2328 bulkxfer->end = (caddr_t)db_tr; 2329 db_tr = STAILQ_NEXT(db_tr, link); 2330 } 2331 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2332 db_tr->db[0].db.desc.depend &= ~0xf; 2333 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2334#if 0 2335/**/ 2336 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2337 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2338/**/ 2339#endif 2340 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2341 /* OHCI 1.1 and above */ 2342 db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2343 2344 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2345 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2346/* 2347device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2348*/ 2349 return; 2350} 2351 2352static int 2353fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2354 int mode, void *buf) 2355{ 2356 volatile struct fwohcidb *db = db_tr->db; 2357 int err = 0; 2358 if(buf == 0){ 2359 err = EINVAL; 2360 return err; 2361 } 2362 db_tr->buf = buf; 2363 db_tr->dbcnt = 3; 2364 db_tr->dummy = NULL; 2365 2366 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2367 2368 db[2].db.desc.depend = 0; 2369 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2370 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2371 2372 db[0].db.desc.status = 0; 2373 db[0].db.desc.count = 0; 2374 2375 db[2].db.desc.status = 0; 2376 db[2].db.desc.count = 0; 2377 if( mode & FWXFERQ_STREAM ){ 2378 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2379 if(mode & FWXFERQ_PACKET ){ 2380 db[2].db.desc.cmd 2381 |= OHCI_INTERRUPT_ALWAYS; 2382 } 2383 } 2384 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2385 return 1; 2386} 2387 2388int 2389fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2390 void *buf, void *dummy) 2391{ 2392 volatile struct fwohcidb *db = db_tr->db; 2393 int i; 2394 void *dbuf[2]; 2395 int dsiz[2]; 2396 2397 if(buf == 0){ 2398 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2399 if(buf == NULL) return 0; 2400 db_tr->buf = buf; 2401 db_tr->dbcnt = 1; 2402 db_tr->dummy = NULL; 2403 dsiz[0] = size; 2404 dbuf[0] = buf; 2405 }else if(dummy == NULL){ 2406 db_tr->buf = buf; 2407 db_tr->dbcnt = 1; 2408 db_tr->dummy = NULL; 2409 dsiz[0] = size; 2410 dbuf[0] = buf; 2411 }else{ 2412 db_tr->buf = buf; 2413 db_tr->dbcnt = 2; 2414 db_tr->dummy = dummy; 2415 dsiz[0] = sizeof(u_int32_t); 2416 dsiz[1] = size; 2417 dbuf[0] = dummy; 2418 dbuf[1] = buf; 2419 } 2420 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2421 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2422 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2423 if( mode & FWXFERQ_STREAM ){ 2424 db[i].db.desc.cmd |= OHCI_UPDATE; 2425 } 2426 db[i].db.desc.status = 0; 2427 db[i].db.desc.count = dsiz[i]; 2428 } 2429 if( mode & FWXFERQ_STREAM ){ 2430 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2431 if(mode & FWXFERQ_PACKET ){ 2432 db[db_tr->dbcnt - 1].db.desc.cmd 2433 |= OHCI_INTERRUPT_ALWAYS; 2434 } 2435 } 2436 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2437 return 1; 2438} 2439 2440static void 2441fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2442{ 2443 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2444 struct firewire_comm *fc = (struct firewire_comm *)sc; 2445 int z = 1; 2446 struct fw_pkt *fp; 2447 u_int8_t *ld; 2448 u_int32_t off = NULL; 2449 u_int32_t stat; 2450 u_int32_t *qld; 2451 u_int32_t reg; 2452 u_int spd; 2453 u_int dmach; 2454 int len, i, plen; 2455 caddr_t buf; 2456 2457 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2458 if( &sc->ir[dmach] == dbch){ 2459 off = OHCI_IROFF(dmach); 2460 break; 2461 } 2462 } 2463 if(off == NULL){ 2464 return; 2465 } 2466 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2467 fwohci_irx_disable(&sc->fc, dmach); 2468 return; 2469 } 2470 2471 odb_tr = NULL; 2472 db_tr = dbch->top; 2473 i = 0; 2474 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2475 if (count >= 0 && count-- == 0) 2476 break; 2477 ld = (u_int8_t *)db_tr->buf; 2478 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2479 /* skip timeStamp */ 2480 ld += sizeof(struct fwohci_trailer); 2481 } 2482 qld = (u_int32_t *)ld; 2483 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2484/* 2485{ 2486device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2487 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2488} 2489*/ 2490 fp=(struct fw_pkt *)ld; 2491 qld[0] = htonl(qld[0]); 2492 plen = sizeof(struct fw_isohdr) 2493 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2494 ld += plen; 2495 len -= plen; 2496 buf = db_tr->buf; 2497 db_tr->buf = NULL; 2498 stat = reg & 0x1f; 2499 spd = reg & 0x3; 2500 switch(stat){ 2501 case FWOHCIEV_ACKCOMPL: 2502 case FWOHCIEV_ACKPEND: 2503 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2504 break; 2505 default: 2506 free(buf, M_DEVBUF); 2507 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2508 break; 2509 } 2510 i++; 2511 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2512 dbch->xferq.flag, 0, NULL); 2513 db_tr->db[0].db.desc.depend &= ~0xf; 2514 if(dbch->pdb_tr != NULL){ 2515 dbch->pdb_tr->db[0].db.desc.depend |= z; 2516 } else { 2517 /* XXX should be rewritten in better way */ 2518 dbch->bottom->db[0].db.desc.depend |= z; 2519 } 2520 dbch->pdb_tr = db_tr; 2521 db_tr = STAILQ_NEXT(db_tr, link); 2522 } 2523 dbch->top = db_tr; 2524 reg = OREAD(sc, OHCI_DMACTL(off)); 2525 if (reg & OHCI_CNTL_DMA_ACTIVE) 2526 return; 2527 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2528 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2529 dbch->top = db_tr; 2530 fwohci_irx_enable(fc, dmach); 2531} 2532 2533#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2534static int 2535fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2536{ 2537 int i; 2538 2539 for( i = 4; i < hlen ; i+=4){ 2540 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2541 } 2542 2543 switch(fp->mode.common.tcode){ 2544 case FWTCODE_RREQQ: 2545 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2546 case FWTCODE_WRES: 2547 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2548 case FWTCODE_WREQQ: 2549 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2550 case FWTCODE_RREQB: 2551 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2552 case FWTCODE_RRESQ: 2553 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2554 case FWTCODE_WREQB: 2555 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2556 + sizeof(u_int32_t); 2557 case FWTCODE_LREQ: 2558 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2559 + sizeof(u_int32_t); 2560 case FWTCODE_RRESB: 2561 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2562 + sizeof(u_int32_t); 2563 case FWTCODE_LRES: 2564 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2565 + sizeof(u_int32_t); 2566 case FWOHCITCODE_PHY: 2567 return 16; 2568 } 2569 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2570 return 0; 2571} 2572 2573static void 2574fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2575{ 2576 struct fwohcidb_tr *db_tr; 2577 int z = 1; 2578 struct fw_pkt *fp; 2579 u_int8_t *ld; 2580 u_int32_t stat, off; 2581 u_int spd; 2582 int len, plen, hlen, pcnt, poff = 0, rlen; 2583 int s; 2584 caddr_t buf; 2585 int resCount; 2586 2587 if(&sc->arrq == dbch){ 2588 off = OHCI_ARQOFF; 2589 }else if(&sc->arrs == dbch){ 2590 off = OHCI_ARSOFF; 2591 }else{ 2592 return; 2593 } 2594 2595 s = splfw(); 2596 db_tr = dbch->top; 2597 pcnt = 0; 2598 /* XXX we cannot handle a packet which lies in more than two buf */ 2599 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2600 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2601 resCount = db_tr->db[0].db.desc.count; 2602 len = dbch->xferq.psize - resCount 2603 - dbch->buf_offset; 2604 while (len > 0 ) { 2605 if (count >= 0 && count-- == 0) 2606 goto out; 2607 if(dbch->frag.buf != NULL){ 2608 buf = dbch->frag.buf; 2609 if (dbch->frag.plen < 0) { 2610 /* incomplete header */ 2611 int hlen; 2612 2613 hlen = - dbch->frag.plen; 2614 rlen = hlen - dbch->frag.len; 2615 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2616 ld += rlen; 2617 len -= rlen; 2618 dbch->frag.len += rlen; 2619#if 0 2620 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2621#endif 2622 fp=(struct fw_pkt *)dbch->frag.buf; 2623 dbch->frag.plen 2624 = fwohci_get_plen(sc, fp, hlen); 2625 if (dbch->frag.plen == 0) 2626 goto out; 2627 } 2628 rlen = dbch->frag.plen - dbch->frag.len; 2629#if 0 2630 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2631#endif 2632 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2633 rlen); 2634 ld += rlen; 2635 len -= rlen; 2636 plen = dbch->frag.plen; 2637 dbch->frag.buf = NULL; 2638 dbch->frag.plen = 0; 2639 dbch->frag.len = 0; 2640 poff = 0; 2641 }else{ 2642 fp=(struct fw_pkt *)ld; 2643 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2644 switch(fp->mode.common.tcode){ 2645 case FWTCODE_RREQQ: 2646 case FWTCODE_WRES: 2647 case FWTCODE_WREQQ: 2648 case FWTCODE_RRESQ: 2649 case FWOHCITCODE_PHY: 2650 hlen = 12; 2651 break; 2652 case FWTCODE_RREQB: 2653 case FWTCODE_WREQB: 2654 case FWTCODE_LREQ: 2655 case FWTCODE_RRESB: 2656 case FWTCODE_LRES: 2657 hlen = 16; 2658 break; 2659 default: 2660 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2661 goto out; 2662 } 2663 if (len >= hlen) { 2664 plen = fwohci_get_plen(sc, fp, hlen); 2665 if (plen == 0) 2666 goto out; 2667 plen = (plen + 3) & ~3; 2668 len -= plen; 2669 } else { 2670 plen = -hlen; 2671 len -= hlen; 2672 } 2673 if(resCount > 0 || len > 0){ 2674 buf = malloc( dbch->xferq.psize, 2675 M_DEVBUF, M_NOWAIT); 2676 if(buf == NULL){ 2677 printf("cannot malloc!\n"); 2678 free(db_tr->buf, M_DEVBUF); 2679 goto out; 2680 } 2681 bcopy(ld, buf, plen); 2682 poff = 0; 2683 dbch->frag.buf = NULL; 2684 dbch->frag.plen = 0; 2685 dbch->frag.len = 0; 2686 }else if(len < 0){ 2687 dbch->frag.buf = db_tr->buf; 2688 if (plen < 0) { 2689#if 0 2690 printf("plen < 0:" 2691 "hlen: %d len: %d\n", 2692 hlen, len); 2693#endif 2694 dbch->frag.len = hlen + len; 2695 dbch->frag.plen = -hlen; 2696 } else { 2697 dbch->frag.len = plen + len; 2698 dbch->frag.plen = plen; 2699 } 2700 bcopy(ld, db_tr->buf, dbch->frag.len); 2701 buf = NULL; 2702 }else{ 2703 buf = db_tr->buf; 2704 poff = ld - (u_int8_t *)buf; 2705 dbch->frag.buf = NULL; 2706 dbch->frag.plen = 0; 2707 dbch->frag.len = 0; 2708 } 2709 ld += plen; 2710 } 2711 if( buf != NULL){ 2712/* DMA result-code will be written at the tail of packet */ 2713 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2714 spd = (stat >> 5) & 0x3; 2715 stat &= 0x1f; 2716 switch(stat){ 2717 case FWOHCIEV_ACKPEND: 2718#if 0 2719 printf("fwohci_arcv: ack pending..\n"); 2720#endif 2721 /* fall through */ 2722 case FWOHCIEV_ACKCOMPL: 2723 if( poff != 0 ) 2724 bcopy(buf+poff, buf, plen - 4); 2725 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2726 break; 2727 case FWOHCIEV_BUSRST: 2728 free(buf, M_DEVBUF); 2729 if (sc->fc.status != FWBUSRESET) 2730 printf("got BUSRST packet!?\n"); 2731 break; 2732 default: 2733 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2734#if 0 /* XXX */ 2735 goto out; 2736#endif 2737 break; 2738 } 2739 } 2740 pcnt ++; 2741 }; 2742out: 2743 if (resCount == 0) { 2744 /* done on this buffer */ 2745 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2746 dbch->xferq.flag, 0, NULL); 2747 dbch->bottom->db[0].db.desc.depend |= z; 2748 dbch->bottom = db_tr; 2749 db_tr = STAILQ_NEXT(db_tr, link); 2750 dbch->top = db_tr; 2751 dbch->buf_offset = 0; 2752 } else { 2753 dbch->buf_offset = dbch->xferq.psize - resCount; 2754 break; 2755 } 2756 /* XXX make sure DMA is not dead */ 2757 } 2758#if 0 2759 if (pcnt < 1) 2760 printf("fwohci_arcv: no packets\n"); 2761#endif 2762 splx(s); 2763} 2764