fwohci.c revision 109644
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the acknowledgement as bellow:
15 *
16 *    This product includes software developed by K. Kobayashi and H. Shimokawa
17 *
18 * 4. The name of the author may not be used to endorse or promote products
19 *    derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109644 2003-01-21 16:24:35Z simokawa $
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4
42#define IRX_CH 0x24
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/types.h>
47#include <sys/mbuf.h>
48#include <sys/mman.h>
49#include <sys/socket.h>
50#include <sys/socketvar.h>
51#include <sys/signalvar.h>
52#include <sys/malloc.h>
53#include <sys/uio.h>
54#include <sys/sockio.h>
55#include <sys/bus.h>
56#include <sys/kernel.h>
57#include <sys/conf.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <sys/rman.h>
62
63#include <machine/cpufunc.h>            /* for rdtsc proto for clock.h below */
64#include <machine/clock.h>
65#include <pci/pcivar.h>
66#include <pci/pcireg.h>
67#include <vm/vm.h>
68#include <vm/vm_extern.h>
69#include <vm/pmap.h>            /* for vtophys proto */
70
71#include <dev/firewire/firewire.h>
72#include <dev/firewire/firewirereg.h>
73#include <dev/firewire/fwohcireg.h>
74#include <dev/firewire/fwohcivar.h>
75#include <dev/firewire/firewire_phy.h>
76
77#include <dev/firewire/iec68113.h>
78
79#undef OHCI_DEBUG
80
81static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
82		"STOR","LOAD","NOP ","STOP",};
83static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
84		"UNDEF","REG","SYS","DEV"};
85char fwohcicode[32][0x20]={
86	"No stat","Undef","long","miss Ack err",
87	"underrun","overrun","desc err", "data read err",
88	"data write err","bus reset","timeout","tcode err",
89	"Undef","Undef","unknown event","flushed",
90	"Undef","ack complete","ack pend","Undef",
91	"ack busy_X","ack busy_A","ack busy_B","Undef",
92	"Undef","Undef","Undef","ack tardy",
93	"Undef","ack data_err","ack type_err",""};
94#define MAX_SPEED 2
95extern char linkspeed[MAX_SPEED+1][0x10];
96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
98
99static struct tcode_info tinfo[] = {
100/*		hdr_len block 	flag*/
101/* 0 WREQQ  */ {16,	FWTI_REQ | FWTI_TLABEL},
102/* 1 WREQB  */ {16,	FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
103/* 2 WRES   */ {12,	FWTI_RES},
104/* 3 XXX    */ { 0,	0},
105/* 4 RREQQ  */ {12,	FWTI_REQ | FWTI_TLABEL},
106/* 5 RREQB  */ {16,	FWTI_REQ | FWTI_TLABEL},
107/* 6 RRESQ  */ {16,	FWTI_RES},
108/* 7 RRESB  */ {16,	FWTI_RES | FWTI_BLOCK_ASY},
109/* 8 CYCS   */ { 0,	0},
110/* 9 LREQ   */ {16,	FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
111/* a STREAM */ { 4,	FWTI_REQ | FWTI_BLOCK_STR},
112/* b LRES   */ {16,	FWTI_RES | FWTI_BLOCK_ASY},
113/* c XXX    */ { 0,	0},
114/* d XXX    */ { 0, 	0},
115/* e PHY    */ {12,	FWTI_REQ},
116/* f XXX    */ { 0,	0}
117};
118
119#define OHCI_WRITE_SIGMASK 0xffff0000
120#define OHCI_READ_SIGMASK 0xffff0000
121
122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
124
125static void fwohci_ibr __P((struct firewire_comm *));
126static void fwohci_db_init __P((struct fwohci_dbch *));
127static void fwohci_db_free __P((struct fwohci_dbch *));
128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *));
131static void fwohci_start_atq __P((struct firewire_comm *));
132static void fwohci_start_ats __P((struct firewire_comm *));
133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *));
134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *));
135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *));
136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *));
137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t));
138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t));
139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
141static int fwohci_irx_enable __P((struct firewire_comm *, int));
142static int fwohci_irxpp_enable __P((struct firewire_comm *, int));
143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int));
144static int fwohci_irx_disable __P((struct firewire_comm *, int));
145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *));
146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int));
147static int fwohci_itx_disable __P((struct firewire_comm *, int));
148static void fwohci_timeout __P((void *));
149static void fwohci_poll __P((struct firewire_comm *, int, int));
150static void fwohci_set_intr __P((struct firewire_comm *, int));
151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *));
152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *));
153static void	dump_db __P((struct fwohci_softc *, u_int32_t));
154static void 	print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t));
155static void	dump_dma __P((struct fwohci_softc *, u_int32_t));
156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *));
157static void fwohci_rbuf_update __P((struct fwohci_softc *, int));
158static void fwohci_tbuf_update __P((struct fwohci_softc *, int));
159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
160
161/*
162 * memory allocated for DMA programs
163 */
164#define DMA_PROG_ALLOC		(8 * PAGE_SIZE)
165
166/* #define NDB 1024 */
167#define NDB FWMAXQUEUE
168#define NDVDB (DVBUF * NDB)
169
170#define	OHCI_VERSION		0x00
171#define	OHCI_CROMHDR		0x18
172#define	OHCI_BUS_OPT		0x20
173#define	OHCI_BUSIRMC		(1 << 31)
174#define	OHCI_BUSCMC		(1 << 30)
175#define	OHCI_BUSISC		(1 << 29)
176#define	OHCI_BUSBMC		(1 << 28)
177#define	OHCI_BUSPMC		(1 << 27)
178#define OHCI_BUSFNC		OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
179				OHCI_BUSBMC | OHCI_BUSPMC
180
181#define	OHCI_EUID_HI		0x24
182#define	OHCI_EUID_LO		0x28
183
184#define	OHCI_CROMPTR		0x34
185#define	OHCI_HCCCTL		0x50
186#define	OHCI_HCCCTLCLR		0x54
187#define	OHCI_AREQHI		0x100
188#define	OHCI_AREQHICLR		0x104
189#define	OHCI_AREQLO		0x108
190#define	OHCI_AREQLOCLR		0x10c
191#define	OHCI_PREQHI		0x110
192#define	OHCI_PREQHICLR		0x114
193#define	OHCI_PREQLO		0x118
194#define	OHCI_PREQLOCLR		0x11c
195#define	OHCI_PREQUPPER		0x120
196
197#define	OHCI_SID_BUF		0x64
198#define	OHCI_SID_CNT		0x68
199#define OHCI_SID_CNT_MASK	0xffc
200
201#define	OHCI_IT_STAT		0x90
202#define	OHCI_IT_STATCLR		0x94
203#define	OHCI_IT_MASK		0x98
204#define	OHCI_IT_MASKCLR		0x9c
205
206#define	OHCI_IR_STAT		0xa0
207#define	OHCI_IR_STATCLR		0xa4
208#define	OHCI_IR_MASK		0xa8
209#define	OHCI_IR_MASKCLR		0xac
210
211#define	OHCI_LNKCTL		0xe0
212#define	OHCI_LNKCTLCLR		0xe4
213
214#define	OHCI_PHYACCESS		0xec
215#define	OHCI_CYCLETIMER		0xf0
216
217#define	OHCI_DMACTL(off)	(off)
218#define	OHCI_DMACTLCLR(off)	(off + 4)
219#define	OHCI_DMACMD(off)	(off + 0xc)
220#define	OHCI_DMAMATCH(off)	(off + 0x10)
221
222#define OHCI_ATQOFF		0x180
223#define OHCI_ATQCTL		OHCI_ATQOFF
224#define OHCI_ATQCTLCLR		(OHCI_ATQOFF + 4)
225#define OHCI_ATQCMD		(OHCI_ATQOFF + 0xc)
226#define OHCI_ATQMATCH		(OHCI_ATQOFF + 0x10)
227
228#define OHCI_ATSOFF		0x1a0
229#define OHCI_ATSCTL		OHCI_ATSOFF
230#define OHCI_ATSCTLCLR		(OHCI_ATSOFF + 4)
231#define OHCI_ATSCMD		(OHCI_ATSOFF + 0xc)
232#define OHCI_ATSMATCH		(OHCI_ATSOFF + 0x10)
233
234#define OHCI_ARQOFF		0x1c0
235#define OHCI_ARQCTL		OHCI_ARQOFF
236#define OHCI_ARQCTLCLR		(OHCI_ARQOFF + 4)
237#define OHCI_ARQCMD		(OHCI_ARQOFF + 0xc)
238#define OHCI_ARQMATCH		(OHCI_ARQOFF + 0x10)
239
240#define OHCI_ARSOFF		0x1e0
241#define OHCI_ARSCTL		OHCI_ARSOFF
242#define OHCI_ARSCTLCLR		(OHCI_ARSOFF + 4)
243#define OHCI_ARSCMD		(OHCI_ARSOFF + 0xc)
244#define OHCI_ARSMATCH		(OHCI_ARSOFF + 0x10)
245
246#define OHCI_ITOFF(CH)		(0x200 + 0x10 * (CH))
247#define OHCI_ITCTL(CH)		(OHCI_ITOFF(CH))
248#define OHCI_ITCTLCLR(CH)	(OHCI_ITOFF(CH) + 4)
249#define OHCI_ITCMD(CH)		(OHCI_ITOFF(CH) + 0xc)
250
251#define OHCI_IROFF(CH)		(0x400 + 0x20 * (CH))
252#define OHCI_IRCTL(CH)		(OHCI_IROFF(CH))
253#define OHCI_IRCTLCLR(CH)	(OHCI_IROFF(CH) + 4)
254#define OHCI_IRCMD(CH)		(OHCI_IROFF(CH) + 0xc)
255#define OHCI_IRMATCH(CH)	(OHCI_IROFF(CH) + 0x10)
256
257d_ioctl_t fwohci_ioctl;
258
259/*
260 * Communication with PHY device
261 */
262static u_int32_t
263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
264{
265	u_int32_t fun;
266
267	addr &= 0xf;
268	data &= 0xff;
269
270	fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
271	OWRITE(sc, OHCI_PHYACCESS, fun);
272	DELAY(100);
273
274	return(fwphy_rddata( sc, addr));
275}
276
277static u_int32_t
278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
279{
280	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
281	int i;
282	u_int32_t bm;
283
284#define OHCI_CSR_DATA	0x0c
285#define OHCI_CSR_COMP	0x10
286#define OHCI_CSR_CONT	0x14
287#define OHCI_BUS_MANAGER_ID	0
288
289	OWRITE(sc, OHCI_CSR_DATA, node);
290	OWRITE(sc, OHCI_CSR_COMP, 0x3f);
291	OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
292 	for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
293		DELAY(10);
294	bm = OREAD(sc, OHCI_CSR_DATA);
295	if((bm & 0x3f) == 0x3f)
296		bm = node;
297	if (bootverbose)
298		device_printf(sc->fc.dev,
299			"fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
300
301	return(bm);
302}
303
304static u_int32_t
305fwphy_rddata(struct fwohci_softc *sc,  u_int addr)
306{
307	u_int32_t fun, stat;
308	u_int i, retry = 0;
309
310	addr &= 0xf;
311#define MAX_RETRY 100
312again:
313	OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
314	fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
315	OWRITE(sc, OHCI_PHYACCESS, fun);
316	for ( i = 0 ; i < MAX_RETRY ; i ++ ){
317		fun = OREAD(sc, OHCI_PHYACCESS);
318		if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
319			break;
320		DELAY(100);
321	}
322	if(i >= MAX_RETRY) {
323		if (bootverbose)
324			device_printf(sc->fc.dev, "phy read failed(1).\n");
325		if (++retry < MAX_RETRY) {
326			DELAY(100);
327			goto again;
328		}
329	}
330	/* Make sure that SCLK is started */
331	stat = OREAD(sc, FWOHCI_INTSTAT);
332	if ((stat & OHCI_INT_REG_FAIL) != 0 ||
333			((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
334		if (bootverbose)
335			device_printf(sc->fc.dev, "phy read failed(2).\n");
336		if (++retry < MAX_RETRY) {
337			DELAY(100);
338			goto again;
339		}
340	}
341	if (bootverbose || retry >= MAX_RETRY)
342		device_printf(sc->fc.dev,
343			"fwphy_rddata: loop=%d, retry=%d\n", i, retry);
344#undef MAX_RETRY
345	return((fun >> PHYDEV_RDDATA )& 0xff);
346}
347/* Device specific ioctl. */
348int
349fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
350{
351	struct firewire_softc *sc;
352	struct fwohci_softc *fc;
353	int unit = DEV2UNIT(dev);
354	int err = 0;
355	struct fw_reg_req_t *reg  = (struct fw_reg_req_t *) data;
356	u_int32_t *dmach = (u_int32_t *) data;
357
358	sc = devclass_get_softc(firewire_devclass, unit);
359	if(sc == NULL){
360		return(EINVAL);
361	}
362	fc = (struct fwohci_softc *)sc->fc;
363
364	if (!data)
365		return(EINVAL);
366
367	switch (cmd) {
368	case FWOHCI_WRREG:
369#define OHCI_MAX_REG 0x800
370		if(reg->addr <= OHCI_MAX_REG){
371			OWRITE(fc, reg->addr, reg->data);
372			reg->data = OREAD(fc, reg->addr);
373		}else{
374			err = EINVAL;
375		}
376		break;
377	case FWOHCI_RDREG:
378		if(reg->addr <= OHCI_MAX_REG){
379			reg->data = OREAD(fc, reg->addr);
380		}else{
381			err = EINVAL;
382		}
383		break;
384/* Read DMA descriptors for debug  */
385	case DUMPDMA:
386		if(*dmach <= OHCI_MAX_DMA_CH ){
387			dump_dma(fc, *dmach);
388			dump_db(fc, *dmach);
389		}else{
390			err = EINVAL;
391		}
392		break;
393	default:
394		break;
395	}
396	return err;
397}
398
399static int
400fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
401{
402	u_int32_t reg, reg2;
403	int e1394a = 1;
404/*
405 * probe PHY parameters
406 * 0. to prove PHY version, whether compliance of 1394a.
407 * 1. to probe maximum speed supported by the PHY and
408 *    number of port supported by core-logic.
409 *    It is not actually available port on your PC .
410 */
411	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
412#if 0
413	/* XXX wait for SCLK. */
414	DELAY(100000);
415#endif
416	reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
417
418	if((reg >> 5) != 7 ){
419		sc->fc.mode &= ~FWPHYASYST;
420		sc->fc.nport = reg & FW_PHY_NP;
421		sc->fc.speed = reg & FW_PHY_SPD >> 6;
422		if (sc->fc.speed > MAX_SPEED) {
423			device_printf(dev, "invalid speed %d (fixed to %d).\n",
424				sc->fc.speed, MAX_SPEED);
425			sc->fc.speed = MAX_SPEED;
426		}
427		device_printf(dev,
428			"Phy 1394 only %s, %d ports.\n",
429			linkspeed[sc->fc.speed], sc->fc.nport);
430	}else{
431		reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
432		sc->fc.mode |= FWPHYASYST;
433		sc->fc.nport = reg & FW_PHY_NP;
434		sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
435		if (sc->fc.speed > MAX_SPEED) {
436			device_printf(dev, "invalid speed %d (fixed to %d).\n",
437				sc->fc.speed, MAX_SPEED);
438			sc->fc.speed = MAX_SPEED;
439		}
440		device_printf(dev,
441			"Phy 1394a available %s, %d ports.\n",
442			linkspeed[sc->fc.speed], sc->fc.nport);
443
444		/* check programPhyEnable */
445		reg2 = fwphy_rddata(sc, 5);
446#if 0
447		if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
448#else	/* XXX force to enable 1394a */
449		if (e1394a) {
450#endif
451			if (bootverbose)
452				device_printf(dev,
453					"Enable 1394a Enhancements\n");
454			/* enable EAA EMC */
455			reg2 |= 0x03;
456			/* set aPhyEnhanceEnable */
457			OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
458			OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
459		} else {
460			/* for safe */
461			reg2 &= ~0x83;
462		}
463		reg2 = fwphy_wrdata(sc, 5, reg2);
464	}
465
466	reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
467	if((reg >> 5) == 7 ){
468		reg = fwphy_rddata(sc, 4);
469		reg |= 1 << 6;
470		fwphy_wrdata(sc, 4, reg);
471		reg = fwphy_rddata(sc, 4);
472	}
473	return 0;
474}
475
476
477void
478fwohci_reset(struct fwohci_softc *sc, device_t dev)
479{
480	int i, max_rec, speed;
481	u_int32_t reg, reg2;
482	struct fwohcidb_tr *db_tr;
483
484	/* Disable interrupt */
485	OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
486
487	/* Now stopping all DMA channel */
488	OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
489	OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
490	OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
491	OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
492
493	OWRITE(sc,  OHCI_IR_MASKCLR, ~0);
494	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
495		OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
496		OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
497	}
498
499	/* FLUSH FIFO and reset Transmitter/Reciever */
500	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
501	if (bootverbose)
502		device_printf(dev, "resetting OHCI...");
503	i = 0;
504	while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
505		if (i++ > 100) break;
506		DELAY(1000);
507	}
508	if (bootverbose)
509		printf("done (loop=%d)\n", i);
510
511	/* Probe phy */
512	fwohci_probe_phy(sc, dev);
513
514	/* Probe link */
515	reg = OREAD(sc,  OHCI_BUS_OPT);
516	reg2 = reg | OHCI_BUSFNC;
517	max_rec = (reg & 0x0000f000) >> 12;
518	speed = (reg & 0x00000007);
519	device_printf(dev, "Link %s, max_rec %d bytes.\n",
520			linkspeed[speed], MAXREC(max_rec));
521	/* XXX fix max_rec */
522	sc->fc.maxrec = sc->fc.speed + 8;
523	if (max_rec != sc->fc.maxrec) {
524		reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
525		device_printf(dev, "max_rec %d -> %d\n",
526				MAXREC(max_rec), MAXREC(sc->fc.maxrec));
527	}
528	if (bootverbose)
529		device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
530	OWRITE(sc,  OHCI_BUS_OPT, reg2);
531
532	/* Initialize registers */
533	OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
534	OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
535	OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
536	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
537	OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
538	OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
539	fw_busreset(&sc->fc);
540
541	/* Enable link */
542	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
543
544	/* Force to start async RX DMA */
545	sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
546	sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
547	fwohci_rx_enable(sc, &sc->arrq);
548	fwohci_rx_enable(sc, &sc->arrs);
549
550	/* Initialize async TX */
551	OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
552	OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
553	/* AT Retries */
554	OWRITE(sc, FWOHCI_RETRY,
555		/* CycleLimit   PhyRespRetries ATRespRetries ATReqRetries */
556		(0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
557	for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
558				i ++, db_tr = STAILQ_NEXT(db_tr, link)){
559		db_tr->xfer = NULL;
560	}
561	for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
562				i ++, db_tr = STAILQ_NEXT(db_tr, link)){
563		db_tr->xfer = NULL;
564	}
565
566
567	/* Enable interrupt */
568	OWRITE(sc, FWOHCI_INTMASK,
569			OHCI_INT_ERR  | OHCI_INT_PHY_SID
570			| OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
571			| OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
572			| OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
573	fwohci_set_intr(&sc->fc, 1);
574
575}
576
577int
578fwohci_init(struct fwohci_softc *sc, device_t dev)
579{
580	int i;
581	u_int32_t reg;
582
583	reg = OREAD(sc, OHCI_VERSION);
584	device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
585			(reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
586
587/* XXX: Available Isochrounous DMA channel probe */
588	for( i = 0 ; i < 0x20 ; i ++ ){
589		OWRITE(sc,  OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN);
590		reg = OREAD(sc, OHCI_IRCTL(i));
591		if(!(reg & OHCI_CNTL_DMA_RUN)) break;
592		OWRITE(sc,  OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN);
593		reg = OREAD(sc, OHCI_ITCTL(i));
594		if(!(reg & OHCI_CNTL_DMA_RUN)) break;
595	}
596	sc->fc.nisodma = i;
597	device_printf(dev, "No. of Isochronous channel is %d.\n", i);
598
599	sc->fc.arq = &sc->arrq.xferq;
600	sc->fc.ars = &sc->arrs.xferq;
601	sc->fc.atq = &sc->atrq.xferq;
602	sc->fc.ats = &sc->atrs.xferq;
603
604	sc->arrq.xferq.start = NULL;
605	sc->arrs.xferq.start = NULL;
606	sc->atrq.xferq.start = fwohci_start_atq;
607	sc->atrs.xferq.start = fwohci_start_ats;
608
609	sc->arrq.xferq.drain = NULL;
610	sc->arrs.xferq.drain = NULL;
611	sc->atrq.xferq.drain = fwohci_drain_atq;
612	sc->atrs.xferq.drain = fwohci_drain_ats;
613
614	sc->arrq.ndesc = 1;
615	sc->arrs.ndesc = 1;
616	sc->atrq.ndesc = 6;	/* equal to maximum of mbuf chains */
617	sc->atrs.ndesc = 6 / 2;
618
619	sc->arrq.ndb = NDB;
620	sc->arrs.ndb = NDB / 2;
621	sc->atrq.ndb = NDB;
622	sc->atrs.ndb = NDB / 2;
623
624	sc->arrq.dummy = NULL;
625	sc->arrs.dummy = NULL;
626	sc->atrq.dummy = NULL;
627	sc->atrs.dummy = NULL;
628	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
629		sc->fc.it[i] = &sc->it[i].xferq;
630		sc->fc.ir[i] = &sc->ir[i].xferq;
631		sc->it[i].ndb = 0;
632		sc->ir[i].ndb = 0;
633	}
634
635	sc->fc.tcode = tinfo;
636
637	sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT);
638
639	if(sc->cromptr == NULL){
640		device_printf(dev, "cromptr alloc failed.");
641		return ENOMEM;
642	}
643	sc->fc.dev = dev;
644	sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]);
645
646	sc->fc.config_rom[1] = 0x31333934;
647	sc->fc.config_rom[2] = 0xf000a002;
648	sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
649	sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
650	sc->fc.config_rom[5] = 0;
651	sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
652
653	sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
654
655
656/* SID recieve buffer must allign 2^11 */
657#define	OHCI_SIDSIZE	(1 << 11)
658	sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT);
659	if (sc->fc.sid_buf == NULL) {
660		device_printf(dev, "sid_buf alloc failed.\n");
661		return ENOMEM;
662	}
663
664
665	fwohci_db_init(&sc->arrq);
666	if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
667		return ENOMEM;
668
669	fwohci_db_init(&sc->arrs);
670	if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
671		return ENOMEM;
672
673	fwohci_db_init(&sc->atrq);
674	if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
675		return ENOMEM;
676
677	fwohci_db_init(&sc->atrs);
678	if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
679		return ENOMEM;
680
681	reg = OREAD(sc, FWOHCIGUID_H);
682	for( i = 0 ; i < 4 ; i ++){
683		sc->fc.eui[3 - i] = reg & 0xff;
684		reg = reg >> 8;
685	}
686	reg = OREAD(sc, FWOHCIGUID_L);
687	for( i = 0 ; i < 4 ; i ++){
688		sc->fc.eui[7 - i] = reg & 0xff;
689		reg = reg >> 8;
690	}
691	device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
692		sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3],
693		sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]);
694	sc->fc.ioctl = fwohci_ioctl;
695	sc->fc.cyctimer = fwohci_cyctimer;
696	sc->fc.set_bmr = fwohci_set_bus_manager;
697	sc->fc.ibr = fwohci_ibr;
698	sc->fc.irx_enable = fwohci_irx_enable;
699	sc->fc.irx_disable = fwohci_irx_disable;
700
701	sc->fc.itx_enable = fwohci_itxbuf_enable;
702	sc->fc.itx_disable = fwohci_itx_disable;
703	sc->fc.irx_post = fwohci_irx_post;
704	sc->fc.itx_post = NULL;
705	sc->fc.timeout = fwohci_timeout;
706	sc->fc.poll = fwohci_poll;
707	sc->fc.set_intr = fwohci_set_intr;
708
709	fw_init(&sc->fc);
710	fwohci_reset(sc, dev);
711
712	return 0;
713}
714
715void
716fwohci_timeout(void *arg)
717{
718	struct fwohci_softc *sc;
719
720	sc = (struct fwohci_softc *)arg;
721	sc->fc.timeouthandle = timeout(fwohci_timeout,
722				(void *)sc, FW_XFERTIMEOUT * hz * 10);
723}
724
725u_int32_t
726fwohci_cyctimer(struct firewire_comm *fc)
727{
728	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
729	return(OREAD(sc, OHCI_CYCLETIMER));
730}
731
732int
733fwohci_detach(struct fwohci_softc *sc, device_t dev)
734{
735	int i;
736
737	if (sc->fc.sid_buf != NULL)
738		free((void *)(uintptr_t)sc->fc.sid_buf, M_DEVBUF);
739	if (sc->cromptr != NULL)
740		free((void *)sc->cromptr, M_DEVBUF);
741
742	fwohci_db_free(&sc->arrq);
743	fwohci_db_free(&sc->arrs);
744
745	fwohci_db_free(&sc->atrq);
746	fwohci_db_free(&sc->atrs);
747
748	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
749		fwohci_db_free(&sc->it[i]);
750		fwohci_db_free(&sc->ir[i]);
751	}
752
753	return 0;
754}
755
756#define LAST_DB(dbtr, db) do {						\
757	struct fwohcidb_tr *_dbtr = (dbtr);				\
758	int _cnt = _dbtr->dbcnt;					\
759	db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0];			\
760} while (0)
761
762static void
763fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
764{
765	int i, s;
766	int tcode, hdr_len, hdr_off, len;
767	int fsegment = -1;
768	u_int32_t off;
769	struct fw_xfer *xfer;
770	struct fw_pkt *fp;
771	volatile struct fwohci_txpkthdr *ohcifp;
772	struct fwohcidb_tr *db_tr;
773	volatile struct fwohcidb *db;
774	struct mbuf *m;
775	struct tcode_info *info;
776	static int maxdesc=0;
777
778	if(&sc->atrq == dbch){
779		off = OHCI_ATQOFF;
780	}else if(&sc->atrs == dbch){
781		off = OHCI_ATSOFF;
782	}else{
783		return;
784	}
785
786	if (dbch->flags & FWOHCI_DBCH_FULL)
787		return;
788
789	s = splfw();
790	db_tr = dbch->top;
791txloop:
792	xfer = STAILQ_FIRST(&dbch->xferq.q);
793	if(xfer == NULL){
794		goto kick;
795	}
796	if(dbch->xferq.queued == 0 ){
797		device_printf(sc->fc.dev, "TX queue empty\n");
798	}
799	STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
800	db_tr->xfer = xfer;
801	xfer->state = FWXF_START;
802	dbch->xferq.packets++;
803
804	fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off);
805	tcode = fp->mode.common.tcode;
806
807	ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
808	info = &tinfo[tcode];
809	hdr_len = hdr_off = info->hdr_len;
810	/* fw_asyreq must pass valid send.len */
811	len = xfer->send.len;
812	for( i = 0 ; i < hdr_off ; i+= 4){
813		ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]);
814	}
815	ohcifp->mode.common.spd = xfer->spd;
816	if (tcode == FWTCODE_STREAM ){
817		hdr_len = 8;
818		ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
819	} else if (tcode == FWTCODE_PHY) {
820		hdr_len = 12;
821		ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]);
822		ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]);
823		ohcifp->mode.common.spd = 0;
824		ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
825	} else {
826		ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst);
827		ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
828		ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
829	}
830	db = &db_tr->db[0];
831 	db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len;
832 	db->db.desc.status = 0;
833/* Specify bound timer of asy. responce */
834	if(&sc->atrs == dbch){
835 		db->db.desc.count
836			 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13);
837	}
838
839	db_tr->dbcnt = 2;
840	db = &db_tr->db[db_tr->dbcnt];
841	if(len > hdr_off){
842		if (xfer->mbuf == NULL) {
843			db->db.desc.addr
844				= vtophys(xfer->send.buf + xfer->send.off) + hdr_off;
845			db->db.desc.cmd
846				= OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff);
847 			db->db.desc.status = 0;
848
849			db_tr->dbcnt++;
850		} else {
851			/* XXX we assume mbuf chain is shorter than ndesc */
852			for (m = xfer->mbuf; m != NULL; m = m->m_next) {
853				if (m->m_len == 0)
854					/* unrecoverable error could ocurre. */
855					continue;
856				if (db_tr->dbcnt >= dbch->ndesc) {
857					device_printf(sc->fc.dev,
858						"dbch->ndesc is too small"
859						", trancated.\n");
860					break;
861				}
862				db->db.desc.addr
863					= vtophys(mtod(m, caddr_t));
864				db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len;
865 				db->db.desc.status = 0;
866				db++;
867				db_tr->dbcnt++;
868			}
869		}
870	}
871	if (maxdesc < db_tr->dbcnt) {
872		maxdesc = db_tr->dbcnt;
873		if (bootverbose)
874			device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
875	}
876	/* last db */
877	LAST_DB(db_tr, db);
878 	db->db.desc.cmd |= OHCI_OUTPUT_LAST
879			| OHCI_INTERRUPT_ALWAYS
880			| OHCI_BRANCH_ALWAYS;
881 	db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db);
882
883	if(fsegment == -1 )
884		fsegment = db_tr->dbcnt;
885	if (dbch->pdb_tr != NULL) {
886		LAST_DB(dbch->pdb_tr, db);
887 		db->db.desc.depend |= db_tr->dbcnt;
888	}
889	dbch->pdb_tr = db_tr;
890	db_tr = STAILQ_NEXT(db_tr, link);
891	if(db_tr != dbch->bottom){
892		goto txloop;
893	} else {
894		device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
895		dbch->flags |= FWOHCI_DBCH_FULL;
896	}
897kick:
898	if (firewire_debug) printf("kick\n");
899	/* kick asy q */
900
901	if(dbch->xferq.flag & FWXFERQ_RUNNING) {
902		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
903	} else {
904		if (bootverbose)
905			device_printf(sc->fc.dev, "start AT DMA status=%x\n",
906					OREAD(sc, OHCI_DMACTL(off)));
907		OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment);
908		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
909		dbch->xferq.flag |= FWXFERQ_RUNNING;
910	}
911
912	dbch->top = db_tr;
913	splx(s);
914	return;
915}
916
917static void
918fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer)
919{
920	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
921	fwohci_drain(&sc->fc, xfer, &(sc->atrq));
922	return;
923}
924
925static void
926fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer)
927{
928	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
929	fwohci_drain(&sc->fc, xfer, &(sc->atrs));
930	return;
931}
932
933static void
934fwohci_start_atq(struct firewire_comm *fc)
935{
936	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
937	fwohci_start( sc, &(sc->atrq));
938	return;
939}
940
941static void
942fwohci_start_ats(struct firewire_comm *fc)
943{
944	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
945	fwohci_start( sc, &(sc->atrs));
946	return;
947}
948
949void
950fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
951{
952	int s, err = 0;
953	struct fwohcidb_tr *tr;
954	volatile struct fwohcidb *db;
955	struct fw_xfer *xfer;
956	u_int32_t off;
957	u_int stat;
958	int	packets;
959	struct firewire_comm *fc = (struct firewire_comm *)sc;
960	if(&sc->atrq == dbch){
961		off = OHCI_ATQOFF;
962	}else if(&sc->atrs == dbch){
963		off = OHCI_ATSOFF;
964	}else{
965		return;
966	}
967	s = splfw();
968	tr = dbch->bottom;
969	packets = 0;
970	while(dbch->xferq.queued > 0){
971		LAST_DB(tr, db);
972		if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){
973			if (fc->status != FWBUSRESET)
974				/* maybe out of order?? */
975				goto out;
976		}
977		if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) {
978#ifdef OHCI_DEBUG
979			dump_dma(sc, ch);
980			dump_db(sc, ch);
981#endif
982/* Stop DMA */
983			OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
984			device_printf(sc->fc.dev, "force reset AT FIFO\n");
985			OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
986			OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
987			OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
988		}
989		stat = db->db.desc.status & FWOHCIEV_MASK;
990		switch(stat){
991		case FWOHCIEV_ACKCOMPL:
992		case FWOHCIEV_ACKPEND:
993			err = 0;
994			break;
995		case FWOHCIEV_ACKBSA:
996		case FWOHCIEV_ACKBSB:
997			device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
998		case FWOHCIEV_ACKBSX:
999			err = EBUSY;
1000			break;
1001		case FWOHCIEV_FLUSHED:
1002		case FWOHCIEV_ACKTARD:
1003			device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1004			err = EAGAIN;
1005			break;
1006		case FWOHCIEV_MISSACK:
1007		case FWOHCIEV_UNDRRUN:
1008		case FWOHCIEV_OVRRUN:
1009		case FWOHCIEV_DESCERR:
1010		case FWOHCIEV_DTRDERR:
1011		case FWOHCIEV_TIMEOUT:
1012		case FWOHCIEV_TCODERR:
1013		case FWOHCIEV_UNKNOWN:
1014		case FWOHCIEV_ACKDERR:
1015		case FWOHCIEV_ACKTERR:
1016		default:
1017			device_printf(sc->fc.dev, "txd err=%2x %s\n",
1018							stat, fwohcicode[stat]);
1019			err = EINVAL;
1020			break;
1021		}
1022		if(tr->xfer != NULL){
1023			xfer = tr->xfer;
1024			xfer->state = FWXF_SENT;
1025			if(err == EBUSY && fc->status != FWBUSRESET){
1026				xfer->state = FWXF_BUSY;
1027				switch(xfer->act_type){
1028				case FWACT_XFER:
1029					xfer->resp = err;
1030					if(xfer->retry_req != NULL){
1031						xfer->retry_req(xfer);
1032					}
1033					break;
1034				default:
1035					break;
1036				}
1037			} else if( stat != FWOHCIEV_ACKPEND){
1038				if (stat != FWOHCIEV_ACKCOMPL)
1039					xfer->state = FWXF_SENTERR;
1040				xfer->resp = err;
1041				switch(xfer->act_type){
1042				case FWACT_XFER:
1043					fw_xfer_done(xfer);
1044					break;
1045				default:
1046					break;
1047				}
1048			}
1049			dbch->xferq.queued --;
1050		}
1051		tr->xfer = NULL;
1052
1053		packets ++;
1054		tr = STAILQ_NEXT(tr, link);
1055		dbch->bottom = tr;
1056	}
1057out:
1058	if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1059		printf("make free slot\n");
1060		dbch->flags &= ~FWOHCI_DBCH_FULL;
1061		fwohci_start(sc, dbch);
1062	}
1063	splx(s);
1064}
1065
1066static void
1067fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch)
1068{
1069	int i, s;
1070	struct fwohcidb_tr *tr;
1071
1072	if(xfer->state != FWXF_START) return;
1073
1074	s = splfw();
1075	tr = dbch->bottom;
1076	for( i = 0 ; i <= dbch->xferq.queued  ; i ++){
1077		if(tr->xfer == xfer){
1078			s = splfw();
1079			tr->xfer = NULL;
1080			dbch->xferq.queued --;
1081#if 1
1082			/* XXX */
1083			if (tr == dbch->bottom)
1084				dbch->bottom = STAILQ_NEXT(tr, link);
1085#endif
1086			if (dbch->flags & FWOHCI_DBCH_FULL) {
1087				printf("fwohci_drain: make slot\n");
1088				dbch->flags &= ~FWOHCI_DBCH_FULL;
1089				fwohci_start((struct fwohci_softc *)fc, dbch);
1090			}
1091
1092			splx(s);
1093			break;
1094		}
1095		tr = STAILQ_NEXT(tr, link);
1096	}
1097	splx(s);
1098	return;
1099}
1100
1101static void
1102fwohci_db_free(struct fwohci_dbch *dbch)
1103{
1104	struct fwohcidb_tr *db_tr;
1105	int idb, i;
1106
1107	if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1108		return;
1109
1110	if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1111		for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0;
1112			idb < dbch->ndb;
1113			db_tr = STAILQ_NEXT(db_tr, link), idb++){
1114			if (db_tr->buf != NULL) {
1115				free(db_tr->buf, M_DEVBUF);
1116				db_tr->buf = NULL;
1117			}
1118		}
1119	}
1120	dbch->ndb = 0;
1121	db_tr = STAILQ_FIRST(&dbch->db_trq);
1122	for (i = 0; i < dbch->npages; i++)
1123		free(dbch->pages[i], M_DEVBUF);
1124	free(db_tr, M_DEVBUF);
1125	STAILQ_INIT(&dbch->db_trq);
1126	dbch->flags &= ~FWOHCI_DBCH_INIT;
1127}
1128
1129static void
1130fwohci_db_init(struct fwohci_dbch *dbch)
1131{
1132	int	idb;
1133	struct fwohcidb_tr *db_tr;
1134	int	ndbpp, i, j;
1135
1136	if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1137		goto out;
1138
1139	/* allocate DB entries and attach one to each DMA channels */
1140	/* DB entry must start at 16 bytes bounary. */
1141	STAILQ_INIT(&dbch->db_trq);
1142	db_tr = (struct fwohcidb_tr *)
1143		malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1144		M_DEVBUF, M_NOWAIT | M_ZERO);
1145	if(db_tr == NULL){
1146		printf("fwohci_db_init: malloc(1) failed\n");
1147		return;
1148	}
1149
1150	ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc);
1151	dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp;
1152	if (firewire_debug)
1153		printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n",
1154			dbch->ndesc, ndbpp, dbch->ndb, dbch->npages);
1155	if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) {
1156		printf("npages(%d) > DBCH_MAX_PAGES(%d)\n",
1157				dbch->npages, FWOHCI_DBCH_MAX_PAGES);
1158		return;
1159	}
1160	for (i = 0; i < dbch->npages; i++) {
1161		dbch->pages[i] = malloc(PAGE_SIZE, M_DEVBUF,
1162						M_NOWAIT | M_ZERO);
1163		if (dbch->pages[i] == NULL) {
1164			printf("fwohci_db_init: malloc(2) failed\n");
1165			for (j = 0; j < i; j ++)
1166				free(dbch->pages[j], M_DEVBUF);
1167			free(db_tr, M_DEVBUF);
1168			return;
1169		}
1170	}
1171	/* Attach DB to DMA ch. */
1172	for(idb = 0 ; idb < dbch->ndb ; idb++){
1173		db_tr->dbcnt = 0;
1174		db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp]
1175					+ dbch->ndesc * (idb % ndbpp);
1176		STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1177		if (!(dbch->xferq.flag & FWXFERQ_PACKET) &&
1178					dbch->xferq.bnpacket != 0) {
1179			if (idb % dbch->xferq.bnpacket == 0)
1180				dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1181						].start = (caddr_t)db_tr;
1182			if ((idb + 1) % dbch->xferq.bnpacket == 0)
1183				dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1184						].end = (caddr_t)db_tr;
1185		}
1186		db_tr++;
1187	}
1188	STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1189			= STAILQ_FIRST(&dbch->db_trq);
1190out:
1191	dbch->frag.buf = NULL;
1192	dbch->frag.len = 0;
1193	dbch->frag.plen = 0;
1194	dbch->xferq.queued = 0;
1195	dbch->pdb_tr = NULL;
1196	dbch->top = STAILQ_FIRST(&dbch->db_trq);
1197	dbch->bottom = dbch->top;
1198	dbch->flags = FWOHCI_DBCH_INIT;
1199}
1200
1201static int
1202fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1203{
1204	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1205	OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1206	OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1207	OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1208	fwohci_db_free(&sc->it[dmach]);
1209	sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1210	return 0;
1211}
1212
1213static int
1214fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1215{
1216	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1217
1218	OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1219	OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1220	OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1221	if(sc->ir[dmach].dummy != NULL){
1222		free(sc->ir[dmach].dummy, M_DEVBUF);
1223	}
1224	sc->ir[dmach].dummy = NULL;
1225	fwohci_db_free(&sc->ir[dmach]);
1226	sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1227	return 0;
1228}
1229
1230static void
1231fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1232{
1233	qld[0] = ntohl(qld[0]);
1234	return;
1235}
1236
1237static int
1238fwohci_irxpp_enable(struct firewire_comm *fc, int dmach)
1239{
1240	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1241	int err = 0;
1242	unsigned short tag, ich;
1243
1244	tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1245	ich = sc->ir[dmach].xferq.flag & 0x3f;
1246
1247#if 0
1248	if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){
1249		wakeup(fc->ir[dmach]);
1250		return err;
1251	}
1252#endif
1253
1254	OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1255	if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1256		sc->ir[dmach].xferq.queued = 0;
1257		sc->ir[dmach].ndb = NDB;
1258		sc->ir[dmach].xferq.psize = PAGE_SIZE;
1259		sc->ir[dmach].ndesc = 1;
1260		fwohci_db_init(&sc->ir[dmach]);
1261		if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0)
1262			return ENOMEM;
1263		err = fwohci_rx_enable(sc, &sc->ir[dmach]);
1264	}
1265	if(err){
1266		device_printf(sc->fc.dev, "err in IRX setting\n");
1267		return err;
1268	}
1269	if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1270		OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1271		OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1272		OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1273		OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1274		OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000);
1275		OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1276		OWRITE(sc, OHCI_IRCMD(dmach),
1277			vtophys(sc->ir[dmach].top->db) | 1);
1278		OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1279		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1280	}
1281	return err;
1282}
1283
1284static int
1285fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1286{
1287	int err = 0;
1288	int idb, z, i, dmach = 0;
1289	u_int32_t off = NULL;
1290	struct fwohcidb_tr *db_tr;
1291
1292	if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1293		err = EINVAL;
1294		return err;
1295	}
1296	z = dbch->ndesc;
1297	for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1298		if( &sc->it[dmach] == dbch){
1299			off = OHCI_ITOFF(dmach);
1300			break;
1301		}
1302	}
1303	if(off == NULL){
1304		err = EINVAL;
1305		return err;
1306	}
1307	if(dbch->xferq.flag & FWXFERQ_RUNNING)
1308		return err;
1309	dbch->xferq.flag |= FWXFERQ_RUNNING;
1310	for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1311		dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1312	}
1313	db_tr = dbch->top;
1314	for( idb = 0 ; idb < dbch->ndb ; idb ++){
1315		fwohci_add_tx_buf(db_tr,
1316			dbch->xferq.psize, dbch->xferq.flag,
1317			dbch->xferq.buf + dbch->xferq.psize * idb);
1318		if(STAILQ_NEXT(db_tr, link) == NULL){
1319			break;
1320		}
1321		db_tr->db[0].db.desc.depend
1322			= vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1323		db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1324			= vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1325		if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1326			if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1327				db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1328					|= OHCI_INTERRUPT_ALWAYS;
1329				db_tr->db[0].db.desc.depend &= ~0xf;
1330				db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1331						~0xf;
1332				/* OHCI 1.1 and above */
1333				db_tr->db[0].db.desc.cmd
1334					|= OHCI_INTERRUPT_ALWAYS;
1335			}
1336		}
1337		db_tr = STAILQ_NEXT(db_tr, link);
1338	}
1339	dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1340	return err;
1341}
1342
1343static int
1344fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1345{
1346	int err = 0;
1347	int idb, z, i, dmach = 0;
1348	u_int32_t off = NULL;
1349	struct fwohcidb_tr *db_tr;
1350
1351	z = dbch->ndesc;
1352	if(&sc->arrq == dbch){
1353		off = OHCI_ARQOFF;
1354	}else if(&sc->arrs == dbch){
1355		off = OHCI_ARSOFF;
1356	}else{
1357		for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1358			if( &sc->ir[dmach] == dbch){
1359				off = OHCI_IROFF(dmach);
1360				break;
1361			}
1362		}
1363	}
1364	if(off == NULL){
1365		err = EINVAL;
1366		return err;
1367	}
1368	if(dbch->xferq.flag & FWXFERQ_STREAM){
1369		if(dbch->xferq.flag & FWXFERQ_RUNNING)
1370			return err;
1371	}else{
1372		if(dbch->xferq.flag & FWXFERQ_RUNNING){
1373			err = EBUSY;
1374			return err;
1375		}
1376	}
1377	dbch->xferq.flag |= FWXFERQ_RUNNING;
1378	dbch->top = STAILQ_FIRST(&dbch->db_trq);
1379	for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1380		dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1381	}
1382	db_tr = dbch->top;
1383	for( idb = 0 ; idb < dbch->ndb ; idb ++){
1384		if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1385			fwohci_add_rx_buf(db_tr,
1386				dbch->xferq.psize, dbch->xferq.flag, 0, NULL);
1387		}else{
1388			fwohci_add_rx_buf(db_tr,
1389				dbch->xferq.psize, dbch->xferq.flag,
1390				dbch->xferq.buf + dbch->xferq.psize * idb,
1391				dbch->dummy + sizeof(u_int32_t) * idb);
1392		}
1393		if(STAILQ_NEXT(db_tr, link) == NULL){
1394			break;
1395		}
1396		db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1397			= vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1398		if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1399			if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1400				db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1401					|= OHCI_INTERRUPT_ALWAYS;
1402				db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1403						~0xf;
1404			}
1405		}
1406		db_tr = STAILQ_NEXT(db_tr, link);
1407	}
1408	dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1409	dbch->buf_offset = 0;
1410	if(dbch->xferq.flag & FWXFERQ_STREAM){
1411		return err;
1412	}else{
1413		OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z);
1414	}
1415	OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1416	return err;
1417}
1418
1419static int
1420fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1421{
1422	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1423	int err = 0;
1424	unsigned short tag, ich;
1425	struct fwohci_dbch *dbch;
1426	struct fw_pkt *fp;
1427	struct fwohcidb_tr *db_tr;
1428	int cycle_now, sec, cycle, cycle_match;
1429	u_int32_t stat;
1430
1431	tag = (sc->it[dmach].xferq.flag >> 6) & 3;
1432	ich = sc->it[dmach].xferq.flag & 0x3f;
1433	dbch = &sc->it[dmach];
1434	if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1435		dbch->xferq.queued = 0;
1436		dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk;
1437		dbch->ndesc = 3;
1438		fwohci_db_init(dbch);
1439		if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1440			return ENOMEM;
1441		err = fwohci_tx_enable(sc, dbch);
1442	}
1443	if(err)
1444		return err;
1445	stat = OREAD(sc, OHCI_ITCTL(dmach));
1446	if (stat & OHCI_CNTL_DMA_ACTIVE) {
1447		if(dbch->xferq.stdma2 != NULL){
1448			fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1449			((struct fwohcidb_tr *)
1450		(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1451			|= OHCI_BRANCH_ALWAYS;
1452			((struct fwohcidb_tr *)
1453		(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1454	    vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1455			((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1456	    vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1457			((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1458			((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1459		} else {
1460			device_printf(fc->dev,
1461				"fwohci_itxbuf_enable: queue underrun\n");
1462		}
1463		return err;
1464	}
1465	if (firewire_debug)
1466		printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1467	fw_tbuf_update(&sc->fc, dmach, 0);
1468	if(dbch->xferq.stdma == NULL){
1469		return err;
1470	}
1471	if(dbch->xferq.stdma2 == NULL){
1472		/* wait until 2 chunks buffered */
1473		return err;
1474	}
1475	OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1476	OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1477	OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1478	fwohci_txbufdb(sc, dmach, dbch->xferq.stdma);
1479	fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1480	((struct fwohcidb_tr *)
1481		(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1482			|= OHCI_BRANCH_ALWAYS;
1483	((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1484		    vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1485	((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1486		    vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1487	((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1488	((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1489	OWRITE(sc, OHCI_ITCMD(dmach),
1490		vtophys(((struct fwohcidb_tr *)
1491			(dbch->xferq.stdma->start))->db) | dbch->ndesc);
1492#define CYCLE_OFFSET	1
1493	if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1494		if(dbch->xferq.flag & FWXFERQ_DV){
1495			db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1496			fp = (struct fw_pkt *)db_tr->buf;
1497			dbch->xferq.dvoffset = CYCLE_OFFSET;
1498			fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12);
1499		}
1500		/* 2bit second + 13bit cycle */
1501		cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1502		cycle = cycle_now & 0x1fff;
1503		sec = cycle_now >> 13;
1504#define CYCLE_MOD	0x10
1505#define CYCLE_DELAY	8	/* min delay to start DMA */
1506		cycle = cycle + CYCLE_DELAY;
1507		if (cycle >= 8000) {
1508			sec ++;
1509			cycle -= 8000;
1510		}
1511		cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD;
1512		if (cycle >= 8000) {
1513			sec ++;
1514			if (cycle == 8000)
1515				cycle = 0;
1516			else
1517				cycle = CYCLE_MOD;
1518		}
1519		cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1520		/* Clear cycle match counter bits */
1521		OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1522		OWRITE(sc, OHCI_ITCTL(dmach),
1523				OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1524				| OHCI_CNTL_DMA_RUN);
1525		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1526		if (firewire_debug)
1527			printf("cycle_match: 0x%04x->0x%04x\n",
1528						cycle_now, cycle_match);
1529	} else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1530		if (firewire_debug)
1531			printf("fwohci_itxbuf_enable: restart 0x%08x\n", stat);
1532		OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1533		OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1534	}
1535	return err;
1536}
1537
1538static int
1539fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1540{
1541	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1542	int err = 0;
1543	unsigned short tag, ich;
1544
1545	if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1546		tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1547		ich = sc->ir[dmach].xferq.flag & 0x3f;
1548		OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1549
1550		sc->ir[dmach].xferq.queued = 0;
1551		sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket *
1552				sc->ir[dmach].xferq.bnchunk;
1553		sc->ir[dmach].dummy =
1554			malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb,
1555			   M_DEVBUF, M_NOWAIT);
1556		if(sc->ir[dmach].dummy == NULL){
1557			err = ENOMEM;
1558			return err;
1559		}
1560		sc->ir[dmach].ndesc = 2;
1561		fwohci_db_init(&sc->ir[dmach]);
1562		if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0)
1563			return ENOMEM;
1564		err = fwohci_rx_enable(sc, &sc->ir[dmach]);
1565	}
1566	if(err)
1567		return err;
1568
1569	if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){
1570		if(sc->ir[dmach].xferq.stdma2 != NULL){
1571			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend =
1572	    vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc;
1573			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend =
1574	    vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db);
1575			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1576			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1577		}
1578	}else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)
1579		&& !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){
1580		fw_rbuf_update(&sc->fc, dmach, 0);
1581
1582		OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1583		OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1584		OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1585		OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1586		OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1587		OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1588		if(sc->ir[dmach].xferq.stdma2 != NULL){
1589			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend =
1590		    vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc;
1591			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend =
1592		    vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db);
1593			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1594		}else{
1595			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1596			((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1597		}
1598		OWRITE(sc, OHCI_IRCMD(dmach),
1599			vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc);
1600		OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1601		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1602	}
1603	return err;
1604}
1605
1606static int
1607fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1608{
1609	struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1610	int err = 0;
1611
1612	if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){
1613		err = fwohci_irxpp_enable(fc, dmach);
1614		return err;
1615	}else{
1616		err = fwohci_irxbuf_enable(fc, dmach);
1617		return err;
1618	}
1619}
1620
1621int
1622fwohci_shutdown(struct fwohci_softc *sc, device_t dev)
1623{
1624	u_int i;
1625
1626/* Now stopping all DMA channel */
1627	OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1628	OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1629	OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1630	OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1631
1632	for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1633		OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1634		OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1635	}
1636
1637/* FLUSH FIFO and reset Transmitter/Reciever */
1638	OWRITE(sc,  OHCI_HCCCTL, OHCI_HCC_RESET);
1639
1640/* Stop interrupt */
1641	OWRITE(sc, FWOHCI_INTMASKCLR,
1642			OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1643			| OHCI_INT_PHY_INT
1644			| OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1645			| OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1646			| OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1647			| OHCI_INT_PHY_BUS_R);
1648/* XXX Link down?  Bus reset? */
1649	return 0;
1650}
1651
1652int
1653fwohci_resume(struct fwohci_softc *sc, device_t dev)
1654{
1655	int i;
1656
1657	fwohci_reset(sc, dev);
1658	/* XXX resume isochronus receive automatically. (how about TX?) */
1659	for(i = 0; i < sc->fc.nisodma; i ++) {
1660		if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) {
1661			device_printf(sc->fc.dev,
1662				"resume iso receive ch: %d\n", i);
1663			sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING;
1664			sc->fc.irx_enable(&sc->fc, i);
1665		}
1666	}
1667
1668	bus_generic_resume(dev);
1669	sc->fc.ibr(&sc->fc);
1670	return 0;
1671}
1672
1673#define ACK_ALL
1674static void
1675fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1676{
1677	u_int32_t irstat, itstat;
1678	u_int i;
1679	struct firewire_comm *fc = (struct firewire_comm *)sc;
1680
1681#ifdef OHCI_DEBUG
1682	if(stat & OREAD(sc, FWOHCI_INTMASK))
1683		device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1684			stat & OHCI_INT_EN ? "DMA_EN ":"",
1685			stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1686			stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1687			stat & OHCI_INT_ERR ? "INT_ERR ":"",
1688			stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1689			stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1690			stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1691			stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1692			stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1693			stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1694			stat & OHCI_INT_PHY_SID ? "SID ":"",
1695			stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1696			stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1697			stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1698			stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
1699			stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
1700			stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
1701			stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
1702			stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
1703			stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
1704			stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
1705			stat, OREAD(sc, FWOHCI_INTMASK)
1706		);
1707#endif
1708/* Bus reset */
1709	if(stat & OHCI_INT_PHY_BUS_R ){
1710		device_printf(fc->dev, "BUS reset\n");
1711		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1712		OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1713
1714		OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1715		sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1716		OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1717		sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1718
1719#if 0
1720		for( i = 0 ; i < fc->nisodma ; i ++ ){
1721			OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1722			OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1723		}
1724
1725#endif
1726		fw_busreset(fc);
1727
1728		/* XXX need to wait DMA to stop */
1729#ifndef ACK_ALL
1730		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1731#endif
1732#if 1
1733		/* pending all pre-bus_reset packets */
1734		fwohci_txd(sc, &sc->atrq);
1735		fwohci_txd(sc, &sc->atrs);
1736		fwohci_arcv(sc, &sc->arrs, -1);
1737		fwohci_arcv(sc, &sc->arrq, -1);
1738#endif
1739
1740
1741		OWRITE(sc, OHCI_AREQHI, 1 << 31);
1742		/* XXX insecure ?? */
1743		OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1744		OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1745		OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1746
1747	}
1748	if((stat & OHCI_INT_DMA_IR )){
1749#ifndef ACK_ALL
1750		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1751#endif
1752		irstat = OREAD(sc, OHCI_IR_STAT);
1753		OWRITE(sc, OHCI_IR_STATCLR, irstat);
1754		for(i = 0; i < fc->nisodma ; i++){
1755			struct fwohci_dbch *dbch;
1756
1757			if((irstat & (1 << i)) != 0){
1758				dbch = &sc->ir[i];
1759				if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1760					device_printf(sc->fc.dev,
1761						"dma(%d) not active\n", i);
1762					continue;
1763				}
1764				if (dbch->xferq.flag & FWXFERQ_PACKET) {
1765					fwohci_ircv(sc, dbch, count);
1766				} else {
1767					fwohci_rbuf_update(sc, i);
1768				}
1769			}
1770		}
1771	}
1772	if((stat & OHCI_INT_DMA_IT )){
1773#ifndef ACK_ALL
1774		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1775#endif
1776		itstat = OREAD(sc, OHCI_IT_STAT);
1777		OWRITE(sc, OHCI_IT_STATCLR, itstat);
1778		for(i = 0; i < fc->nisodma ; i++){
1779			if((itstat & (1 << i)) != 0){
1780				fwohci_tbuf_update(sc, i);
1781			}
1782		}
1783	}
1784	if((stat & OHCI_INT_DMA_PRRS )){
1785#ifndef ACK_ALL
1786		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1787#endif
1788#if 0
1789		dump_dma(sc, ARRS_CH);
1790		dump_db(sc, ARRS_CH);
1791#endif
1792		fwohci_arcv(sc, &sc->arrs, count);
1793	}
1794	if((stat & OHCI_INT_DMA_PRRQ )){
1795#ifndef ACK_ALL
1796		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1797#endif
1798#if 0
1799		dump_dma(sc, ARRQ_CH);
1800		dump_db(sc, ARRQ_CH);
1801#endif
1802		fwohci_arcv(sc, &sc->arrq, count);
1803	}
1804	if(stat & OHCI_INT_PHY_SID){
1805		caddr_t buf;
1806		int plen;
1807
1808#ifndef ACK_ALL
1809		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1810#endif
1811/*
1812** Checking whether the node is root or not. If root, turn on
1813** cycle master.
1814*/
1815		device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID));
1816		if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){
1817			printf("Bus reset failure\n");
1818			goto sidout;
1819		}
1820		if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){
1821			printf("CYCLEMASTER mode\n");
1822			OWRITE(sc, OHCI_LNKCTL,
1823				OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1824		}else{
1825			printf("non CYCLEMASTER mode\n");
1826			OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1827			OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1828		}
1829		fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f;
1830
1831		plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK;
1832		plen -= 4; /* chop control info */
1833		buf = malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT);
1834		if(buf == NULL) goto sidout;
1835		bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1),
1836								buf, plen);
1837		fw_sidrcv(fc, buf, plen, 0);
1838	}
1839sidout:
1840	if((stat & OHCI_INT_DMA_ATRQ )){
1841#ifndef ACK_ALL
1842		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1843#endif
1844		fwohci_txd(sc, &(sc->atrq));
1845	}
1846	if((stat & OHCI_INT_DMA_ATRS )){
1847#ifndef ACK_ALL
1848		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1849#endif
1850		fwohci_txd(sc, &(sc->atrs));
1851	}
1852	if((stat & OHCI_INT_PW_ERR )){
1853#ifndef ACK_ALL
1854		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1855#endif
1856		device_printf(fc->dev, "posted write error\n");
1857	}
1858	if((stat & OHCI_INT_ERR )){
1859#ifndef ACK_ALL
1860		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1861#endif
1862		device_printf(fc->dev, "unrecoverable error\n");
1863	}
1864	if((stat & OHCI_INT_PHY_INT)) {
1865#ifndef ACK_ALL
1866		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1867#endif
1868		device_printf(fc->dev, "phy int\n");
1869	}
1870
1871	return;
1872}
1873
1874void
1875fwohci_intr(void *arg)
1876{
1877	struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1878	u_int32_t stat;
1879
1880	if (!(sc->intmask & OHCI_INT_EN)) {
1881		/* polling mode */
1882		return;
1883	}
1884
1885	while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) {
1886		if (stat == 0xffffffff) {
1887			device_printf(sc->fc.dev,
1888				"device physically ejected?\n");
1889			return;
1890		}
1891#ifdef ACK_ALL
1892		OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1893#endif
1894		fwohci_intr_body(sc, stat, -1);
1895	}
1896}
1897
1898static void
1899fwohci_poll(struct firewire_comm *fc, int quick, int count)
1900{
1901	int s;
1902	u_int32_t stat;
1903	struct fwohci_softc *sc;
1904
1905
1906	sc = (struct fwohci_softc *)fc;
1907	stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
1908		OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
1909		OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
1910#if 0
1911	if (!quick) {
1912#else
1913	if (1) {
1914#endif
1915		stat = OREAD(sc, FWOHCI_INTSTAT);
1916		if (stat == 0)
1917			return;
1918		if (stat == 0xffffffff) {
1919			device_printf(sc->fc.dev,
1920				"device physically ejected?\n");
1921			return;
1922		}
1923#ifdef ACK_ALL
1924		OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1925#endif
1926	}
1927	s = splfw();
1928	fwohci_intr_body(sc, stat, count);
1929	splx(s);
1930}
1931
1932static void
1933fwohci_set_intr(struct firewire_comm *fc, int enable)
1934{
1935	struct fwohci_softc *sc;
1936
1937	sc = (struct fwohci_softc *)fc;
1938	if (bootverbose)
1939		device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
1940	if (enable) {
1941		sc->intmask |= OHCI_INT_EN;
1942		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1943	} else {
1944		sc->intmask &= ~OHCI_INT_EN;
1945		OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1946	}
1947}
1948
1949static void
1950fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
1951{
1952	int stat;
1953	struct firewire_comm *fc = &sc->fc;
1954	struct fw_pkt *fp;
1955	struct fwohci_dbch *dbch;
1956	struct fwohcidb_tr *db_tr;
1957
1958	dbch = &sc->it[dmach];
1959#if 0	/* XXX OHCI interrupt before the last packet is really on the wire */
1960	if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){
1961		db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start;
1962/*
1963 * Overwrite highest significant 4 bits timestamp information
1964 */
1965		fp = (struct fw_pkt *)db_tr->buf;
1966		fp->mode.ld[2] &= htonl(0xffff0fff);
1967		fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000);
1968	}
1969#endif
1970	/*
1971	 * XXX interrupt could be missed.
1972	 * We have to check more than one buffer/chunk
1973	 */
1974	if (firewire_debug && dbch->xferq.stdma2 != NULL) {
1975		db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->end;
1976		stat = db_tr->db[2].db.desc.status;
1977		if (stat)
1978			device_printf(fc->dev,
1979				"stdma2 already done stat:0x%x\n", stat);
1980	}
1981
1982	stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f;
1983	switch(stat){
1984	case FWOHCIEV_ACKCOMPL:
1985#if 1
1986	if (dbch->xferq.flag & FWXFERQ_DV) {
1987		struct ciphdr *ciph;
1988		int timer, timestamp, cycl, diff;
1989		static int last_timer=0;
1990
1991		timer = (fc->cyctimer(fc) >> 12) & 0xffff;
1992		db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1993		fp = (struct fw_pkt *)db_tr->buf;
1994		ciph = (struct ciphdr *) &fp->mode.ld[1];
1995		timestamp = db_tr->db[2].db.desc.count & 0xffff;
1996		cycl = ntohs(ciph->fdf.dv.cyc) >> 12;
1997		diff = cycl - (timestamp & 0xf) - CYCLE_OFFSET;
1998		if (diff < 0)
1999			diff += 16;
2000		if (diff > 8)
2001			diff -= 16;
2002		if (firewire_debug || diff != 0)
2003			printf("dbc: %3d timer: 0x%04x packet: 0x%04x"
2004				" cyc: 0x%x diff: %+1d\n",
2005				ciph->dbc, last_timer, timestamp, cycl, diff);
2006		last_timer = timer;
2007		/* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */
2008	}
2009#endif
2010		fw_tbuf_update(fc, dmach, 1);
2011		break;
2012	default:
2013		device_printf(fc->dev, "Isochronous transmit err %02x\n", stat);
2014		fw_tbuf_update(fc, dmach, 0);
2015		break;
2016	}
2017	fwohci_itxbuf_enable(fc, dmach);
2018}
2019
2020static void
2021fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2022{
2023	struct firewire_comm *fc = &sc->fc;
2024	int stat;
2025
2026	stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f;
2027	switch(stat){
2028	case FWOHCIEV_ACKCOMPL:
2029		fw_rbuf_update(fc, dmach, 1);
2030		wakeup(fc->ir[dmach]);
2031		fwohci_irx_enable(fc, dmach);
2032		break;
2033	default:
2034		device_printf(fc->dev, "Isochronous receive err %02x\n",
2035									stat);
2036		break;
2037	}
2038}
2039
2040void
2041dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2042{
2043	u_int32_t off, cntl, stat, cmd, match;
2044
2045	if(ch == 0){
2046		off = OHCI_ATQOFF;
2047	}else if(ch == 1){
2048		off = OHCI_ATSOFF;
2049	}else if(ch == 2){
2050		off = OHCI_ARQOFF;
2051	}else if(ch == 3){
2052		off = OHCI_ARSOFF;
2053	}else if(ch < IRX_CH){
2054		off = OHCI_ITCTL(ch - ITX_CH);
2055	}else{
2056		off = OHCI_IRCTL(ch - IRX_CH);
2057	}
2058	cntl = stat = OREAD(sc, off);
2059	cmd = OREAD(sc, off + 0xc);
2060	match = OREAD(sc, off + 0x10);
2061
2062	device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n",
2063		ch,
2064		cntl,
2065		stat,
2066		cmd,
2067		match);
2068	stat &= 0xffff ;
2069	if(stat & 0xff00){
2070		device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2071			ch,
2072			stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2073			stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2074			stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2075			stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2076			stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2077			stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2078			fwohcicode[stat & 0x1f],
2079			stat & 0x1f
2080		);
2081	}else{
2082		device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2083	}
2084}
2085
2086void
2087dump_db(struct fwohci_softc *sc, u_int32_t ch)
2088{
2089	struct fwohci_dbch *dbch;
2090	struct fwohcidb_tr *cp = NULL, *pp, *np;
2091	volatile struct fwohcidb *curr = NULL, *prev, *next = NULL;
2092	int idb, jdb;
2093	u_int32_t cmd, off;
2094	if(ch == 0){
2095		off = OHCI_ATQOFF;
2096		dbch = &sc->atrq;
2097	}else if(ch == 1){
2098		off = OHCI_ATSOFF;
2099		dbch = &sc->atrs;
2100	}else if(ch == 2){
2101		off = OHCI_ARQOFF;
2102		dbch = &sc->arrq;
2103	}else if(ch == 3){
2104		off = OHCI_ARSOFF;
2105		dbch = &sc->arrs;
2106	}else if(ch < IRX_CH){
2107		off = OHCI_ITCTL(ch - ITX_CH);
2108		dbch = &sc->it[ch - ITX_CH];
2109	}else {
2110		off = OHCI_IRCTL(ch - IRX_CH);
2111		dbch = &sc->ir[ch - IRX_CH];
2112	}
2113	cmd = OREAD(sc, off + 0xc);
2114
2115	if( dbch->ndb == 0 ){
2116		device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2117		return;
2118	}
2119	pp = dbch->top;
2120	prev = pp->db;
2121	for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2122		if(pp == NULL){
2123			curr = NULL;
2124			goto outdb;
2125		}
2126		cp = STAILQ_NEXT(pp, link);
2127		if(cp == NULL){
2128			curr = NULL;
2129			goto outdb;
2130		}
2131		np = STAILQ_NEXT(cp, link);
2132		if(cp == NULL) break;
2133		for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2134			if((cmd  & 0xfffffff0)
2135				== vtophys(&(cp->db[jdb]))){
2136				curr = cp->db;
2137				if(np != NULL){
2138					next = np->db;
2139				}else{
2140					next = NULL;
2141				}
2142				goto outdb;
2143			}
2144		}
2145		pp = STAILQ_NEXT(pp, link);
2146		prev = pp->db;
2147	}
2148outdb:
2149	if( curr != NULL){
2150		printf("Prev DB %d\n", ch);
2151		print_db(prev, ch, dbch->ndesc);
2152		printf("Current DB %d\n", ch);
2153		print_db(curr, ch, dbch->ndesc);
2154		printf("Next DB %d\n", ch);
2155		print_db(next, ch, dbch->ndesc);
2156	}else{
2157		printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2158	}
2159	return;
2160}
2161
2162void
2163print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max)
2164{
2165	fwohcireg_t stat;
2166	int i, key;
2167
2168	if(db == NULL){
2169		printf("No Descriptor is found\n");
2170		return;
2171	}
2172
2173	printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2174		ch,
2175		"Current",
2176		"OP  ",
2177		"KEY",
2178		"INT",
2179		"BR ",
2180		"len",
2181		"Addr",
2182		"Depend",
2183		"Stat",
2184		"Cnt");
2185	for( i = 0 ; i <= max ; i ++){
2186		key = db[i].db.desc.cmd & OHCI_KEY_MASK;
2187#if __FreeBSD_version >= 500000
2188		printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x",
2189#else
2190		printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2191#endif
2192				vtophys(&db[i]),
2193				dbcode[(db[i].db.desc.cmd >> 28) & 0xf],
2194				dbkey[(db[i].db.desc.cmd >> 24) & 0x7],
2195				dbcond[(db[i].db.desc.cmd >> 20) & 0x3],
2196				dbcond[(db[i].db.desc.cmd >> 18) & 0x3],
2197				db[i].db.desc.cmd & 0xffff,
2198				db[i].db.desc.addr,
2199				db[i].db.desc.depend,
2200				db[i].db.desc.status,
2201				db[i].db.desc.count);
2202		stat = db[i].db.desc.status;
2203		if(stat & 0xff00){
2204			printf(" %s%s%s%s%s%s %s(%x)\n",
2205				stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2206				stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2207				stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2208				stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2209				stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2210				stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2211				fwohcicode[stat & 0x1f],
2212				stat & 0x1f
2213			);
2214		}else{
2215			printf(" Nostat\n");
2216		}
2217		if(key == OHCI_KEY_ST2 ){
2218			printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2219				db[i+1].db.immed[0],
2220				db[i+1].db.immed[1],
2221				db[i+1].db.immed[2],
2222				db[i+1].db.immed[3]);
2223		}
2224		if(key == OHCI_KEY_DEVICE){
2225			return;
2226		}
2227		if((db[i].db.desc.cmd & OHCI_BRANCH_MASK)
2228				== OHCI_BRANCH_ALWAYS){
2229			return;
2230		}
2231		if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2232				== OHCI_OUTPUT_LAST){
2233			return;
2234		}
2235		if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2236				== OHCI_INPUT_LAST){
2237			return;
2238		}
2239		if(key == OHCI_KEY_ST2 ){
2240			i++;
2241		}
2242	}
2243	return;
2244}
2245
2246void
2247fwohci_ibr(struct firewire_comm *fc)
2248{
2249	struct fwohci_softc *sc;
2250	u_int32_t fun;
2251
2252	sc = (struct fwohci_softc *)fc;
2253
2254	/*
2255	 * Set root hold-off bit so that non cyclemaster capable node
2256	 * shouldn't became the root node.
2257	 */
2258#if 1
2259	fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2260	fun |= FW_PHY_IBR | FW_PHY_RHB;
2261	fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2262#else	/* Short bus reset */
2263	fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2264	fun |= FW_PHY_ISBR | FW_PHY_RHB;
2265	fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2266#endif
2267}
2268
2269void
2270fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2271{
2272	struct fwohcidb_tr *db_tr, *fdb_tr;
2273	struct fwohci_dbch *dbch;
2274	struct fw_pkt *fp;
2275	volatile struct fwohci_txpkthdr *ohcifp;
2276	unsigned short chtag;
2277	int idb;
2278
2279	dbch = &sc->it[dmach];
2280	chtag = sc->it[dmach].xferq.flag & 0xff;
2281
2282	db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2283	fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2284/*
2285device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db));
2286*/
2287	if(bulkxfer->flag != 0){
2288		return;
2289	}
2290	bulkxfer->flag = 1;
2291	for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){
2292		db_tr->db[0].db.desc.cmd
2293			= OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2294		fp = (struct fw_pkt *)db_tr->buf;
2295		ohcifp = (volatile struct fwohci_txpkthdr *)
2296						db_tr->db[1].db.immed;
2297		ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]);
2298		ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
2299		ohcifp->mode.stream.chtag = chtag;
2300		ohcifp->mode.stream.tcode = 0xa;
2301		ohcifp->mode.stream.spd = 4;
2302		ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]);
2303		ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]);
2304
2305		db_tr->db[2].db.desc.cmd
2306			= OHCI_OUTPUT_LAST
2307			| OHCI_UPDATE
2308			| OHCI_BRANCH_ALWAYS
2309			| ((ntohs(fp->mode.stream.len) ) & 0xffff);
2310		db_tr->db[2].db.desc.status = 0;
2311		db_tr->db[2].db.desc.count = 0;
2312		db_tr->db[0].db.desc.depend
2313			= vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2314		db_tr->db[dbch->ndesc - 1].db.desc.depend
2315			= vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2316		bulkxfer->end = (caddr_t)db_tr;
2317		db_tr = STAILQ_NEXT(db_tr, link);
2318	}
2319	db_tr = (struct fwohcidb_tr *)bulkxfer->end;
2320	db_tr->db[0].db.desc.depend &= ~0xf;
2321	db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
2322#if 0
2323/**/
2324	db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS;
2325	db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER;
2326/**/
2327#endif
2328	db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
2329	/* OHCI 1.1 and above */
2330	db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
2331
2332	db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2333	fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2334/*
2335device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db));
2336*/
2337	return;
2338}
2339
2340static int
2341fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size,
2342	int mode, void *buf)
2343{
2344	volatile struct fwohcidb *db = db_tr->db;
2345	int err = 0;
2346	if(buf == 0){
2347		err = EINVAL;
2348		return err;
2349	}
2350	db_tr->buf = buf;
2351	db_tr->dbcnt = 3;
2352	db_tr->dummy = NULL;
2353
2354	db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2355
2356	db[2].db.desc.depend = 0;
2357	db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t);
2358	db[2].db.desc.cmd = OHCI_OUTPUT_MORE;
2359
2360	db[0].db.desc.status = 0;
2361	db[0].db.desc.count = 0;
2362
2363	db[2].db.desc.status = 0;
2364	db[2].db.desc.count = 0;
2365	if( mode & FWXFERQ_STREAM ){
2366		db[2].db.desc.cmd |= OHCI_OUTPUT_LAST;
2367		if(mode & FWXFERQ_PACKET ){
2368			db[2].db.desc.cmd
2369					|= OHCI_INTERRUPT_ALWAYS;
2370		}
2371	}
2372	db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2373	return 1;
2374}
2375
2376int
2377fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode,
2378	void *buf, void *dummy)
2379{
2380	volatile struct fwohcidb *db = db_tr->db;
2381	int i;
2382	void *dbuf[2];
2383	int dsiz[2];
2384
2385	if(buf == 0){
2386		buf = malloc(size, M_DEVBUF, M_NOWAIT);
2387		if(buf == NULL) return 0;
2388		db_tr->buf = buf;
2389		db_tr->dbcnt = 1;
2390		db_tr->dummy = NULL;
2391		dsiz[0] = size;
2392		dbuf[0] = buf;
2393	}else if(dummy == NULL){
2394		db_tr->buf = buf;
2395		db_tr->dbcnt = 1;
2396		db_tr->dummy = NULL;
2397		dsiz[0] = size;
2398		dbuf[0] = buf;
2399	}else{
2400		db_tr->buf = buf;
2401		db_tr->dbcnt = 2;
2402		db_tr->dummy = dummy;
2403		dsiz[0] = sizeof(u_int32_t);
2404		dsiz[1] = size;
2405		dbuf[0] = dummy;
2406		dbuf[1] = buf;
2407	}
2408	for(i = 0 ; i < db_tr->dbcnt ; i++){
2409		db[i].db.desc.addr = vtophys(dbuf[i]) ;
2410		db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i];
2411		if( mode & FWXFERQ_STREAM ){
2412			db[i].db.desc.cmd |= OHCI_UPDATE;
2413		}
2414		db[i].db.desc.status = 0;
2415		db[i].db.desc.count = dsiz[i];
2416	}
2417	if( mode & FWXFERQ_STREAM ){
2418		db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST;
2419		if(mode & FWXFERQ_PACKET ){
2420			db[db_tr->dbcnt - 1].db.desc.cmd
2421					|= OHCI_INTERRUPT_ALWAYS;
2422		}
2423	}
2424	db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2425	return 1;
2426}
2427
2428static void
2429fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2430{
2431	struct fwohcidb_tr *db_tr = dbch->top, *odb_tr;
2432	struct firewire_comm *fc = (struct firewire_comm *)sc;
2433	int z = 1;
2434	struct fw_pkt *fp;
2435	u_int8_t *ld;
2436	u_int32_t off = NULL;
2437	u_int32_t stat;
2438	u_int32_t *qld;
2439	u_int32_t reg;
2440	u_int spd;
2441	u_int dmach;
2442	int len, i, plen;
2443	caddr_t buf;
2444
2445	for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
2446		if( &sc->ir[dmach] == dbch){
2447			off = OHCI_IROFF(dmach);
2448			break;
2449		}
2450	}
2451	if(off == NULL){
2452		return;
2453	}
2454	if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){
2455		fwohci_irx_disable(&sc->fc, dmach);
2456		return;
2457	}
2458
2459	odb_tr = NULL;
2460	db_tr = dbch->top;
2461	i = 0;
2462	while ((reg = db_tr->db[0].db.desc.status) & 0x1f) {
2463		if (count >= 0 && count-- == 0)
2464			break;
2465		ld = (u_int8_t *)db_tr->buf;
2466		if (dbch->xferq.flag & FWXFERQ_PACKET) {
2467			/* skip timeStamp */
2468			ld += sizeof(struct fwohci_trailer);
2469		}
2470		qld = (u_int32_t *)ld;
2471		len = dbch->xferq.psize - (db_tr->db[0].db.desc.count);
2472/*
2473{
2474device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len,
2475		db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]);
2476}
2477*/
2478		fp=(struct fw_pkt *)ld;
2479		qld[0] = htonl(qld[0]);
2480		plen = sizeof(struct fw_isohdr)
2481			+ ntohs(fp->mode.stream.len) + sizeof(u_int32_t);
2482		ld += plen;
2483		len -= plen;
2484		buf = db_tr->buf;
2485		db_tr->buf = NULL;
2486		stat = reg & 0x1f;
2487		spd =  reg & 0x3;
2488		switch(stat){
2489			case FWOHCIEV_ACKCOMPL:
2490			case FWOHCIEV_ACKPEND:
2491				fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd);
2492				break;
2493			default:
2494				free(buf, M_DEVBUF);
2495				device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat);
2496				break;
2497		}
2498		i++;
2499		fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2500					dbch->xferq.flag, 0, NULL);
2501		db_tr->db[0].db.desc.depend &= ~0xf;
2502		if(dbch->pdb_tr != NULL){
2503			dbch->pdb_tr->db[0].db.desc.depend |= z;
2504		} else {
2505			/* XXX should be rewritten in better way */
2506			dbch->bottom->db[0].db.desc.depend |= z;
2507		}
2508		dbch->pdb_tr = db_tr;
2509		db_tr = STAILQ_NEXT(db_tr, link);
2510	}
2511	dbch->top = db_tr;
2512	reg = OREAD(sc, OHCI_DMACTL(off));
2513	if (reg & OHCI_CNTL_DMA_ACTIVE)
2514		return;
2515	device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n",
2516			dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i);
2517	dbch->top = db_tr;
2518	fwohci_irx_enable(fc, dmach);
2519}
2520
2521#define PLEN(x)	(((ntohs(x))+0x3) & ~0x3)
2522static int
2523fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen)
2524{
2525	int i;
2526
2527	for( i = 4; i < hlen ; i+=4){
2528		fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]);
2529	}
2530
2531	switch(fp->mode.common.tcode){
2532	case FWTCODE_RREQQ:
2533		return sizeof(fp->mode.rreqq) + sizeof(u_int32_t);
2534	case FWTCODE_WRES:
2535		return sizeof(fp->mode.wres) + sizeof(u_int32_t);
2536	case FWTCODE_WREQQ:
2537		return sizeof(fp->mode.wreqq) + sizeof(u_int32_t);
2538	case FWTCODE_RREQB:
2539		return sizeof(fp->mode.rreqb) + sizeof(u_int32_t);
2540	case FWTCODE_RRESQ:
2541		return sizeof(fp->mode.rresq) + sizeof(u_int32_t);
2542	case FWTCODE_WREQB:
2543		return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len)
2544						+ sizeof(u_int32_t);
2545	case FWTCODE_LREQ:
2546		return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len)
2547						+ sizeof(u_int32_t);
2548	case FWTCODE_RRESB:
2549		return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len)
2550						+ sizeof(u_int32_t);
2551	case FWTCODE_LRES:
2552		return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len)
2553						+ sizeof(u_int32_t);
2554	case FWOHCITCODE_PHY:
2555		return 16;
2556	}
2557	device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2558	return 0;
2559}
2560
2561static void
2562fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2563{
2564	struct fwohcidb_tr *db_tr;
2565	int z = 1;
2566	struct fw_pkt *fp;
2567	u_int8_t *ld;
2568	u_int32_t stat, off;
2569	u_int spd;
2570	int len, plen, hlen, pcnt, poff = 0, rlen;
2571	int s;
2572	caddr_t buf;
2573	int resCount;
2574
2575	if(&sc->arrq == dbch){
2576		off = OHCI_ARQOFF;
2577	}else if(&sc->arrs == dbch){
2578		off = OHCI_ARSOFF;
2579	}else{
2580		return;
2581	}
2582
2583	s = splfw();
2584	db_tr = dbch->top;
2585	pcnt = 0;
2586	/* XXX we cannot handle a packet which lies in more than two buf */
2587	while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) {
2588		ld = (u_int8_t *)db_tr->buf + dbch->buf_offset;
2589		resCount = db_tr->db[0].db.desc.count;
2590		len = dbch->xferq.psize - resCount
2591					- dbch->buf_offset;
2592		while (len > 0 ) {
2593			if (count >= 0 && count-- == 0)
2594				goto out;
2595			if(dbch->frag.buf != NULL){
2596				buf = dbch->frag.buf;
2597				if (dbch->frag.plen < 0) {
2598					/* incomplete header */
2599					int hlen;
2600
2601					hlen = - dbch->frag.plen;
2602					rlen = hlen - dbch->frag.len;
2603					bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen);
2604					ld += rlen;
2605					len -= rlen;
2606					dbch->frag.len += rlen;
2607#if 0
2608					printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2609#endif
2610					fp=(struct fw_pkt *)dbch->frag.buf;
2611					dbch->frag.plen
2612						= fwohci_get_plen(sc, fp, hlen);
2613					if (dbch->frag.plen == 0)
2614						goto out;
2615				}
2616				rlen = dbch->frag.plen - dbch->frag.len;
2617#if 0
2618				printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2619#endif
2620				bcopy(ld, dbch->frag.buf + dbch->frag.len,
2621						rlen);
2622				ld += rlen;
2623				len -= rlen;
2624				plen = dbch->frag.plen;
2625				dbch->frag.buf = NULL;
2626				dbch->frag.plen = 0;
2627				dbch->frag.len = 0;
2628				poff = 0;
2629			}else{
2630				fp=(struct fw_pkt *)ld;
2631				fp->mode.ld[0] = htonl(fp->mode.ld[0]);
2632				switch(fp->mode.common.tcode){
2633				case FWTCODE_RREQQ:
2634				case FWTCODE_WRES:
2635				case FWTCODE_WREQQ:
2636				case FWTCODE_RRESQ:
2637				case FWOHCITCODE_PHY:
2638					hlen = 12;
2639					break;
2640				case FWTCODE_RREQB:
2641				case FWTCODE_WREQB:
2642				case FWTCODE_LREQ:
2643				case FWTCODE_RRESB:
2644				case FWTCODE_LRES:
2645					hlen = 16;
2646					break;
2647				default:
2648					device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2649					goto out;
2650				}
2651				if (len >= hlen) {
2652					plen = fwohci_get_plen(sc, fp, hlen);
2653					if (plen == 0)
2654						goto out;
2655					plen = (plen + 3) & ~3;
2656					len -= plen;
2657				} else {
2658					plen = -hlen;
2659					len -= hlen;
2660				}
2661				if(resCount > 0 || len > 0){
2662					buf = malloc( dbch->xferq.psize,
2663							M_DEVBUF, M_NOWAIT);
2664					if(buf == NULL){
2665						printf("cannot malloc!\n");
2666						free(db_tr->buf, M_DEVBUF);
2667						goto out;
2668					}
2669					bcopy(ld, buf, plen);
2670					poff = 0;
2671					dbch->frag.buf = NULL;
2672					dbch->frag.plen = 0;
2673					dbch->frag.len = 0;
2674				}else if(len < 0){
2675					dbch->frag.buf = db_tr->buf;
2676					if (plen < 0) {
2677#if 0
2678						printf("plen < 0:"
2679						"hlen: %d  len: %d\n",
2680						hlen, len);
2681#endif
2682						dbch->frag.len = hlen + len;
2683						dbch->frag.plen = -hlen;
2684					} else {
2685						dbch->frag.len = plen + len;
2686						dbch->frag.plen = plen;
2687					}
2688					bcopy(ld, db_tr->buf, dbch->frag.len);
2689					buf = NULL;
2690				}else{
2691					buf = db_tr->buf;
2692					poff = ld - (u_int8_t *)buf;
2693					dbch->frag.buf = NULL;
2694					dbch->frag.plen = 0;
2695					dbch->frag.len = 0;
2696				}
2697				ld += plen;
2698			}
2699			if( buf != NULL){
2700/* DMA result-code will be written at the tail of packet */
2701				stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2702				spd = (stat >> 5) & 0x3;
2703				stat &= 0x1f;
2704				switch(stat){
2705				case FWOHCIEV_ACKPEND:
2706#if 0
2707					printf("fwohci_arcv: ack pending..\n");
2708#endif
2709					/* fall through */
2710				case FWOHCIEV_ACKCOMPL:
2711					if( poff != 0 )
2712						bcopy(buf+poff, buf, plen - 4);
2713					fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd);
2714					break;
2715				case FWOHCIEV_BUSRST:
2716					free(buf, M_DEVBUF);
2717					if (sc->fc.status != FWBUSRESET)
2718						printf("got BUSRST packet!?\n");
2719					break;
2720				default:
2721					device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2722#if 0 /* XXX */
2723					goto out;
2724#endif
2725					break;
2726				}
2727			}
2728			pcnt ++;
2729		};
2730out:
2731		if (resCount == 0) {
2732			/* done on this buffer */
2733			fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2734						dbch->xferq.flag, 0, NULL);
2735			dbch->bottom->db[0].db.desc.depend |= z;
2736			dbch->bottom = db_tr;
2737			db_tr = STAILQ_NEXT(db_tr, link);
2738			dbch->top = db_tr;
2739			dbch->buf_offset = 0;
2740		} else {
2741			dbch->buf_offset = dbch->xferq.psize - resCount;
2742			break;
2743		}
2744		/* XXX make sure DMA is not dead */
2745	}
2746#if 0
2747	if (pcnt < 1)
2748		printf("fwohci_arcv: no packets\n");
2749#endif
2750	splx(s);
2751}
2752