fwohci.c revision 109379
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109379 2003-01-16 13:09:33Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirereg.h> 73#include <dev/firewire/fwohcireg.h> 74#include <dev/firewire/fwohcivar.h> 75#include <dev/firewire/firewire_phy.h> 76 77#include <dev/firewire/iec68113.h> 78 79#undef OHCI_DEBUG 80 81static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82 "STOR","LOAD","NOP ","STOP",}; 83static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84 "UNDEF","REG","SYS","DEV"}; 85char fwohcicode[32][0x20]={ 86 "No stat","Undef","long","miss Ack err", 87 "underrun","overrun","desc err", "data read err", 88 "data write err","bus reset","timeout","tcode err", 89 "Undef","Undef","unknown event","flushed", 90 "Undef","ack complete","ack pend","Undef", 91 "ack busy_X","ack busy_A","ack busy_B","Undef", 92 "Undef","Undef","Undef","ack tardy", 93 "Undef","ack data_err","ack type_err",""}; 94#define MAX_SPEED 2 95extern char linkspeed[MAX_SPEED+1][0x10]; 96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr __P((struct firewire_comm *)); 126static void fwohci_db_init __P((struct fwohci_dbch *)); 127static void fwohci_db_free __P((struct fwohci_dbch *)); 128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_start_atq __P((struct firewire_comm *)); 132static void fwohci_start_ats __P((struct firewire_comm *)); 133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144static int fwohci_irx_disable __P((struct firewire_comm *, int)); 145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_poll __P((struct firewire_comm *, int, int)); 150static void fwohci_set_intr __P((struct firewire_comm *, int)); 151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160 161/* 162 * memory allocated for DMA programs 163 */ 164#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166/* #define NDB 1024 */ 167#define NDB FWMAXQUEUE 168#define NDVDB (DVBUF * NDB) 169 170#define OHCI_VERSION 0x00 171#define OHCI_CROMHDR 0x18 172#define OHCI_BUS_OPT 0x20 173#define OHCI_BUSIRMC (1 << 31) 174#define OHCI_BUSCMC (1 << 30) 175#define OHCI_BUSISC (1 << 29) 176#define OHCI_BUSBMC (1 << 28) 177#define OHCI_BUSPMC (1 << 27) 178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181#define OHCI_EUID_HI 0x24 182#define OHCI_EUID_LO 0x28 183 184#define OHCI_CROMPTR 0x34 185#define OHCI_HCCCTL 0x50 186#define OHCI_HCCCTLCLR 0x54 187#define OHCI_AREQHI 0x100 188#define OHCI_AREQHICLR 0x104 189#define OHCI_AREQLO 0x108 190#define OHCI_AREQLOCLR 0x10c 191#define OHCI_PREQHI 0x110 192#define OHCI_PREQHICLR 0x114 193#define OHCI_PREQLO 0x118 194#define OHCI_PREQLOCLR 0x11c 195#define OHCI_PREQUPPER 0x120 196 197#define OHCI_SID_BUF 0x64 198#define OHCI_SID_CNT 0x68 199#define OHCI_SID_CNT_MASK 0xffc 200 201#define OHCI_IT_STAT 0x90 202#define OHCI_IT_STATCLR 0x94 203#define OHCI_IT_MASK 0x98 204#define OHCI_IT_MASKCLR 0x9c 205 206#define OHCI_IR_STAT 0xa0 207#define OHCI_IR_STATCLR 0xa4 208#define OHCI_IR_MASK 0xa8 209#define OHCI_IR_MASKCLR 0xac 210 211#define OHCI_LNKCTL 0xe0 212#define OHCI_LNKCTLCLR 0xe4 213 214#define OHCI_PHYACCESS 0xec 215#define OHCI_CYCLETIMER 0xf0 216 217#define OHCI_DMACTL(off) (off) 218#define OHCI_DMACTLCLR(off) (off + 4) 219#define OHCI_DMACMD(off) (off + 0xc) 220#define OHCI_DMAMATCH(off) (off + 0x10) 221 222#define OHCI_ATQOFF 0x180 223#define OHCI_ATQCTL OHCI_ATQOFF 224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228#define OHCI_ATSOFF 0x1a0 229#define OHCI_ATSCTL OHCI_ATSOFF 230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234#define OHCI_ARQOFF 0x1c0 235#define OHCI_ARQCTL OHCI_ARQOFF 236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240#define OHCI_ARSOFF 0x1e0 241#define OHCI_ARSCTL OHCI_ARSOFF 242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257d_ioctl_t fwohci_ioctl; 258 259/* 260 * Communication with PHY device 261 */ 262static u_int32_t 263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264{ 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275} 276 277static u_int32_t 278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279{ 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284#define OHCI_CSR_DATA 0x0c 285#define OHCI_CSR_COMP 0x10 286#define OHCI_CSR_CONT 0x14 287#define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(10); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302} 303 304static u_int32_t 305fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306{ 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311#define MAX_RETRY 100 312again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(100); 321 } 322 if(i >= MAX_RETRY) { 323 if (bootverbose) 324 device_printf(sc->fc.dev, "phy read failed(1).\n"); 325 if (++retry < MAX_RETRY) { 326 DELAY(100); 327 goto again; 328 } 329 } 330 /* Make sure that SCLK is started */ 331 stat = OREAD(sc, FWOHCI_INTSTAT); 332 if ((stat & OHCI_INT_REG_FAIL) != 0 || 333 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 334 if (bootverbose) 335 device_printf(sc->fc.dev, "phy read failed(2).\n"); 336 if (++retry < MAX_RETRY) { 337 DELAY(100); 338 goto again; 339 } 340 } 341 if (bootverbose || retry >= MAX_RETRY) 342 device_printf(sc->fc.dev, 343 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 344#undef MAX_RETRY 345 return((fun >> PHYDEV_RDDATA )& 0xff); 346} 347/* Device specific ioctl. */ 348int 349fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350{ 351 struct firewire_softc *sc; 352 struct fwohci_softc *fc; 353 int unit = DEV2UNIT(dev); 354 int err = 0; 355 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356 u_int32_t *dmach = (u_int32_t *) data; 357 358 sc = devclass_get_softc(firewire_devclass, unit); 359 if(sc == NULL){ 360 return(EINVAL); 361 } 362 fc = (struct fwohci_softc *)sc->fc; 363 364 if (!data) 365 return(EINVAL); 366 367 switch (cmd) { 368 case FWOHCI_WRREG: 369#define OHCI_MAX_REG 0x800 370 if(reg->addr <= OHCI_MAX_REG){ 371 OWRITE(fc, reg->addr, reg->data); 372 reg->data = OREAD(fc, reg->addr); 373 }else{ 374 err = EINVAL; 375 } 376 break; 377 case FWOHCI_RDREG: 378 if(reg->addr <= OHCI_MAX_REG){ 379 reg->data = OREAD(fc, reg->addr); 380 }else{ 381 err = EINVAL; 382 } 383 break; 384/* Read DMA descriptors for debug */ 385 case DUMPDMA: 386 if(*dmach <= OHCI_MAX_DMA_CH ){ 387 dump_dma(fc, *dmach); 388 dump_db(fc, *dmach); 389 }else{ 390 err = EINVAL; 391 } 392 break; 393 default: 394 break; 395 } 396 return err; 397} 398 399static int 400fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 401{ 402 u_int32_t reg, reg2; 403 int e1394a = 1; 404/* 405 * probe PHY parameters 406 * 0. to prove PHY version, whether compliance of 1394a. 407 * 1. to probe maximum speed supported by the PHY and 408 * number of port supported by core-logic. 409 * It is not actually available port on your PC . 410 */ 411 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 412#if 0 413 /* XXX wait for SCLK. */ 414 DELAY(100000); 415#endif 416 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417 418 if((reg >> 5) != 7 ){ 419 sc->fc.mode &= ~FWPHYASYST; 420 sc->fc.nport = reg & FW_PHY_NP; 421 sc->fc.speed = reg & FW_PHY_SPD >> 6; 422 if (sc->fc.speed > MAX_SPEED) { 423 device_printf(dev, "invalid speed %d (fixed to %d).\n", 424 sc->fc.speed, MAX_SPEED); 425 sc->fc.speed = MAX_SPEED; 426 } 427 device_printf(dev, 428 "Phy 1394 only %s, %d ports.\n", 429 linkspeed[sc->fc.speed], sc->fc.nport); 430 }else{ 431 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432 sc->fc.mode |= FWPHYASYST; 433 sc->fc.nport = reg & FW_PHY_NP; 434 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435 if (sc->fc.speed > MAX_SPEED) { 436 device_printf(dev, "invalid speed %d (fixed to %d).\n", 437 sc->fc.speed, MAX_SPEED); 438 sc->fc.speed = MAX_SPEED; 439 } 440 device_printf(dev, 441 "Phy 1394a available %s, %d ports.\n", 442 linkspeed[sc->fc.speed], sc->fc.nport); 443 444 /* check programPhyEnable */ 445 reg2 = fwphy_rddata(sc, 5); 446#if 0 447 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448#else /* XXX force to enable 1394a */ 449 if (e1394a) { 450#endif 451 if (bootverbose) 452 device_printf(dev, 453 "Enable 1394a Enhancements\n"); 454 /* enable EAA EMC */ 455 reg2 |= 0x03; 456 /* set aPhyEnhanceEnable */ 457 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459 } else { 460 /* for safe */ 461 reg2 &= ~0x83; 462 } 463 reg2 = fwphy_wrdata(sc, 5, reg2); 464 } 465 466 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467 if((reg >> 5) == 7 ){ 468 reg = fwphy_rddata(sc, 4); 469 reg |= 1 << 6; 470 fwphy_wrdata(sc, 4, reg); 471 reg = fwphy_rddata(sc, 4); 472 } 473 return 0; 474} 475 476 477void 478fwohci_reset(struct fwohci_softc *sc, device_t dev) 479{ 480 int i, max_rec, speed; 481 u_int32_t reg, reg2; 482 struct fwohcidb_tr *db_tr; 483 484 /* Disable interrupt */ 485 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486 487 /* Now stopping all DMA channel */ 488 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492 493 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 } 498 499 /* FLUSH FIFO and reset Transmitter/Reciever */ 500 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501 if (bootverbose) 502 device_printf(dev, "resetting OHCI..."); 503 i = 0; 504 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505 if (i++ > 100) break; 506 DELAY(1000); 507 } 508 if (bootverbose) 509 printf("done (loop=%d)\n", i); 510 511 /* Probe phy */ 512 fwohci_probe_phy(sc, dev); 513 514 /* Probe link */ 515 reg = OREAD(sc, OHCI_BUS_OPT); 516 reg2 = reg | OHCI_BUSFNC; 517 max_rec = (reg & 0x0000f000) >> 12; 518 speed = (reg & 0x00000007); 519 device_printf(dev, "Link %s, max_rec %d bytes.\n", 520 linkspeed[speed], MAXREC(max_rec)); 521 /* XXX fix max_rec */ 522 sc->fc.maxrec = sc->fc.speed + 8; 523 if (max_rec != sc->fc.maxrec) { 524 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525 device_printf(dev, "max_rec %d -> %d\n", 526 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527 } 528 if (bootverbose) 529 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530 OWRITE(sc, OHCI_BUS_OPT, reg2); 531 532 /* Initialize registers */ 533 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 535 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 538 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539 fw_busreset(&sc->fc); 540 541 /* Enable link */ 542 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543 544 /* Force to start async RX DMA */ 545 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547 fwohci_rx_enable(sc, &sc->arrq); 548 fwohci_rx_enable(sc, &sc->arrs); 549 550 /* Initialize async TX */ 551 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 /* AT Retries */ 554 OWRITE(sc, FWOHCI_RETRY, 555 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559 db_tr->xfer = NULL; 560 } 561 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563 db_tr->xfer = NULL; 564 } 565 566 567 /* Enable interrupt */ 568 OWRITE(sc, FWOHCI_INTMASK, 569 OHCI_INT_ERR | OHCI_INT_PHY_SID 570 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573 fwohci_set_intr(&sc->fc, 1); 574 575} 576 577int 578fwohci_init(struct fwohci_softc *sc, device_t dev) 579{ 580 int i; 581 u_int32_t reg; 582 583 reg = OREAD(sc, OHCI_VERSION); 584 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586 587/* XXX: Available Isochrounous DMA channel probe */ 588 for( i = 0 ; i < 0x20 ; i ++ ){ 589 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 590 reg = OREAD(sc, OHCI_IRCTL(i)); 591 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 592 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 593 reg = OREAD(sc, OHCI_ITCTL(i)); 594 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 595 } 596 sc->fc.nisodma = i; 597 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 598 599 sc->fc.arq = &sc->arrq.xferq; 600 sc->fc.ars = &sc->arrs.xferq; 601 sc->fc.atq = &sc->atrq.xferq; 602 sc->fc.ats = &sc->atrs.xferq; 603 604 sc->arrq.xferq.start = NULL; 605 sc->arrs.xferq.start = NULL; 606 sc->atrq.xferq.start = fwohci_start_atq; 607 sc->atrs.xferq.start = fwohci_start_ats; 608 609 sc->arrq.xferq.drain = NULL; 610 sc->arrs.xferq.drain = NULL; 611 sc->atrq.xferq.drain = fwohci_drain_atq; 612 sc->atrs.xferq.drain = fwohci_drain_ats; 613 614 sc->arrq.ndesc = 1; 615 sc->arrs.ndesc = 1; 616 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 617 sc->atrs.ndesc = 6 / 2; 618 619 sc->arrq.ndb = NDB; 620 sc->arrs.ndb = NDB / 2; 621 sc->atrq.ndb = NDB; 622 sc->atrs.ndb = NDB / 2; 623 624 sc->arrq.dummy = NULL; 625 sc->arrs.dummy = NULL; 626 sc->atrq.dummy = NULL; 627 sc->atrs.dummy = NULL; 628 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 629 sc->fc.it[i] = &sc->it[i].xferq; 630 sc->fc.ir[i] = &sc->ir[i].xferq; 631 sc->it[i].ndb = 0; 632 sc->ir[i].ndb = 0; 633 } 634 635 sc->fc.tcode = tinfo; 636 637 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT); 638 639 if(sc->cromptr == NULL){ 640 device_printf(dev, "cromptr alloc failed."); 641 return ENOMEM; 642 } 643 sc->fc.dev = dev; 644 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 645 646 sc->fc.config_rom[1] = 0x31333934; 647 sc->fc.config_rom[2] = 0xf000a002; 648 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 649 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 650 sc->fc.config_rom[5] = 0; 651 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 652 653 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 654 655 656/* SID recieve buffer must allign 2^11 */ 657#define OHCI_SIDSIZE (1 << 11) 658 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 659 if (sc->fc.sid_buf == NULL) { 660 device_printf(dev, "sid_buf alloc failed.\n"); 661 return ENOMEM; 662 } 663 664 665 fwohci_db_init(&sc->arrq); 666 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 667 return ENOMEM; 668 669 fwohci_db_init(&sc->arrs); 670 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 671 return ENOMEM; 672 673 fwohci_db_init(&sc->atrq); 674 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 675 return ENOMEM; 676 677 fwohci_db_init(&sc->atrs); 678 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 679 return ENOMEM; 680 681 reg = OREAD(sc, FWOHCIGUID_H); 682 for( i = 0 ; i < 4 ; i ++){ 683 sc->fc.eui[3 - i] = reg & 0xff; 684 reg = reg >> 8; 685 } 686 reg = OREAD(sc, FWOHCIGUID_L); 687 for( i = 0 ; i < 4 ; i ++){ 688 sc->fc.eui[7 - i] = reg & 0xff; 689 reg = reg >> 8; 690 } 691 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 693 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 694 sc->fc.ioctl = fwohci_ioctl; 695 sc->fc.cyctimer = fwohci_cyctimer; 696 sc->fc.set_bmr = fwohci_set_bus_manager; 697 sc->fc.ibr = fwohci_ibr; 698 sc->fc.irx_enable = fwohci_irx_enable; 699 sc->fc.irx_disable = fwohci_irx_disable; 700 701 sc->fc.itx_enable = fwohci_itxbuf_enable; 702 sc->fc.itx_disable = fwohci_itx_disable; 703 sc->fc.irx_post = fwohci_irx_post; 704 sc->fc.itx_post = NULL; 705 sc->fc.timeout = fwohci_timeout; 706 sc->fc.poll = fwohci_poll; 707 sc->fc.set_intr = fwohci_set_intr; 708 709 fw_init(&sc->fc); 710 fwohci_reset(sc, dev); 711 712 return 0; 713} 714 715void 716fwohci_timeout(void *arg) 717{ 718 struct fwohci_softc *sc; 719 720 sc = (struct fwohci_softc *)arg; 721 sc->fc.timeouthandle = timeout(fwohci_timeout, 722 (void *)sc, FW_XFERTIMEOUT * hz * 10); 723} 724 725u_int32_t 726fwohci_cyctimer(struct firewire_comm *fc) 727{ 728 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 729 return(OREAD(sc, OHCI_CYCLETIMER)); 730} 731 732int 733fwohci_detach(struct fwohci_softc *sc, device_t dev) 734{ 735 int i; 736 737 if (sc->fc.sid_buf != NULL) 738 free((void *)(uintptr_t)sc->fc.sid_buf, M_DEVBUF); 739 if (sc->cromptr != NULL) 740 free((void *)sc->cromptr, M_DEVBUF); 741 742 fwohci_db_free(&sc->arrq); 743 fwohci_db_free(&sc->arrs); 744 745 fwohci_db_free(&sc->atrq); 746 fwohci_db_free(&sc->atrs); 747 748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749 fwohci_db_free(&sc->it[i]); 750 fwohci_db_free(&sc->ir[i]); 751 } 752 753 return 0; 754} 755 756#define LAST_DB(dbtr, db) do { \ 757 struct fwohcidb_tr *_dbtr = (dbtr); \ 758 int _cnt = _dbtr->dbcnt; \ 759 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 760} while (0) 761 762static void 763fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 764{ 765 int i, s; 766 int tcode, hdr_len, hdr_off, len; 767 int fsegment = -1; 768 u_int32_t off; 769 struct fw_xfer *xfer; 770 struct fw_pkt *fp; 771 volatile struct fwohci_txpkthdr *ohcifp; 772 struct fwohcidb_tr *db_tr; 773 volatile struct fwohcidb *db; 774 struct mbuf *m; 775 struct tcode_info *info; 776 static int maxdesc=0; 777 778 if(&sc->atrq == dbch){ 779 off = OHCI_ATQOFF; 780 }else if(&sc->atrs == dbch){ 781 off = OHCI_ATSOFF; 782 }else{ 783 return; 784 } 785 786 if (dbch->flags & FWOHCI_DBCH_FULL) 787 return; 788 789 s = splfw(); 790 db_tr = dbch->top; 791txloop: 792 xfer = STAILQ_FIRST(&dbch->xferq.q); 793 if(xfer == NULL){ 794 goto kick; 795 } 796 if(dbch->xferq.queued == 0 ){ 797 device_printf(sc->fc.dev, "TX queue empty\n"); 798 } 799 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 800 db_tr->xfer = xfer; 801 xfer->state = FWXF_START; 802 dbch->xferq.packets++; 803 804 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 805 tcode = fp->mode.common.tcode; 806 807 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 808 info = &tinfo[tcode]; 809 hdr_len = hdr_off = info->hdr_len; 810 /* fw_asyreq must pass valid send.len */ 811 len = xfer->send.len; 812 for( i = 0 ; i < hdr_off ; i+= 4){ 813 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 814 } 815 ohcifp->mode.common.spd = xfer->spd; 816 if (tcode == FWTCODE_STREAM ){ 817 hdr_len = 8; 818 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 819 } else if (tcode == FWTCODE_PHY) { 820 hdr_len = 12; 821 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 822 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 823 ohcifp->mode.common.spd = 0; 824 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 825 } else { 826 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 827 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 828 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 829 } 830 db = &db_tr->db[0]; 831 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 832 db->db.desc.status = 0; 833/* Specify bound timer of asy. responce */ 834 if(&sc->atrs == dbch){ 835 db->db.desc.count 836 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 837 } 838 839 db_tr->dbcnt = 2; 840 db = &db_tr->db[db_tr->dbcnt]; 841 if(len > hdr_off){ 842 if (xfer->mbuf == NULL) { 843 db->db.desc.addr 844 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 845 db->db.desc.cmd 846 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 847 db->db.desc.status = 0; 848 849 db_tr->dbcnt++; 850 } else { 851 /* XXX we assume mbuf chain is shorter than ndesc */ 852 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 853 if (m->m_len == 0) 854 /* unrecoverable error could ocurre. */ 855 continue; 856 if (db_tr->dbcnt >= dbch->ndesc) { 857 device_printf(sc->fc.dev, 858 "dbch->ndesc is too small" 859 ", trancated.\n"); 860 break; 861 } 862 db->db.desc.addr 863 = vtophys(mtod(m, caddr_t)); 864 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 865 db->db.desc.status = 0; 866 db++; 867 db_tr->dbcnt++; 868 } 869 } 870 } 871 if (maxdesc < db_tr->dbcnt) { 872 maxdesc = db_tr->dbcnt; 873 if (bootverbose) 874 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 875 } 876 /* last db */ 877 LAST_DB(db_tr, db); 878 db->db.desc.cmd |= OHCI_OUTPUT_LAST 879 | OHCI_INTERRUPT_ALWAYS 880 | OHCI_BRANCH_ALWAYS; 881 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 882 883 if(fsegment == -1 ) 884 fsegment = db_tr->dbcnt; 885 if (dbch->pdb_tr != NULL) { 886 LAST_DB(dbch->pdb_tr, db); 887 db->db.desc.depend |= db_tr->dbcnt; 888 } 889 dbch->pdb_tr = db_tr; 890 db_tr = STAILQ_NEXT(db_tr, link); 891 if(db_tr != dbch->bottom){ 892 goto txloop; 893 } else { 894 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 895 dbch->flags |= FWOHCI_DBCH_FULL; 896 } 897kick: 898 if (firewire_debug) printf("kick\n"); 899 /* kick asy q */ 900 901 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 902 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 903 } else { 904 if (bootverbose) 905 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 906 OREAD(sc, OHCI_DMACTL(off))); 907 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 908 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 909 dbch->xferq.flag |= FWXFERQ_RUNNING; 910 } 911 912 dbch->top = db_tr; 913 splx(s); 914 return; 915} 916 917static void 918fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 919{ 920 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 921 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 922 return; 923} 924 925static void 926fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 927{ 928 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 929 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 930 return; 931} 932 933static void 934fwohci_start_atq(struct firewire_comm *fc) 935{ 936 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 937 fwohci_start( sc, &(sc->atrq)); 938 return; 939} 940 941static void 942fwohci_start_ats(struct firewire_comm *fc) 943{ 944 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 945 fwohci_start( sc, &(sc->atrs)); 946 return; 947} 948 949void 950fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 951{ 952 int s, err = 0; 953 struct fwohcidb_tr *tr; 954 volatile struct fwohcidb *db; 955 struct fw_xfer *xfer; 956 u_int32_t off; 957 u_int stat; 958 int packets; 959 struct firewire_comm *fc = (struct firewire_comm *)sc; 960 if(&sc->atrq == dbch){ 961 off = OHCI_ATQOFF; 962 }else if(&sc->atrs == dbch){ 963 off = OHCI_ATSOFF; 964 }else{ 965 return; 966 } 967 s = splfw(); 968 tr = dbch->bottom; 969 packets = 0; 970 while(dbch->xferq.queued > 0){ 971 LAST_DB(tr, db); 972 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 973 if (fc->status != FWBUSRESET) 974 /* maybe out of order?? */ 975 goto out; 976 } 977 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 978#ifdef OHCI_DEBUG 979 dump_dma(sc, ch); 980 dump_db(sc, ch); 981#endif 982/* Stop DMA */ 983 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 984 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 985 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 986 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 987 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 988 } 989 stat = db->db.desc.status & FWOHCIEV_MASK; 990 switch(stat){ 991 case FWOHCIEV_ACKCOMPL: 992 case FWOHCIEV_ACKPEND: 993 err = 0; 994 break; 995 case FWOHCIEV_ACKBSA: 996 case FWOHCIEV_ACKBSB: 997 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 998 case FWOHCIEV_ACKBSX: 999 err = EBUSY; 1000 break; 1001 case FWOHCIEV_FLUSHED: 1002 case FWOHCIEV_ACKTARD: 1003 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1004 err = EAGAIN; 1005 break; 1006 case FWOHCIEV_MISSACK: 1007 case FWOHCIEV_UNDRRUN: 1008 case FWOHCIEV_OVRRUN: 1009 case FWOHCIEV_DESCERR: 1010 case FWOHCIEV_DTRDERR: 1011 case FWOHCIEV_TIMEOUT: 1012 case FWOHCIEV_TCODERR: 1013 case FWOHCIEV_UNKNOWN: 1014 case FWOHCIEV_ACKDERR: 1015 case FWOHCIEV_ACKTERR: 1016 default: 1017 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1018 stat, fwohcicode[stat]); 1019 err = EINVAL; 1020 break; 1021 } 1022 if(tr->xfer != NULL){ 1023 xfer = tr->xfer; 1024 xfer->state = FWXF_SENT; 1025 if(err == EBUSY && fc->status != FWBUSRESET){ 1026 xfer->state = FWXF_BUSY; 1027 switch(xfer->act_type){ 1028 case FWACT_XFER: 1029 xfer->resp = err; 1030 if(xfer->retry_req != NULL){ 1031 xfer->retry_req(xfer); 1032 } 1033 break; 1034 default: 1035 break; 1036 } 1037 } else if( stat != FWOHCIEV_ACKPEND){ 1038 if (stat != FWOHCIEV_ACKCOMPL) 1039 xfer->state = FWXF_SENTERR; 1040 xfer->resp = err; 1041 switch(xfer->act_type){ 1042 case FWACT_XFER: 1043 fw_xfer_done(xfer); 1044 break; 1045 default: 1046 break; 1047 } 1048 } 1049 dbch->xferq.queued --; 1050 } 1051 tr->xfer = NULL; 1052 1053 packets ++; 1054 tr = STAILQ_NEXT(tr, link); 1055 dbch->bottom = tr; 1056 } 1057out: 1058 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1059 printf("make free slot\n"); 1060 dbch->flags &= ~FWOHCI_DBCH_FULL; 1061 fwohci_start(sc, dbch); 1062 } 1063 splx(s); 1064} 1065 1066static void 1067fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1068{ 1069 int i, s; 1070 struct fwohcidb_tr *tr; 1071 1072 if(xfer->state != FWXF_START) return; 1073 1074 s = splfw(); 1075 tr = dbch->bottom; 1076 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1077 if(tr->xfer == xfer){ 1078 s = splfw(); 1079 tr->xfer = NULL; 1080 dbch->xferq.queued --; 1081#if 1 1082 /* XXX */ 1083 if (tr == dbch->bottom) 1084 dbch->bottom = STAILQ_NEXT(tr, link); 1085#endif 1086 if (dbch->flags & FWOHCI_DBCH_FULL) { 1087 printf("fwohci_drain: make slot\n"); 1088 dbch->flags &= ~FWOHCI_DBCH_FULL; 1089 fwohci_start((struct fwohci_softc *)fc, dbch); 1090 } 1091 1092 splx(s); 1093 break; 1094 } 1095 tr = STAILQ_NEXT(tr, link); 1096 } 1097 splx(s); 1098 return; 1099} 1100 1101static void 1102fwohci_db_free(struct fwohci_dbch *dbch) 1103{ 1104 struct fwohcidb_tr *db_tr; 1105 int idb, i; 1106 1107 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1108 return; 1109 1110 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1111 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1112 idb < dbch->ndb; 1113 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1114 if (db_tr->buf != NULL) { 1115 free(db_tr->buf, M_DEVBUF); 1116 db_tr->buf = NULL; 1117 } 1118 } 1119 } 1120 dbch->ndb = 0; 1121 db_tr = STAILQ_FIRST(&dbch->db_trq); 1122 for (i = 0; i < dbch->npages; i++) 1123 free(dbch->pages[i], M_DEVBUF); 1124 free(db_tr, M_DEVBUF); 1125 STAILQ_INIT(&dbch->db_trq); 1126 dbch->flags &= ~FWOHCI_DBCH_INIT; 1127} 1128 1129static void 1130fwohci_db_init(struct fwohci_dbch *dbch) 1131{ 1132 int idb; 1133 struct fwohcidb_tr *db_tr; 1134 int ndbpp, i, j; 1135 1136 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1137 goto out; 1138 1139 /* allocate DB entries and attach one to each DMA channels */ 1140 /* DB entry must start at 16 bytes bounary. */ 1141 STAILQ_INIT(&dbch->db_trq); 1142 db_tr = (struct fwohcidb_tr *) 1143 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1144 M_DEVBUF, M_DONTWAIT | M_ZERO); 1145 if(db_tr == NULL){ 1146 printf("fwohci_db_init: malloc(1) failed\n"); 1147 return; 1148 } 1149 1150 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1151 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1152#if 0 1153 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1154 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1155#endif 1156 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1157 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1158 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1159 return; 1160 } 1161 for (i = 0; i < dbch->npages; i++) { 1162 dbch->pages[i] = malloc(PAGE_SIZE, M_DEVBUF, 1163 M_DONTWAIT | M_ZERO); 1164 if (dbch->pages[i] == NULL) { 1165 printf("fwohci_db_init: malloc(2) failed\n"); 1166 for (j = 0; j < i; j ++) 1167 free(dbch->pages[j], M_DEVBUF); 1168 free(db_tr, M_DEVBUF); 1169 return; 1170 } 1171 } 1172 /* Attach DB to DMA ch. */ 1173 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1174 db_tr->dbcnt = 0; 1175 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1176 + dbch->ndesc * (idb % ndbpp); 1177 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1178 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1179 dbch->xferq.bnpacket != 0) { 1180 if (idb % dbch->xferq.bnpacket == 0) 1181 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1182 ].start = (caddr_t)db_tr; 1183 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1184 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1185 ].end = (caddr_t)db_tr; 1186 } 1187 db_tr++; 1188 } 1189 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1190 = STAILQ_FIRST(&dbch->db_trq); 1191out: 1192 dbch->frag.buf = NULL; 1193 dbch->frag.len = 0; 1194 dbch->frag.plen = 0; 1195 dbch->xferq.queued = 0; 1196 dbch->pdb_tr = NULL; 1197 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1198 dbch->bottom = dbch->top; 1199 dbch->flags = FWOHCI_DBCH_INIT; 1200} 1201 1202static int 1203fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1204{ 1205 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1206 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1207 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1208 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1209 fwohci_db_free(&sc->it[dmach]); 1210 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1211 return 0; 1212} 1213 1214static int 1215fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1216{ 1217 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1218 1219 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1220 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1221 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1222 if(sc->ir[dmach].dummy != NULL){ 1223 free(sc->ir[dmach].dummy, M_DEVBUF); 1224 } 1225 sc->ir[dmach].dummy = NULL; 1226 fwohci_db_free(&sc->ir[dmach]); 1227 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1228 return 0; 1229} 1230 1231static void 1232fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1233{ 1234 qld[0] = ntohl(qld[0]); 1235 return; 1236} 1237 1238static int 1239fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1240{ 1241 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1242 int err = 0; 1243 unsigned short tag, ich; 1244 1245 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1246 ich = sc->ir[dmach].xferq.flag & 0x3f; 1247 1248#if 0 1249 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1250 wakeup(fc->ir[dmach]); 1251 return err; 1252 } 1253#endif 1254 1255 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1256 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1257 sc->ir[dmach].xferq.queued = 0; 1258 sc->ir[dmach].ndb = NDB; 1259 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1260 sc->ir[dmach].ndesc = 1; 1261 fwohci_db_init(&sc->ir[dmach]); 1262 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1263 return ENOMEM; 1264 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1265 } 1266 if(err){ 1267 device_printf(sc->fc.dev, "err in IRX setting\n"); 1268 return err; 1269 } 1270 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1271 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1272 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1273 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1274 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1275 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1276 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1277 OWRITE(sc, OHCI_IRCMD(dmach), 1278 vtophys(sc->ir[dmach].top->db) | 1); 1279 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1280 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1281 } 1282 return err; 1283} 1284 1285static int 1286fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1287{ 1288 int err = 0; 1289 int idb, z, i, dmach = 0; 1290 u_int32_t off = NULL; 1291 struct fwohcidb_tr *db_tr; 1292 1293 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1294 err = EINVAL; 1295 return err; 1296 } 1297 z = dbch->ndesc; 1298 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1299 if( &sc->it[dmach] == dbch){ 1300 off = OHCI_ITOFF(dmach); 1301 break; 1302 } 1303 } 1304 if(off == NULL){ 1305 err = EINVAL; 1306 return err; 1307 } 1308 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1309 return err; 1310 dbch->xferq.flag |= FWXFERQ_RUNNING; 1311 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1312 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1313 } 1314 db_tr = dbch->top; 1315 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1316 fwohci_add_tx_buf(db_tr, 1317 dbch->xferq.psize, dbch->xferq.flag, 1318 dbch->xferq.buf + dbch->xferq.psize * idb); 1319 if(STAILQ_NEXT(db_tr, link) == NULL){ 1320 break; 1321 } 1322 db_tr->db[0].db.desc.depend 1323 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1324 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1325 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1326 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1327 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1328 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1329 |= OHCI_INTERRUPT_ALWAYS; 1330 db_tr->db[0].db.desc.depend &= ~0xf; 1331 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1332 ~0xf; 1333 /* OHCI 1.1 and above */ 1334 db_tr->db[0].db.desc.cmd 1335 |= OHCI_INTERRUPT_ALWAYS; 1336 } 1337 } 1338 db_tr = STAILQ_NEXT(db_tr, link); 1339 } 1340 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1341 return err; 1342} 1343 1344static int 1345fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1346{ 1347 int err = 0; 1348 int idb, z, i, dmach = 0; 1349 u_int32_t off = NULL; 1350 struct fwohcidb_tr *db_tr; 1351 1352 z = dbch->ndesc; 1353 if(&sc->arrq == dbch){ 1354 off = OHCI_ARQOFF; 1355 }else if(&sc->arrs == dbch){ 1356 off = OHCI_ARSOFF; 1357 }else{ 1358 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1359 if( &sc->ir[dmach] == dbch){ 1360 off = OHCI_IROFF(dmach); 1361 break; 1362 } 1363 } 1364 } 1365 if(off == NULL){ 1366 err = EINVAL; 1367 return err; 1368 } 1369 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1370 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1371 return err; 1372 }else{ 1373 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1374 err = EBUSY; 1375 return err; 1376 } 1377 } 1378 dbch->xferq.flag |= FWXFERQ_RUNNING; 1379 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1380 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1381 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1382 } 1383 db_tr = dbch->top; 1384 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1385 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1386 fwohci_add_rx_buf(db_tr, 1387 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1388 }else{ 1389 fwohci_add_rx_buf(db_tr, 1390 dbch->xferq.psize, dbch->xferq.flag, 1391 dbch->xferq.buf + dbch->xferq.psize * idb, 1392 dbch->dummy + sizeof(u_int32_t) * idb); 1393 } 1394 if(STAILQ_NEXT(db_tr, link) == NULL){ 1395 break; 1396 } 1397 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1398 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1399 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1400 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1401 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1402 |= OHCI_INTERRUPT_ALWAYS; 1403 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1404 ~0xf; 1405 } 1406 } 1407 db_tr = STAILQ_NEXT(db_tr, link); 1408 } 1409 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1410 dbch->buf_offset = 0; 1411 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1412 return err; 1413 }else{ 1414 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1415 } 1416 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1417 return err; 1418} 1419 1420static int 1421fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1422{ 1423 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1424 int err = 0; 1425 unsigned short tag, ich; 1426 struct fwohci_dbch *dbch; 1427 struct fw_pkt *fp; 1428 struct fwohcidb_tr *db_tr; 1429 int cycle_now, sec, cycle, cycle_match; 1430 u_int32_t stat; 1431 1432 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1433 ich = sc->it[dmach].xferq.flag & 0x3f; 1434 dbch = &sc->it[dmach]; 1435 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1436 dbch->xferq.queued = 0; 1437 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1438 dbch->ndesc = 3; 1439 fwohci_db_init(dbch); 1440 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1441 return ENOMEM; 1442 err = fwohci_tx_enable(sc, dbch); 1443 } 1444 if(err) 1445 return err; 1446 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1447 if (stat & OHCI_CNTL_DMA_ACTIVE) { 1448 if(dbch->xferq.stdma2 != NULL){ 1449 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1450 ((struct fwohcidb_tr *) 1451 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1452 |= OHCI_BRANCH_ALWAYS; 1453 ((struct fwohcidb_tr *) 1454 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1455 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1456 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1457 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1458 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1459 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1460 } 1461 } else if(!(stat & OHCI_CNTL_DMA_RUN)) { 1462 if (firewire_debug) 1463 printf("fwohci_itxbuf_enable: kick 0x%08x\n", 1464 OREAD(sc, OHCI_ITCTL(dmach))); 1465 fw_tbuf_update(&sc->fc, dmach, 0); 1466 if(dbch->xferq.stdma == NULL){ 1467 return err; 1468 } 1469#if 0 1470 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1471#endif 1472 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1473 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1474 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1475 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1476 if(dbch->xferq.stdma2 != NULL){ 1477 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1478 ((struct fwohcidb_tr *) 1479 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1480 |= OHCI_BRANCH_ALWAYS; 1481 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1482 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1483 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1484 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1485 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1486 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1487 }else{ 1488 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1489 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1490 } 1491 OWRITE(sc, OHCI_ITCMD(dmach), 1492 vtophys(((struct fwohcidb_tr *) 1493 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1494#define CYCLE_OFFSET 1 1495 if(dbch->xferq.flag & FWXFERQ_DV){ 1496 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1497 fp = (struct fw_pkt *)db_tr->buf; 1498 dbch->xferq.dvoffset = CYCLE_OFFSET; 1499 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1500 } 1501 /* 2bit second + 13bit cycle */ 1502 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1503 cycle = cycle_now & 0x1fff; 1504 sec = cycle_now >> 13; 1505#define CYCLE_MOD 0x10 1506#define CYCLE_DELAY 8 /* min delay to start DMA */ 1507 cycle = cycle + CYCLE_DELAY; 1508 if (cycle >= 8000) { 1509 sec ++; 1510 cycle -= 8000; 1511 } 1512 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1513 if (cycle >= 8000) { 1514 sec ++; 1515 if (cycle == 8000) 1516 cycle = 0; 1517 else 1518 cycle = CYCLE_MOD; 1519 } 1520 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1521 if (firewire_debug) 1522 printf("cycle_match: 0x%04x->0x%04x\n", 1523 cycle_now, cycle_match); 1524 /* Clear cycle match counter bits */ 1525 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1526 OWRITE(sc, OHCI_ITCTL(dmach), 1527 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1528 | OHCI_CNTL_DMA_RUN); 1529 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1530 } else { 1531 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1532 } 1533 return err; 1534} 1535 1536static int 1537fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1538{ 1539 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1540 int err = 0; 1541 unsigned short tag, ich; 1542 1543 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1544 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1545 ich = sc->ir[dmach].xferq.flag & 0x3f; 1546 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1547 1548 sc->ir[dmach].xferq.queued = 0; 1549 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1550 sc->ir[dmach].xferq.bnchunk; 1551 sc->ir[dmach].dummy = 1552 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1553 M_DEVBUF, M_DONTWAIT); 1554 if(sc->ir[dmach].dummy == NULL){ 1555 err = ENOMEM; 1556 return err; 1557 } 1558 sc->ir[dmach].ndesc = 2; 1559 fwohci_db_init(&sc->ir[dmach]); 1560 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1561 return ENOMEM; 1562 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1563 } 1564 if(err) 1565 return err; 1566 1567 if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1568 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1569 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1570 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1571 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1572 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1573 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1574 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1575 } 1576 }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1577 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1578 fw_rbuf_update(&sc->fc, dmach, 0); 1579 1580 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1581 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1582 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1583 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1584 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1585 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1586 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1587 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1588 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1589 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1590 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1591 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1592 }else{ 1593 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1594 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1595 } 1596 OWRITE(sc, OHCI_IRCMD(dmach), 1597 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1598 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1599 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1600 } 1601 return err; 1602} 1603 1604static int 1605fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1606{ 1607 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1608 int err = 0; 1609 1610 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1611 err = fwohci_irxpp_enable(fc, dmach); 1612 return err; 1613 }else{ 1614 err = fwohci_irxbuf_enable(fc, dmach); 1615 return err; 1616 } 1617} 1618 1619int 1620fwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1621{ 1622 u_int i; 1623 1624/* Now stopping all DMA channel */ 1625 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1626 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1627 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1628 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1629 1630 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1631 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1632 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1633 } 1634 1635/* FLUSH FIFO and reset Transmitter/Reciever */ 1636 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1637 1638/* Stop interrupt */ 1639 OWRITE(sc, FWOHCI_INTMASKCLR, 1640 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1641 | OHCI_INT_PHY_INT 1642 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1643 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1644 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1645 | OHCI_INT_PHY_BUS_R); 1646/* XXX Link down? Bus reset? */ 1647 return 0; 1648} 1649 1650int 1651fwohci_resume(struct fwohci_softc *sc, device_t dev) 1652{ 1653 int i; 1654 1655 fwohci_reset(sc, dev); 1656 /* XXX resume isochronus receive automatically. (how about TX?) */ 1657 for(i = 0; i < sc->fc.nisodma; i ++) { 1658 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1659 device_printf(sc->fc.dev, 1660 "resume iso receive ch: %d\n", i); 1661 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1662 sc->fc.irx_enable(&sc->fc, i); 1663 } 1664 } 1665 1666 bus_generic_resume(dev); 1667 sc->fc.ibr(&sc->fc); 1668 return 0; 1669} 1670 1671#define ACK_ALL 1672static void 1673fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1674{ 1675 u_int32_t irstat, itstat; 1676 u_int i; 1677 struct firewire_comm *fc = (struct firewire_comm *)sc; 1678 1679#ifdef OHCI_DEBUG 1680 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1681 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1682 stat & OHCI_INT_EN ? "DMA_EN ":"", 1683 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1684 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1685 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1686 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1687 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1688 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1689 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1690 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1691 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1692 stat & OHCI_INT_PHY_SID ? "SID ":"", 1693 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1694 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1695 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1696 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1697 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1698 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1699 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1700 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1701 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1702 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1703 stat, OREAD(sc, FWOHCI_INTMASK) 1704 ); 1705#endif 1706/* Bus reset */ 1707 if(stat & OHCI_INT_PHY_BUS_R ){ 1708 device_printf(fc->dev, "BUS reset\n"); 1709 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1710 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1711 1712 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1713 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1714 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1715 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1716 1717#if 0 1718 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1719 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1720 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1721 } 1722 1723#endif 1724 fw_busreset(fc); 1725 1726 /* XXX need to wait DMA to stop */ 1727#ifndef ACK_ALL 1728 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1729#endif 1730#if 1 1731 /* pending all pre-bus_reset packets */ 1732 fwohci_txd(sc, &sc->atrq); 1733 fwohci_txd(sc, &sc->atrs); 1734 fwohci_arcv(sc, &sc->arrs, -1); 1735 fwohci_arcv(sc, &sc->arrq, -1); 1736#endif 1737 1738 1739 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1740 /* XXX insecure ?? */ 1741 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1742 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1743 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1744 1745 } 1746 if((stat & OHCI_INT_DMA_IR )){ 1747#ifndef ACK_ALL 1748 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1749#endif 1750 irstat = OREAD(sc, OHCI_IR_STAT); 1751 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1752 for(i = 0; i < fc->nisodma ; i++){ 1753 if((irstat & (1 << i)) != 0){ 1754 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1755 fwohci_ircv(sc, &sc->ir[i], count); 1756 }else{ 1757 fwohci_rbuf_update(sc, i); 1758 } 1759 } 1760 } 1761 } 1762 if((stat & OHCI_INT_DMA_IT )){ 1763#ifndef ACK_ALL 1764 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1765#endif 1766 itstat = OREAD(sc, OHCI_IT_STAT); 1767 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1768 for(i = 0; i < fc->nisodma ; i++){ 1769 if((itstat & (1 << i)) != 0){ 1770 fwohci_tbuf_update(sc, i); 1771 } 1772 } 1773 } 1774 if((stat & OHCI_INT_DMA_PRRS )){ 1775#ifndef ACK_ALL 1776 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1777#endif 1778#if 0 1779 dump_dma(sc, ARRS_CH); 1780 dump_db(sc, ARRS_CH); 1781#endif 1782 fwohci_arcv(sc, &sc->arrs, count); 1783 } 1784 if((stat & OHCI_INT_DMA_PRRQ )){ 1785#ifndef ACK_ALL 1786 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1787#endif 1788#if 0 1789 dump_dma(sc, ARRQ_CH); 1790 dump_db(sc, ARRQ_CH); 1791#endif 1792 fwohci_arcv(sc, &sc->arrq, count); 1793 } 1794 if(stat & OHCI_INT_PHY_SID){ 1795 caddr_t buf; 1796 int plen; 1797 1798#ifndef ACK_ALL 1799 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1800#endif 1801/* 1802** Checking whether the node is root or not. If root, turn on 1803** cycle master. 1804*/ 1805 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1806 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1807 printf("Bus reset failure\n"); 1808 goto sidout; 1809 } 1810 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1811 printf("CYCLEMASTER mode\n"); 1812 OWRITE(sc, OHCI_LNKCTL, 1813 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1814 }else{ 1815 printf("non CYCLEMASTER mode\n"); 1816 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1817 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1818 } 1819 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1820 1821 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1822 plen -= 4; /* chop control info */ 1823 buf = malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 1824 if(buf == NULL) goto sidout; 1825 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1826 buf, plen); 1827 fw_sidrcv(fc, buf, plen, 0); 1828 } 1829sidout: 1830 if((stat & OHCI_INT_DMA_ATRQ )){ 1831#ifndef ACK_ALL 1832 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1833#endif 1834 fwohci_txd(sc, &(sc->atrq)); 1835 } 1836 if((stat & OHCI_INT_DMA_ATRS )){ 1837#ifndef ACK_ALL 1838 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1839#endif 1840 fwohci_txd(sc, &(sc->atrs)); 1841 } 1842 if((stat & OHCI_INT_PW_ERR )){ 1843#ifndef ACK_ALL 1844 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1845#endif 1846 device_printf(fc->dev, "posted write error\n"); 1847 } 1848 if((stat & OHCI_INT_ERR )){ 1849#ifndef ACK_ALL 1850 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1851#endif 1852 device_printf(fc->dev, "unrecoverable error\n"); 1853 } 1854 if((stat & OHCI_INT_PHY_INT)) { 1855#ifndef ACK_ALL 1856 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1857#endif 1858 device_printf(fc->dev, "phy int\n"); 1859 } 1860 1861 return; 1862} 1863 1864void 1865fwohci_intr(void *arg) 1866{ 1867 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1868 u_int32_t stat; 1869 1870 if (!(sc->intmask & OHCI_INT_EN)) { 1871 /* polling mode */ 1872 return; 1873 } 1874 1875 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1876 if (stat == 0xffffffff) { 1877 device_printf(sc->fc.dev, 1878 "device physically ejected?\n"); 1879 return; 1880 } 1881#ifdef ACK_ALL 1882 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1883#endif 1884 fwohci_intr_body(sc, stat, -1); 1885 } 1886} 1887 1888static void 1889fwohci_poll(struct firewire_comm *fc, int quick, int count) 1890{ 1891 int s; 1892 u_int32_t stat; 1893 struct fwohci_softc *sc; 1894 1895 1896 sc = (struct fwohci_softc *)fc; 1897 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1898 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1899 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1900#if 0 1901 if (!quick) { 1902#else 1903 if (1) { 1904#endif 1905 stat = OREAD(sc, FWOHCI_INTSTAT); 1906 if (stat == 0) 1907 return; 1908 if (stat == 0xffffffff) { 1909 device_printf(sc->fc.dev, 1910 "device physically ejected?\n"); 1911 return; 1912 } 1913#ifdef ACK_ALL 1914 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1915#endif 1916 } 1917 s = splfw(); 1918 fwohci_intr_body(sc, stat, count); 1919 splx(s); 1920} 1921 1922static void 1923fwohci_set_intr(struct firewire_comm *fc, int enable) 1924{ 1925 struct fwohci_softc *sc; 1926 1927 sc = (struct fwohci_softc *)fc; 1928 if (bootverbose) 1929 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1930 if (enable) { 1931 sc->intmask |= OHCI_INT_EN; 1932 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1933 } else { 1934 sc->intmask &= ~OHCI_INT_EN; 1935 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1936 } 1937} 1938 1939static void 1940fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1941{ 1942 int stat; 1943 struct firewire_comm *fc = &sc->fc; 1944 struct fw_pkt *fp; 1945 struct fwohci_dbch *dbch; 1946 struct fwohcidb_tr *db_tr; 1947 1948 dbch = &sc->it[dmach]; 1949#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1950 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1951 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1952/* 1953 * Overwrite highest significant 4 bits timestamp information 1954 */ 1955 fp = (struct fw_pkt *)db_tr->buf; 1956 fp->mode.ld[2] &= htonl(0xffff0fff); 1957 fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1958 } 1959#endif 1960 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1961 switch(stat){ 1962 case FWOHCIEV_ACKCOMPL: 1963#if 1 1964 if (dbch->xferq.flag & FWXFERQ_DV) { 1965 struct ciphdr *ciph; 1966 int timer, timestamp, cycl, diff; 1967 static int last_timer=0; 1968 1969 timer = (fc->cyctimer(fc) >> 12) & 0xffff; 1970 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1971 fp = (struct fw_pkt *)db_tr->buf; 1972 ciph = (struct ciphdr *) &fp->mode.ld[1]; 1973 timestamp = db_tr->db[2].db.desc.count & 0xffff; 1974 cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 1975 diff = cycl - (timestamp & 0xf) - CYCLE_OFFSET; 1976 if (diff < 0) 1977 diff += 16; 1978 if (diff > 8) 1979 diff -= 16; 1980 if (firewire_debug || diff != 0) 1981 printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 1982 " cyc: 0x%x diff: %+1d\n", 1983 ciph->dbc, last_timer, timestamp, cycl, diff); 1984 last_timer = timer; 1985 /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 1986 } 1987#endif 1988 fw_tbuf_update(fc, dmach, 1); 1989 break; 1990 default: 1991 device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 1992 fw_tbuf_update(fc, dmach, 0); 1993 break; 1994 } 1995 fwohci_itxbuf_enable(fc, dmach); 1996} 1997 1998static void 1999fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2000{ 2001 struct firewire_comm *fc = &sc->fc; 2002 int stat; 2003 2004 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 2005 switch(stat){ 2006 case FWOHCIEV_ACKCOMPL: 2007 fw_rbuf_update(fc, dmach, 1); 2008 wakeup(fc->ir[dmach]); 2009 fwohci_irx_enable(fc, dmach); 2010 break; 2011 default: 2012 device_printf(fc->dev, "Isochronous receive err %02x\n", 2013 stat); 2014 break; 2015 } 2016} 2017 2018void 2019dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2020{ 2021 u_int32_t off, cntl, stat, cmd, match; 2022 2023 if(ch == 0){ 2024 off = OHCI_ATQOFF; 2025 }else if(ch == 1){ 2026 off = OHCI_ATSOFF; 2027 }else if(ch == 2){ 2028 off = OHCI_ARQOFF; 2029 }else if(ch == 3){ 2030 off = OHCI_ARSOFF; 2031 }else if(ch < IRX_CH){ 2032 off = OHCI_ITCTL(ch - ITX_CH); 2033 }else{ 2034 off = OHCI_IRCTL(ch - IRX_CH); 2035 } 2036 cntl = stat = OREAD(sc, off); 2037 cmd = OREAD(sc, off + 0xc); 2038 match = OREAD(sc, off + 0x10); 2039 2040 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2041 ch, 2042 cntl, 2043 stat, 2044 cmd, 2045 match); 2046 stat &= 0xffff ; 2047 if(stat & 0xff00){ 2048 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2049 ch, 2050 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2051 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2052 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2053 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2054 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2055 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2056 fwohcicode[stat & 0x1f], 2057 stat & 0x1f 2058 ); 2059 }else{ 2060 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2061 } 2062} 2063 2064void 2065dump_db(struct fwohci_softc *sc, u_int32_t ch) 2066{ 2067 struct fwohci_dbch *dbch; 2068 struct fwohcidb_tr *cp = NULL, *pp, *np; 2069 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2070 int idb, jdb; 2071 u_int32_t cmd, off; 2072 if(ch == 0){ 2073 off = OHCI_ATQOFF; 2074 dbch = &sc->atrq; 2075 }else if(ch == 1){ 2076 off = OHCI_ATSOFF; 2077 dbch = &sc->atrs; 2078 }else if(ch == 2){ 2079 off = OHCI_ARQOFF; 2080 dbch = &sc->arrq; 2081 }else if(ch == 3){ 2082 off = OHCI_ARSOFF; 2083 dbch = &sc->arrs; 2084 }else if(ch < IRX_CH){ 2085 off = OHCI_ITCTL(ch - ITX_CH); 2086 dbch = &sc->it[ch - ITX_CH]; 2087 }else { 2088 off = OHCI_IRCTL(ch - IRX_CH); 2089 dbch = &sc->ir[ch - IRX_CH]; 2090 } 2091 cmd = OREAD(sc, off + 0xc); 2092 2093 if( dbch->ndb == 0 ){ 2094 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2095 return; 2096 } 2097 pp = dbch->top; 2098 prev = pp->db; 2099 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2100 if(pp == NULL){ 2101 curr = NULL; 2102 goto outdb; 2103 } 2104 cp = STAILQ_NEXT(pp, link); 2105 if(cp == NULL){ 2106 curr = NULL; 2107 goto outdb; 2108 } 2109 np = STAILQ_NEXT(cp, link); 2110 if(cp == NULL) break; 2111 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2112 if((cmd & 0xfffffff0) 2113 == vtophys(&(cp->db[jdb]))){ 2114 curr = cp->db; 2115 if(np != NULL){ 2116 next = np->db; 2117 }else{ 2118 next = NULL; 2119 } 2120 goto outdb; 2121 } 2122 } 2123 pp = STAILQ_NEXT(pp, link); 2124 prev = pp->db; 2125 } 2126outdb: 2127 if( curr != NULL){ 2128 printf("Prev DB %d\n", ch); 2129 print_db(prev, ch, dbch->ndesc); 2130 printf("Current DB %d\n", ch); 2131 print_db(curr, ch, dbch->ndesc); 2132 printf("Next DB %d\n", ch); 2133 print_db(next, ch, dbch->ndesc); 2134 }else{ 2135 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2136 } 2137 return; 2138} 2139 2140void 2141print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2142{ 2143 fwohcireg_t stat; 2144 int i, key; 2145 2146 if(db == NULL){ 2147 printf("No Descriptor is found\n"); 2148 return; 2149 } 2150 2151 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2152 ch, 2153 "Current", 2154 "OP ", 2155 "KEY", 2156 "INT", 2157 "BR ", 2158 "len", 2159 "Addr", 2160 "Depend", 2161 "Stat", 2162 "Cnt"); 2163 for( i = 0 ; i <= max ; i ++){ 2164 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2165#if __FreeBSD_version >= 500000 2166 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2167#else 2168 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2169#endif 2170 vtophys(&db[i]), 2171 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2172 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2173 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2174 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2175 db[i].db.desc.cmd & 0xffff, 2176 db[i].db.desc.addr, 2177 db[i].db.desc.depend, 2178 db[i].db.desc.status, 2179 db[i].db.desc.count); 2180 stat = db[i].db.desc.status; 2181 if(stat & 0xff00){ 2182 printf(" %s%s%s%s%s%s %s(%x)\n", 2183 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2184 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2185 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2186 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2187 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2188 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2189 fwohcicode[stat & 0x1f], 2190 stat & 0x1f 2191 ); 2192 }else{ 2193 printf(" Nostat\n"); 2194 } 2195 if(key == OHCI_KEY_ST2 ){ 2196 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2197 db[i+1].db.immed[0], 2198 db[i+1].db.immed[1], 2199 db[i+1].db.immed[2], 2200 db[i+1].db.immed[3]); 2201 } 2202 if(key == OHCI_KEY_DEVICE){ 2203 return; 2204 } 2205 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2206 == OHCI_BRANCH_ALWAYS){ 2207 return; 2208 } 2209 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2210 == OHCI_OUTPUT_LAST){ 2211 return; 2212 } 2213 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2214 == OHCI_INPUT_LAST){ 2215 return; 2216 } 2217 if(key == OHCI_KEY_ST2 ){ 2218 i++; 2219 } 2220 } 2221 return; 2222} 2223 2224void 2225fwohci_ibr(struct firewire_comm *fc) 2226{ 2227 struct fwohci_softc *sc; 2228 u_int32_t fun; 2229 2230 sc = (struct fwohci_softc *)fc; 2231 2232 /* 2233 * Set root hold-off bit so that non cyclemaster capable node 2234 * shouldn't became the root node. 2235 */ 2236#if 1 2237 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2238 fun |= FW_PHY_IBR | FW_PHY_RHB; 2239 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2240#else /* Short bus reset */ 2241 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2242 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2243 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2244#endif 2245} 2246 2247void 2248fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2249{ 2250 struct fwohcidb_tr *db_tr, *fdb_tr; 2251 struct fwohci_dbch *dbch; 2252 struct fw_pkt *fp; 2253 volatile struct fwohci_txpkthdr *ohcifp; 2254 unsigned short chtag; 2255 int idb; 2256 2257 dbch = &sc->it[dmach]; 2258 chtag = sc->it[dmach].xferq.flag & 0xff; 2259 2260 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2261 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2262/* 2263device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2264*/ 2265 if(bulkxfer->flag != 0){ 2266 return; 2267 } 2268 bulkxfer->flag = 1; 2269 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2270 db_tr->db[0].db.desc.cmd 2271 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2272 fp = (struct fw_pkt *)db_tr->buf; 2273 ohcifp = (volatile struct fwohci_txpkthdr *) 2274 db_tr->db[1].db.immed; 2275 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2276 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2277 ohcifp->mode.stream.chtag = chtag; 2278 ohcifp->mode.stream.tcode = 0xa; 2279 ohcifp->mode.stream.spd = 4; 2280 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2281 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2282 2283 db_tr->db[2].db.desc.cmd 2284 = OHCI_OUTPUT_LAST 2285 | OHCI_UPDATE 2286 | OHCI_BRANCH_ALWAYS 2287 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2288 db_tr->db[2].db.desc.status = 0; 2289 db_tr->db[2].db.desc.count = 0; 2290 db_tr->db[0].db.desc.depend 2291 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2292 db_tr->db[dbch->ndesc - 1].db.desc.depend 2293 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2294 bulkxfer->end = (caddr_t)db_tr; 2295 db_tr = STAILQ_NEXT(db_tr, link); 2296 } 2297 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2298 db_tr->db[0].db.desc.depend &= ~0xf; 2299 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2300#if 0 2301/**/ 2302 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2303 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2304/**/ 2305#endif 2306 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2307 /* OHCI 1.1 and above */ 2308 db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2309 2310 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2311 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2312/* 2313device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2314*/ 2315 return; 2316} 2317 2318static int 2319fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2320 int mode, void *buf) 2321{ 2322 volatile struct fwohcidb *db = db_tr->db; 2323 int err = 0; 2324 if(buf == 0){ 2325 err = EINVAL; 2326 return err; 2327 } 2328 db_tr->buf = buf; 2329 db_tr->dbcnt = 3; 2330 db_tr->dummy = NULL; 2331 2332 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2333 2334 db[2].db.desc.depend = 0; 2335 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2336 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2337 2338 db[0].db.desc.status = 0; 2339 db[0].db.desc.count = 0; 2340 2341 db[2].db.desc.status = 0; 2342 db[2].db.desc.count = 0; 2343 if( mode & FWXFERQ_STREAM ){ 2344 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2345 if(mode & FWXFERQ_PACKET ){ 2346 db[2].db.desc.cmd 2347 |= OHCI_INTERRUPT_ALWAYS; 2348 } 2349 } 2350 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2351 return 1; 2352} 2353 2354int 2355fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2356 void *buf, void *dummy) 2357{ 2358 volatile struct fwohcidb *db = db_tr->db; 2359 int i; 2360 void *dbuf[2]; 2361 int dsiz[2]; 2362 2363 if(buf == 0){ 2364 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2365 if(buf == NULL) return 0; 2366 db_tr->buf = buf; 2367 db_tr->dbcnt = 1; 2368 db_tr->dummy = NULL; 2369 dsiz[0] = size; 2370 dbuf[0] = buf; 2371 }else if(dummy == NULL){ 2372 db_tr->buf = buf; 2373 db_tr->dbcnt = 1; 2374 db_tr->dummy = NULL; 2375 dsiz[0] = size; 2376 dbuf[0] = buf; 2377 }else{ 2378 db_tr->buf = buf; 2379 db_tr->dbcnt = 2; 2380 db_tr->dummy = dummy; 2381 dsiz[0] = sizeof(u_int32_t); 2382 dsiz[1] = size; 2383 dbuf[0] = dummy; 2384 dbuf[1] = buf; 2385 } 2386 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2387 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2388 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2389 if( mode & FWXFERQ_STREAM ){ 2390 db[i].db.desc.cmd |= OHCI_UPDATE; 2391 } 2392 db[i].db.desc.status = 0; 2393 db[i].db.desc.count = dsiz[i]; 2394 } 2395 if( mode & FWXFERQ_STREAM ){ 2396 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2397 if(mode & FWXFERQ_PACKET ){ 2398 db[db_tr->dbcnt - 1].db.desc.cmd 2399 |= OHCI_INTERRUPT_ALWAYS; 2400 } 2401 } 2402 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2403 return 1; 2404} 2405 2406static void 2407fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2408{ 2409 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2410 struct firewire_comm *fc = (struct firewire_comm *)sc; 2411 int z = 1; 2412 struct fw_pkt *fp; 2413 u_int8_t *ld; 2414 u_int32_t off = NULL; 2415 u_int32_t stat; 2416 u_int32_t *qld; 2417 u_int32_t reg; 2418 u_int spd; 2419 u_int dmach; 2420 int len, i, plen; 2421 caddr_t buf; 2422 2423 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2424 if( &sc->ir[dmach] == dbch){ 2425 off = OHCI_IROFF(dmach); 2426 break; 2427 } 2428 } 2429 if(off == NULL){ 2430 return; 2431 } 2432 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2433 fwohci_irx_disable(&sc->fc, dmach); 2434 return; 2435 } 2436 2437 odb_tr = NULL; 2438 db_tr = dbch->top; 2439 i = 0; 2440 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2441 if (count >= 0 && count-- == 0) 2442 break; 2443 ld = (u_int8_t *)db_tr->buf; 2444 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2445 /* skip timeStamp */ 2446 ld += sizeof(struct fwohci_trailer); 2447 } 2448 qld = (u_int32_t *)ld; 2449 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2450/* 2451{ 2452device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2453 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2454} 2455*/ 2456 fp=(struct fw_pkt *)ld; 2457 qld[0] = htonl(qld[0]); 2458 plen = sizeof(struct fw_isohdr) 2459 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2460 ld += plen; 2461 len -= plen; 2462 buf = db_tr->buf; 2463 db_tr->buf = NULL; 2464 stat = reg & 0x1f; 2465 spd = reg & 0x3; 2466 switch(stat){ 2467 case FWOHCIEV_ACKCOMPL: 2468 case FWOHCIEV_ACKPEND: 2469 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2470 break; 2471 default: 2472 free(buf, M_DEVBUF); 2473 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2474 break; 2475 } 2476 i++; 2477 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2478 dbch->xferq.flag, 0, NULL); 2479 db_tr->db[0].db.desc.depend &= ~0xf; 2480 if(dbch->pdb_tr != NULL){ 2481 dbch->pdb_tr->db[0].db.desc.depend |= z; 2482 } else { 2483 /* XXX should be rewritten in better way */ 2484 dbch->bottom->db[0].db.desc.depend |= z; 2485 } 2486 dbch->pdb_tr = db_tr; 2487 db_tr = STAILQ_NEXT(db_tr, link); 2488 } 2489 dbch->top = db_tr; 2490 reg = OREAD(sc, OHCI_DMACTL(off)); 2491 if (reg & OHCI_CNTL_DMA_ACTIVE) 2492 return; 2493 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2494 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2495 dbch->top = db_tr; 2496 fwohci_irx_enable(fc, dmach); 2497} 2498 2499#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2500static int 2501fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2502{ 2503 int i; 2504 2505 for( i = 4; i < hlen ; i+=4){ 2506 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2507 } 2508 2509 switch(fp->mode.common.tcode){ 2510 case FWTCODE_RREQQ: 2511 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2512 case FWTCODE_WRES: 2513 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2514 case FWTCODE_WREQQ: 2515 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2516 case FWTCODE_RREQB: 2517 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2518 case FWTCODE_RRESQ: 2519 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2520 case FWTCODE_WREQB: 2521 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2522 + sizeof(u_int32_t); 2523 case FWTCODE_LREQ: 2524 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2525 + sizeof(u_int32_t); 2526 case FWTCODE_RRESB: 2527 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2528 + sizeof(u_int32_t); 2529 case FWTCODE_LRES: 2530 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2531 + sizeof(u_int32_t); 2532 case FWOHCITCODE_PHY: 2533 return 16; 2534 } 2535 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2536 return 0; 2537} 2538 2539static void 2540fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2541{ 2542 struct fwohcidb_tr *db_tr; 2543 int z = 1; 2544 struct fw_pkt *fp; 2545 u_int8_t *ld; 2546 u_int32_t stat, off; 2547 u_int spd; 2548 int len, plen, hlen, pcnt, poff = 0, rlen; 2549 int s; 2550 caddr_t buf; 2551 int resCount; 2552 2553 if(&sc->arrq == dbch){ 2554 off = OHCI_ARQOFF; 2555 }else if(&sc->arrs == dbch){ 2556 off = OHCI_ARSOFF; 2557 }else{ 2558 return; 2559 } 2560 2561 s = splfw(); 2562 db_tr = dbch->top; 2563 pcnt = 0; 2564 /* XXX we cannot handle a packet which lies in more than two buf */ 2565 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2566 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2567 resCount = db_tr->db[0].db.desc.count; 2568 len = dbch->xferq.psize - resCount 2569 - dbch->buf_offset; 2570 while (len > 0 ) { 2571 if (count >= 0 && count-- == 0) 2572 goto out; 2573 if(dbch->frag.buf != NULL){ 2574 buf = dbch->frag.buf; 2575 if (dbch->frag.plen < 0) { 2576 /* incomplete header */ 2577 int hlen; 2578 2579 hlen = - dbch->frag.plen; 2580 rlen = hlen - dbch->frag.len; 2581 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2582 ld += rlen; 2583 len -= rlen; 2584 dbch->frag.len += rlen; 2585#if 0 2586 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2587#endif 2588 fp=(struct fw_pkt *)dbch->frag.buf; 2589 dbch->frag.plen 2590 = fwohci_get_plen(sc, fp, hlen); 2591 if (dbch->frag.plen == 0) 2592 goto out; 2593 } 2594 rlen = dbch->frag.plen - dbch->frag.len; 2595#if 0 2596 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2597#endif 2598 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2599 rlen); 2600 ld += rlen; 2601 len -= rlen; 2602 plen = dbch->frag.plen; 2603 dbch->frag.buf = NULL; 2604 dbch->frag.plen = 0; 2605 dbch->frag.len = 0; 2606 poff = 0; 2607 }else{ 2608 fp=(struct fw_pkt *)ld; 2609 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2610 switch(fp->mode.common.tcode){ 2611 case FWTCODE_RREQQ: 2612 case FWTCODE_WRES: 2613 case FWTCODE_WREQQ: 2614 case FWTCODE_RRESQ: 2615 case FWOHCITCODE_PHY: 2616 hlen = 12; 2617 break; 2618 case FWTCODE_RREQB: 2619 case FWTCODE_WREQB: 2620 case FWTCODE_LREQ: 2621 case FWTCODE_RRESB: 2622 case FWTCODE_LRES: 2623 hlen = 16; 2624 break; 2625 default: 2626 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2627 goto out; 2628 } 2629 if (len >= hlen) { 2630 plen = fwohci_get_plen(sc, fp, hlen); 2631 if (plen == 0) 2632 goto out; 2633 plen = (plen + 3) & ~3; 2634 len -= plen; 2635 } else { 2636 plen = -hlen; 2637 len -= hlen; 2638 } 2639 if(resCount > 0 || len > 0){ 2640 buf = malloc( dbch->xferq.psize, 2641 M_DEVBUF, M_NOWAIT); 2642 if(buf == NULL){ 2643 printf("cannot malloc!\n"); 2644 free(db_tr->buf, M_DEVBUF); 2645 goto out; 2646 } 2647 bcopy(ld, buf, plen); 2648 poff = 0; 2649 dbch->frag.buf = NULL; 2650 dbch->frag.plen = 0; 2651 dbch->frag.len = 0; 2652 }else if(len < 0){ 2653 dbch->frag.buf = db_tr->buf; 2654 if (plen < 0) { 2655#if 0 2656 printf("plen < 0:" 2657 "hlen: %d len: %d\n", 2658 hlen, len); 2659#endif 2660 dbch->frag.len = hlen + len; 2661 dbch->frag.plen = -hlen; 2662 } else { 2663 dbch->frag.len = plen + len; 2664 dbch->frag.plen = plen; 2665 } 2666 bcopy(ld, db_tr->buf, dbch->frag.len); 2667 buf = NULL; 2668 }else{ 2669 buf = db_tr->buf; 2670 poff = ld - (u_int8_t *)buf; 2671 dbch->frag.buf = NULL; 2672 dbch->frag.plen = 0; 2673 dbch->frag.len = 0; 2674 } 2675 ld += plen; 2676 } 2677 if( buf != NULL){ 2678/* DMA result-code will be written at the tail of packet */ 2679 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2680 spd = (stat >> 5) & 0x3; 2681 stat &= 0x1f; 2682 switch(stat){ 2683 case FWOHCIEV_ACKPEND: 2684#if 0 2685 printf("fwohci_arcv: ack pending..\n"); 2686#endif 2687 /* fall through */ 2688 case FWOHCIEV_ACKCOMPL: 2689 if( poff != 0 ) 2690 bcopy(buf+poff, buf, plen - 4); 2691 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2692 break; 2693 case FWOHCIEV_BUSRST: 2694 free(buf, M_DEVBUF); 2695 if (sc->fc.status != FWBUSRESET) 2696 printf("got BUSRST packet!?\n"); 2697 break; 2698 default: 2699 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2700#if 0 /* XXX */ 2701 goto out; 2702#endif 2703 break; 2704 } 2705 } 2706 pcnt ++; 2707 }; 2708out: 2709 if (resCount == 0) { 2710 /* done on this buffer */ 2711 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2712 dbch->xferq.flag, 0, NULL); 2713 dbch->bottom->db[0].db.desc.depend |= z; 2714 dbch->bottom = db_tr; 2715 db_tr = STAILQ_NEXT(db_tr, link); 2716 dbch->top = db_tr; 2717 dbch->buf_offset = 0; 2718 } else { 2719 dbch->buf_offset = dbch->xferq.psize - resCount; 2720 break; 2721 } 2722 /* XXX make sure DMA is not dead */ 2723 } 2724#if 0 2725 if (pcnt < 1) 2726 printf("fwohci_arcv: no packets\n"); 2727#endif 2728 splx(s); 2729} 2730