fwohci.c revision 108655
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108655 2003-01-04 10:21:11Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirereg.h> 73#include <dev/firewire/fwohcireg.h> 74#include <dev/firewire/fwohcivar.h> 75#include <dev/firewire/firewire_phy.h> 76 77#undef OHCI_DEBUG 78 79static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 80 "STOR","LOAD","NOP ","STOP",}; 81static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 82 "UNDEF","REG","SYS","DEV"}; 83char fwohcicode[32][0x20]={ 84 "No stat","Undef","long","miss Ack err", 85 "underrun","overrun","desc err", "data read err", 86 "data write err","bus reset","timeout","tcode err", 87 "Undef","Undef","unknown event","flushed", 88 "Undef","ack complete","ack pend","Undef", 89 "ack busy_X","ack busy_A","ack busy_B","Undef", 90 "Undef","Undef","Undef","ack tardy", 91 "Undef","ack data_err","ack type_err",""}; 92#define MAX_SPEED 2 93extern char linkspeed[MAX_SPEED+1][0x10]; 94extern int maxrec[MAX_SPEED+1]; 95static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 96u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 97 98static struct tcode_info tinfo[] = { 99/* hdr_len block flag*/ 100/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 101/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102/* 2 WRES */ {12, FWTI_RES}, 103/* 3 XXX */ { 0, 0}, 104/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 105/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 106/* 6 RRESQ */ {16, FWTI_RES}, 107/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 108/* 8 CYCS */ { 0, 0}, 109/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 110/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 111/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 112/* c XXX */ { 0, 0}, 113/* d XXX */ { 0, 0}, 114/* e PHY */ {12, FWTI_REQ}, 115/* f XXX */ { 0, 0} 116}; 117 118#define OHCI_WRITE_SIGMASK 0xffff0000 119#define OHCI_READ_SIGMASK 0xffff0000 120 121#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 122#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 123 124static void fwohci_ibr __P((struct firewire_comm *)); 125static void fwohci_db_init __P((struct fwohci_dbch *)); 126static void fwohci_db_free __P((struct fwohci_dbch *)); 127static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 128static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 130static void fwohci_start_atq __P((struct firewire_comm *)); 131static void fwohci_start_ats __P((struct firewire_comm *)); 132static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 133static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 134static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 136static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 137static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 138static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 139static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_irx_enable __P((struct firewire_comm *, int)); 141static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 143static int fwohci_irx_disable __P((struct firewire_comm *, int)); 144static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 145static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 146static int fwohci_itx_disable __P((struct firewire_comm *, int)); 147static void fwohci_timeout __P((void *)); 148static void fwohci_poll __P((struct firewire_comm *, int, int)); 149static void fwohci_set_intr __P((struct firewire_comm *, int)); 150static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 151static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 152static void dump_db __P((struct fwohci_softc *, u_int32_t)); 153static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 154static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 155static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 156static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 157static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 158void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 159 160/* 161 * memory allocated for DMA programs 162 */ 163#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 164 165/* #define NDB 1024 */ 166#define NDB FWMAXQUEUE 167#define NDVDB (DVBUF * NDB) 168 169#define OHCI_VERSION 0x00 170#define OHCI_CROMHDR 0x18 171#define OHCI_BUS_OPT 0x20 172#define OHCI_BUSIRMC (1 << 31) 173#define OHCI_BUSCMC (1 << 30) 174#define OHCI_BUSISC (1 << 29) 175#define OHCI_BUSBMC (1 << 28) 176#define OHCI_BUSPMC (1 << 27) 177#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 178 OHCI_BUSBMC | OHCI_BUSPMC 179 180#define OHCI_EUID_HI 0x24 181#define OHCI_EUID_LO 0x28 182 183#define OHCI_CROMPTR 0x34 184#define OHCI_HCCCTL 0x50 185#define OHCI_HCCCTLCLR 0x54 186#define OHCI_AREQHI 0x100 187#define OHCI_AREQHICLR 0x104 188#define OHCI_AREQLO 0x108 189#define OHCI_AREQLOCLR 0x10c 190#define OHCI_PREQHI 0x110 191#define OHCI_PREQHICLR 0x114 192#define OHCI_PREQLO 0x118 193#define OHCI_PREQLOCLR 0x11c 194#define OHCI_PREQUPPER 0x120 195 196#define OHCI_SID_BUF 0x64 197#define OHCI_SID_CNT 0x68 198#define OHCI_SID_CNT_MASK 0xffc 199 200#define OHCI_IT_STAT 0x90 201#define OHCI_IT_STATCLR 0x94 202#define OHCI_IT_MASK 0x98 203#define OHCI_IT_MASKCLR 0x9c 204 205#define OHCI_IR_STAT 0xa0 206#define OHCI_IR_STATCLR 0xa4 207#define OHCI_IR_MASK 0xa8 208#define OHCI_IR_MASKCLR 0xac 209 210#define OHCI_LNKCTL 0xe0 211#define OHCI_LNKCTLCLR 0xe4 212 213#define OHCI_PHYACCESS 0xec 214#define OHCI_CYCLETIMER 0xf0 215 216#define OHCI_DMACTL(off) (off) 217#define OHCI_DMACTLCLR(off) (off + 4) 218#define OHCI_DMACMD(off) (off + 0xc) 219#define OHCI_DMAMATCH(off) (off + 0x10) 220 221#define OHCI_ATQOFF 0x180 222#define OHCI_ATQCTL OHCI_ATQOFF 223#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 224#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 225#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 226 227#define OHCI_ATSOFF 0x1a0 228#define OHCI_ATSCTL OHCI_ATSOFF 229#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 230#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 231#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 232 233#define OHCI_ARQOFF 0x1c0 234#define OHCI_ARQCTL OHCI_ARQOFF 235#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 236#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 237#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 238 239#define OHCI_ARSOFF 0x1e0 240#define OHCI_ARSCTL OHCI_ARSOFF 241#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 242#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 243#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 244 245#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 246#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 247#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 248#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 249 250#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 251#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 252#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 253#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 254#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 255 256d_ioctl_t fwohci_ioctl; 257 258/* 259 * Communication with PHY device 260 */ 261static u_int32_t 262fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 263{ 264 u_int32_t fun; 265 266 addr &= 0xf; 267 data &= 0xff; 268 269 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 270 OWRITE(sc, OHCI_PHYACCESS, fun); 271 DELAY(100); 272 273 return(fwphy_rddata( sc, addr)); 274} 275 276static u_int32_t 277fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 278{ 279 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 280 int i; 281 u_int32_t bm; 282 283#define OHCI_CSR_DATA 0x0c 284#define OHCI_CSR_COMP 0x10 285#define OHCI_CSR_CONT 0x14 286#define OHCI_BUS_MANAGER_ID 0 287 288 OWRITE(sc, OHCI_CSR_DATA, node); 289 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 290 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 291 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 292 DELAY(100); 293 bm = OREAD(sc, OHCI_CSR_DATA); 294 if((bm & 0x3f) == 0x3f) 295 bm = node; 296 if (bootverbose) 297 device_printf(sc->fc.dev, 298 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 299 300 return(bm); 301} 302 303static u_int32_t 304fwphy_rddata(struct fwohci_softc *sc, u_int addr) 305{ 306 u_int32_t fun, stat; 307 u_int i, retry = 0; 308 309 addr &= 0xf; 310#define MAX_RETRY 100 311again: 312 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 313 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 314 OWRITE(sc, OHCI_PHYACCESS, fun); 315 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 316 fun = OREAD(sc, OHCI_PHYACCESS); 317 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 318 break; 319 DELAY(1000); 320 } 321 if(i >= MAX_RETRY) { 322 device_printf(sc->fc.dev, "cannot read phy\n"); 323#if 0 324 return 0; /* XXX */ 325#else 326 if (++retry < MAX_RETRY) { 327 DELAY(1000); 328 goto again; 329 } 330#endif 331 } 332 /* Make sure that SCLK is started */ 333 stat = OREAD(sc, FWOHCI_INTSTAT); 334 if ((stat & OHCI_INT_REG_FAIL) != 0 || 335 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 336 if (++retry < MAX_RETRY) { 337 DELAY(1000); 338 goto again; 339 } 340 } 341 if (bootverbose || retry >= MAX_RETRY) 342 device_printf(sc->fc.dev, 343 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 344#undef MAX_RETRY 345 return((fun >> PHYDEV_RDDATA )& 0xff); 346} 347/* Device specific ioctl. */ 348int 349fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350{ 351 struct firewire_softc *sc; 352 struct fwohci_softc *fc; 353 int unit = DEV2UNIT(dev); 354 int err = 0; 355 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356 u_int32_t *dmach = (u_int32_t *) data; 357 358 sc = devclass_get_softc(firewire_devclass, unit); 359 if(sc == NULL){ 360 return(EINVAL); 361 } 362 fc = (struct fwohci_softc *)sc->fc; 363 364 if (!data) 365 return(EINVAL); 366 367 switch (cmd) { 368 case FWOHCI_WRREG: 369#define OHCI_MAX_REG 0x800 370 if(reg->addr <= OHCI_MAX_REG){ 371 OWRITE(fc, reg->addr, reg->data); 372 reg->data = OREAD(fc, reg->addr); 373 }else{ 374 err = EINVAL; 375 } 376 break; 377 case FWOHCI_RDREG: 378 if(reg->addr <= OHCI_MAX_REG){ 379 reg->data = OREAD(fc, reg->addr); 380 }else{ 381 err = EINVAL; 382 } 383 break; 384/* Read DMA descriptors for debug */ 385 case DUMPDMA: 386 if(*dmach <= OHCI_MAX_DMA_CH ){ 387 dump_dma(fc, *dmach); 388 dump_db(fc, *dmach); 389 }else{ 390 err = EINVAL; 391 } 392 break; 393 default: 394 break; 395 } 396 return err; 397} 398 399static int 400fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 401{ 402 u_int32_t reg, reg2; 403 int e1394a = 1; 404/* 405 * probe PHY parameters 406 * 0. to prove PHY version, whether compliance of 1394a. 407 * 1. to probe maximum speed supported by the PHY and 408 * number of port supported by core-logic. 409 * It is not actually available port on your PC . 410 */ 411 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 412#if 0 413 /* XXX wait for SCLK. */ 414 DELAY(100000); 415#endif 416 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417 418 if((reg >> 5) != 7 ){ 419 sc->fc.mode &= ~FWPHYASYST; 420 sc->fc.nport = reg & FW_PHY_NP; 421 sc->fc.speed = reg & FW_PHY_SPD >> 6; 422 if (sc->fc.speed > MAX_SPEED) { 423 device_printf(dev, "invalid speed %d (fixed to %d).\n", 424 sc->fc.speed, MAX_SPEED); 425 sc->fc.speed = MAX_SPEED; 426 } 427 sc->fc.maxrec = maxrec[sc->fc.speed]; 428 device_printf(dev, 429 "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 sc->fc.maxrec = maxrec[sc->fc.speed]; 442 device_printf(dev, 443 "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 444 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 445 446 /* check programPhyEnable */ 447 reg2 = fwphy_rddata(sc, 5); 448#if 0 449 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 450#else /* XXX force to enable 1394a */ 451 if (e1394a) { 452#endif 453 if (bootverbose) 454 device_printf(dev, 455 "Enable 1394a Enhancements\n"); 456 /* enable EAA EMC */ 457 reg2 |= 0x03; 458 /* set aPhyEnhanceEnable */ 459 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 460 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 461 } else { 462 /* for safe */ 463 reg2 &= ~0x83; 464 } 465 reg2 = fwphy_wrdata(sc, 5, reg2); 466 } 467 468 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 469 if((reg >> 5) == 7 ){ 470 reg = fwphy_rddata(sc, 4); 471 reg |= 1 << 6; 472 fwphy_wrdata(sc, 4, reg); 473 reg = fwphy_rddata(sc, 4); 474 } 475 return 0; 476} 477 478 479void 480fwohci_reset(struct fwohci_softc *sc, device_t dev) 481{ 482 int i; 483 u_int32_t reg, reg2; 484 struct fwohcidb_tr *db_tr; 485 486/* Disable interrupt */ 487 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 488 489/* Now stopping all DMA channel */ 490 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 493 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 494 495 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 496 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 497 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 499 } 500 501/* FLUSH FIFO and reset Transmitter/Reciever */ 502 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 503 if (bootverbose) 504 device_printf(dev, "resetting OHCI..."); 505 i = 0; 506 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 507 if (i++ > 100) break; 508 DELAY(1000); 509 } 510 if (bootverbose) 511 printf("done (loop=%d)\n", i); 512 513 reg = OREAD(sc, OHCI_BUS_OPT); 514 reg2 = reg | OHCI_BUSFNC; 515 /* XXX */ 516 if (((reg & 0x0000f000) >> 12) < 10) 517 reg2 = (reg2 & 0xffff0fff) | (10 << 12); 518 if (bootverbose) 519 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 520 OWRITE(sc, OHCI_BUS_OPT, reg2); 521 522 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 523 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 524 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 525 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 526 527 fwohci_probe_phy(sc, dev); 528 529 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 530 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 531 532 /* enable link */ 533 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 534 fw_busreset(&sc->fc); 535 536 /* force to start rx dma */ 537 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 538 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 539 fwohci_rx_enable(sc, &sc->arrq); 540 fwohci_rx_enable(sc, &sc->arrs); 541 542 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 543 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 544 db_tr->xfer = NULL; 545 } 546 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 547 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 548 db_tr->xfer = NULL; 549 } 550 551 OWRITE(sc, FWOHCI_RETRY, 552 (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 553 OWRITE(sc, FWOHCI_INTMASK, 554 OHCI_INT_ERR | OHCI_INT_PHY_SID 555 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 556 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 557 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 558 fwohci_set_intr(&sc->fc, 1); 559 560 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 561 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562} 563 564int 565fwohci_init(struct fwohci_softc *sc, device_t dev) 566{ 567 int i; 568 u_int32_t reg; 569 570 reg = OREAD(sc, OHCI_VERSION); 571 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 572 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 573 574/* XXX: Available Isochrounous DMA channel probe */ 575 for( i = 0 ; i < 0x20 ; i ++ ){ 576 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 577 reg = OREAD(sc, OHCI_IRCTL(i)); 578 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 579 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 580 reg = OREAD(sc, OHCI_ITCTL(i)); 581 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 582 } 583 sc->fc.nisodma = i; 584 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 585 586 sc->fc.arq = &sc->arrq.xferq; 587 sc->fc.ars = &sc->arrs.xferq; 588 sc->fc.atq = &sc->atrq.xferq; 589 sc->fc.ats = &sc->atrs.xferq; 590 591 sc->arrq.xferq.start = NULL; 592 sc->arrs.xferq.start = NULL; 593 sc->atrq.xferq.start = fwohci_start_atq; 594 sc->atrs.xferq.start = fwohci_start_ats; 595 596 sc->arrq.xferq.drain = NULL; 597 sc->arrs.xferq.drain = NULL; 598 sc->atrq.xferq.drain = fwohci_drain_atq; 599 sc->atrs.xferq.drain = fwohci_drain_ats; 600 601 sc->arrq.ndesc = 1; 602 sc->arrs.ndesc = 1; 603 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 604 sc->atrs.ndesc = 6 / 2; 605 606 sc->arrq.ndb = NDB; 607 sc->arrs.ndb = NDB / 2; 608 sc->atrq.ndb = NDB; 609 sc->atrs.ndb = NDB / 2; 610 611 sc->arrq.dummy = NULL; 612 sc->arrs.dummy = NULL; 613 sc->atrq.dummy = NULL; 614 sc->atrs.dummy = NULL; 615 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 616 sc->fc.it[i] = &sc->it[i].xferq; 617 sc->fc.ir[i] = &sc->ir[i].xferq; 618 sc->it[i].ndb = 0; 619 sc->ir[i].ndb = 0; 620 } 621 622 sc->fc.tcode = tinfo; 623 624 sc->cromptr = (u_int32_t *) 625 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 626 627 if(sc->cromptr == NULL){ 628 device_printf(dev, "cromptr alloc failed."); 629 return ENOMEM; 630 } 631 sc->fc.dev = dev; 632 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 633 634 sc->fc.config_rom[1] = 0x31333934; 635 sc->fc.config_rom[2] = 0xf000a002; 636 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 637 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 638 sc->fc.config_rom[5] = 0; 639 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 640 641 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 642 643 644/* SID recieve buffer must allign 2^11 */ 645#define OHCI_SIDSIZE (1 << 11) 646 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 647 0x10000, 0xffffffff, OHCI_SIDSIZE); 648 if (sc->fc.sid_buf == NULL) { 649 device_printf(dev, "sid_buf alloc failed.\n"); 650 return ENOMEM; 651 } 652 653 654 fwohci_db_init(&sc->arrq); 655 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 656 return ENOMEM; 657 658 fwohci_db_init(&sc->arrs); 659 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 660 return ENOMEM; 661 662 fwohci_db_init(&sc->atrq); 663 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 664 return ENOMEM; 665 666 fwohci_db_init(&sc->atrs); 667 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 668 return ENOMEM; 669 670 reg = OREAD(sc, FWOHCIGUID_H); 671 for( i = 0 ; i < 4 ; i ++){ 672 sc->fc.eui[3 - i] = reg & 0xff; 673 reg = reg >> 8; 674 } 675 reg = OREAD(sc, FWOHCIGUID_L); 676 for( i = 0 ; i < 4 ; i ++){ 677 sc->fc.eui[7 - i] = reg & 0xff; 678 reg = reg >> 8; 679 } 680 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 681 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 682 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 683 sc->fc.ioctl = fwohci_ioctl; 684 sc->fc.cyctimer = fwohci_cyctimer; 685 sc->fc.set_bmr = fwohci_set_bus_manager; 686 sc->fc.ibr = fwohci_ibr; 687 sc->fc.irx_enable = fwohci_irx_enable; 688 sc->fc.irx_disable = fwohci_irx_disable; 689 690 sc->fc.itx_enable = fwohci_itxbuf_enable; 691 sc->fc.itx_disable = fwohci_itx_disable; 692 sc->fc.irx_post = fwohci_irx_post; 693 sc->fc.itx_post = NULL; 694 sc->fc.timeout = fwohci_timeout; 695 sc->fc.poll = fwohci_poll; 696 sc->fc.set_intr = fwohci_set_intr; 697 698 fw_init(&sc->fc); 699 fwohci_reset(sc, dev); 700 701 return 0; 702} 703 704void 705fwohci_timeout(void *arg) 706{ 707 struct fwohci_softc *sc; 708 709 sc = (struct fwohci_softc *)arg; 710 sc->fc.timeouthandle = timeout(fwohci_timeout, 711 (void *)sc, FW_XFERTIMEOUT * hz * 10); 712} 713 714u_int32_t 715fwohci_cyctimer(struct firewire_comm *fc) 716{ 717 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 718 return(OREAD(sc, OHCI_CYCLETIMER)); 719} 720 721int 722fwohci_detach(struct fwohci_softc *sc, device_t dev) 723{ 724 int i; 725 726 if (sc->fc.sid_buf != NULL) 727 contigfree((void *)(uintptr_t)sc->fc.sid_buf, 728 OHCI_SIDSIZE, M_DEVBUF); 729 if (sc->cromptr != NULL) 730 contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF); 731 732 fwohci_db_free(&sc->arrq); 733 fwohci_db_free(&sc->arrs); 734 735 fwohci_db_free(&sc->atrq); 736 fwohci_db_free(&sc->atrs); 737 738 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 739 fwohci_db_free(&sc->it[i]); 740 fwohci_db_free(&sc->ir[i]); 741 } 742 743 return 0; 744} 745 746#define LAST_DB(dbtr, db) do { \ 747 struct fwohcidb_tr *_dbtr = (dbtr); \ 748 int _cnt = _dbtr->dbcnt; \ 749 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 750} while (0) 751 752static void 753fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 754{ 755 int i, s; 756 int tcode, hdr_len, hdr_off, len; 757 int fsegment = -1; 758 u_int32_t off; 759 struct fw_xfer *xfer; 760 struct fw_pkt *fp; 761 volatile struct fwohci_txpkthdr *ohcifp; 762 struct fwohcidb_tr *db_tr; 763 volatile struct fwohcidb *db; 764 struct mbuf *m; 765 struct tcode_info *info; 766 static int maxdesc=0; 767 768 if(&sc->atrq == dbch){ 769 off = OHCI_ATQOFF; 770 }else if(&sc->atrs == dbch){ 771 off = OHCI_ATSOFF; 772 }else{ 773 return; 774 } 775 776 if (dbch->flags & FWOHCI_DBCH_FULL) 777 return; 778 779 s = splfw(); 780 db_tr = dbch->top; 781txloop: 782 xfer = STAILQ_FIRST(&dbch->xferq.q); 783 if(xfer == NULL){ 784 goto kick; 785 } 786 if(dbch->xferq.queued == 0 ){ 787 device_printf(sc->fc.dev, "TX queue empty\n"); 788 } 789 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 790 db_tr->xfer = xfer; 791 xfer->state = FWXF_START; 792 dbch->xferq.packets++; 793 794 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 795 tcode = fp->mode.common.tcode; 796 797 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 798 info = &tinfo[tcode]; 799 hdr_len = hdr_off = info->hdr_len; 800 /* fw_asyreq must pass valid send.len */ 801 len = xfer->send.len; 802 for( i = 0 ; i < hdr_off ; i+= 4){ 803 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 804 } 805 ohcifp->mode.common.spd = xfer->spd; 806 if (tcode == FWTCODE_STREAM ){ 807 hdr_len = 8; 808 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 809 } else if (tcode == FWTCODE_PHY) { 810 hdr_len = 12; 811 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 812 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 813 ohcifp->mode.common.spd = 0; 814 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 815 } else { 816 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 817 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 818 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 819 } 820 db = &db_tr->db[0]; 821 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 822 db->db.desc.status = 0; 823/* Specify bound timer of asy. responce */ 824 if(&sc->atrs == dbch){ 825 db->db.desc.count 826 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 827 } 828 829 db_tr->dbcnt = 2; 830 db = &db_tr->db[db_tr->dbcnt]; 831 if(len > hdr_off){ 832 if (xfer->mbuf == NULL) { 833 db->db.desc.addr 834 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 835 db->db.desc.cmd 836 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 837 db->db.desc.status = 0; 838 839 db_tr->dbcnt++; 840 } else { 841 /* XXX we assume mbuf chain is shorter than ndesc */ 842 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 843 if (m->m_len == 0) 844 /* unrecoverable error could ocurre. */ 845 continue; 846 if (db_tr->dbcnt >= dbch->ndesc) { 847 device_printf(sc->fc.dev, 848 "dbch->ndesc is too small" 849 ", trancated.\n"); 850 break; 851 } 852 db->db.desc.addr 853 = vtophys(mtod(m, caddr_t)); 854 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 855 db->db.desc.status = 0; 856 db++; 857 db_tr->dbcnt++; 858 } 859 } 860 } 861 if (maxdesc < db_tr->dbcnt) { 862 maxdesc = db_tr->dbcnt; 863 if (bootverbose) 864 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 865 } 866 /* last db */ 867 LAST_DB(db_tr, db); 868 db->db.desc.cmd |= OHCI_OUTPUT_LAST 869 | OHCI_INTERRUPT_ALWAYS 870 | OHCI_BRANCH_ALWAYS; 871 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 872 873 if(fsegment == -1 ) 874 fsegment = db_tr->dbcnt; 875 if (dbch->pdb_tr != NULL) { 876 LAST_DB(dbch->pdb_tr, db); 877 db->db.desc.depend |= db_tr->dbcnt; 878 } 879 dbch->pdb_tr = db_tr; 880 db_tr = STAILQ_NEXT(db_tr, link); 881 if(db_tr != dbch->bottom){ 882 goto txloop; 883 } else { 884 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 885 dbch->flags |= FWOHCI_DBCH_FULL; 886 } 887kick: 888 if (firewire_debug) printf("kick\n"); 889 /* kick asy q */ 890 891 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 892 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 893 } else { 894 if (bootverbose) 895 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 896 OREAD(sc, OHCI_DMACTL(off))); 897 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 898 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 899 dbch->xferq.flag |= FWXFERQ_RUNNING; 900 } 901 902 dbch->top = db_tr; 903 splx(s); 904 return; 905} 906 907static void 908fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 909{ 910 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 911 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 912 return; 913} 914 915static void 916fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 917{ 918 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 919 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 920 return; 921} 922 923static void 924fwohci_start_atq(struct firewire_comm *fc) 925{ 926 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 927 fwohci_start( sc, &(sc->atrq)); 928 return; 929} 930 931static void 932fwohci_start_ats(struct firewire_comm *fc) 933{ 934 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 935 fwohci_start( sc, &(sc->atrs)); 936 return; 937} 938 939void 940fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 941{ 942 int s, err = 0; 943 struct fwohcidb_tr *tr; 944 volatile struct fwohcidb *db; 945 struct fw_xfer *xfer; 946 u_int32_t off; 947 u_int stat; 948 int packets; 949 struct firewire_comm *fc = (struct firewire_comm *)sc; 950 if(&sc->atrq == dbch){ 951 off = OHCI_ATQOFF; 952 }else if(&sc->atrs == dbch){ 953 off = OHCI_ATSOFF; 954 }else{ 955 return; 956 } 957 s = splfw(); 958 tr = dbch->bottom; 959 packets = 0; 960 while(dbch->xferq.queued > 0){ 961 LAST_DB(tr, db); 962 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 963 if (fc->status != FWBUSRESET) 964 /* maybe out of order?? */ 965 goto out; 966 } 967 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 968#ifdef OHCI_DEBUG 969 dump_dma(sc, ch); 970 dump_db(sc, ch); 971#endif 972/* Stop DMA */ 973 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 974 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 975 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 976 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 977 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 978 } 979 stat = db->db.desc.status & FWOHCIEV_MASK; 980 switch(stat){ 981 case FWOHCIEV_ACKCOMPL: 982 case FWOHCIEV_ACKPEND: 983 err = 0; 984 break; 985 case FWOHCIEV_ACKBSA: 986 case FWOHCIEV_ACKBSB: 987 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 988 case FWOHCIEV_ACKBSX: 989 err = EBUSY; 990 break; 991 case FWOHCIEV_FLUSHED: 992 case FWOHCIEV_ACKTARD: 993 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 994 err = EAGAIN; 995 break; 996 case FWOHCIEV_MISSACK: 997 case FWOHCIEV_UNDRRUN: 998 case FWOHCIEV_OVRRUN: 999 case FWOHCIEV_DESCERR: 1000 case FWOHCIEV_DTRDERR: 1001 case FWOHCIEV_TIMEOUT: 1002 case FWOHCIEV_TCODERR: 1003 case FWOHCIEV_UNKNOWN: 1004 case FWOHCIEV_ACKDERR: 1005 case FWOHCIEV_ACKTERR: 1006 default: 1007 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1008 stat, fwohcicode[stat]); 1009 err = EINVAL; 1010 break; 1011 } 1012 if(tr->xfer != NULL){ 1013 xfer = tr->xfer; 1014 xfer->state = FWXF_SENT; 1015 if(err == EBUSY && fc->status != FWBUSRESET){ 1016 xfer->state = FWXF_BUSY; 1017 switch(xfer->act_type){ 1018 case FWACT_XFER: 1019 xfer->resp = err; 1020 if(xfer->retry_req != NULL){ 1021 xfer->retry_req(xfer); 1022 } 1023 break; 1024 default: 1025 break; 1026 } 1027 } else if( stat != FWOHCIEV_ACKPEND){ 1028 if (stat != FWOHCIEV_ACKCOMPL) 1029 xfer->state = FWXF_SENTERR; 1030 xfer->resp = err; 1031 switch(xfer->act_type){ 1032 case FWACT_XFER: 1033 fw_xfer_done(xfer); 1034 break; 1035 default: 1036 break; 1037 } 1038 } 1039 dbch->xferq.queued --; 1040 } 1041 tr->xfer = NULL; 1042 1043 packets ++; 1044 tr = STAILQ_NEXT(tr, link); 1045 dbch->bottom = tr; 1046 } 1047out: 1048 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1049 printf("make free slot\n"); 1050 dbch->flags &= ~FWOHCI_DBCH_FULL; 1051 fwohci_start(sc, dbch); 1052 } 1053 splx(s); 1054} 1055 1056static void 1057fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1058{ 1059 int i, s; 1060 struct fwohcidb_tr *tr; 1061 1062 if(xfer->state != FWXF_START) return; 1063 1064 s = splfw(); 1065 tr = dbch->bottom; 1066 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1067 if(tr->xfer == xfer){ 1068 s = splfw(); 1069 tr->xfer = NULL; 1070 dbch->xferq.queued --; 1071#if 1 1072 /* XXX */ 1073 if (tr == dbch->bottom) 1074 dbch->bottom = STAILQ_NEXT(tr, link); 1075#endif 1076 if (dbch->flags & FWOHCI_DBCH_FULL) { 1077 printf("fwohci_drain: make slot\n"); 1078 dbch->flags &= ~FWOHCI_DBCH_FULL; 1079 fwohci_start((struct fwohci_softc *)fc, dbch); 1080 } 1081 1082 splx(s); 1083 break; 1084 } 1085 tr = STAILQ_NEXT(tr, link); 1086 } 1087 splx(s); 1088 return; 1089} 1090 1091static void 1092fwohci_db_free(struct fwohci_dbch *dbch) 1093{ 1094 struct fwohcidb_tr *db_tr; 1095 int idb; 1096 1097 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1098 return; 1099 1100 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1101 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1102 idb < dbch->ndb; 1103 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1104 if (db_tr->buf != NULL) { 1105 free(db_tr->buf, M_DEVBUF); 1106 db_tr->buf = NULL; 1107 } 1108 } 1109 } 1110 dbch->ndb = 0; 1111 db_tr = STAILQ_FIRST(&dbch->db_trq); 1112 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1113 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1114 free(db_tr, M_DEVBUF); 1115 STAILQ_INIT(&dbch->db_trq); 1116 dbch->flags &= ~FWOHCI_DBCH_INIT; 1117} 1118 1119static void 1120fwohci_db_init(struct fwohci_dbch *dbch) 1121{ 1122 int idb; 1123 struct fwohcidb *db; 1124 struct fwohcidb_tr *db_tr; 1125 1126 1127 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1128 goto out; 1129 1130 /* allocate DB entries and attach one to each DMA channels */ 1131 /* DB entry must start at 16 bytes bounary. */ 1132 STAILQ_INIT(&dbch->db_trq); 1133 db_tr = (struct fwohcidb_tr *) 1134 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1135 M_DEVBUF, M_DONTWAIT | M_ZERO); 1136 if(db_tr == NULL){ 1137 printf("fwohci_db_init: malloc failed\n"); 1138 return; 1139 } 1140 db = (struct fwohcidb *) 1141 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1142 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1143 if(db == NULL){ 1144 printf("fwohci_db_init: contigmalloc failed\n"); 1145 free(db_tr, M_DEVBUF); 1146 return; 1147 } 1148 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1149 /* Attach DB to DMA ch. */ 1150 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1151 db_tr->dbcnt = 0; 1152 db_tr->db = &db[idb * dbch->ndesc]; 1153 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1154 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1155 dbch->xferq.bnpacket != 0) { 1156 /* XXX what thoes for? */ 1157 if (idb % dbch->xferq.bnpacket == 0) 1158 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1159 ].start = (caddr_t)db_tr; 1160 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1161 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1162 ].end = (caddr_t)db_tr; 1163 } 1164 db_tr++; 1165 } 1166 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1167 = STAILQ_FIRST(&dbch->db_trq); 1168out: 1169 dbch->frag.buf = NULL; 1170 dbch->frag.len = 0; 1171 dbch->frag.plen = 0; 1172 dbch->xferq.queued = 0; 1173 dbch->pdb_tr = NULL; 1174 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1175 dbch->bottom = dbch->top; 1176 dbch->flags = FWOHCI_DBCH_INIT; 1177} 1178 1179static int 1180fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1181{ 1182 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1183 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1184 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1185 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1186 fwohci_db_free(&sc->it[dmach]); 1187 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1188 return 0; 1189} 1190 1191static int 1192fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1193{ 1194 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1195 1196 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1197 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1198 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1199 if(sc->ir[dmach].dummy != NULL){ 1200 free(sc->ir[dmach].dummy, M_DEVBUF); 1201 } 1202 sc->ir[dmach].dummy = NULL; 1203 fwohci_db_free(&sc->ir[dmach]); 1204 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1205 return 0; 1206} 1207 1208static void 1209fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1210{ 1211 qld[0] = ntohl(qld[0]); 1212 return; 1213} 1214 1215static int 1216fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1217{ 1218 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1219 int err = 0; 1220 unsigned short tag, ich; 1221 1222 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1223 ich = sc->ir[dmach].xferq.flag & 0x3f; 1224 1225#if 0 1226 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1227 wakeup(fc->ir[dmach]); 1228 return err; 1229 } 1230#endif 1231 1232 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1233 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1234 sc->ir[dmach].xferq.queued = 0; 1235 sc->ir[dmach].ndb = NDB; 1236 sc->ir[dmach].xferq.psize = FWPMAX_S400; 1237 sc->ir[dmach].ndesc = 1; 1238 fwohci_db_init(&sc->ir[dmach]); 1239 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1240 } 1241 if(err){ 1242 device_printf(sc->fc.dev, "err in IRX setting\n"); 1243 return err; 1244 } 1245 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1246 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1247 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1248 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1249 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1250 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1251 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1252 OWRITE(sc, OHCI_IRCMD(dmach), 1253 vtophys(sc->ir[dmach].top->db) | 1); 1254 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1255 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1256 } 1257 return err; 1258} 1259 1260static int 1261fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1262{ 1263 int err = 0; 1264 int idb, z, i, dmach = 0; 1265 u_int32_t off = NULL; 1266 struct fwohcidb_tr *db_tr; 1267 1268 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1269 err = EINVAL; 1270 return err; 1271 } 1272 z = dbch->ndesc; 1273 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1274 if( &sc->it[dmach] == dbch){ 1275 off = OHCI_ITOFF(dmach); 1276 break; 1277 } 1278 } 1279 if(off == NULL){ 1280 err = EINVAL; 1281 return err; 1282 } 1283 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1284 return err; 1285 dbch->xferq.flag |= FWXFERQ_RUNNING; 1286 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1287 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1288 } 1289 db_tr = dbch->top; 1290 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1291 fwohci_add_tx_buf(db_tr, 1292 dbch->xferq.psize, dbch->xferq.flag, 1293 dbch->xferq.buf + dbch->xferq.psize * idb); 1294 if(STAILQ_NEXT(db_tr, link) == NULL){ 1295 break; 1296 } 1297 db_tr->db[0].db.desc.depend 1298 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1299 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1300 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1301 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1302 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1303 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1304 |= OHCI_INTERRUPT_ALWAYS; 1305 db_tr->db[0].db.desc.depend &= ~0xf; 1306 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1307 ~0xf; 1308 } 1309 } 1310 db_tr = STAILQ_NEXT(db_tr, link); 1311 } 1312 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1313 return err; 1314} 1315 1316static int 1317fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1318{ 1319 int err = 0; 1320 int idb, z, i, dmach = 0; 1321 u_int32_t off = NULL; 1322 struct fwohcidb_tr *db_tr; 1323 1324 z = dbch->ndesc; 1325 if(&sc->arrq == dbch){ 1326 off = OHCI_ARQOFF; 1327 }else if(&sc->arrs == dbch){ 1328 off = OHCI_ARSOFF; 1329 }else{ 1330 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1331 if( &sc->ir[dmach] == dbch){ 1332 off = OHCI_IROFF(dmach); 1333 break; 1334 } 1335 } 1336 } 1337 if(off == NULL){ 1338 err = EINVAL; 1339 return err; 1340 } 1341 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1342 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1343 return err; 1344 }else{ 1345 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1346 err = EBUSY; 1347 return err; 1348 } 1349 } 1350 dbch->xferq.flag |= FWXFERQ_RUNNING; 1351 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1352 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1353 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1354 } 1355 db_tr = dbch->top; 1356 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1357 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1358 fwohci_add_rx_buf(db_tr, 1359 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1360 }else{ 1361 fwohci_add_rx_buf(db_tr, 1362 dbch->xferq.psize, dbch->xferq.flag, 1363 dbch->xferq.buf + dbch->xferq.psize * idb, 1364 dbch->dummy + sizeof(u_int32_t) * idb); 1365 } 1366 if(STAILQ_NEXT(db_tr, link) == NULL){ 1367 break; 1368 } 1369 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1370 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1371 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1372 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1373 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1374 |= OHCI_INTERRUPT_ALWAYS; 1375 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1376 ~0xf; 1377 } 1378 } 1379 db_tr = STAILQ_NEXT(db_tr, link); 1380 } 1381 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1382 dbch->buf_offset = 0; 1383 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1384 return err; 1385 }else{ 1386 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1387 } 1388 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1389 return err; 1390} 1391 1392static int 1393fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1394{ 1395 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1396 int err = 0; 1397 unsigned short tag, ich; 1398 struct fwohci_dbch *dbch; 1399 struct fw_pkt *fp; 1400 struct fwohcidb_tr *db_tr; 1401 1402 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1403 ich = sc->it[dmach].xferq.flag & 0x3f; 1404 dbch = &sc->it[dmach]; 1405 if(dbch->ndb == 0){ 1406 dbch->xferq.queued = 0; 1407 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1408 dbch->ndesc = 3; 1409 fwohci_db_init(dbch); 1410 err = fwohci_tx_enable(sc, dbch); 1411 } 1412 if(err) 1413 return err; 1414 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1415 if(dbch->xferq.stdma2 != NULL){ 1416 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1417 ((struct fwohcidb_tr *) 1418 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1419 |= OHCI_BRANCH_ALWAYS; 1420 ((struct fwohcidb_tr *) 1421 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1422 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1423 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1424 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1425 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1426 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1427 } 1428 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1429 fw_tbuf_update(&sc->fc, dmach, 0); 1430 if(dbch->xferq.stdma == NULL){ 1431 return err; 1432 } 1433 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1434 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1435 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1436 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1437 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1438 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1439 if(dbch->xferq.stdma2 != NULL){ 1440 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1441 ((struct fwohcidb_tr *) 1442 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1443 |= OHCI_BRANCH_ALWAYS; 1444 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1445 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1446 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1447 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1448 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1449 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1450 }else{ 1451 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1452 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1453 } 1454 OWRITE(sc, OHCI_ITCMD(dmach), 1455 vtophys(((struct fwohcidb_tr *) 1456 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1457 if(dbch->xferq.flag & FWXFERQ_DV){ 1458 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1459 fp = (struct fw_pkt *)db_tr->buf; 1460 fp->mode.ld[2] = htonl(0x80000000 + 1461 ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1462 } 1463 1464 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1465 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1466 } 1467 return err; 1468} 1469 1470static int 1471fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1472{ 1473 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1474 int err = 0; 1475 unsigned short tag, ich; 1476 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1477 ich = sc->ir[dmach].xferq.flag & 0x3f; 1478 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1479 1480 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1481 sc->ir[dmach].xferq.queued = 0; 1482 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1483 sc->ir[dmach].xferq.bnchunk; 1484 sc->ir[dmach].dummy = 1485 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1486 M_DEVBUF, M_DONTWAIT); 1487 if(sc->ir[dmach].dummy == NULL){ 1488 err = ENOMEM; 1489 return err; 1490 } 1491 sc->ir[dmach].ndesc = 2; 1492 fwohci_db_init(&sc->ir[dmach]); 1493 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1494 } 1495 if(err) 1496 return err; 1497 1498 if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1499 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1500 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1501 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1502 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1503 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1504 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1505 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1506 } 1507 }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1508 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1509 fw_rbuf_update(&sc->fc, dmach, 0); 1510 1511 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1512 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1513 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1514 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1515 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1516 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1517 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1518 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1519 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1520 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1521 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1522 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1523 }else{ 1524 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1525 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1526 } 1527 OWRITE(sc, OHCI_IRCMD(dmach), 1528 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1529 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1530 } 1531 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1532 return err; 1533} 1534 1535static int 1536fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1537{ 1538 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1539 int err = 0; 1540 1541 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1542 err = fwohci_irxpp_enable(fc, dmach); 1543 return err; 1544 }else{ 1545 err = fwohci_irxbuf_enable(fc, dmach); 1546 return err; 1547 } 1548} 1549 1550int 1551fwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1552{ 1553 u_int i; 1554 1555/* Now stopping all DMA channel */ 1556 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1557 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1558 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1559 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1560 1561 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1562 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1563 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1564 } 1565 1566/* FLUSH FIFO and reset Transmitter/Reciever */ 1567 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1568 1569/* Stop interrupt */ 1570 OWRITE(sc, FWOHCI_INTMASKCLR, 1571 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1572 | OHCI_INT_PHY_INT 1573 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1574 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1575 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1576 | OHCI_INT_PHY_BUS_R); 1577/* XXX Link down? Bus reset? */ 1578 return 0; 1579} 1580 1581int 1582fwohci_resume(struct fwohci_softc *sc, device_t dev) 1583{ 1584 int i; 1585 1586 fwohci_reset(sc, dev); 1587 /* XXX resume isochronus receive automatically. (how about TX?) */ 1588 for(i = 0; i < sc->fc.nisodma; i ++) { 1589 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1590 device_printf(sc->fc.dev, 1591 "resume iso receive ch: %d\n", i); 1592 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1593 sc->fc.irx_enable(&sc->fc, i); 1594 } 1595 } 1596 1597 bus_generic_resume(dev); 1598 sc->fc.ibr(&sc->fc); 1599 return 0; 1600} 1601 1602#define ACK_ALL 1603static void 1604fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1605{ 1606 u_int32_t irstat, itstat; 1607 u_int i; 1608 struct firewire_comm *fc = (struct firewire_comm *)sc; 1609 1610#ifdef OHCI_DEBUG 1611 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1612 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1613 stat & OHCI_INT_EN ? "DMA_EN ":"", 1614 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1615 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1616 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1617 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1618 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1619 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1620 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1621 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1622 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1623 stat & OHCI_INT_PHY_SID ? "SID ":"", 1624 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1625 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1626 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1627 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1628 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1629 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1630 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1631 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1632 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1633 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1634 stat, OREAD(sc, FWOHCI_INTMASK) 1635 ); 1636#endif 1637/* Bus reset */ 1638 if(stat & OHCI_INT_PHY_BUS_R ){ 1639 device_printf(fc->dev, "BUS reset\n"); 1640 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1641 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1642 1643 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1644 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1645 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1646 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1647 1648#if 0 1649 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1650 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1651 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1652 } 1653 1654#endif 1655 fw_busreset(fc); 1656 1657 /* XXX need to wait DMA to stop */ 1658#ifndef ACK_ALL 1659 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1660#endif 1661#if 1 1662 /* pending all pre-bus_reset packets */ 1663 fwohci_txd(sc, &sc->atrq); 1664 fwohci_txd(sc, &sc->atrs); 1665 fwohci_arcv(sc, &sc->arrs, -1); 1666 fwohci_arcv(sc, &sc->arrq, -1); 1667#endif 1668 1669 1670 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1671 /* XXX insecure ?? */ 1672 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1673 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1674 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1675 1676 } 1677 if((stat & OHCI_INT_DMA_IR )){ 1678#ifndef ACK_ALL 1679 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1680#endif 1681 irstat = OREAD(sc, OHCI_IR_STAT); 1682 OWRITE(sc, OHCI_IR_STATCLR, ~0); 1683 for(i = 0; i < fc->nisodma ; i++){ 1684 if((irstat & (1 << i)) != 0){ 1685 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1686 fwohci_ircv(sc, &sc->ir[i], count); 1687 }else{ 1688 fwohci_rbuf_update(sc, i); 1689 } 1690 } 1691 } 1692 } 1693 if((stat & OHCI_INT_DMA_IT )){ 1694#ifndef ACK_ALL 1695 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1696#endif 1697 itstat = OREAD(sc, OHCI_IT_STAT); 1698 OWRITE(sc, OHCI_IT_STATCLR, ~0); 1699 for(i = 0; i < fc->nisodma ; i++){ 1700 if((itstat & (1 << i)) != 0){ 1701 fwohci_tbuf_update(sc, i); 1702 } 1703 } 1704 } 1705 if((stat & OHCI_INT_DMA_PRRS )){ 1706#ifndef ACK_ALL 1707 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1708#endif 1709#if 0 1710 dump_dma(sc, ARRS_CH); 1711 dump_db(sc, ARRS_CH); 1712#endif 1713 fwohci_arcv(sc, &sc->arrs, count); 1714 } 1715 if((stat & OHCI_INT_DMA_PRRQ )){ 1716#ifndef ACK_ALL 1717 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1718#endif 1719#if 0 1720 dump_dma(sc, ARRQ_CH); 1721 dump_db(sc, ARRQ_CH); 1722#endif 1723 fwohci_arcv(sc, &sc->arrq, count); 1724 } 1725 if(stat & OHCI_INT_PHY_SID){ 1726 caddr_t buf; 1727 int plen; 1728 1729#ifndef ACK_ALL 1730 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1731#endif 1732/* 1733** Checking whether the node is root or not. If root, turn on 1734** cycle master. 1735*/ 1736 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1737 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1738 printf("Bus reset failure\n"); 1739 goto sidout; 1740 } 1741 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1742 printf("CYCLEMASTER mode\n"); 1743 OWRITE(sc, OHCI_LNKCTL, 1744 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1745 }else{ 1746 printf("non CYCLEMASTER mode\n"); 1747 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1748 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1749 } 1750 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1751 1752 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1753 plen -= 4; /* chop control info */ 1754 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1755 if(buf == NULL) goto sidout; 1756 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1757 buf, plen); 1758 fw_sidrcv(fc, buf, plen, 0); 1759 } 1760sidout: 1761 if((stat & OHCI_INT_DMA_ATRQ )){ 1762#ifndef ACK_ALL 1763 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1764#endif 1765 fwohci_txd(sc, &(sc->atrq)); 1766 } 1767 if((stat & OHCI_INT_DMA_ATRS )){ 1768#ifndef ACK_ALL 1769 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1770#endif 1771 fwohci_txd(sc, &(sc->atrs)); 1772 } 1773 if((stat & OHCI_INT_PW_ERR )){ 1774#ifndef ACK_ALL 1775 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1776#endif 1777 device_printf(fc->dev, "posted write error\n"); 1778 } 1779 if((stat & OHCI_INT_ERR )){ 1780#ifndef ACK_ALL 1781 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1782#endif 1783 device_printf(fc->dev, "unrecoverable error\n"); 1784 } 1785 if((stat & OHCI_INT_PHY_INT)) { 1786#ifndef ACK_ALL 1787 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1788#endif 1789 device_printf(fc->dev, "phy int\n"); 1790 } 1791 1792 return; 1793} 1794 1795void 1796fwohci_intr(void *arg) 1797{ 1798 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1799 u_int32_t stat; 1800 1801 if (!(sc->intmask & OHCI_INT_EN)) { 1802 /* polling mode */ 1803 return; 1804 } 1805 1806 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1807 if (stat == 0xffffffff) { 1808 device_printf(sc->fc.dev, 1809 "device physically ejected?\n"); 1810 return; 1811 } 1812#ifdef ACK_ALL 1813 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1814#endif 1815 fwohci_intr_body(sc, stat, -1); 1816 } 1817} 1818 1819static void 1820fwohci_poll(struct firewire_comm *fc, int quick, int count) 1821{ 1822 int s; 1823 u_int32_t stat; 1824 struct fwohci_softc *sc; 1825 1826 1827 sc = (struct fwohci_softc *)fc; 1828 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1829 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1830 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1831#if 0 1832 if (!quick) { 1833#else 1834 if (1) { 1835#endif 1836 stat = OREAD(sc, FWOHCI_INTSTAT); 1837 if (stat == 0) 1838 return; 1839 if (stat == 0xffffffff) { 1840 device_printf(sc->fc.dev, 1841 "device physically ejected?\n"); 1842 return; 1843 } 1844#ifdef ACK_ALL 1845 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1846#endif 1847 } 1848 s = splfw(); 1849 fwohci_intr_body(sc, stat, count); 1850 splx(s); 1851} 1852 1853static void 1854fwohci_set_intr(struct firewire_comm *fc, int enable) 1855{ 1856 struct fwohci_softc *sc; 1857 1858 sc = (struct fwohci_softc *)fc; 1859 if (bootverbose) 1860 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1861 if (enable) { 1862 sc->intmask |= OHCI_INT_EN; 1863 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1864 } else { 1865 sc->intmask &= ~OHCI_INT_EN; 1866 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1867 } 1868} 1869 1870static void 1871fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1872{ 1873 int stat; 1874 struct firewire_comm *fc = &sc->fc; 1875 struct fw_pkt *fp; 1876 struct fwohci_dbch *dbch; 1877 struct fwohcidb_tr *db_tr; 1878 1879 dbch = &sc->it[dmach]; 1880 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1881 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1882/* 1883 * Overwrite highest significant 4 bits timestamp information 1884 */ 1885 fp = (struct fw_pkt *)db_tr->buf; 1886 fp->mode.ld[2] |= htonl(0x80000000 | 1887 ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1888 } 1889 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1890 switch(stat){ 1891 case FWOHCIEV_ACKCOMPL: 1892 fw_tbuf_update(fc, dmach, 1); 1893 break; 1894 default: 1895 fw_tbuf_update(fc, dmach, 0); 1896 break; 1897 } 1898 fwohci_itxbuf_enable(&sc->fc, dmach); 1899} 1900 1901static void 1902fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1903{ 1904 int stat; 1905 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1906 switch(stat){ 1907 case FWOHCIEV_ACKCOMPL: 1908 fw_rbuf_update(&sc->fc, dmach, 1); 1909 wakeup(sc->fc.ir[dmach]); 1910 fwohci_irx_enable(&sc->fc, dmach); 1911 break; 1912 default: 1913 break; 1914 } 1915} 1916 1917void 1918dump_dma(struct fwohci_softc *sc, u_int32_t ch) 1919{ 1920 u_int32_t off, cntl, stat, cmd, match; 1921 1922 if(ch == 0){ 1923 off = OHCI_ATQOFF; 1924 }else if(ch == 1){ 1925 off = OHCI_ATSOFF; 1926 }else if(ch == 2){ 1927 off = OHCI_ARQOFF; 1928 }else if(ch == 3){ 1929 off = OHCI_ARSOFF; 1930 }else if(ch < IRX_CH){ 1931 off = OHCI_ITCTL(ch - ITX_CH); 1932 }else{ 1933 off = OHCI_IRCTL(ch - IRX_CH); 1934 } 1935 cntl = stat = OREAD(sc, off); 1936 cmd = OREAD(sc, off + 0xc); 1937 match = OREAD(sc, off + 0x10); 1938 1939 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1940 ch, 1941 cntl, 1942 stat, 1943 cmd, 1944 match); 1945 stat &= 0xffff ; 1946 if(stat & 0xff00){ 1947 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1948 ch, 1949 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1950 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1951 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1952 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1953 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1954 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1955 fwohcicode[stat & 0x1f], 1956 stat & 0x1f 1957 ); 1958 }else{ 1959 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1960 } 1961} 1962 1963void 1964dump_db(struct fwohci_softc *sc, u_int32_t ch) 1965{ 1966 struct fwohci_dbch *dbch; 1967 struct fwohcidb_tr *cp = NULL, *pp, *np; 1968 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1969 int idb, jdb; 1970 u_int32_t cmd, off; 1971 if(ch == 0){ 1972 off = OHCI_ATQOFF; 1973 dbch = &sc->atrq; 1974 }else if(ch == 1){ 1975 off = OHCI_ATSOFF; 1976 dbch = &sc->atrs; 1977 }else if(ch == 2){ 1978 off = OHCI_ARQOFF; 1979 dbch = &sc->arrq; 1980 }else if(ch == 3){ 1981 off = OHCI_ARSOFF; 1982 dbch = &sc->arrs; 1983 }else if(ch < IRX_CH){ 1984 off = OHCI_ITCTL(ch - ITX_CH); 1985 dbch = &sc->it[ch - ITX_CH]; 1986 }else { 1987 off = OHCI_IRCTL(ch - IRX_CH); 1988 dbch = &sc->ir[ch - IRX_CH]; 1989 } 1990 cmd = OREAD(sc, off + 0xc); 1991 1992 if( dbch->ndb == 0 ){ 1993 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1994 return; 1995 } 1996 pp = dbch->top; 1997 prev = pp->db; 1998 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1999 if(pp == NULL){ 2000 curr = NULL; 2001 goto outdb; 2002 } 2003 cp = STAILQ_NEXT(pp, link); 2004 if(cp == NULL){ 2005 curr = NULL; 2006 goto outdb; 2007 } 2008 np = STAILQ_NEXT(cp, link); 2009 if(cp == NULL) break; 2010 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2011 if((cmd & 0xfffffff0) 2012 == vtophys(&(cp->db[jdb]))){ 2013 curr = cp->db; 2014 if(np != NULL){ 2015 next = np->db; 2016 }else{ 2017 next = NULL; 2018 } 2019 goto outdb; 2020 } 2021 } 2022 pp = STAILQ_NEXT(pp, link); 2023 prev = pp->db; 2024 } 2025outdb: 2026 if( curr != NULL){ 2027 printf("Prev DB %d\n", ch); 2028 print_db(prev, ch, dbch->ndesc); 2029 printf("Current DB %d\n", ch); 2030 print_db(curr, ch, dbch->ndesc); 2031 printf("Next DB %d\n", ch); 2032 print_db(next, ch, dbch->ndesc); 2033 }else{ 2034 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2035 } 2036 return; 2037} 2038 2039void 2040print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2041{ 2042 fwohcireg_t stat; 2043 int i, key; 2044 2045 if(db == NULL){ 2046 printf("No Descriptor is found\n"); 2047 return; 2048 } 2049 2050 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2051 ch, 2052 "Current", 2053 "OP ", 2054 "KEY", 2055 "INT", 2056 "BR ", 2057 "len", 2058 "Addr", 2059 "Depend", 2060 "Stat", 2061 "Cnt"); 2062 for( i = 0 ; i <= max ; i ++){ 2063 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2064 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2065 vtophys(&db[i]), 2066 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2067 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2068 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2069 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2070 db[i].db.desc.cmd & 0xffff, 2071 db[i].db.desc.addr, 2072 db[i].db.desc.depend, 2073 db[i].db.desc.status, 2074 db[i].db.desc.count); 2075 stat = db[i].db.desc.status; 2076 if(stat & 0xff00){ 2077 printf(" %s%s%s%s%s%s %s(%x)\n", 2078 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2079 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2080 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2081 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2082 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2083 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2084 fwohcicode[stat & 0x1f], 2085 stat & 0x1f 2086 ); 2087 }else{ 2088 printf(" Nostat\n"); 2089 } 2090 if(key == OHCI_KEY_ST2 ){ 2091 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2092 db[i+1].db.immed[0], 2093 db[i+1].db.immed[1], 2094 db[i+1].db.immed[2], 2095 db[i+1].db.immed[3]); 2096 } 2097 if(key == OHCI_KEY_DEVICE){ 2098 return; 2099 } 2100 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2101 == OHCI_BRANCH_ALWAYS){ 2102 return; 2103 } 2104 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2105 == OHCI_OUTPUT_LAST){ 2106 return; 2107 } 2108 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2109 == OHCI_INPUT_LAST){ 2110 return; 2111 } 2112 if(key == OHCI_KEY_ST2 ){ 2113 i++; 2114 } 2115 } 2116 return; 2117} 2118 2119void 2120fwohci_ibr(struct firewire_comm *fc) 2121{ 2122 struct fwohci_softc *sc; 2123 u_int32_t fun; 2124 2125 sc = (struct fwohci_softc *)fc; 2126 2127 /* 2128 * Set root hold-off bit so that non cyclemaster capable node 2129 * shouldn't became the root node. 2130 */ 2131 fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2132 fun |= FW_PHY_RHB; 2133 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2134#if 1 2135 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2136 fun |= FW_PHY_IBR; 2137 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2138#else 2139 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2140 fun |= FW_PHY_ISBR; 2141 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2142#endif 2143} 2144 2145void 2146fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2147{ 2148 struct fwohcidb_tr *db_tr, *fdb_tr; 2149 struct fwohci_dbch *dbch; 2150 struct fw_pkt *fp; 2151 volatile struct fwohci_txpkthdr *ohcifp; 2152 unsigned short chtag; 2153 int idb; 2154 2155 dbch = &sc->it[dmach]; 2156 chtag = sc->it[dmach].xferq.flag & 0xff; 2157 2158 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2159 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2160/* 2161device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2162*/ 2163 if(bulkxfer->flag != 0){ 2164 return; 2165 } 2166 bulkxfer->flag = 1; 2167 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2168 db_tr->db[0].db.desc.cmd 2169 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2170 fp = (struct fw_pkt *)db_tr->buf; 2171 ohcifp = (volatile struct fwohci_txpkthdr *) 2172 db_tr->db[1].db.immed; 2173 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2174 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2175 ohcifp->mode.stream.chtag = chtag; 2176 ohcifp->mode.stream.tcode = 0xa; 2177 ohcifp->mode.stream.spd = 4; 2178 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2179 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2180 2181 db_tr->db[2].db.desc.cmd 2182 = OHCI_OUTPUT_LAST 2183 | OHCI_UPDATE 2184 | OHCI_BRANCH_ALWAYS 2185 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2186 db_tr->db[2].db.desc.status = 0; 2187 db_tr->db[2].db.desc.count = 0; 2188 if(dbch->xferq.flag & FWXFERQ_DV){ 2189 db_tr->db[0].db.desc.depend 2190 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2191 db_tr->db[dbch->ndesc - 1].db.desc.depend 2192 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2193 }else{ 2194 db_tr->db[0].db.desc.depend 2195 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2196 db_tr->db[dbch->ndesc - 1].db.desc.depend 2197 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2198 } 2199 bulkxfer->end = (caddr_t)db_tr; 2200 db_tr = STAILQ_NEXT(db_tr, link); 2201 } 2202 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2203 db_tr->db[0].db.desc.depend &= ~0xf; 2204 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2205/**/ 2206 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2207 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2208/**/ 2209 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2210 2211 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2212 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2213/* 2214device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2215*/ 2216 return; 2217} 2218 2219static int 2220fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2221 int mode, void *buf) 2222{ 2223 volatile struct fwohcidb *db = db_tr->db; 2224 int err = 0; 2225 if(buf == 0){ 2226 err = EINVAL; 2227 return err; 2228 } 2229 db_tr->buf = buf; 2230 db_tr->dbcnt = 3; 2231 db_tr->dummy = NULL; 2232 2233 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2234 2235 db[2].db.desc.depend = 0; 2236 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2237 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2238 2239 db[0].db.desc.status = 0; 2240 db[0].db.desc.count = 0; 2241 2242 db[2].db.desc.status = 0; 2243 db[2].db.desc.count = 0; 2244 if( mode & FWXFERQ_STREAM ){ 2245 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2246 if(mode & FWXFERQ_PACKET ){ 2247 db[2].db.desc.cmd 2248 |= OHCI_INTERRUPT_ALWAYS; 2249 } 2250 } 2251 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2252 return 1; 2253} 2254 2255int 2256fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2257 void *buf, void *dummy) 2258{ 2259 volatile struct fwohcidb *db = db_tr->db; 2260 int i; 2261 void *dbuf[2]; 2262 int dsiz[2]; 2263 2264 if(buf == 0){ 2265 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2266 if(buf == NULL) return 0; 2267 db_tr->buf = buf; 2268 db_tr->dbcnt = 1; 2269 db_tr->dummy = NULL; 2270 dsiz[0] = size; 2271 dbuf[0] = buf; 2272 }else if(dummy == NULL){ 2273 db_tr->buf = buf; 2274 db_tr->dbcnt = 1; 2275 db_tr->dummy = NULL; 2276 dsiz[0] = size; 2277 dbuf[0] = buf; 2278 }else{ 2279 db_tr->buf = buf; 2280 db_tr->dbcnt = 2; 2281 db_tr->dummy = dummy; 2282 dsiz[0] = sizeof(u_int32_t); 2283 dsiz[1] = size; 2284 dbuf[0] = dummy; 2285 dbuf[1] = buf; 2286 } 2287 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2288 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2289 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2290 if( mode & FWXFERQ_STREAM ){ 2291 db[i].db.desc.cmd |= OHCI_UPDATE; 2292 } 2293 db[i].db.desc.status = 0; 2294 db[i].db.desc.count = dsiz[i]; 2295 } 2296 if( mode & FWXFERQ_STREAM ){ 2297 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2298 if(mode & FWXFERQ_PACKET ){ 2299 db[db_tr->dbcnt - 1].db.desc.cmd 2300 |= OHCI_INTERRUPT_ALWAYS; 2301 } 2302 } 2303 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2304 return 1; 2305} 2306 2307static void 2308fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2309{ 2310 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2311 struct firewire_comm *fc = (struct firewire_comm *)sc; 2312 int z = 1; 2313 struct fw_pkt *fp; 2314 u_int8_t *ld; 2315 u_int32_t off = NULL; 2316 u_int32_t stat; 2317 u_int32_t *qld; 2318 u_int32_t reg; 2319 u_int spd; 2320 u_int dmach; 2321 int len, i, plen; 2322 caddr_t buf; 2323 2324 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2325 if( &sc->ir[dmach] == dbch){ 2326 off = OHCI_IROFF(dmach); 2327 break; 2328 } 2329 } 2330 if(off == NULL){ 2331 return; 2332 } 2333 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2334 fwohci_irx_disable(&sc->fc, dmach); 2335 return; 2336 } 2337 2338 odb_tr = NULL; 2339 db_tr = dbch->top; 2340 i = 0; 2341 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2342 if (count >= 0 && count-- == 0) 2343 break; 2344 ld = (u_int8_t *)db_tr->buf; 2345 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2346 /* skip timeStamp */ 2347 ld += sizeof(struct fwohci_trailer); 2348 } 2349 qld = (u_int32_t *)ld; 2350 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2351/* 2352{ 2353device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2354 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2355} 2356*/ 2357 fp=(struct fw_pkt *)ld; 2358 qld[0] = htonl(qld[0]); 2359 plen = sizeof(struct fw_isohdr) 2360 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2361 ld += plen; 2362 len -= plen; 2363 buf = db_tr->buf; 2364 db_tr->buf = NULL; 2365 stat = reg & 0x1f; 2366 spd = reg & 0x3; 2367 switch(stat){ 2368 case FWOHCIEV_ACKCOMPL: 2369 case FWOHCIEV_ACKPEND: 2370 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2371 break; 2372 default: 2373 free(buf, M_DEVBUF); 2374 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2375 break; 2376 } 2377 i++; 2378 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2379 dbch->xferq.flag, 0, NULL); 2380 db_tr->db[0].db.desc.depend &= ~0xf; 2381 if(dbch->pdb_tr != NULL){ 2382 dbch->pdb_tr->db[0].db.desc.depend |= z; 2383 } else { 2384 /* XXX should be rewritten in better way */ 2385 dbch->bottom->db[0].db.desc.depend |= z; 2386 } 2387 dbch->pdb_tr = db_tr; 2388 db_tr = STAILQ_NEXT(db_tr, link); 2389 } 2390 dbch->top = db_tr; 2391 reg = OREAD(sc, OHCI_DMACTL(off)); 2392 if (reg & OHCI_CNTL_DMA_ACTIVE) 2393 return; 2394 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2395 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2396 dbch->top = db_tr; 2397 fwohci_irx_enable(fc, dmach); 2398} 2399 2400#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2401static int 2402fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2403{ 2404 int i; 2405 2406 for( i = 4; i < hlen ; i+=4){ 2407 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2408 } 2409 2410 switch(fp->mode.common.tcode){ 2411 case FWTCODE_RREQQ: 2412 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2413 case FWTCODE_WRES: 2414 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2415 case FWTCODE_WREQQ: 2416 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2417 case FWTCODE_RREQB: 2418 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2419 case FWTCODE_RRESQ: 2420 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2421 case FWTCODE_WREQB: 2422 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2423 + sizeof(u_int32_t); 2424 case FWTCODE_LREQ: 2425 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2426 + sizeof(u_int32_t); 2427 case FWTCODE_RRESB: 2428 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2429 + sizeof(u_int32_t); 2430 case FWTCODE_LRES: 2431 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2432 + sizeof(u_int32_t); 2433 case FWOHCITCODE_PHY: 2434 return 16; 2435 } 2436 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2437 return 0; 2438} 2439 2440static void 2441fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2442{ 2443 struct fwohcidb_tr *db_tr; 2444 int z = 1; 2445 struct fw_pkt *fp; 2446 u_int8_t *ld; 2447 u_int32_t stat, off; 2448 u_int spd; 2449 int len, plen, hlen, pcnt, poff = 0, rlen; 2450 int s; 2451 caddr_t buf; 2452 int resCount; 2453 2454 if(&sc->arrq == dbch){ 2455 off = OHCI_ARQOFF; 2456 }else if(&sc->arrs == dbch){ 2457 off = OHCI_ARSOFF; 2458 }else{ 2459 return; 2460 } 2461 2462 s = splfw(); 2463 db_tr = dbch->top; 2464 pcnt = 0; 2465 /* XXX we cannot handle a packet which lies in more than two buf */ 2466 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2467 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2468 resCount = db_tr->db[0].db.desc.count; 2469 len = dbch->xferq.psize - resCount 2470 - dbch->buf_offset; 2471 while (len > 0 ) { 2472 if (count >= 0 && count-- == 0) 2473 goto out; 2474 if(dbch->frag.buf != NULL){ 2475 buf = dbch->frag.buf; 2476 if (dbch->frag.plen < 0) { 2477 /* incomplete header */ 2478 int hlen; 2479 2480 hlen = - dbch->frag.plen; 2481 rlen = hlen - dbch->frag.len; 2482 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2483 ld += rlen; 2484 len -= rlen; 2485 dbch->frag.len += rlen; 2486#if 0 2487 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2488#endif 2489 fp=(struct fw_pkt *)dbch->frag.buf; 2490 dbch->frag.plen 2491 = fwohci_get_plen(sc, fp, hlen); 2492 if (dbch->frag.plen == 0) 2493 goto out; 2494 } 2495 rlen = dbch->frag.plen - dbch->frag.len; 2496#if 0 2497 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2498#endif 2499 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2500 rlen); 2501 ld += rlen; 2502 len -= rlen; 2503 plen = dbch->frag.plen; 2504 dbch->frag.buf = NULL; 2505 dbch->frag.plen = 0; 2506 dbch->frag.len = 0; 2507 poff = 0; 2508 }else{ 2509 fp=(struct fw_pkt *)ld; 2510 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2511 switch(fp->mode.common.tcode){ 2512 case FWTCODE_RREQQ: 2513 case FWTCODE_WRES: 2514 case FWTCODE_WREQQ: 2515 case FWTCODE_RRESQ: 2516 case FWOHCITCODE_PHY: 2517 hlen = 12; 2518 break; 2519 case FWTCODE_RREQB: 2520 case FWTCODE_WREQB: 2521 case FWTCODE_LREQ: 2522 case FWTCODE_RRESB: 2523 case FWTCODE_LRES: 2524 hlen = 16; 2525 break; 2526 default: 2527 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2528 goto out; 2529 } 2530 if (len >= hlen) { 2531 plen = fwohci_get_plen(sc, fp, hlen); 2532 if (plen == 0) 2533 goto out; 2534 plen = (plen + 3) & ~3; 2535 len -= plen; 2536 } else { 2537 plen = -hlen; 2538 len -= hlen; 2539 } 2540 if(resCount > 0 || len > 0){ 2541 buf = malloc( dbch->xferq.psize, 2542 M_DEVBUF, M_NOWAIT); 2543 if(buf == NULL){ 2544 printf("cannot malloc!\n"); 2545 free(db_tr->buf, M_DEVBUF); 2546 goto out; 2547 } 2548 bcopy(ld, buf, plen); 2549 poff = 0; 2550 dbch->frag.buf = NULL; 2551 dbch->frag.plen = 0; 2552 dbch->frag.len = 0; 2553 }else if(len < 0){ 2554 dbch->frag.buf = db_tr->buf; 2555 if (plen < 0) { 2556#if 0 2557 printf("plen < 0:" 2558 "hlen: %d len: %d\n", 2559 hlen, len); 2560#endif 2561 dbch->frag.len = hlen + len; 2562 dbch->frag.plen = -hlen; 2563 } else { 2564 dbch->frag.len = plen + len; 2565 dbch->frag.plen = plen; 2566 } 2567 bcopy(ld, db_tr->buf, dbch->frag.len); 2568 buf = NULL; 2569 }else{ 2570 buf = db_tr->buf; 2571 poff = ld - (u_int8_t *)buf; 2572 dbch->frag.buf = NULL; 2573 dbch->frag.plen = 0; 2574 dbch->frag.len = 0; 2575 } 2576 ld += plen; 2577 } 2578 if( buf != NULL){ 2579/* DMA result-code will be written at the tail of packet */ 2580 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2581 spd = (stat >> 5) & 0x3; 2582 stat &= 0x1f; 2583 switch(stat){ 2584 case FWOHCIEV_ACKPEND: 2585#if 0 2586 printf("fwohci_arcv: ack pending..\n"); 2587#endif 2588 /* fall through */ 2589 case FWOHCIEV_ACKCOMPL: 2590 if( poff != 0 ) 2591 bcopy(buf+poff, buf, plen - 4); 2592 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2593 break; 2594 case FWOHCIEV_BUSRST: 2595 free(buf, M_DEVBUF); 2596 if (sc->fc.status != FWBUSRESET) 2597 printf("got BUSRST packet!?\n"); 2598 break; 2599 default: 2600 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2601#if 0 /* XXX */ 2602 goto out; 2603#endif 2604 break; 2605 } 2606 } 2607 pcnt ++; 2608 }; 2609out: 2610 if (resCount == 0) { 2611 /* done on this buffer */ 2612 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2613 dbch->xferq.flag, 0, NULL); 2614 dbch->bottom->db[0].db.desc.depend |= z; 2615 dbch->bottom = db_tr; 2616 db_tr = STAILQ_NEXT(db_tr, link); 2617 dbch->top = db_tr; 2618 dbch->buf_offset = 0; 2619 } else { 2620 dbch->buf_offset = dbch->xferq.psize - resCount; 2621 break; 2622 } 2623 /* XXX make sure DMA is not dead */ 2624 } 2625#if 0 2626 if (pcnt < 1) 2627 printf("fwohci_arcv: no packets\n"); 2628#endif 2629 splx(s); 2630} 2631