fwohci.c revision 108500
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108500 2002-12-31 10:00:36Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirebusreg.h> 73#include <dev/firewire/firewirereg.h> 74#include <dev/firewire/fwohcireg.h> 75#include <dev/firewire/fwohcivar.h> 76#include <dev/firewire/firewire_phy.h> 77 78#undef OHCI_DEBUG 79 80static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 81 "STOR","LOAD","NOP ","STOP",}; 82static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83 "UNDEF","REG","SYS","DEV"}; 84char fwohcicode[32][0x20]={ 85 "No stat","Undef","long","miss Ack err", 86 "underrun","overrun","desc err", "data read err", 87 "data write err","bus reset","timeout","tcode err", 88 "Undef","Undef","unknown event","flushed", 89 "Undef","ack complete","ack pend","Undef", 90 "ack busy_X","ack busy_A","ack busy_B","Undef", 91 "Undef","Undef","Undef","ack tardy", 92 "Undef","ack data_err","ack type_err",""}; 93#define MAX_SPEED 2 94extern char linkspeed[MAX_SPEED+1][0x10]; 95extern int maxrec[MAX_SPEED+1]; 96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr __P((struct firewire_comm *)); 126static void fwohci_db_init __P((struct fwohci_dbch *)); 127static void fwohci_db_free __P((struct fwohci_dbch *)); 128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_start_atq __P((struct firewire_comm *)); 132static void fwohci_start_ats __P((struct firewire_comm *)); 133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144static int fwohci_irx_disable __P((struct firewire_comm *, int)); 145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_poll __P((struct firewire_comm *, int, int)); 150static void fwohci_set_intr __P((struct firewire_comm *, int)); 151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160 161/* 162 * memory allocated for DMA programs 163 */ 164#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166/* #define NDB 1024 */ 167#define NDB FWMAXQUEUE 168#define NDVDB (DVBUF * NDB) 169 170#define OHCI_VERSION 0x00 171#define OHCI_CROMHDR 0x18 172#define OHCI_BUS_OPT 0x20 173#define OHCI_BUSIRMC (1 << 31) 174#define OHCI_BUSCMC (1 << 30) 175#define OHCI_BUSISC (1 << 29) 176#define OHCI_BUSBMC (1 << 28) 177#define OHCI_BUSPMC (1 << 27) 178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181#define OHCI_EUID_HI 0x24 182#define OHCI_EUID_LO 0x28 183 184#define OHCI_CROMPTR 0x34 185#define OHCI_HCCCTL 0x50 186#define OHCI_HCCCTLCLR 0x54 187#define OHCI_AREQHI 0x100 188#define OHCI_AREQHICLR 0x104 189#define OHCI_AREQLO 0x108 190#define OHCI_AREQLOCLR 0x10c 191#define OHCI_PREQHI 0x110 192#define OHCI_PREQHICLR 0x114 193#define OHCI_PREQLO 0x118 194#define OHCI_PREQLOCLR 0x11c 195#define OHCI_PREQUPPER 0x120 196 197#define OHCI_SID_BUF 0x64 198#define OHCI_SID_CNT 0x68 199#define OHCI_SID_CNT_MASK 0xffc 200 201#define OHCI_IT_STAT 0x90 202#define OHCI_IT_STATCLR 0x94 203#define OHCI_IT_MASK 0x98 204#define OHCI_IT_MASKCLR 0x9c 205 206#define OHCI_IR_STAT 0xa0 207#define OHCI_IR_STATCLR 0xa4 208#define OHCI_IR_MASK 0xa8 209#define OHCI_IR_MASKCLR 0xac 210 211#define OHCI_LNKCTL 0xe0 212#define OHCI_LNKCTLCLR 0xe4 213 214#define OHCI_PHYACCESS 0xec 215#define OHCI_CYCLETIMER 0xf0 216 217#define OHCI_DMACTL(off) (off) 218#define OHCI_DMACTLCLR(off) (off + 4) 219#define OHCI_DMACMD(off) (off + 0xc) 220#define OHCI_DMAMATCH(off) (off + 0x10) 221 222#define OHCI_ATQOFF 0x180 223#define OHCI_ATQCTL OHCI_ATQOFF 224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228#define OHCI_ATSOFF 0x1a0 229#define OHCI_ATSCTL OHCI_ATSOFF 230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234#define OHCI_ARQOFF 0x1c0 235#define OHCI_ARQCTL OHCI_ARQOFF 236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240#define OHCI_ARSOFF 0x1e0 241#define OHCI_ARSCTL OHCI_ARSOFF 242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257d_ioctl_t fwohci_ioctl; 258 259/* 260 * Communication with PHY device 261 */ 262static u_int32_t 263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264{ 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275} 276 277static u_int32_t 278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279{ 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284#define OHCI_CSR_DATA 0x0c 285#define OHCI_CSR_COMP 0x10 286#define OHCI_CSR_CONT 0x14 287#define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(100); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302} 303 304static u_int32_t 305fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306{ 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311#define MAX_RETRY 100 312again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(1000); 321 } 322 if(i >= MAX_RETRY) { 323 device_printf(sc->fc.dev, "cannot read phy\n"); 324 return 0; /* XXX */ 325 } 326 /* Make sure that SCLK is started */ 327 stat = OREAD(sc, FWOHCI_INTSTAT); 328 if ((stat & OHCI_INT_REG_FAIL) != 0 || 329 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 330 if (++retry < MAX_RETRY) { 331 DELAY(1000); 332 goto again; 333 } 334 } 335 if (bootverbose || retry >= MAX_RETRY) 336 device_printf(sc->fc.dev, 337 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 338#undef MAX_RETRY 339 return((fun >> PHYDEV_RDDATA )& 0xff); 340} 341/* Device specific ioctl. */ 342int 343fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 344{ 345 struct firewire_softc *sc; 346 struct fwohci_softc *fc; 347 int unit = DEV2UNIT(dev); 348 int err = 0; 349 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 350 u_int32_t *dmach = (u_int32_t *) data; 351 352 sc = devclass_get_softc(firewire_devclass, unit); 353 if(sc == NULL){ 354 return(EINVAL); 355 } 356 fc = (struct fwohci_softc *)sc->fc; 357 358 if (!data) 359 return(EINVAL); 360 361 switch (cmd) { 362 case FWOHCI_WRREG: 363#define OHCI_MAX_REG 0x800 364 if(reg->addr <= OHCI_MAX_REG){ 365 OWRITE(fc, reg->addr, reg->data); 366 reg->data = OREAD(fc, reg->addr); 367 }else{ 368 err = EINVAL; 369 } 370 break; 371 case FWOHCI_RDREG: 372 if(reg->addr <= OHCI_MAX_REG){ 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378/* Read DMA descriptors for debug */ 379 case DUMPDMA: 380 if(*dmach <= OHCI_MAX_DMA_CH ){ 381 dump_dma(fc, *dmach); 382 dump_db(fc, *dmach); 383 }else{ 384 err = EINVAL; 385 } 386 break; 387 default: 388 break; 389 } 390 return err; 391} 392 393int 394fwohci_init(struct fwohci_softc *sc, device_t dev) 395{ 396 int err = 0; 397 int i; 398 u_int32_t reg, reg2; 399 struct fwohcidb_tr *db_tr; 400 int e1394a = 1; 401 402 reg = OREAD(sc, OHCI_VERSION); 403 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 404 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 405 406/* XXX: Available Isochrounous DMA channel probe */ 407 for( i = 0 ; i < 0x20 ; i ++ ){ 408 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 409 reg = OREAD(sc, OHCI_IRCTL(i)); 410 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 411 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 412 reg = OREAD(sc, OHCI_ITCTL(i)); 413 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 414 } 415 sc->fc.nisodma = i; 416 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 417 418 sc->fc.arq = &sc->arrq.xferq; 419 sc->fc.ars = &sc->arrs.xferq; 420 sc->fc.atq = &sc->atrq.xferq; 421 sc->fc.ats = &sc->atrs.xferq; 422 423 sc->arrq.xferq.start = NULL; 424 sc->arrs.xferq.start = NULL; 425 sc->atrq.xferq.start = fwohci_start_atq; 426 sc->atrs.xferq.start = fwohci_start_ats; 427 428 sc->arrq.xferq.drain = NULL; 429 sc->arrs.xferq.drain = NULL; 430 sc->atrq.xferq.drain = fwohci_drain_atq; 431 sc->atrs.xferq.drain = fwohci_drain_ats; 432 433 sc->arrq.ndesc = 1; 434 sc->arrs.ndesc = 1; 435 sc->atrq.ndesc = 10; 436 sc->atrs.ndesc = 10 / 2; 437 438 sc->arrq.ndb = NDB; 439 sc->arrs.ndb = NDB / 2; 440 sc->atrq.ndb = NDB; 441 sc->atrs.ndb = NDB / 2; 442 443 sc->arrq.dummy = NULL; 444 sc->arrs.dummy = NULL; 445 sc->atrq.dummy = NULL; 446 sc->atrs.dummy = NULL; 447 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 448 sc->fc.it[i] = &sc->it[i].xferq; 449 sc->fc.ir[i] = &sc->ir[i].xferq; 450 sc->it[i].ndb = 0; 451 sc->ir[i].ndb = 0; 452 } 453 454 sc->fc.tcode = tinfo; 455 456 sc->cromptr = (u_int32_t *) 457 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 458 459 if(sc->cromptr == NULL){ 460 return ENOMEM; 461 } 462 sc->fc.dev = dev; 463 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 464 465 sc->fc.config_rom[1] = 0x31333934; 466 sc->fc.config_rom[2] = 0xf000a002; 467 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 468 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 469 sc->fc.config_rom[5] = 0; 470 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 471 472 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 473 474 475 fw_init(&sc->fc); 476 477/* Disable interrupt */ 478 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 479 480/* Now stopping all DMA channel */ 481 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 482 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 483 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 484 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 485 486 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 487 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 488 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 489 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 490 } 491 492/* FLUSH FIFO and reset Transmitter/Reciever */ 493 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 494 if (bootverbose) 495 device_printf(dev, "resetting OHCI..."); 496 i = 0; 497 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 498 if (i++ > 100) break; 499 DELAY(1000); 500 } 501 if (bootverbose) 502 printf("done (loop=%d)\n", i); 503 504 reg = OREAD(sc, OHCI_BUS_OPT); 505 reg2 = reg | OHCI_BUSFNC; 506 /* XXX */ 507 if (((reg & 0x0000f000) >> 12) < 10) 508 reg2 = (reg2 & 0xffff0fff) | (10 << 12); 509 if (bootverbose) 510 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 511 OWRITE(sc, OHCI_BUS_OPT, reg2); 512 513 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 514 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 515 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 516 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 517 518/* 519 * probe PHY parameters 520 * 0. to prove PHY version, whether compliance of 1394a. 521 * 1. to probe maximum speed supported by the PHY and 522 * number of port supported by core-logic. 523 * It is not actually available port on your PC . 524 */ 525 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 526#if 0 527 /* XXX wait for SCLK. */ 528 DELAY(100000); 529#endif 530 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 531 532 if((reg >> 5) != 7 ){ 533 sc->fc.mode &= ~FWPHYASYST; 534 sc->fc.nport = reg & FW_PHY_NP; 535 sc->fc.speed = reg & FW_PHY_SPD >> 6; 536 if (sc->fc.speed > MAX_SPEED) { 537 device_printf(dev, "invalid speed %d (fixed to %d).\n", 538 sc->fc.speed, MAX_SPEED); 539 sc->fc.speed = MAX_SPEED; 540 } 541 sc->fc.maxrec = maxrec[sc->fc.speed]; 542 device_printf(dev, 543 "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 544 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 545 }else{ 546 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 547 sc->fc.mode |= FWPHYASYST; 548 sc->fc.nport = reg & FW_PHY_NP; 549 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 550 if (sc->fc.speed > MAX_SPEED) { 551 device_printf(dev, "invalid speed %d (fixed to %d).\n", 552 sc->fc.speed, MAX_SPEED); 553 sc->fc.speed = MAX_SPEED; 554 } 555 sc->fc.maxrec = maxrec[sc->fc.speed]; 556 device_printf(dev, 557 "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 558 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 559 560 /* check programPhyEnable */ 561 reg2 = fwphy_rddata(sc, 5); 562#if 0 563 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 564#else /* XXX force to enable 1394a */ 565 if (e1394a) { 566#endif 567 if (bootverbose) 568 device_printf(dev, 569 "Enable 1394a Enhancements\n"); 570 /* enable EAA EMC */ 571 reg2 |= 0x03; 572 /* set aPhyEnhanceEnable */ 573 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 574 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 575 } else { 576 /* for safe */ 577 reg2 &= ~0x83; 578 } 579 reg2 = fwphy_wrdata(sc, 5, reg2); 580 } 581 582 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 583 if((reg >> 5) == 7 ){ 584 reg = fwphy_rddata(sc, 4); 585 reg |= 1 << 6; 586 fwphy_wrdata(sc, 4, reg); 587 reg = fwphy_rddata(sc, 4); 588 } 589 590/* SID recieve buffer must allign 2^11 */ 591#define OHCI_SIDSIZE (1 << 11) 592 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 593 0x10000, 0xffffffff, OHCI_SIDSIZE); 594 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 595 sc->fc.sid_buf++; 596 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 597 598 fwohci_db_init(&sc->arrq); 599 fwohci_db_init(&sc->arrs); 600 601 fwohci_db_init(&sc->atrq); 602 fwohci_db_init(&sc->atrs); 603 604 reg = OREAD(sc, FWOHCIGUID_H); 605 for( i = 0 ; i < 4 ; i ++){ 606 sc->fc.eui[3 - i] = reg & 0xff; 607 reg = reg >> 8; 608 } 609 reg = OREAD(sc, FWOHCIGUID_L); 610 for( i = 0 ; i < 4 ; i ++){ 611 sc->fc.eui[7 - i] = reg & 0xff; 612 reg = reg >> 8; 613 } 614 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 615 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 616 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 617 sc->fc.ioctl = fwohci_ioctl; 618 sc->fc.cyctimer = fwohci_cyctimer; 619 sc->fc.set_bmr = fwohci_set_bus_manager; 620 sc->fc.ibr = fwohci_ibr; 621 sc->fc.irx_enable = fwohci_irx_enable; 622 sc->fc.irx_disable = fwohci_irx_disable; 623 624 sc->fc.itx_enable = fwohci_itxbuf_enable; 625 sc->fc.itx_disable = fwohci_itx_disable; 626 sc->fc.irx_post = fwohci_irx_post; 627 sc->fc.itx_post = NULL; 628 sc->fc.timeout = fwohci_timeout; 629 sc->fc.poll = fwohci_poll; 630 sc->fc.set_intr = fwohci_set_intr; 631 632 /* enable link */ 633 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 634 fw_busreset(&sc->fc); 635 fwohci_rx_enable(sc, &sc->arrq); 636 fwohci_rx_enable(sc, &sc->arrs); 637 638 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 639 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 640 db_tr->xfer = NULL; 641 } 642 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 643 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 644 db_tr->xfer = NULL; 645 } 646 sc->atrq.flags = sc->atrs.flags = 0; 647 648 OWRITE(sc, FWOHCI_RETRY, 649 (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 650 OWRITE(sc, FWOHCI_INTMASK, 651 OHCI_INT_ERR | OHCI_INT_PHY_SID 652 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 653 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 654 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 655 fwohci_set_intr(&sc->fc, 1); 656 657 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 658 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 659 660 return err; 661} 662 663void 664fwohci_timeout(void *arg) 665{ 666 struct fwohci_softc *sc; 667 668 sc = (struct fwohci_softc *)arg; 669 sc->fc.timeouthandle = timeout(fwohci_timeout, 670 (void *)sc, FW_XFERTIMEOUT * hz * 10); 671} 672 673u_int32_t 674fwohci_cyctimer(struct firewire_comm *fc) 675{ 676 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 677 return(OREAD(sc, OHCI_CYCLETIMER)); 678} 679 680#define LAST_DB(dbtr, db) do { \ 681 struct fwohcidb_tr *_dbtr = (dbtr); \ 682 int _cnt = _dbtr->dbcnt; \ 683 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 684} while (0) 685 686static void 687fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 688{ 689 int i, s; 690 int tcode, hdr_len, hdr_off, len; 691 int fsegment = -1; 692 u_int32_t off; 693 struct fw_xfer *xfer; 694 struct fw_pkt *fp; 695 volatile struct fwohci_txpkthdr *ohcifp; 696 struct fwohcidb_tr *db_tr; 697 volatile struct fwohcidb *db; 698 struct mbuf *m; 699 struct tcode_info *info; 700 701 if(&sc->atrq == dbch){ 702 off = OHCI_ATQOFF; 703 }else if(&sc->atrs == dbch){ 704 off = OHCI_ATSOFF; 705 }else{ 706 return; 707 } 708 709 if (dbch->flags & FWOHCI_DBCH_FULL) 710 return; 711 712 s = splfw(); 713 db_tr = dbch->top; 714txloop: 715 xfer = STAILQ_FIRST(&dbch->xferq.q); 716 if(xfer == NULL){ 717 goto kick; 718 } 719 if(dbch->xferq.queued == 0 ){ 720 device_printf(sc->fc.dev, "TX queue empty\n"); 721 } 722 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 723 db_tr->xfer = xfer; 724 xfer->state = FWXF_START; 725 dbch->xferq.packets++; 726 727 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 728 tcode = fp->mode.common.tcode; 729 730 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 731 info = &tinfo[tcode]; 732 hdr_len = hdr_off = info->hdr_len; 733 /* fw_asyreq must pass valid send.len */ 734 len = xfer->send.len; 735 for( i = 0 ; i < hdr_off ; i+= 4){ 736 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 737 } 738 ohcifp->mode.common.spd = xfer->spd; 739 if (tcode == FWTCODE_STREAM ){ 740 hdr_len = 8; 741 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 742 } else if (tcode == FWTCODE_PHY) { 743 hdr_len = 12; 744 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 745 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 746 ohcifp->mode.common.spd = 0; 747 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 748 } else { 749 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 750 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 751 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 752 } 753 db = &db_tr->db[0]; 754 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 755 db->db.desc.status = 0; 756/* Specify bound timer of asy. responce */ 757 if(&sc->atrs == dbch){ 758 db->db.desc.count 759 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 760 } 761 762 db_tr->dbcnt = 2; 763 db = &db_tr->db[db_tr->dbcnt]; 764 if(len > hdr_off){ 765 if (xfer->mbuf == NULL) { 766 db->db.desc.addr 767 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 768 db->db.desc.cmd 769 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 770 db->db.desc.status = 0; 771 772 db_tr->dbcnt++; 773 } else { 774 /* XXX we assume mbuf chain is shorter than ndesc */ 775 m = xfer->mbuf; 776 do { 777 db->db.desc.addr 778 = vtophys(mtod(m, caddr_t)); 779 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 780 db->db.desc.status = 0; 781 db++; 782 db_tr->dbcnt++; 783 m = m->m_next; 784 } while (m != NULL); 785 } 786 } 787 /* last db */ 788 LAST_DB(db_tr, db); 789 db->db.desc.cmd |= OHCI_OUTPUT_LAST 790 | OHCI_INTERRUPT_ALWAYS 791 | OHCI_BRANCH_ALWAYS; 792 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 793 794 if(fsegment == -1 ) 795 fsegment = db_tr->dbcnt; 796 if (dbch->pdb_tr != NULL) { 797 LAST_DB(dbch->pdb_tr, db); 798 db->db.desc.depend |= db_tr->dbcnt; 799 } 800 dbch->pdb_tr = db_tr; 801 db_tr = STAILQ_NEXT(db_tr, link); 802 if(db_tr != dbch->bottom){ 803 goto txloop; 804 } else { 805 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 806 dbch->flags |= FWOHCI_DBCH_FULL; 807 } 808kick: 809 if (firewire_debug) printf("kick\n"); 810 /* kick asy q */ 811 812 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 813 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 814 } else { 815 if (bootverbose) 816 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 817 OREAD(sc, OHCI_DMACTL(off))); 818 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 819 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 820 dbch->xferq.flag |= FWXFERQ_RUNNING; 821 } 822 823 dbch->top = db_tr; 824 splx(s); 825 return; 826} 827 828static void 829fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 830{ 831 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 832 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 833 return; 834} 835 836static void 837fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 838{ 839 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 840 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 841 return; 842} 843 844static void 845fwohci_start_atq(struct firewire_comm *fc) 846{ 847 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 848 fwohci_start( sc, &(sc->atrq)); 849 return; 850} 851 852static void 853fwohci_start_ats(struct firewire_comm *fc) 854{ 855 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 856 fwohci_start( sc, &(sc->atrs)); 857 return; 858} 859 860void 861fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 862{ 863 int s, err = 0; 864 struct fwohcidb_tr *tr; 865 volatile struct fwohcidb *db; 866 struct fw_xfer *xfer; 867 u_int32_t off; 868 u_int stat; 869 int packets; 870 struct firewire_comm *fc = (struct firewire_comm *)sc; 871 if(&sc->atrq == dbch){ 872 off = OHCI_ATQOFF; 873 }else if(&sc->atrs == dbch){ 874 off = OHCI_ATSOFF; 875 }else{ 876 return; 877 } 878 s = splfw(); 879 tr = dbch->bottom; 880 packets = 0; 881 while(dbch->xferq.queued > 0){ 882 LAST_DB(tr, db); 883 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 884 if (fc->status != FWBUSRESET) 885 /* maybe out of order?? */ 886 goto out; 887 } 888 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 889#ifdef OHCI_DEBUG 890 dump_dma(sc, ch); 891 dump_db(sc, ch); 892#endif 893/* Stop DMA */ 894 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 895 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 896 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 897 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 898 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 899 } 900 stat = db->db.desc.status & FWOHCIEV_MASK; 901 switch(stat){ 902 case FWOHCIEV_ACKCOMPL: 903 case FWOHCIEV_ACKPEND: 904 err = 0; 905 break; 906 case FWOHCIEV_ACKBSA: 907 case FWOHCIEV_ACKBSB: 908 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 909 case FWOHCIEV_ACKBSX: 910 err = EBUSY; 911 break; 912 case FWOHCIEV_FLUSHED: 913 case FWOHCIEV_ACKTARD: 914 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 915 err = EAGAIN; 916 break; 917 case FWOHCIEV_MISSACK: 918 case FWOHCIEV_UNDRRUN: 919 case FWOHCIEV_OVRRUN: 920 case FWOHCIEV_DESCERR: 921 case FWOHCIEV_DTRDERR: 922 case FWOHCIEV_TIMEOUT: 923 case FWOHCIEV_TCODERR: 924 case FWOHCIEV_UNKNOWN: 925 case FWOHCIEV_ACKDERR: 926 case FWOHCIEV_ACKTERR: 927 default: 928 device_printf(sc->fc.dev, "txd err=%2x %s\n", 929 stat, fwohcicode[stat]); 930 err = EINVAL; 931 break; 932 } 933 if(tr->xfer != NULL){ 934 xfer = tr->xfer; 935 xfer->state = FWXF_SENT; 936 if(err == EBUSY && fc->status != FWBUSRESET){ 937 xfer->state = FWXF_BUSY; 938 switch(xfer->act_type){ 939 case FWACT_XFER: 940 xfer->resp = err; 941 if(xfer->retry_req != NULL){ 942 xfer->retry_req(xfer); 943 } 944 break; 945 default: 946 break; 947 } 948 } else if( stat != FWOHCIEV_ACKPEND){ 949 if (stat != FWOHCIEV_ACKCOMPL) 950 xfer->state = FWXF_SENTERR; 951 xfer->resp = err; 952 switch(xfer->act_type){ 953 case FWACT_XFER: 954 fw_xfer_done(xfer); 955 break; 956 default: 957 break; 958 } 959 } 960 dbch->xferq.queued --; 961 } 962 tr->xfer = NULL; 963 964 packets ++; 965 tr = STAILQ_NEXT(tr, link); 966 dbch->bottom = tr; 967 } 968out: 969 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 970 printf("make free slot\n"); 971 dbch->flags &= ~FWOHCI_DBCH_FULL; 972 fwohci_start(sc, dbch); 973 } 974 splx(s); 975} 976 977static void 978fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 979{ 980 int i, s; 981 struct fwohcidb_tr *tr; 982 983 if(xfer->state != FWXF_START) return; 984 985 s = splfw(); 986 tr = dbch->bottom; 987 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 988 if(tr->xfer == xfer){ 989 s = splfw(); 990 tr->xfer = NULL; 991 dbch->xferq.queued --; 992#if 1 993 /* XXX */ 994 if (tr == dbch->bottom) 995 dbch->bottom = STAILQ_NEXT(tr, link); 996#endif 997 if (dbch->flags & FWOHCI_DBCH_FULL) { 998 printf("fwohci_drain: make slot\n"); 999 dbch->flags &= ~FWOHCI_DBCH_FULL; 1000 fwohci_start((struct fwohci_softc *)fc, dbch); 1001 } 1002 1003 splx(s); 1004 break; 1005 } 1006 tr = STAILQ_NEXT(tr, link); 1007 } 1008 splx(s); 1009 return; 1010} 1011 1012static void 1013fwohci_db_free(struct fwohci_dbch *dbch) 1014{ 1015 struct fwohcidb_tr *db_tr; 1016 int idb; 1017 1018 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1019 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1020 idb < dbch->ndb; 1021 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1022 free(db_tr->buf, M_DEVBUF); 1023 db_tr->buf = NULL; 1024 } 1025 } 1026 dbch->ndb = 0; 1027 db_tr = STAILQ_FIRST(&dbch->db_trq); 1028 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1029 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1030 /* Attach DB to DMA ch. */ 1031 free(db_tr, M_DEVBUF); 1032 STAILQ_INIT(&dbch->db_trq); 1033} 1034 1035static void 1036fwohci_db_init(struct fwohci_dbch *dbch) 1037{ 1038 int idb; 1039 struct fwohcidb *db; 1040 struct fwohcidb_tr *db_tr; 1041 /* allocate DB entries and attach one to each DMA channels */ 1042 /* DB entry must start at 16 bytes bounary. */ 1043 dbch->frag.buf = NULL; 1044 dbch->frag.len = 0; 1045 dbch->frag.plen = 0; 1046 dbch->xferq.queued = 0; 1047 dbch->pdb_tr = NULL; 1048 1049 STAILQ_INIT(&dbch->db_trq); 1050 db_tr = (struct fwohcidb_tr *) 1051 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1052 M_DEVBUF, M_DONTWAIT); 1053 if(db_tr == NULL){ 1054 return; 1055 } 1056 db = (struct fwohcidb *) 1057 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1058 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1059 if(db == NULL){ 1060 printf("fwochi_db_init: contigmalloc failed\n"); 1061 return; 1062 } 1063 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1064 /* Attach DB to DMA ch. */ 1065 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1066 db_tr->dbcnt = 0; 1067 db_tr->db = &db[idb * dbch->ndesc]; 1068 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1069 if(!(dbch->xferq.flag & FWXFERQ_PACKET) && 1070 (idb % dbch->xferq.bnpacket == 0)){ 1071 dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].start 1072 = (caddr_t)db_tr; 1073 } 1074 if((!(dbch->xferq.flag & FWXFERQ_PACKET)) && 1075 ((idb + 1)% dbch->xferq.bnpacket == 0)){ 1076 dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].end 1077 = (caddr_t)db_tr; 1078 } 1079 db_tr++; 1080 } 1081 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1082 = STAILQ_FIRST(&dbch->db_trq); 1083 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1084 dbch->bottom = dbch->top; 1085} 1086 1087static int 1088fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1089{ 1090 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1091 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1092 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1093 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1094 fwohci_db_free(&sc->it[dmach]); 1095 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1096 return 0; 1097} 1098 1099static int 1100fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1101{ 1102 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1103 1104 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1105 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1106 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1107 if(sc->ir[dmach].dummy != NULL){ 1108 free(sc->ir[dmach].dummy, M_DEVBUF); 1109 } 1110 sc->ir[dmach].dummy = NULL; 1111 fwohci_db_free(&sc->ir[dmach]); 1112 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1113 return 0; 1114} 1115 1116static void 1117fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1118{ 1119 qld[0] = ntohl(qld[0]); 1120 return; 1121} 1122 1123static int 1124fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1125{ 1126 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1127 int err = 0; 1128 unsigned short tag, ich; 1129 1130 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1131 ich = sc->ir[dmach].xferq.flag & 0x3f; 1132 1133#if 0 1134 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1135 wakeup(fc->ir[dmach]); 1136 return err; 1137 } 1138#endif 1139 1140 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1141 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1142 sc->ir[dmach].xferq.queued = 0; 1143 sc->ir[dmach].ndb = NDB; 1144 sc->ir[dmach].xferq.psize = FWPMAX_S400; 1145 sc->ir[dmach].ndesc = 1; 1146 fwohci_db_init(&sc->ir[dmach]); 1147 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1148 } 1149 if(err){ 1150 device_printf(sc->fc.dev, "err in IRX setting\n"); 1151 return err; 1152 } 1153 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1154 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1155 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1156 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1157 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1158 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1159 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1160 OWRITE(sc, OHCI_IRCMD(dmach), 1161 vtophys(sc->ir[dmach].top->db) | 1); 1162 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1163 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1164 } 1165 return err; 1166} 1167 1168static int 1169fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1170{ 1171 int err = 0; 1172 int idb, z, i, dmach = 0; 1173 u_int32_t off = NULL; 1174 struct fwohcidb_tr *db_tr; 1175 1176 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1177 err = EINVAL; 1178 return err; 1179 } 1180 z = dbch->ndesc; 1181 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1182 if( &sc->it[dmach] == dbch){ 1183 off = OHCI_ITOFF(dmach); 1184 break; 1185 } 1186 } 1187 if(off == NULL){ 1188 err = EINVAL; 1189 return err; 1190 } 1191 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1192 return err; 1193 dbch->xferq.flag |= FWXFERQ_RUNNING; 1194 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1195 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1196 } 1197 db_tr = dbch->top; 1198 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1199 fwohci_add_tx_buf(db_tr, 1200 dbch->xferq.psize, dbch->xferq.flag, 1201 dbch->xferq.buf + dbch->xferq.psize * idb); 1202 if(STAILQ_NEXT(db_tr, link) == NULL){ 1203 break; 1204 } 1205 db_tr->db[0].db.desc.depend 1206 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1207 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1208 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1209 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1210 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1211 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1212 |= OHCI_INTERRUPT_ALWAYS; 1213 db_tr->db[0].db.desc.depend &= ~0xf; 1214 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1215 ~0xf; 1216 } 1217 } 1218 db_tr = STAILQ_NEXT(db_tr, link); 1219 } 1220 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1221 return err; 1222} 1223 1224static int 1225fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1226{ 1227 int err = 0; 1228 int idb, z, i, dmach = 0; 1229 u_int32_t off = NULL; 1230 struct fwohcidb_tr *db_tr; 1231 1232 z = dbch->ndesc; 1233 if(&sc->arrq == dbch){ 1234 off = OHCI_ARQOFF; 1235 }else if(&sc->arrs == dbch){ 1236 off = OHCI_ARSOFF; 1237 }else{ 1238 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1239 if( &sc->ir[dmach] == dbch){ 1240 off = OHCI_IROFF(dmach); 1241 break; 1242 } 1243 } 1244 } 1245 if(off == NULL){ 1246 err = EINVAL; 1247 return err; 1248 } 1249 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1250 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1251 return err; 1252 }else{ 1253 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1254 err = EBUSY; 1255 return err; 1256 } 1257 } 1258 dbch->xferq.flag |= FWXFERQ_RUNNING; 1259 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1260 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1261 } 1262 db_tr = dbch->top; 1263 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1264 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1265 fwohci_add_rx_buf(db_tr, 1266 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1267 }else{ 1268 fwohci_add_rx_buf(db_tr, 1269 dbch->xferq.psize, dbch->xferq.flag, 1270 dbch->xferq.buf + dbch->xferq.psize * idb, 1271 dbch->dummy + sizeof(u_int32_t) * idb); 1272 } 1273 if(STAILQ_NEXT(db_tr, link) == NULL){ 1274 break; 1275 } 1276 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1277 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1278 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1279 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1280 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1281 |= OHCI_INTERRUPT_ALWAYS; 1282 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1283 ~0xf; 1284 } 1285 } 1286 db_tr = STAILQ_NEXT(db_tr, link); 1287 } 1288 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1289 dbch->buf_offset = 0; 1290 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1291 return err; 1292 }else{ 1293 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1294 } 1295 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1296 return err; 1297} 1298 1299static int 1300fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1301{ 1302 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1303 int err = 0; 1304 unsigned short tag, ich; 1305 struct fwohci_dbch *dbch; 1306 struct fw_pkt *fp; 1307 struct fwohcidb_tr *db_tr; 1308 1309 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1310 ich = sc->it[dmach].xferq.flag & 0x3f; 1311 dbch = &sc->it[dmach]; 1312 if(dbch->ndb == 0){ 1313 dbch->xferq.queued = 0; 1314 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1315 dbch->ndesc = 3; 1316 fwohci_db_init(dbch); 1317 err = fwohci_tx_enable(sc, dbch); 1318 } 1319 if(err) 1320 return err; 1321 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1322 if(dbch->xferq.stdma2 != NULL){ 1323 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1324 ((struct fwohcidb_tr *) 1325 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1326 |= OHCI_BRANCH_ALWAYS; 1327 ((struct fwohcidb_tr *) 1328 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1329 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1330 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1331 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1332 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1333 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1334 } 1335 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1336 fw_tbuf_update(&sc->fc, dmach, 0); 1337 if(dbch->xferq.stdma == NULL){ 1338 return err; 1339 } 1340 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1341 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1342 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1343 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1344 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1345 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1346 if(dbch->xferq.stdma2 != NULL){ 1347 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1348 ((struct fwohcidb_tr *) 1349 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1350 |= OHCI_BRANCH_ALWAYS; 1351 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1352 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1353 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1354 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1355 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1356 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1357 }else{ 1358 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1359 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1360 } 1361 OWRITE(sc, OHCI_ITCMD(dmach), 1362 vtophys(((struct fwohcidb_tr *) 1363 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1364 if(dbch->xferq.flag & FWXFERQ_DV){ 1365 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1366 fp = (struct fw_pkt *)db_tr->buf; 1367 fp->mode.ld[2] = htonl(0x80000000 + 1368 ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1369 } 1370 1371 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1372 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1373 } 1374 return err; 1375} 1376 1377static int 1378fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1379{ 1380 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1381 int err = 0; 1382 unsigned short tag, ich; 1383 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1384 ich = sc->ir[dmach].xferq.flag & 0x3f; 1385 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1386 1387 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1388 sc->ir[dmach].xferq.queued = 0; 1389 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1390 sc->ir[dmach].xferq.bnchunk; 1391 sc->ir[dmach].dummy = 1392 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1393 M_DEVBUF, M_DONTWAIT); 1394 if(sc->ir[dmach].dummy == NULL){ 1395 err = ENOMEM; 1396 return err; 1397 } 1398 sc->ir[dmach].ndesc = 2; 1399 fwohci_db_init(&sc->ir[dmach]); 1400 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1401 } 1402 if(err) 1403 return err; 1404 1405 if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1406 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1407 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1408 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1409 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1410 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1411 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1412 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1413 } 1414 }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1415 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1416 fw_rbuf_update(&sc->fc, dmach, 0); 1417 1418 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1419 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1420 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1421 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1422 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1423 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1424 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1425 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1426 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1427 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1428 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1429 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1430 }else{ 1431 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1432 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1433 } 1434 OWRITE(sc, OHCI_IRCMD(dmach), 1435 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1436 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1437 } 1438 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1439 return err; 1440} 1441 1442static int 1443fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1444{ 1445 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1446 int err = 0; 1447 1448 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1449 err = fwohci_irxpp_enable(fc, dmach); 1450 return err; 1451 }else{ 1452 err = fwohci_irxbuf_enable(fc, dmach); 1453 return err; 1454 } 1455} 1456 1457int 1458fwohci_shutdown(device_t dev) 1459{ 1460 u_int i; 1461 struct fwohci_softc *sc = device_get_softc(dev); 1462 1463/* Now stopping all DMA channel */ 1464 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1465 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1466 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1467 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1468 1469 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1470 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1471 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1472 } 1473 1474/* FLUSH FIFO and reset Transmitter/Reciever */ 1475 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1476 1477/* Stop interrupt */ 1478 OWRITE(sc, FWOHCI_INTMASKCLR, 1479 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1480 | OHCI_INT_PHY_INT 1481 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1482 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1483 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1484 | OHCI_INT_PHY_BUS_R); 1485 return 0; 1486} 1487 1488#define ACK_ALL 1489static void 1490fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1491{ 1492 u_int32_t irstat, itstat; 1493 u_int i; 1494 struct firewire_comm *fc = (struct firewire_comm *)sc; 1495 1496#ifdef OHCI_DEBUG 1497 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1498 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1499 stat & OHCI_INT_EN ? "DMA_EN ":"", 1500 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1501 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1502 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1503 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1504 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1505 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1506 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1507 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1508 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1509 stat & OHCI_INT_PHY_SID ? "SID ":"", 1510 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1511 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1512 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1513 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1514 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1515 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1516 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1517 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1518 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1519 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1520 stat, OREAD(sc, FWOHCI_INTMASK) 1521 ); 1522#endif 1523/* Bus reset */ 1524 if(stat & OHCI_INT_PHY_BUS_R ){ 1525 device_printf(fc->dev, "BUS reset\n"); 1526 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1527 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1528 1529 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1530 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1531 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1532 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1533 1534#if 0 1535 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1536 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1537 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1538 } 1539 1540#endif 1541 fw_busreset(fc); 1542 1543 /* XXX need to wait DMA to stop */ 1544#ifndef ACK_ALL 1545 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1546#endif 1547#if 1 1548 /* pending all pre-bus_reset packets */ 1549 fwohci_txd(sc, &sc->atrq); 1550 fwohci_txd(sc, &sc->atrs); 1551 fwohci_arcv(sc, &sc->arrs, -1); 1552 fwohci_arcv(sc, &sc->arrq, -1); 1553#endif 1554 1555 1556 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1557 /* XXX insecure ?? */ 1558 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1559 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1560 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1561 1562 } 1563 if((stat & OHCI_INT_DMA_IR )){ 1564#ifndef ACK_ALL 1565 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1566#endif 1567 irstat = OREAD(sc, OHCI_IR_STAT); 1568 OWRITE(sc, OHCI_IR_STATCLR, ~0); 1569 for(i = 0; i < fc->nisodma ; i++){ 1570 if((irstat & (1 << i)) != 0){ 1571 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1572 fwohci_ircv(sc, &sc->ir[i], count); 1573 }else{ 1574 fwohci_rbuf_update(sc, i); 1575 } 1576 } 1577 } 1578 } 1579 if((stat & OHCI_INT_DMA_IT )){ 1580#ifndef ACK_ALL 1581 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1582#endif 1583 itstat = OREAD(sc, OHCI_IT_STAT); 1584 OWRITE(sc, OHCI_IT_STATCLR, ~0); 1585 for(i = 0; i < fc->nisodma ; i++){ 1586 if((itstat & (1 << i)) != 0){ 1587 fwohci_tbuf_update(sc, i); 1588 } 1589 } 1590 } 1591 if((stat & OHCI_INT_DMA_PRRS )){ 1592#ifndef ACK_ALL 1593 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1594#endif 1595#if 0 1596 dump_dma(sc, ARRS_CH); 1597 dump_db(sc, ARRS_CH); 1598#endif 1599 fwohci_arcv(sc, &sc->arrs, count); 1600 } 1601 if((stat & OHCI_INT_DMA_PRRQ )){ 1602#ifndef ACK_ALL 1603 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1604#endif 1605#if 0 1606 dump_dma(sc, ARRQ_CH); 1607 dump_db(sc, ARRQ_CH); 1608#endif 1609 fwohci_arcv(sc, &sc->arrq, count); 1610 } 1611 if(stat & OHCI_INT_PHY_SID){ 1612 caddr_t buf; 1613 int plen; 1614 1615#ifndef ACK_ALL 1616 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1617#endif 1618/* 1619** Checking whether the node is root or not. If root, turn on 1620** cycle master. 1621*/ 1622 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1623 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1624 printf("Bus reset failure\n"); 1625 goto sidout; 1626 } 1627 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1628 printf("CYCLEMASTER mode\n"); 1629 OWRITE(sc, OHCI_LNKCTL, 1630 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1631 }else{ 1632 printf("non CYCLEMASTER mode\n"); 1633 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1634 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1635 } 1636 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1637 1638 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1639 plen -= 4; /* chop control info */ 1640 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1641 if(buf == NULL) goto sidout; 1642 bcopy((void *)(uintptr_t)(volatile void *)fc->sid_buf, 1643 buf, plen); 1644 fw_sidrcv(fc, buf, plen, 0); 1645 } 1646sidout: 1647 if((stat & OHCI_INT_DMA_ATRQ )){ 1648#ifndef ACK_ALL 1649 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1650#endif 1651 fwohci_txd(sc, &(sc->atrq)); 1652 } 1653 if((stat & OHCI_INT_DMA_ATRS )){ 1654#ifndef ACK_ALL 1655 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1656#endif 1657 fwohci_txd(sc, &(sc->atrs)); 1658 } 1659 if((stat & OHCI_INT_PW_ERR )){ 1660#ifndef ACK_ALL 1661 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1662#endif 1663 device_printf(fc->dev, "posted write error\n"); 1664 } 1665 if((stat & OHCI_INT_ERR )){ 1666#ifndef ACK_ALL 1667 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1668#endif 1669 device_printf(fc->dev, "unrecoverable error\n"); 1670 } 1671 if((stat & OHCI_INT_PHY_INT)) { 1672#ifndef ACK_ALL 1673 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1674#endif 1675 device_printf(fc->dev, "phy int\n"); 1676 } 1677 1678 return; 1679} 1680 1681void 1682fwohci_intr(void *arg) 1683{ 1684 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1685 u_int32_t stat; 1686 1687 if (!(sc->intmask & OHCI_INT_EN)) { 1688 /* polling mode */ 1689 return; 1690 } 1691 1692 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1693 if (stat == 0xffffffff) { 1694 device_printf(sc->fc.dev, 1695 "device physically ejected?\n"); 1696 return; 1697 } 1698#ifdef ACK_ALL 1699 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1700#endif 1701 fwohci_intr_body(sc, stat, -1); 1702 } 1703} 1704 1705static void 1706fwohci_poll(struct firewire_comm *fc, int quick, int count) 1707{ 1708 int s; 1709 u_int32_t stat; 1710 struct fwohci_softc *sc; 1711 1712 1713 sc = (struct fwohci_softc *)fc; 1714 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1715 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1716 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1717#if 0 1718 if (!quick) { 1719#else 1720 if (1) { 1721#endif 1722 stat = OREAD(sc, FWOHCI_INTSTAT); 1723 if (stat == 0) 1724 return; 1725 if (stat == 0xffffffff) { 1726 device_printf(sc->fc.dev, 1727 "device physically ejected?\n"); 1728 return; 1729 } 1730#ifdef ACK_ALL 1731 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1732#endif 1733 } 1734 s = splfw(); 1735 fwohci_intr_body(sc, stat, count); 1736 splx(s); 1737} 1738 1739static void 1740fwohci_set_intr(struct firewire_comm *fc, int enable) 1741{ 1742 struct fwohci_softc *sc; 1743 1744 sc = (struct fwohci_softc *)fc; 1745 if (bootverbose) 1746 device_printf(sc->fc.dev, "fwochi_set_intr: %d\n", enable); 1747 if (enable) { 1748 sc->intmask |= OHCI_INT_EN; 1749 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1750 } else { 1751 sc->intmask &= ~OHCI_INT_EN; 1752 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1753 } 1754} 1755 1756static void 1757fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1758{ 1759 int stat; 1760 struct firewire_comm *fc = &sc->fc; 1761 struct fw_pkt *fp; 1762 struct fwohci_dbch *dbch; 1763 struct fwohcidb_tr *db_tr; 1764 1765 dbch = &sc->it[dmach]; 1766 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1767 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1768/* 1769 * Overwrite highest significant 4 bits timestamp information 1770 */ 1771 fp = (struct fw_pkt *)db_tr->buf; 1772 fp->mode.ld[2] |= htonl(0x80000000 | 1773 ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1774 } 1775 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1776 switch(stat){ 1777 case FWOHCIEV_ACKCOMPL: 1778 fw_tbuf_update(fc, dmach, 1); 1779 break; 1780 default: 1781 fw_tbuf_update(fc, dmach, 0); 1782 break; 1783 } 1784 fwohci_itxbuf_enable(&sc->fc, dmach); 1785} 1786 1787static void 1788fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1789{ 1790 int stat; 1791 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1792 switch(stat){ 1793 case FWOHCIEV_ACKCOMPL: 1794 fw_rbuf_update(&sc->fc, dmach, 1); 1795 wakeup(sc->fc.ir[dmach]); 1796 fwohci_irx_enable(&sc->fc, dmach); 1797 break; 1798 default: 1799 break; 1800 } 1801} 1802 1803void 1804dump_dma(struct fwohci_softc *sc, u_int32_t ch) 1805{ 1806 u_int32_t off, cntl, stat, cmd, match; 1807 1808 if(ch == 0){ 1809 off = OHCI_ATQOFF; 1810 }else if(ch == 1){ 1811 off = OHCI_ATSOFF; 1812 }else if(ch == 2){ 1813 off = OHCI_ARQOFF; 1814 }else if(ch == 3){ 1815 off = OHCI_ARSOFF; 1816 }else if(ch < IRX_CH){ 1817 off = OHCI_ITCTL(ch - ITX_CH); 1818 }else{ 1819 off = OHCI_IRCTL(ch - IRX_CH); 1820 } 1821 cntl = stat = OREAD(sc, off); 1822 cmd = OREAD(sc, off + 0xc); 1823 match = OREAD(sc, off + 0x10); 1824 1825 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1826 ch, 1827 cntl, 1828 stat, 1829 cmd, 1830 match); 1831 stat &= 0xffff ; 1832 if(stat & 0xff00){ 1833 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1834 ch, 1835 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1836 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1837 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1838 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1839 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1840 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1841 fwohcicode[stat & 0x1f], 1842 stat & 0x1f 1843 ); 1844 }else{ 1845 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1846 } 1847} 1848 1849void 1850dump_db(struct fwohci_softc *sc, u_int32_t ch) 1851{ 1852 struct fwohci_dbch *dbch; 1853 struct fwohcidb_tr *cp = NULL, *pp, *np; 1854 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1855 int idb, jdb; 1856 u_int32_t cmd, off; 1857 if(ch == 0){ 1858 off = OHCI_ATQOFF; 1859 dbch = &sc->atrq; 1860 }else if(ch == 1){ 1861 off = OHCI_ATSOFF; 1862 dbch = &sc->atrs; 1863 }else if(ch == 2){ 1864 off = OHCI_ARQOFF; 1865 dbch = &sc->arrq; 1866 }else if(ch == 3){ 1867 off = OHCI_ARSOFF; 1868 dbch = &sc->arrs; 1869 }else if(ch < IRX_CH){ 1870 off = OHCI_ITCTL(ch - ITX_CH); 1871 dbch = &sc->it[ch - ITX_CH]; 1872 }else { 1873 off = OHCI_IRCTL(ch - IRX_CH); 1874 dbch = &sc->ir[ch - IRX_CH]; 1875 } 1876 cmd = OREAD(sc, off + 0xc); 1877 1878 if( dbch->ndb == 0 ){ 1879 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1880 return; 1881 } 1882 pp = dbch->top; 1883 prev = pp->db; 1884 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1885 if(pp == NULL){ 1886 curr = NULL; 1887 goto outdb; 1888 } 1889 cp = STAILQ_NEXT(pp, link); 1890 if(cp == NULL){ 1891 curr = NULL; 1892 goto outdb; 1893 } 1894 np = STAILQ_NEXT(cp, link); 1895 if(cp == NULL) break; 1896 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 1897 if((cmd & 0xfffffff0) 1898 == vtophys(&(cp->db[jdb]))){ 1899 curr = cp->db; 1900 if(np != NULL){ 1901 next = np->db; 1902 }else{ 1903 next = NULL; 1904 } 1905 goto outdb; 1906 } 1907 } 1908 pp = STAILQ_NEXT(pp, link); 1909 prev = pp->db; 1910 } 1911outdb: 1912 if( curr != NULL){ 1913 printf("Prev DB %d\n", ch); 1914 print_db(prev, ch, dbch->ndesc); 1915 printf("Current DB %d\n", ch); 1916 print_db(curr, ch, dbch->ndesc); 1917 printf("Next DB %d\n", ch); 1918 print_db(next, ch, dbch->ndesc); 1919 }else{ 1920 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 1921 } 1922 return; 1923} 1924 1925void 1926print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 1927{ 1928 fwohcireg_t stat; 1929 int i, key; 1930 1931 if(db == NULL){ 1932 printf("No Descriptor is found\n"); 1933 return; 1934 } 1935 1936 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 1937 ch, 1938 "Current", 1939 "OP ", 1940 "KEY", 1941 "INT", 1942 "BR ", 1943 "len", 1944 "Addr", 1945 "Depend", 1946 "Stat", 1947 "Cnt"); 1948 for( i = 0 ; i <= max ; i ++){ 1949 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 1950 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 1951 vtophys(&db[i]), 1952 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 1953 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 1954 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 1955 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 1956 db[i].db.desc.cmd & 0xffff, 1957 db[i].db.desc.addr, 1958 db[i].db.desc.depend, 1959 db[i].db.desc.status, 1960 db[i].db.desc.count); 1961 stat = db[i].db.desc.status; 1962 if(stat & 0xff00){ 1963 printf(" %s%s%s%s%s%s %s(%x)\n", 1964 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1965 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1966 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1967 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1968 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1969 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1970 fwohcicode[stat & 0x1f], 1971 stat & 0x1f 1972 ); 1973 }else{ 1974 printf(" Nostat\n"); 1975 } 1976 if(key == OHCI_KEY_ST2 ){ 1977 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 1978 db[i+1].db.immed[0], 1979 db[i+1].db.immed[1], 1980 db[i+1].db.immed[2], 1981 db[i+1].db.immed[3]); 1982 } 1983 if(key == OHCI_KEY_DEVICE){ 1984 return; 1985 } 1986 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 1987 == OHCI_BRANCH_ALWAYS){ 1988 return; 1989 } 1990 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 1991 == OHCI_OUTPUT_LAST){ 1992 return; 1993 } 1994 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 1995 == OHCI_INPUT_LAST){ 1996 return; 1997 } 1998 if(key == OHCI_KEY_ST2 ){ 1999 i++; 2000 } 2001 } 2002 return; 2003} 2004 2005void 2006fwohci_ibr(struct firewire_comm *fc) 2007{ 2008 struct fwohci_softc *sc; 2009 u_int32_t fun; 2010 2011 sc = (struct fwohci_softc *)fc; 2012 2013 /* 2014 * Set root hold-off bit so that non cyclemaster capable node 2015 * shouldn't became the root node. 2016 */ 2017 fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2018 fun |= FW_PHY_RHB; 2019 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2020#if 1 2021 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2022 fun |= FW_PHY_IBR; 2023 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2024#else 2025 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2026 fun |= FW_PHY_ISBR; 2027 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2028#endif 2029} 2030 2031void 2032fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2033{ 2034 struct fwohcidb_tr *db_tr, *fdb_tr; 2035 struct fwohci_dbch *dbch; 2036 struct fw_pkt *fp; 2037 volatile struct fwohci_txpkthdr *ohcifp; 2038 unsigned short chtag; 2039 int idb; 2040 2041 dbch = &sc->it[dmach]; 2042 chtag = sc->it[dmach].xferq.flag & 0xff; 2043 2044 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2045 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2046/* 2047device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2048*/ 2049 if(bulkxfer->flag != 0){ 2050 return; 2051 } 2052 bulkxfer->flag = 1; 2053 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2054 db_tr->db[0].db.desc.cmd 2055 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2056 fp = (struct fw_pkt *)db_tr->buf; 2057 ohcifp = (volatile struct fwohci_txpkthdr *) 2058 db_tr->db[1].db.immed; 2059 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2060 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2061 ohcifp->mode.stream.chtag = chtag; 2062 ohcifp->mode.stream.tcode = 0xa; 2063 ohcifp->mode.stream.spd = 4; 2064 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2065 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2066 2067 db_tr->db[2].db.desc.cmd 2068 = OHCI_OUTPUT_LAST 2069 | OHCI_UPDATE 2070 | OHCI_BRANCH_ALWAYS 2071 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2072 db_tr->db[2].db.desc.status = 0; 2073 db_tr->db[2].db.desc.count = 0; 2074 if(dbch->xferq.flag & FWXFERQ_DV){ 2075 db_tr->db[0].db.desc.depend 2076 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2077 db_tr->db[dbch->ndesc - 1].db.desc.depend 2078 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2079 }else{ 2080 db_tr->db[0].db.desc.depend 2081 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2082 db_tr->db[dbch->ndesc - 1].db.desc.depend 2083 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2084 } 2085 bulkxfer->end = (caddr_t)db_tr; 2086 db_tr = STAILQ_NEXT(db_tr, link); 2087 } 2088 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2089 db_tr->db[0].db.desc.depend &= ~0xf; 2090 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2091/**/ 2092 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2093 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2094/**/ 2095 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2096 2097 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2098 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2099/* 2100device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2101*/ 2102 return; 2103} 2104 2105static int 2106fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2107 int mode, void *buf) 2108{ 2109 volatile struct fwohcidb *db = db_tr->db; 2110 int err = 0; 2111 if(buf == 0){ 2112 err = EINVAL; 2113 return err; 2114 } 2115 db_tr->buf = buf; 2116 db_tr->dbcnt = 3; 2117 db_tr->dummy = NULL; 2118 2119 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2120 2121 db[2].db.desc.depend = 0; 2122 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2123 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2124 2125 db[0].db.desc.status = 0; 2126 db[0].db.desc.count = 0; 2127 2128 db[2].db.desc.status = 0; 2129 db[2].db.desc.count = 0; 2130 if( mode & FWXFERQ_STREAM ){ 2131 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2132 if(mode & FWXFERQ_PACKET ){ 2133 db[2].db.desc.cmd 2134 |= OHCI_INTERRUPT_ALWAYS; 2135 } 2136 } 2137 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2138 return 1; 2139} 2140 2141int 2142fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2143 void *buf, void *dummy) 2144{ 2145 volatile struct fwohcidb *db = db_tr->db; 2146 int i; 2147 void *dbuf[2]; 2148 int dsiz[2]; 2149 2150 if(buf == 0){ 2151 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2152 if(buf == NULL) return 0; 2153 db_tr->buf = buf; 2154 db_tr->dbcnt = 1; 2155 db_tr->dummy = NULL; 2156 dsiz[0] = size; 2157 dbuf[0] = buf; 2158 }else if(dummy == NULL){ 2159 db_tr->buf = buf; 2160 db_tr->dbcnt = 1; 2161 db_tr->dummy = NULL; 2162 dsiz[0] = size; 2163 dbuf[0] = buf; 2164 }else{ 2165 db_tr->buf = buf; 2166 db_tr->dbcnt = 2; 2167 db_tr->dummy = dummy; 2168 dsiz[0] = sizeof(u_int32_t); 2169 dsiz[1] = size; 2170 dbuf[0] = dummy; 2171 dbuf[1] = buf; 2172 } 2173 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2174 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2175 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2176 if( mode & FWXFERQ_STREAM ){ 2177 db[i].db.desc.cmd |= OHCI_UPDATE; 2178 } 2179 db[i].db.desc.status = 0; 2180 db[i].db.desc.count = dsiz[i]; 2181 } 2182 if( mode & FWXFERQ_STREAM ){ 2183 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2184 if(mode & FWXFERQ_PACKET ){ 2185 db[db_tr->dbcnt - 1].db.desc.cmd 2186 |= OHCI_INTERRUPT_ALWAYS; 2187 } 2188 } 2189 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2190 return 1; 2191} 2192 2193static void 2194fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2195{ 2196 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2197 struct firewire_comm *fc = (struct firewire_comm *)sc; 2198 int z = 1; 2199 struct fw_pkt *fp; 2200 u_int8_t *ld; 2201 u_int32_t off = NULL; 2202 u_int32_t stat; 2203 u_int32_t *qld; 2204 u_int32_t reg; 2205 u_int spd; 2206 u_int dmach; 2207 int len, i, plen; 2208 caddr_t buf; 2209 2210 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2211 if( &sc->ir[dmach] == dbch){ 2212 off = OHCI_IROFF(dmach); 2213 break; 2214 } 2215 } 2216 if(off == NULL){ 2217 return; 2218 } 2219 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2220 fwohci_irx_disable(&sc->fc, dmach); 2221 return; 2222 } 2223 2224 odb_tr = NULL; 2225 db_tr = dbch->top; 2226 i = 0; 2227 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2228 if (count >= 0 && count-- == 0) 2229 break; 2230 ld = (u_int8_t *)db_tr->buf; 2231 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2232 /* skip timeStamp */ 2233 ld += sizeof(struct fwohci_trailer); 2234 } 2235 qld = (u_int32_t *)ld; 2236 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2237/* 2238{ 2239device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2240 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2241} 2242*/ 2243 fp=(struct fw_pkt *)ld; 2244 qld[0] = htonl(qld[0]); 2245 plen = sizeof(struct fw_isohdr) 2246 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2247 ld += plen; 2248 len -= plen; 2249 buf = db_tr->buf; 2250 db_tr->buf = NULL; 2251 stat = reg & 0x1f; 2252 spd = reg & 0x3; 2253 switch(stat){ 2254 case FWOHCIEV_ACKCOMPL: 2255 case FWOHCIEV_ACKPEND: 2256 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2257 break; 2258 default: 2259 free(buf, M_DEVBUF); 2260 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2261 break; 2262 } 2263 i++; 2264 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2265 dbch->xferq.flag, 0, NULL); 2266 db_tr->db[0].db.desc.depend &= ~0xf; 2267 if(dbch->pdb_tr != NULL){ 2268 dbch->pdb_tr->db[0].db.desc.depend |= z; 2269 } else { 2270 /* XXX should be rewritten in better way */ 2271 dbch->bottom->db[0].db.desc.depend |= z; 2272 } 2273 dbch->pdb_tr = db_tr; 2274 db_tr = STAILQ_NEXT(db_tr, link); 2275 } 2276 dbch->top = db_tr; 2277 reg = OREAD(sc, OHCI_DMACTL(off)); 2278 if (reg & OHCI_CNTL_DMA_ACTIVE) 2279 return; 2280 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2281 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2282 dbch->top = db_tr; 2283 fwohci_irx_enable(fc, dmach); 2284} 2285 2286#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2287static int 2288fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2289{ 2290 int i; 2291 2292 for( i = 4; i < hlen ; i+=4){ 2293 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2294 } 2295 2296 switch(fp->mode.common.tcode){ 2297 case FWTCODE_RREQQ: 2298 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2299 case FWTCODE_WRES: 2300 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2301 case FWTCODE_WREQQ: 2302 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2303 case FWTCODE_RREQB: 2304 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2305 case FWTCODE_RRESQ: 2306 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2307 case FWTCODE_WREQB: 2308 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2309 + sizeof(u_int32_t); 2310 case FWTCODE_LREQ: 2311 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2312 + sizeof(u_int32_t); 2313 case FWTCODE_RRESB: 2314 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2315 + sizeof(u_int32_t); 2316 case FWTCODE_LRES: 2317 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2318 + sizeof(u_int32_t); 2319 case FWOHCITCODE_PHY: 2320 return 16; 2321 } 2322 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2323 return 0; 2324} 2325 2326static void 2327fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2328{ 2329 struct fwohcidb_tr *db_tr; 2330 int z = 1; 2331 struct fw_pkt *fp; 2332 u_int8_t *ld; 2333 u_int32_t stat, off; 2334 u_int spd; 2335 int len, plen, hlen, pcnt, poff = 0, rlen; 2336 int s; 2337 caddr_t buf; 2338 int resCount; 2339 2340 if(&sc->arrq == dbch){ 2341 off = OHCI_ARQOFF; 2342 }else if(&sc->arrs == dbch){ 2343 off = OHCI_ARSOFF; 2344 }else{ 2345 return; 2346 } 2347 2348 s = splfw(); 2349 db_tr = dbch->top; 2350 pcnt = 0; 2351 /* XXX we cannot handle a packet which lies in more than two buf */ 2352 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2353 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2354 resCount = db_tr->db[0].db.desc.count; 2355 len = dbch->xferq.psize - resCount 2356 - dbch->buf_offset; 2357 while (len > 0 ) { 2358 if (count >= 0 && count-- == 0) 2359 goto out; 2360 if(dbch->frag.buf != NULL){ 2361 buf = dbch->frag.buf; 2362 if (dbch->frag.plen < 0) { 2363 /* incomplete header */ 2364 int hlen; 2365 2366 hlen = - dbch->frag.plen; 2367 rlen = hlen - dbch->frag.len; 2368 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2369 ld += rlen; 2370 len -= rlen; 2371 dbch->frag.len += rlen; 2372#if 0 2373 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2374#endif 2375 fp=(struct fw_pkt *)dbch->frag.buf; 2376 dbch->frag.plen 2377 = fwohci_get_plen(sc, fp, hlen); 2378 if (dbch->frag.plen == 0) 2379 goto out; 2380 } 2381 rlen = dbch->frag.plen - dbch->frag.len; 2382#if 0 2383 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2384#endif 2385 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2386 rlen); 2387 ld += rlen; 2388 len -= rlen; 2389 plen = dbch->frag.plen; 2390 dbch->frag.buf = NULL; 2391 dbch->frag.plen = 0; 2392 dbch->frag.len = 0; 2393 poff = 0; 2394 }else{ 2395 fp=(struct fw_pkt *)ld; 2396 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2397 switch(fp->mode.common.tcode){ 2398 case FWTCODE_RREQQ: 2399 case FWTCODE_WRES: 2400 case FWTCODE_WREQQ: 2401 case FWTCODE_RRESQ: 2402 case FWOHCITCODE_PHY: 2403 hlen = 12; 2404 break; 2405 case FWTCODE_RREQB: 2406 case FWTCODE_WREQB: 2407 case FWTCODE_LREQ: 2408 case FWTCODE_RRESB: 2409 case FWTCODE_LRES: 2410 hlen = 16; 2411 break; 2412 default: 2413 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2414 goto out; 2415 } 2416 if (len >= hlen) { 2417 plen = fwohci_get_plen(sc, fp, hlen); 2418 if (plen == 0) 2419 goto out; 2420 plen = (plen + 3) & ~3; 2421 len -= plen; 2422 } else { 2423 plen = -hlen; 2424 len -= hlen; 2425 } 2426 if(resCount > 0 || len > 0){ 2427 buf = malloc( dbch->xferq.psize, 2428 M_DEVBUF, M_NOWAIT); 2429 if(buf == NULL){ 2430 printf("cannot malloc!\n"); 2431 free(db_tr->buf, M_DEVBUF); 2432 goto out; 2433 } 2434 bcopy(ld, buf, plen); 2435 poff = 0; 2436 dbch->frag.buf = NULL; 2437 dbch->frag.plen = 0; 2438 dbch->frag.len = 0; 2439 }else if(len < 0){ 2440 dbch->frag.buf = db_tr->buf; 2441 if (plen < 0) { 2442#if 0 2443 printf("plen < 0:" 2444 "hlen: %d len: %d\n", 2445 hlen, len); 2446#endif 2447 dbch->frag.len = hlen + len; 2448 dbch->frag.plen = -hlen; 2449 } else { 2450 dbch->frag.len = plen + len; 2451 dbch->frag.plen = plen; 2452 } 2453 bcopy(ld, db_tr->buf, dbch->frag.len); 2454 buf = NULL; 2455 }else{ 2456 buf = db_tr->buf; 2457 poff = ld - (u_int8_t *)buf; 2458 dbch->frag.buf = NULL; 2459 dbch->frag.plen = 0; 2460 dbch->frag.len = 0; 2461 } 2462 ld += plen; 2463 } 2464 if( buf != NULL){ 2465/* DMA result-code will be written at the tail of packet */ 2466 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2467 spd = (stat >> 5) & 0x3; 2468 stat &= 0x1f; 2469 switch(stat){ 2470 case FWOHCIEV_ACKPEND: 2471#if 0 2472 printf("fwohci_arcv: ack pending..\n"); 2473#endif 2474 /* fall through */ 2475 case FWOHCIEV_ACKCOMPL: 2476 if( poff != 0 ) 2477 bcopy(buf+poff, buf, plen - 4); 2478 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2479 break; 2480 case FWOHCIEV_BUSRST: 2481 free(buf, M_DEVBUF); 2482 if (sc->fc.status != FWBUSRESET) 2483 printf("got BUSRST packet!?\n"); 2484 break; 2485 default: 2486 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2487#if 0 /* XXX */ 2488 goto out; 2489#endif 2490 break; 2491 } 2492 } 2493 pcnt ++; 2494 }; 2495out: 2496 if (resCount == 0) { 2497 /* done on this buffer */ 2498 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2499 dbch->xferq.flag, 0, NULL); 2500 dbch->bottom->db[0].db.desc.depend |= z; 2501 dbch->bottom = db_tr; 2502 db_tr = STAILQ_NEXT(db_tr, link); 2503 dbch->top = db_tr; 2504 dbch->buf_offset = 0; 2505 } else { 2506 dbch->buf_offset = dbch->xferq.psize - resCount; 2507 break; 2508 } 2509 /* XXX make sure DMA is not dead */ 2510 } 2511#if 0 2512 if (pcnt < 1) 2513 printf("fwohci_arcv: no packets\n"); 2514#endif 2515 splx(s); 2516} 2517