fwohci.c revision 214021
1139749Simp/*- 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 214021 2010-10-18 14:26:29Z brucec $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50169123Ssimokawa#include <sys/sysctl.h> 51103285Sikob#include <sys/bus.h> 52103285Sikob#include <sys/kernel.h> 53103285Sikob#include <sys/conf.h> 54113584Ssimokawa#include <sys/endian.h> 55170374Ssimokawa#include <sys/kdb.h> 56103285Sikob 57103285Sikob#include <machine/bus.h> 58103285Sikob 59127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 60117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 61117067Ssimokawa#endif 62117067Ssimokawa 63127468Ssimokawa#ifdef __DragonFly__ 64127468Ssimokawa#include "firewire.h" 65127468Ssimokawa#include "firewirereg.h" 66127468Ssimokawa#include "fwdma.h" 67127468Ssimokawa#include "fwohcireg.h" 68127468Ssimokawa#include "fwohcivar.h" 69127468Ssimokawa#include "firewire_phy.h" 70127468Ssimokawa#else 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirereg.h> 73113584Ssimokawa#include <dev/firewire/fwdma.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77127468Ssimokawa#endif 78103285Sikob 79103285Sikob#undef OHCI_DEBUG 80106802Ssimokawa 81169123Ssimokawastatic int nocyclemaster = 0; 82170400Ssimokawaint firewire_phydma_enable = 1; 83169123SsimokawaSYSCTL_DECL(_hw_firewire); 84169123SsimokawaSYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 85169123Ssimokawa "Do not send cycle start packets"); 86170400SsimokawaSYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW, 87170400Ssimokawa &firewire_phydma_enable, 1, "Allow physical request DMA from firewire"); 88170400SsimokawaTUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable); 89169123Ssimokawa 90103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 91103285Sikob "STOR","LOAD","NOP ","STOP",}; 92113584Ssimokawa 93103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 94103285Sikob "UNDEF","REG","SYS","DEV"}; 95113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 96103285Sikobchar fwohcicode[32][0x20]={ 97103285Sikob "No stat","Undef","long","miss Ack err", 98170374Ssimokawa "FIFO underrun","FIFO overrun","desc err", "data read err", 99103285Sikob "data write err","bus reset","timeout","tcode err", 100103285Sikob "Undef","Undef","unknown event","flushed", 101103285Sikob "Undef","ack complete","ack pend","Undef", 102103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 103103285Sikob "Undef","Undef","Undef","ack tardy", 104103285Sikob "Undef","ack data_err","ack type_err",""}; 105113584Ssimokawa 106116376Ssimokawa#define MAX_SPEED 3 107124378Ssimokawaextern char *linkspeed[]; 108129585Sdfruint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 109103285Sikob 110103285Sikobstatic struct tcode_info tinfo[] = { 111170374Ssimokawa/* hdr_len block flag valid_response */ 112170374Ssimokawa/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES}, 113170374Ssimokawa/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES}, 114170374Ssimokawa/* 2 WRES */ {12, FWTI_RES, 0xff}, 115170374Ssimokawa/* 3 XXX */ { 0, 0, 0xff}, 116170374Ssimokawa/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ}, 117170374Ssimokawa/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB}, 118170374Ssimokawa/* 6 RRESQ */ {16, FWTI_RES, 0xff}, 119170374Ssimokawa/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 120170374Ssimokawa/* 8 CYCS */ { 0, 0, 0xff}, 121170374Ssimokawa/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES}, 122170374Ssimokawa/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff}, 123170374Ssimokawa/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 124170374Ssimokawa/* c XXX */ { 0, 0, 0xff}, 125170374Ssimokawa/* d XXX */ { 0, 0, 0xff}, 126170374Ssimokawa/* e PHY */ {12, FWTI_REQ, 0xff}, 127170374Ssimokawa/* f XXX */ { 0, 0, 0xff} 128103285Sikob}; 129103285Sikob 130103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 131103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 132103285Sikob 133103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 134103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 135103285Sikob 136124169Ssimokawastatic void fwohci_ibr (struct firewire_comm *); 137124169Ssimokawastatic void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 138124169Ssimokawastatic void fwohci_db_free (struct fwohci_dbch *); 139124169Ssimokawastatic void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 140124169Ssimokawastatic void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 141124169Ssimokawastatic void fwohci_start_atq (struct firewire_comm *); 142124169Ssimokawastatic void fwohci_start_ats (struct firewire_comm *); 143124169Ssimokawastatic void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 144129585Sdfrstatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 145129585Sdfrstatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 146124169Ssimokawastatic int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 147124169Ssimokawastatic int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 148124169Ssimokawastatic int fwohci_irx_enable (struct firewire_comm *, int); 149124169Ssimokawastatic int fwohci_irx_disable (struct firewire_comm *, int); 150113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 151129585Sdfrstatic void fwohci_irx_post (struct firewire_comm *, uint32_t *); 152113584Ssimokawa#endif 153124169Ssimokawastatic int fwohci_itxbuf_enable (struct firewire_comm *, int); 154124169Ssimokawastatic int fwohci_itx_disable (struct firewire_comm *, int); 155124169Ssimokawastatic void fwohci_timeout (void *); 156124169Ssimokawastatic void fwohci_set_intr (struct firewire_comm *, int); 157113584Ssimokawa 158124169Ssimokawastatic int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 159124169Ssimokawastatic int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 160129585Sdfrstatic void dump_db (struct fwohci_softc *, uint32_t); 161129585Sdfrstatic void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 162129585Sdfrstatic void dump_dma (struct fwohci_softc *, uint32_t); 163129585Sdfrstatic uint32_t fwohci_cyctimer (struct firewire_comm *); 164124169Ssimokawastatic void fwohci_rbuf_update (struct fwohci_softc *, int); 165124169Ssimokawastatic void fwohci_tbuf_update (struct fwohci_softc *, int); 166124169Ssimokawavoid fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 167170374Ssimokawastatic void fwohci_task_busreset(void *, int); 168170374Ssimokawastatic void fwohci_task_sid(void *, int); 169170374Ssimokawastatic void fwohci_task_dma(void *, int); 170103285Sikob 171103285Sikob/* 172103285Sikob * memory allocated for DMA programs 173103285Sikob */ 174103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 175103285Sikob 176103285Sikob#define NDB FWMAXQUEUE 177103285Sikob 178103285Sikob#define OHCI_VERSION 0x00 179112523Ssimokawa#define OHCI_ATRETRY 0x08 180103285Sikob#define OHCI_CROMHDR 0x18 181103285Sikob#define OHCI_BUS_OPT 0x20 182103285Sikob#define OHCI_BUSIRMC (1 << 31) 183103285Sikob#define OHCI_BUSCMC (1 << 30) 184103285Sikob#define OHCI_BUSISC (1 << 29) 185103285Sikob#define OHCI_BUSBMC (1 << 28) 186103285Sikob#define OHCI_BUSPMC (1 << 27) 187103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 188103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 189103285Sikob 190103285Sikob#define OHCI_EUID_HI 0x24 191103285Sikob#define OHCI_EUID_LO 0x28 192103285Sikob 193103285Sikob#define OHCI_CROMPTR 0x34 194103285Sikob#define OHCI_HCCCTL 0x50 195103285Sikob#define OHCI_HCCCTLCLR 0x54 196103285Sikob#define OHCI_AREQHI 0x100 197103285Sikob#define OHCI_AREQHICLR 0x104 198103285Sikob#define OHCI_AREQLO 0x108 199103285Sikob#define OHCI_AREQLOCLR 0x10c 200103285Sikob#define OHCI_PREQHI 0x110 201103285Sikob#define OHCI_PREQHICLR 0x114 202103285Sikob#define OHCI_PREQLO 0x118 203103285Sikob#define OHCI_PREQLOCLR 0x11c 204103285Sikob#define OHCI_PREQUPPER 0x120 205103285Sikob 206103285Sikob#define OHCI_SID_BUF 0x64 207103285Sikob#define OHCI_SID_CNT 0x68 208113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 209103285Sikob#define OHCI_SID_CNT_MASK 0xffc 210103285Sikob 211103285Sikob#define OHCI_IT_STAT 0x90 212103285Sikob#define OHCI_IT_STATCLR 0x94 213103285Sikob#define OHCI_IT_MASK 0x98 214103285Sikob#define OHCI_IT_MASKCLR 0x9c 215103285Sikob 216103285Sikob#define OHCI_IR_STAT 0xa0 217103285Sikob#define OHCI_IR_STATCLR 0xa4 218103285Sikob#define OHCI_IR_MASK 0xa8 219103285Sikob#define OHCI_IR_MASKCLR 0xac 220103285Sikob 221103285Sikob#define OHCI_LNKCTL 0xe0 222103285Sikob#define OHCI_LNKCTLCLR 0xe4 223103285Sikob 224103285Sikob#define OHCI_PHYACCESS 0xec 225103285Sikob#define OHCI_CYCLETIMER 0xf0 226103285Sikob 227103285Sikob#define OHCI_DMACTL(off) (off) 228103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 229103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 230103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 231103285Sikob 232103285Sikob#define OHCI_ATQOFF 0x180 233103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 234103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 235103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 236103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 237103285Sikob 238103285Sikob#define OHCI_ATSOFF 0x1a0 239103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 240103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 241103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 242103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 243103285Sikob 244103285Sikob#define OHCI_ARQOFF 0x1c0 245103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 246103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 247103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 248103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 249103285Sikob 250103285Sikob#define OHCI_ARSOFF 0x1e0 251103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 252103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 253103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 254103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 255103285Sikob 256103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 257103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 258103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 259103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 260103285Sikob 261103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 262103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 263103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 264103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 265103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 266103285Sikob 267103285Sikobd_ioctl_t fwohci_ioctl; 268103285Sikob 269103285Sikob/* 270103285Sikob * Communication with PHY device 271103285Sikob */ 272170374Ssimokawa/* XXX need lock for phy access */ 273129585Sdfrstatic uint32_t 274129585Sdfrfwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 275103285Sikob{ 276129585Sdfr uint32_t fun; 277103285Sikob 278103285Sikob addr &= 0xf; 279103285Sikob data &= 0xff; 280103285Sikob 281103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 282103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 283103285Sikob DELAY(100); 284103285Sikob 285103285Sikob return(fwphy_rddata( sc, addr)); 286103285Sikob} 287103285Sikob 288129585Sdfrstatic uint32_t 289103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 290103285Sikob{ 291103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 292103285Sikob int i; 293129585Sdfr uint32_t bm; 294103285Sikob 295103285Sikob#define OHCI_CSR_DATA 0x0c 296103285Sikob#define OHCI_CSR_COMP 0x10 297103285Sikob#define OHCI_CSR_CONT 0x14 298103285Sikob#define OHCI_BUS_MANAGER_ID 0 299103285Sikob 300103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 301103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 302103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 303103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 304109280Ssimokawa DELAY(10); 305103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 306107653Ssimokawa if((bm & 0x3f) == 0x3f) 307103285Sikob bm = node; 308132432Ssimokawa if (firewire_debug) 309188509Ssbruno device_printf(sc->fc.dev, "%s: %d->%d (loop=%d)\n", 310188509Ssbruno __func__, bm, node, i); 311103285Sikob 312103285Sikob return(bm); 313103285Sikob} 314103285Sikob 315129585Sdfrstatic uint32_t 316106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 317103285Sikob{ 318129585Sdfr uint32_t fun, stat; 319108500Ssimokawa u_int i, retry = 0; 320103285Sikob 321103285Sikob addr &= 0xf; 322108500Ssimokawa#define MAX_RETRY 100 323108500Ssimokawaagain: 324108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 325103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 326103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 327108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 328103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 329103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 330103285Sikob break; 331109280Ssimokawa DELAY(100); 332103285Sikob } 333108500Ssimokawa if(i >= MAX_RETRY) { 334132432Ssimokawa if (firewire_debug) 335188509Ssbruno device_printf(sc->fc.dev, "%s: failed(1).\n", __func__); 336108527Ssimokawa if (++retry < MAX_RETRY) { 337109280Ssimokawa DELAY(100); 338108527Ssimokawa goto again; 339108527Ssimokawa } 340108500Ssimokawa } 341108500Ssimokawa /* Make sure that SCLK is started */ 342108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 343108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 344108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 345132432Ssimokawa if (firewire_debug) 346188509Ssbruno device_printf(sc->fc.dev, "%s: failed(2).\n", __func__); 347108500Ssimokawa if (++retry < MAX_RETRY) { 348109280Ssimokawa DELAY(100); 349108500Ssimokawa goto again; 350108500Ssimokawa } 351108500Ssimokawa } 352188509Ssbruno if (firewire_debug > 1 || retry >= MAX_RETRY) 353108500Ssimokawa device_printf(sc->fc.dev, 354188509Ssbruno "%s:: 0x%x loop=%d, retry=%d\n", 355188509Ssbruno __func__, addr, i, retry); 356108500Ssimokawa#undef MAX_RETRY 357103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 358103285Sikob} 359103285Sikob/* Device specific ioctl. */ 360103285Sikobint 361130585Sphkfwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 362103285Sikob{ 363103285Sikob struct firewire_softc *sc; 364103285Sikob struct fwohci_softc *fc; 365103285Sikob int unit = DEV2UNIT(dev); 366103285Sikob int err = 0; 367103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 368129585Sdfr uint32_t *dmach = (uint32_t *) data; 369103285Sikob 370103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 371103285Sikob if(sc == NULL){ 372103285Sikob return(EINVAL); 373103285Sikob } 374103285Sikob fc = (struct fwohci_softc *)sc->fc; 375103285Sikob 376103285Sikob if (!data) 377103285Sikob return(EINVAL); 378103285Sikob 379103285Sikob switch (cmd) { 380103285Sikob case FWOHCI_WRREG: 381103285Sikob#define OHCI_MAX_REG 0x800 382103285Sikob if(reg->addr <= OHCI_MAX_REG){ 383103285Sikob OWRITE(fc, reg->addr, reg->data); 384103285Sikob reg->data = OREAD(fc, reg->addr); 385103285Sikob }else{ 386103285Sikob err = EINVAL; 387103285Sikob } 388103285Sikob break; 389103285Sikob case FWOHCI_RDREG: 390103285Sikob if(reg->addr <= OHCI_MAX_REG){ 391103285Sikob reg->data = OREAD(fc, reg->addr); 392103285Sikob }else{ 393103285Sikob err = EINVAL; 394103285Sikob } 395103285Sikob break; 396103285Sikob/* Read DMA descriptors for debug */ 397103285Sikob case DUMPDMA: 398103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 399103285Sikob dump_dma(fc, *dmach); 400103285Sikob dump_db(fc, *dmach); 401103285Sikob }else{ 402103285Sikob err = EINVAL; 403103285Sikob } 404103285Sikob break; 405119118Ssimokawa/* Read/Write Phy registers */ 406119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 407119118Ssimokawa case FWOHCI_RDPHYREG: 408119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 409119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 410119118Ssimokawa else 411119118Ssimokawa err = EINVAL; 412119118Ssimokawa break; 413119118Ssimokawa case FWOHCI_WRPHYREG: 414119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 415119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 416119118Ssimokawa else 417119118Ssimokawa err = EINVAL; 418119118Ssimokawa break; 419103285Sikob default: 420119118Ssimokawa err = EINVAL; 421103285Sikob break; 422103285Sikob } 423103285Sikob return err; 424103285Sikob} 425106790Ssimokawa 426108530Ssimokawastatic int 427108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 428103285Sikob{ 429129585Sdfr uint32_t reg, reg2; 430108530Ssimokawa int e1394a = 1; 431108530Ssimokawa/* 432108530Ssimokawa * probe PHY parameters 433108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 434108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 435108530Ssimokawa * number of port supported by core-logic. 436108530Ssimokawa * It is not actually available port on your PC . 437108530Ssimokawa */ 438108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 439167685Ssimokawa DELAY(500); 440167685Ssimokawa 441108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 442108530Ssimokawa 443108530Ssimokawa if((reg >> 5) != 7 ){ 444108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 445108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 446108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 447108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 448108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 449108530Ssimokawa sc->fc.speed, MAX_SPEED); 450108530Ssimokawa sc->fc.speed = MAX_SPEED; 451108530Ssimokawa } 452108530Ssimokawa device_printf(dev, 453108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 454108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 455108530Ssimokawa }else{ 456108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 457108530Ssimokawa sc->fc.mode |= FWPHYASYST; 458108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 459108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 460108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 461108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 462108530Ssimokawa sc->fc.speed, MAX_SPEED); 463108530Ssimokawa sc->fc.speed = MAX_SPEED; 464108530Ssimokawa } 465108530Ssimokawa device_printf(dev, 466108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 467108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 468108530Ssimokawa 469108530Ssimokawa /* check programPhyEnable */ 470108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 471108530Ssimokawa#if 0 472108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 473108530Ssimokawa#else /* XXX force to enable 1394a */ 474108530Ssimokawa if (e1394a) { 475108530Ssimokawa#endif 476132432Ssimokawa if (firewire_debug) 477108530Ssimokawa device_printf(dev, 478108530Ssimokawa "Enable 1394a Enhancements\n"); 479108530Ssimokawa /* enable EAA EMC */ 480108530Ssimokawa reg2 |= 0x03; 481108530Ssimokawa /* set aPhyEnhanceEnable */ 482108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 483108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 484108530Ssimokawa } else { 485108530Ssimokawa /* for safe */ 486108530Ssimokawa reg2 &= ~0x83; 487108530Ssimokawa } 488108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 489108530Ssimokawa } 490108530Ssimokawa 491108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 492108530Ssimokawa if((reg >> 5) == 7 ){ 493108530Ssimokawa reg = fwphy_rddata(sc, 4); 494108530Ssimokawa reg |= 1 << 6; 495108530Ssimokawa fwphy_wrdata(sc, 4, reg); 496108530Ssimokawa reg = fwphy_rddata(sc, 4); 497108530Ssimokawa } 498108530Ssimokawa return 0; 499108530Ssimokawa} 500108530Ssimokawa 501108530Ssimokawa 502108530Ssimokawavoid 503108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 504108530Ssimokawa{ 505108701Ssimokawa int i, max_rec, speed; 506129585Sdfr uint32_t reg, reg2; 507103285Sikob struct fwohcidb_tr *db_tr; 508103285Sikob 509129541Sdfr /* Disable interrupts */ 510108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 511108530Ssimokawa 512129541Sdfr /* Now stopping all DMA channels */ 513108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 514108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 515108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 516108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 517108530Ssimokawa 518108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 519108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 520108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 521108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 522108530Ssimokawa } 523108530Ssimokawa 524108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 525108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 526132432Ssimokawa if (firewire_debug) 527108530Ssimokawa device_printf(dev, "resetting OHCI..."); 528108530Ssimokawa i = 0; 529108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 530108530Ssimokawa if (i++ > 100) break; 531108530Ssimokawa DELAY(1000); 532108530Ssimokawa } 533132432Ssimokawa if (firewire_debug) 534108530Ssimokawa printf("done (loop=%d)\n", i); 535108530Ssimokawa 536108701Ssimokawa /* Probe phy */ 537108701Ssimokawa fwohci_probe_phy(sc, dev); 538108701Ssimokawa 539108701Ssimokawa /* Probe link */ 540108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 541108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 542108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 543108701Ssimokawa speed = (reg & 0x00000007); 544108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 545108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 546108701Ssimokawa /* XXX fix max_rec */ 547108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 548108701Ssimokawa if (max_rec != sc->fc.maxrec) { 549108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 550108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 551108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 552108701Ssimokawa } 553132432Ssimokawa if (firewire_debug) 554108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 555108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 556108530Ssimokawa 557108701Ssimokawa /* Initialize registers */ 558108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 559113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 560108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 561108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 562113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 563108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 564108530Ssimokawa 565108701Ssimokawa /* Enable link */ 566108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 567108642Ssimokawa 568108701Ssimokawa /* Force to start async RX DMA */ 569108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 570108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 571108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 572108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 573108530Ssimokawa 574108701Ssimokawa /* Initialize async TX */ 575108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 576108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 577116978Ssimokawa 578108701Ssimokawa /* AT Retries */ 579108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 580108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 581108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 582116978Ssimokawa 583116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 584116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 585116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 586116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 587116978Ssimokawa 588108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 589108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 590108530Ssimokawa db_tr->xfer = NULL; 591108530Ssimokawa } 592108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 593108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 594108530Ssimokawa db_tr->xfer = NULL; 595108530Ssimokawa } 596108530Ssimokawa 597108701Ssimokawa 598129541Sdfr /* Enable interrupts */ 599170374Ssimokawa sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID 600108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 601108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 602108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 603170374Ssimokawa sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT; 604170374Ssimokawa sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT; 605170374Ssimokawa OWRITE(sc, FWOHCI_INTMASK, sc->intmask); 606108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 607108530Ssimokawa 608108530Ssimokawa} 609108530Ssimokawa 610108530Ssimokawaint 611108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 612108530Ssimokawa{ 613121781Ssimokawa int i, mver; 614129585Sdfr uint32_t reg; 615129585Sdfr uint8_t ui[8]; 616108530Ssimokawa 617121781Ssimokawa/* OHCI version */ 618103285Sikob reg = OREAD(sc, OHCI_VERSION); 619121781Ssimokawa mver = (reg >> 16) & 0xff; 620103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 621121781Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 622121781Ssimokawa if (mver < 1 || mver > 9) { 623118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 624118416Ssimokawa return (ENXIO); 625118416Ssimokawa } 626118416Ssimokawa 627129541Sdfr/* Available Isochronous DMA channel probe */ 628110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 629110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 630110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 631110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 632110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 633110045Ssimokawa for (i = 0; i < 0x20; i++) 634110045Ssimokawa if ((reg & (1 << i)) == 0) 635110045Ssimokawa break; 636103285Sikob sc->fc.nisodma = i; 637129541Sdfr device_printf(dev, "No. of Isochronous channels is %d.\n", i); 638118820Ssimokawa if (i == 0) 639118820Ssimokawa return (ENXIO); 640103285Sikob 641103285Sikob sc->fc.arq = &sc->arrq.xferq; 642103285Sikob sc->fc.ars = &sc->arrs.xferq; 643103285Sikob sc->fc.atq = &sc->atrq.xferq; 644103285Sikob sc->fc.ats = &sc->atrs.xferq; 645103285Sikob 646113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 647113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 648113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 649113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 650113584Ssimokawa 651103285Sikob sc->arrq.xferq.start = NULL; 652103285Sikob sc->arrs.xferq.start = NULL; 653103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 654103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 655103285Sikob 656113584Ssimokawa sc->arrq.xferq.buf = NULL; 657113584Ssimokawa sc->arrs.xferq.buf = NULL; 658113584Ssimokawa sc->atrq.xferq.buf = NULL; 659113584Ssimokawa sc->atrs.xferq.buf = NULL; 660103285Sikob 661118293Ssimokawa sc->arrq.xferq.dmach = -1; 662118293Ssimokawa sc->arrs.xferq.dmach = -1; 663118293Ssimokawa sc->atrq.xferq.dmach = -1; 664118293Ssimokawa sc->atrs.xferq.dmach = -1; 665118293Ssimokawa 666103285Sikob sc->arrq.ndesc = 1; 667103285Sikob sc->arrs.ndesc = 1; 668110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 669110593Ssimokawa sc->atrs.ndesc = 2; 670103285Sikob 671103285Sikob sc->arrq.ndb = NDB; 672103285Sikob sc->arrs.ndb = NDB / 2; 673103285Sikob sc->atrq.ndb = NDB; 674103285Sikob sc->atrs.ndb = NDB / 2; 675103285Sikob 676103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 677103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 678103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 679118293Ssimokawa sc->it[i].xferq.dmach = i; 680118293Ssimokawa sc->ir[i].xferq.dmach = i; 681103285Sikob sc->it[i].ndb = 0; 682103285Sikob sc->ir[i].ndb = 0; 683103285Sikob } 684103285Sikob 685103285Sikob sc->fc.tcode = tinfo; 686113584Ssimokawa sc->fc.dev = dev; 687103285Sikob 688113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 689113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 690113584Ssimokawa if(sc->fc.config_rom == NULL){ 691113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 692103285Sikob return ENOMEM; 693103285Sikob } 694103285Sikob 695116376Ssimokawa#if 0 696116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 697103285Sikob sc->fc.config_rom[1] = 0x31333934; 698103285Sikob sc->fc.config_rom[2] = 0xf000a002; 699103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 700103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 701103285Sikob sc->fc.config_rom[5] = 0; 702103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 703103285Sikob 704103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 705113584Ssimokawa#endif 706103285Sikob 707103285Sikob 708129541Sdfr/* SID recieve buffer must align 2^11 */ 709103285Sikob#define OHCI_SIDSIZE (1 << 11) 710113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 711113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 712113584Ssimokawa if (sc->sid_buf == NULL) { 713113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 714108527Ssimokawa return ENOMEM; 715108527Ssimokawa } 716113584Ssimokawa 717129585Sdfr fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 718113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 719113584Ssimokawa 720113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 721113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 722109736Ssimokawa return ENOMEM; 723109736Ssimokawa } 724113584Ssimokawa 725113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 726108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 727108527Ssimokawa return ENOMEM; 728108527Ssimokawa 729113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 730108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 731108527Ssimokawa return ENOMEM; 732103285Sikob 733113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 734108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 735108527Ssimokawa return ENOMEM; 736108527Ssimokawa 737113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 738108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 739108527Ssimokawa return ENOMEM; 740103285Sikob 741109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 742109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 743109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 744109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 745103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 746109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 747109814Ssimokawa 748103285Sikob sc->fc.ioctl = fwohci_ioctl; 749103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 750103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 751103285Sikob sc->fc.ibr = fwohci_ibr; 752103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 753103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 754103285Sikob 755103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 756103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 757113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 758103285Sikob sc->fc.irx_post = fwohci_irx_post; 759113584Ssimokawa#else 760113584Ssimokawa sc->fc.irx_post = NULL; 761113584Ssimokawa#endif 762103285Sikob sc->fc.itx_post = NULL; 763103285Sikob sc->fc.timeout = fwohci_timeout; 764103285Sikob sc->fc.poll = fwohci_poll; 765103285Sikob sc->fc.set_intr = fwohci_set_intr; 766106790Ssimokawa 767113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 768113584Ssimokawa 769170374Ssimokawa /* Init task queue */ 770170374Ssimokawa sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK, 771170374Ssimokawa taskqueue_thread_enqueue, &sc->fc.taskqueue); 772170374Ssimokawa taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq", 773170374Ssimokawa device_get_unit(dev)); 774170374Ssimokawa TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc); 775170374Ssimokawa TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc); 776170374Ssimokawa TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc); 777170374Ssimokawa 778108530Ssimokawa fw_init(&sc->fc); 779108530Ssimokawa fwohci_reset(sc, dev); 780103285Sikob 781108530Ssimokawa return 0; 782103285Sikob} 783106790Ssimokawa 784106790Ssimokawavoid 785106790Ssimokawafwohci_timeout(void *arg) 786103285Sikob{ 787103285Sikob struct fwohci_softc *sc; 788103285Sikob 789103285Sikob sc = (struct fwohci_softc *)arg; 790103285Sikob} 791106790Ssimokawa 792129585Sdfruint32_t 793106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 794103285Sikob{ 795103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 796103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 797103285Sikob} 798103285Sikob 799108527Ssimokawaint 800108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 801108527Ssimokawa{ 802108527Ssimokawa int i; 803108527Ssimokawa 804113584Ssimokawa if (sc->sid_buf != NULL) 805113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 806113584Ssimokawa if (sc->fc.config_rom != NULL) 807113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 808108527Ssimokawa 809108527Ssimokawa fwohci_db_free(&sc->arrq); 810108527Ssimokawa fwohci_db_free(&sc->arrs); 811108527Ssimokawa 812108527Ssimokawa fwohci_db_free(&sc->atrq); 813108527Ssimokawa fwohci_db_free(&sc->atrs); 814108527Ssimokawa 815108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 816108527Ssimokawa fwohci_db_free(&sc->it[i]); 817108527Ssimokawa fwohci_db_free(&sc->ir[i]); 818108527Ssimokawa } 819170374Ssimokawa if (sc->fc.taskqueue != NULL) { 820170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset); 821170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid); 822170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma); 823170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout); 824170374Ssimokawa taskqueue_free(sc->fc.taskqueue); 825170374Ssimokawa sc->fc.taskqueue = NULL; 826170374Ssimokawa } 827108527Ssimokawa 828108527Ssimokawa return 0; 829108527Ssimokawa} 830108527Ssimokawa 831108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 832108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 833108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 834108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 835108655Ssimokawa} while (0) 836108655Ssimokawa 837106790Ssimokawastatic void 838113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 839113584Ssimokawa{ 840113584Ssimokawa struct fwohcidb_tr *db_tr; 841120660Ssimokawa struct fwohcidb *db; 842113584Ssimokawa bus_dma_segment_t *s; 843113584Ssimokawa int i; 844113584Ssimokawa 845113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 846113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 847113584Ssimokawa if (error) { 848113584Ssimokawa if (firewire_debug || error != EFBIG) 849113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 850113584Ssimokawa return; 851113584Ssimokawa } 852113584Ssimokawa for (i = 0; i < nseg; i++) { 853113584Ssimokawa s = &segs[i]; 854113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 855113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 856113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 857113584Ssimokawa db++; 858113584Ssimokawa db_tr->dbcnt++; 859113584Ssimokawa } 860113584Ssimokawa} 861113584Ssimokawa 862113584Ssimokawastatic void 863113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 864113584Ssimokawa bus_size_t size, int error) 865113584Ssimokawa{ 866113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 867113584Ssimokawa} 868113584Ssimokawa 869113584Ssimokawastatic void 870106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 871103285Sikob{ 872103285Sikob int i, s; 873120660Ssimokawa int tcode, hdr_len, pl_off; 874103285Sikob int fsegment = -1; 875129585Sdfr uint32_t off; 876103285Sikob struct fw_xfer *xfer; 877103285Sikob struct fw_pkt *fp; 878120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 879103285Sikob struct fwohcidb_tr *db_tr; 880120660Ssimokawa struct fwohcidb *db; 881129585Sdfr uint32_t *ld; 882103285Sikob struct tcode_info *info; 883108655Ssimokawa static int maxdesc=0; 884103285Sikob 885170374Ssimokawa FW_GLOCK_ASSERT(&sc->fc); 886170374Ssimokawa 887103285Sikob if(&sc->atrq == dbch){ 888103285Sikob off = OHCI_ATQOFF; 889103285Sikob }else if(&sc->atrs == dbch){ 890103285Sikob off = OHCI_ATSOFF; 891103285Sikob }else{ 892103285Sikob return; 893103285Sikob } 894103285Sikob 895103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 896103285Sikob return; 897103285Sikob 898103285Sikob s = splfw(); 899103285Sikob db_tr = dbch->top; 900103285Sikobtxloop: 901103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 902103285Sikob if(xfer == NULL){ 903103285Sikob goto kick; 904103285Sikob } 905170374Ssimokawa#if 0 906103285Sikob if(dbch->xferq.queued == 0 ){ 907103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 908103285Sikob } 909170374Ssimokawa#endif 910103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 911103285Sikob db_tr->xfer = xfer; 912170374Ssimokawa xfer->flag = FWXF_START; 913103285Sikob 914120660Ssimokawa fp = &xfer->send.hdr; 915103285Sikob tcode = fp->mode.common.tcode; 916103285Sikob 917120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 918103285Sikob info = &tinfo[tcode]; 919113584Ssimokawa hdr_len = pl_off = info->hdr_len; 920119155Ssimokawa 921119155Ssimokawa ld = &ohcifp->mode.ld[0]; 922119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 923119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 924119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 925119155Ssimokawa 926120660Ssimokawa ohcifp->mode.common.spd = xfer->send.spd & 0x7; 927103285Sikob if (tcode == FWTCODE_STREAM ){ 928103285Sikob hdr_len = 8; 929113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 930103285Sikob } else if (tcode == FWTCODE_PHY) { 931103285Sikob hdr_len = 12; 932119155Ssimokawa ld[1] = fp->mode.ld[1]; 933119155Ssimokawa ld[2] = fp->mode.ld[2]; 934103285Sikob ohcifp->mode.common.spd = 0; 935103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 936103285Sikob } else { 937113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 938103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 939103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 940103285Sikob } 941103285Sikob db = &db_tr->db[0]; 942113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 943113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 944119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 945113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 946103285Sikob/* Specify bound timer of asy. responce */ 947103285Sikob if(&sc->atrs == dbch){ 948113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 949113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 950103285Sikob } 951113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 952113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 953113584Ssimokawa hdr_len = 12; 954113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 955119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 956113584Ssimokawa#endif 957103285Sikob 958111942Ssimokawaagain: 959103285Sikob db_tr->dbcnt = 2; 960103285Sikob db = &db_tr->db[db_tr->dbcnt]; 961120660Ssimokawa if (xfer->send.pay_len > 0) { 962113584Ssimokawa int err; 963113584Ssimokawa /* handle payload */ 964103285Sikob if (xfer->mbuf == NULL) { 965113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 966120660Ssimokawa &xfer->send.payload[0], xfer->send.pay_len, 967113584Ssimokawa fwohci_execute_db, db_tr, 968113584Ssimokawa /*flags*/0); 969103285Sikob } else { 970111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 971113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 972113584Ssimokawa xfer->mbuf, 973113584Ssimokawa fwohci_execute_db2, db_tr, 974113584Ssimokawa /* flags */0); 975113584Ssimokawa if (err == EFBIG) { 976113584Ssimokawa struct mbuf *m0; 977113584Ssimokawa 978113584Ssimokawa if (firewire_debug) 979113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 980113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 981113584Ssimokawa if (m0 != NULL) { 982111942Ssimokawa m_copydata(xfer->mbuf, 0, 983111942Ssimokawa xfer->mbuf->m_pkthdr.len, 984113584Ssimokawa mtod(m0, caddr_t)); 985113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 986111942Ssimokawa xfer->mbuf->m_pkthdr.len; 987111942Ssimokawa m_freem(xfer->mbuf); 988113584Ssimokawa xfer->mbuf = m0; 989111942Ssimokawa goto again; 990111942Ssimokawa } 991111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 992111942Ssimokawa } 993103285Sikob } 994113584Ssimokawa if (err) 995113584Ssimokawa printf("dmamap_load: err=%d\n", err); 996113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 997113584Ssimokawa BUS_DMASYNC_PREWRITE); 998113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 999113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 1000113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1001113584Ssimokawa OHCI_OUTPUT_MORE); 1002113584Ssimokawa#endif 1003103285Sikob } 1004108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 1005108655Ssimokawa maxdesc = db_tr->dbcnt; 1006132432Ssimokawa if (firewire_debug) 1007187993Ssbruno device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc); 1008108655Ssimokawa } 1009103285Sikob /* last db */ 1010103285Sikob LAST_DB(db_tr, db); 1011113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 1012113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1013113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 1014113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 1015103285Sikob 1016103285Sikob if(fsegment == -1 ) 1017103285Sikob fsegment = db_tr->dbcnt; 1018103285Sikob if (dbch->pdb_tr != NULL) { 1019103285Sikob LAST_DB(dbch->pdb_tr, db); 1020113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1021103285Sikob } 1022170374Ssimokawa dbch->xferq.queued ++; 1023103285Sikob dbch->pdb_tr = db_tr; 1024103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1025103285Sikob if(db_tr != dbch->bottom){ 1026103285Sikob goto txloop; 1027103285Sikob } else { 1028107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1029103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 1030103285Sikob } 1031103285Sikobkick: 1032103285Sikob /* kick asy q */ 1033113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1034113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1035103285Sikob 1036103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1037103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1038103285Sikob } else { 1039132432Ssimokawa if (firewire_debug) 1040107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1041103285Sikob OREAD(sc, OHCI_DMACTL(off))); 1042113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1043103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1044103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1045103285Sikob } 1046106790Ssimokawa 1047103285Sikob dbch->top = db_tr; 1048103285Sikob splx(s); 1049103285Sikob return; 1050103285Sikob} 1051106790Ssimokawa 1052106790Ssimokawastatic void 1053106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1054103285Sikob{ 1055103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1056170374Ssimokawa FW_GLOCK(&sc->fc); 1057103285Sikob fwohci_start( sc, &(sc->atrq)); 1058170374Ssimokawa FW_GUNLOCK(&sc->fc); 1059103285Sikob return; 1060103285Sikob} 1061106790Ssimokawa 1062106790Ssimokawastatic void 1063106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1064103285Sikob{ 1065103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1066170374Ssimokawa FW_GLOCK(&sc->fc); 1067103285Sikob fwohci_start( sc, &(sc->atrs)); 1068170374Ssimokawa FW_GUNLOCK(&sc->fc); 1069103285Sikob return; 1070103285Sikob} 1071106790Ssimokawa 1072106790Ssimokawavoid 1073106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1074103285Sikob{ 1075113584Ssimokawa int s, ch, err = 0; 1076103285Sikob struct fwohcidb_tr *tr; 1077120660Ssimokawa struct fwohcidb *db; 1078103285Sikob struct fw_xfer *xfer; 1079129585Sdfr uint32_t off; 1080113584Ssimokawa u_int stat, status; 1081103285Sikob int packets; 1082103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1083113584Ssimokawa 1084103285Sikob if(&sc->atrq == dbch){ 1085103285Sikob off = OHCI_ATQOFF; 1086113584Ssimokawa ch = ATRQ_CH; 1087103285Sikob }else if(&sc->atrs == dbch){ 1088103285Sikob off = OHCI_ATSOFF; 1089113584Ssimokawa ch = ATRS_CH; 1090103285Sikob }else{ 1091103285Sikob return; 1092103285Sikob } 1093103285Sikob s = splfw(); 1094103285Sikob tr = dbch->bottom; 1095103285Sikob packets = 0; 1096113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1097113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1098103285Sikob while(dbch->xferq.queued > 0){ 1099103285Sikob LAST_DB(tr, db); 1100113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1101113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1102170425Ssimokawa if (fc->status != FWBUSINIT) 1103103285Sikob /* maybe out of order?? */ 1104103285Sikob goto out; 1105103285Sikob } 1106113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1107113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1108113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1109119155Ssimokawa#if 1 1110167629Ssimokawa if (firewire_debug > 1) 1111119155Ssimokawa dump_db(sc, ch); 1112103285Sikob#endif 1113113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1114113584Ssimokawa /* Stop DMA */ 1115103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1116103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1117103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1118103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1119103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1120103285Sikob } 1121113584Ssimokawa stat = status & FWOHCIEV_MASK; 1122103285Sikob switch(stat){ 1123110577Ssimokawa case FWOHCIEV_ACKPEND: 1124103285Sikob case FWOHCIEV_ACKCOMPL: 1125103285Sikob err = 0; 1126103285Sikob break; 1127103285Sikob case FWOHCIEV_ACKBSA: 1128103285Sikob case FWOHCIEV_ACKBSB: 1129110577Ssimokawa case FWOHCIEV_ACKBSX: 1130103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1131103285Sikob err = EBUSY; 1132103285Sikob break; 1133103285Sikob case FWOHCIEV_FLUSHED: 1134103285Sikob case FWOHCIEV_ACKTARD: 1135103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1136103285Sikob err = EAGAIN; 1137103285Sikob break; 1138103285Sikob case FWOHCIEV_MISSACK: 1139103285Sikob case FWOHCIEV_UNDRRUN: 1140103285Sikob case FWOHCIEV_OVRRUN: 1141103285Sikob case FWOHCIEV_DESCERR: 1142103285Sikob case FWOHCIEV_DTRDERR: 1143103285Sikob case FWOHCIEV_TIMEOUT: 1144103285Sikob case FWOHCIEV_TCODERR: 1145103285Sikob case FWOHCIEV_UNKNOWN: 1146103285Sikob case FWOHCIEV_ACKDERR: 1147103285Sikob case FWOHCIEV_ACKTERR: 1148103285Sikob default: 1149103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1150103285Sikob stat, fwohcicode[stat]); 1151103285Sikob err = EINVAL; 1152103285Sikob break; 1153103285Sikob } 1154110577Ssimokawa if (tr->xfer != NULL) { 1155103285Sikob xfer = tr->xfer; 1156170374Ssimokawa if (xfer->flag & FWXF_RCVD) { 1157119289Ssimokawa#if 0 1158113584Ssimokawa if (firewire_debug) 1159113584Ssimokawa printf("already rcvd\n"); 1160119289Ssimokawa#endif 1161113584Ssimokawa fw_xfer_done(xfer); 1162113584Ssimokawa } else { 1163170427Ssimokawa microtime(&xfer->tv); 1164170374Ssimokawa xfer->flag = FWXF_SENT; 1165170425Ssimokawa if (err == EBUSY) { 1166170374Ssimokawa xfer->flag = FWXF_BUSY; 1167114218Ssimokawa xfer->resp = err; 1168167630Ssimokawa xfer->recv.pay_len = 0; 1169167630Ssimokawa fw_xfer_done(xfer); 1170114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1171114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1172170374Ssimokawa xfer->flag = FWXF_SENTERR; 1173114218Ssimokawa xfer->resp = err; 1174120660Ssimokawa xfer->recv.pay_len = 0; 1175113584Ssimokawa fw_xfer_done(xfer); 1176114218Ssimokawa } 1177103285Sikob } 1178110577Ssimokawa /* 1179110577Ssimokawa * The watchdog timer takes care of split 1180110577Ssimokawa * transcation timeout for ACKPEND case. 1181110577Ssimokawa */ 1182113584Ssimokawa } else { 1183113584Ssimokawa printf("this shouldn't happen\n"); 1184103285Sikob } 1185170374Ssimokawa FW_GLOCK(fc); 1186110269Ssimokawa dbch->xferq.queued --; 1187170374Ssimokawa FW_GUNLOCK(fc); 1188103285Sikob tr->xfer = NULL; 1189103285Sikob 1190103285Sikob packets ++; 1191103285Sikob tr = STAILQ_NEXT(tr, link); 1192103285Sikob dbch->bottom = tr; 1193111956Ssimokawa if (dbch->bottom == dbch->top) { 1194111956Ssimokawa /* we reaches the end of context program */ 1195111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1196111956Ssimokawa printf("queued > 0\n"); 1197111956Ssimokawa break; 1198111956Ssimokawa } 1199103285Sikob } 1200103285Sikobout: 1201103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1202103285Sikob printf("make free slot\n"); 1203103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1204170374Ssimokawa FW_GLOCK(fc); 1205103285Sikob fwohci_start(sc, dbch); 1206170374Ssimokawa FW_GUNLOCK(fc); 1207103285Sikob } 1208103285Sikob splx(s); 1209103285Sikob} 1210106790Ssimokawa 1211106790Ssimokawastatic void 1212106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1213103285Sikob{ 1214103285Sikob struct fwohcidb_tr *db_tr; 1215113584Ssimokawa int idb; 1216103285Sikob 1217108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1218108527Ssimokawa return; 1219108527Ssimokawa 1220113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1221103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1222113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1223113584Ssimokawa db_tr->buf != NULL) { 1224113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1225113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1226113584Ssimokawa db_tr->buf = NULL; 1227113584Ssimokawa } else if (db_tr->dma_map != NULL) 1228113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1229103285Sikob } 1230103285Sikob dbch->ndb = 0; 1231103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1232113584Ssimokawa fwdma_free_multiseg(dbch->am); 1233110195Ssimokawa free(db_tr, M_FW); 1234103285Sikob STAILQ_INIT(&dbch->db_trq); 1235108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1236103285Sikob} 1237106790Ssimokawa 1238106790Ssimokawastatic void 1239113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1240103285Sikob{ 1241103285Sikob int idb; 1242103285Sikob struct fwohcidb_tr *db_tr; 1243108642Ssimokawa 1244108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1245108642Ssimokawa goto out; 1246108642Ssimokawa 1247113584Ssimokawa /* create dma_tag for buffers */ 1248113584Ssimokawa#define MAX_REQCOUNT 0xffff 1249113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1250113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1251113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1252113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1253113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1254113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1255113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1256113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1257117126Sscottl /*flags*/ 0, 1258127468Ssimokawa#if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1259117126Sscottl /*lockfunc*/busdma_lock_mutex, 1260170374Ssimokawa /*lockarg*/FW_GMTX(&sc->fc), 1261117228Ssimokawa#endif 1262117228Ssimokawa &dbch->dmat)) 1263113584Ssimokawa return; 1264113584Ssimokawa 1265103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1266103285Sikob /* DB entry must start at 16 bytes bounary. */ 1267103285Sikob STAILQ_INIT(&dbch->db_trq); 1268103285Sikob db_tr = (struct fwohcidb_tr *) 1269103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1270113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1271103285Sikob if(db_tr == NULL){ 1272109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1273103285Sikob return; 1274103285Sikob } 1275109379Ssimokawa 1276113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1277113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1278113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1279113584Ssimokawa if (dbch->am == NULL) { 1280113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1281124836Ssimokawa free(db_tr, M_FW); 1282103285Sikob return; 1283103285Sikob } 1284103285Sikob /* Attach DB to DMA ch. */ 1285103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1286103285Sikob db_tr->dbcnt = 0; 1287113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1288113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1289113584Ssimokawa /* create dmamap for buffers */ 1290113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1291113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1292113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1293113584Ssimokawa printf("bus_dmamap_create failed\n"); 1294113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1295113584Ssimokawa fwohci_db_free(dbch); 1296113584Ssimokawa return; 1297113584Ssimokawa } 1298103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1299113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1300108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1301108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1302108530Ssimokawa ].start = (caddr_t)db_tr; 1303108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1304108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1305108530Ssimokawa ].end = (caddr_t)db_tr; 1306103285Sikob } 1307103285Sikob db_tr++; 1308103285Sikob } 1309103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1310103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1311108642Ssimokawaout: 1312108642Ssimokawa dbch->xferq.queued = 0; 1313108642Ssimokawa dbch->pdb_tr = NULL; 1314103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1315103285Sikob dbch->bottom = dbch->top; 1316108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1317103285Sikob} 1318106790Ssimokawa 1319106790Ssimokawastatic int 1320106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1321103285Sikob{ 1322103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1323109890Ssimokawa 1324113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1325113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1326103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1327103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1328109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1329167086Sjhb pause("fwitxd", hz); 1330103285Sikob fwohci_db_free(&sc->it[dmach]); 1331103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1332103285Sikob return 0; 1333103285Sikob} 1334106790Ssimokawa 1335106790Ssimokawastatic int 1336106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1337103285Sikob{ 1338103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1339103285Sikob 1340103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1341103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1342103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1343109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1344167086Sjhb pause("fwirxd", hz); 1345103285Sikob fwohci_db_free(&sc->ir[dmach]); 1346103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1347103285Sikob return 0; 1348103285Sikob} 1349106790Ssimokawa 1350113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1351106790Ssimokawastatic void 1352129585Sdfrfwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1353103285Sikob{ 1354113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1355103285Sikob return; 1356103285Sikob} 1357103285Sikob#endif 1358103285Sikob 1359106790Ssimokawastatic int 1360106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1361103285Sikob{ 1362103285Sikob int err = 0; 1363113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1364129585Sdfr uint32_t off = 0; 1365103285Sikob struct fwohcidb_tr *db_tr; 1366120660Ssimokawa struct fwohcidb *db; 1367103285Sikob 1368103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1369103285Sikob err = EINVAL; 1370103285Sikob return err; 1371103285Sikob } 1372103285Sikob z = dbch->ndesc; 1373103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1374103285Sikob if( &sc->it[dmach] == dbch){ 1375103285Sikob off = OHCI_ITOFF(dmach); 1376103285Sikob break; 1377103285Sikob } 1378103285Sikob } 1379123740Speter if(off == 0){ 1380103285Sikob err = EINVAL; 1381103285Sikob return err; 1382103285Sikob } 1383103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1384103285Sikob return err; 1385103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1386103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1387103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1388103285Sikob } 1389103285Sikob db_tr = dbch->top; 1390113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1391113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1392103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1393103285Sikob break; 1394103285Sikob } 1395109892Ssimokawa db = db_tr->db; 1396113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1397113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1398113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1399113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1400103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1401103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1402113584Ssimokawa FWOHCI_DMA_SET( 1403113584Ssimokawa db[ldesc].db.desc.cmd, 1404113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1405109280Ssimokawa /* OHCI 1.1 and above */ 1406113584Ssimokawa FWOHCI_DMA_SET( 1407113584Ssimokawa db[0].db.desc.cmd, 1408113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1409103285Sikob } 1410103285Sikob } 1411103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1412103285Sikob } 1413113584Ssimokawa FWOHCI_DMA_CLEAR( 1414113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1415103285Sikob return err; 1416103285Sikob} 1417106790Ssimokawa 1418106790Ssimokawastatic int 1419106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1420103285Sikob{ 1421103285Sikob int err = 0; 1422109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1423129585Sdfr uint32_t off = 0; 1424103285Sikob struct fwohcidb_tr *db_tr; 1425120660Ssimokawa struct fwohcidb *db; 1426103285Sikob 1427103285Sikob z = dbch->ndesc; 1428103285Sikob if(&sc->arrq == dbch){ 1429103285Sikob off = OHCI_ARQOFF; 1430103285Sikob }else if(&sc->arrs == dbch){ 1431103285Sikob off = OHCI_ARSOFF; 1432103285Sikob }else{ 1433103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1434103285Sikob if( &sc->ir[dmach] == dbch){ 1435103285Sikob off = OHCI_IROFF(dmach); 1436103285Sikob break; 1437103285Sikob } 1438103285Sikob } 1439103285Sikob } 1440123740Speter if(off == 0){ 1441103285Sikob err = EINVAL; 1442103285Sikob return err; 1443103285Sikob } 1444103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1445103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1446103285Sikob return err; 1447103285Sikob }else{ 1448103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1449103285Sikob err = EBUSY; 1450103285Sikob return err; 1451103285Sikob } 1452103285Sikob } 1453103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1454108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1455103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1456103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1457103285Sikob } 1458103285Sikob db_tr = dbch->top; 1459113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1460113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1461113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1462103285Sikob break; 1463109892Ssimokawa db = db_tr->db; 1464109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1465113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1466113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1467103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1468103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1469113584Ssimokawa FWOHCI_DMA_SET( 1470113584Ssimokawa db[ldesc].db.desc.cmd, 1471113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1472113584Ssimokawa FWOHCI_DMA_CLEAR( 1473113584Ssimokawa db[ldesc].db.desc.depend, 1474113584Ssimokawa 0xf); 1475103285Sikob } 1476103285Sikob } 1477103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1478103285Sikob } 1479113584Ssimokawa FWOHCI_DMA_CLEAR( 1480113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1481103285Sikob dbch->buf_offset = 0; 1482113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1483113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1484103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1485103285Sikob return err; 1486103285Sikob }else{ 1487113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1488103285Sikob } 1489103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1490103285Sikob return err; 1491103285Sikob} 1492106790Ssimokawa 1493106790Ssimokawastatic int 1494113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1495109890Ssimokawa{ 1496109890Ssimokawa int sec, cycle, cycle_match; 1497109890Ssimokawa 1498109890Ssimokawa cycle = cycle_now & 0x1fff; 1499109890Ssimokawa sec = cycle_now >> 13; 1500109890Ssimokawa#define CYCLE_MOD 0x10 1501113584Ssimokawa#if 1 1502109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1503113584Ssimokawa#else 1504113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1505113584Ssimokawa#endif 1506109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1507109890Ssimokawa if (cycle >= 8000) { 1508109890Ssimokawa sec ++; 1509109890Ssimokawa cycle -= 8000; 1510109890Ssimokawa } 1511113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1512109890Ssimokawa if (cycle >= 8000) { 1513109890Ssimokawa sec ++; 1514109890Ssimokawa if (cycle == 8000) 1515109890Ssimokawa cycle = 0; 1516109890Ssimokawa else 1517109890Ssimokawa cycle = CYCLE_MOD; 1518109890Ssimokawa } 1519109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1520109890Ssimokawa 1521109890Ssimokawa return(cycle_match); 1522109890Ssimokawa} 1523109890Ssimokawa 1524109890Ssimokawastatic int 1525106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1526103285Sikob{ 1527103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1528103285Sikob int err = 0; 1529103285Sikob unsigned short tag, ich; 1530103285Sikob struct fwohci_dbch *dbch; 1531109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1532129585Sdfr uint32_t stat; 1533109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1534109890Ssimokawa struct fw_xferq *it; 1535103285Sikob 1536103285Sikob dbch = &sc->it[dmach]; 1537109890Ssimokawa it = &dbch->xferq; 1538109890Ssimokawa 1539109890Ssimokawa tag = (it->flag >> 6) & 3; 1540109890Ssimokawa ich = it->flag & 0x3f; 1541109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1542109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1543103285Sikob dbch->ndesc = 3; 1544113584Ssimokawa fwohci_db_init(sc, dbch); 1545109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1546109179Ssimokawa return ENOMEM; 1547170374Ssimokawa 1548103285Sikob err = fwohci_tx_enable(sc, dbch); 1549103285Sikob } 1550103285Sikob if(err) 1551103285Sikob return err; 1552109890Ssimokawa 1553109892Ssimokawa ldesc = dbch->ndesc - 1; 1554109890Ssimokawa s = splfw(); 1555170374Ssimokawa FW_GLOCK(fc); 1556109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1557109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1558120660Ssimokawa struct fwohcidb *db; 1559109890Ssimokawa 1560113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1561113584Ssimokawa BUS_DMASYNC_PREWRITE); 1562109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1563109890Ssimokawa if (prev != NULL) { 1564109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1565113584Ssimokawa#if 0 /* XXX necessary? */ 1566113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1567113584Ssimokawa OHCI_BRANCH_ALWAYS); 1568113584Ssimokawa#endif 1569109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1570109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1571113584Ssimokawa ((struct fwohcidb_tr *) 1572113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1573109892Ssimokawa#else 1574113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1575113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1576109892Ssimokawa#endif 1577103285Sikob } 1578109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1579109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1580109890Ssimokawa prev = chunk; 1581109403Ssimokawa } 1582170374Ssimokawa FW_GUNLOCK(fc); 1583113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1584113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1585109890Ssimokawa splx(s); 1586109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1587113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1588113584Ssimokawa printf("stat 0x%x\n", stat); 1589113584Ssimokawa 1590109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1591109890Ssimokawa return 0; 1592109890Ssimokawa 1593113584Ssimokawa#if 0 1594109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1595113584Ssimokawa#endif 1596109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1597109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1598109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1599113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1600109890Ssimokawa 1601109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1602113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1603113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1604167629Ssimokawa if (firewire_debug > 1) { 1605109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1606113584Ssimokawa#if 1 1607113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1608113584Ssimokawa#endif 1609113584Ssimokawa } 1610109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1611109890Ssimokawa#if 1 1612109890Ssimokawa /* Don't start until all chunks are buffered */ 1613109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1614109890Ssimokawa goto out; 1615109890Ssimokawa#endif 1616113584Ssimokawa#if 1 1617109890Ssimokawa /* Clear cycle match counter bits */ 1618109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1619109890Ssimokawa 1620109356Ssimokawa /* 2bit second + 13bit cycle */ 1621109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1622113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1623109890Ssimokawa 1624109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1625109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1626109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1627113584Ssimokawa#else 1628113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1629113584Ssimokawa#endif 1630167629Ssimokawa if (firewire_debug > 1) { 1631109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1632109403Ssimokawa cycle_now, cycle_match); 1633113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1634113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1635113584Ssimokawa } 1636109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1637109890Ssimokawa device_printf(sc->fc.dev, 1638109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1639113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1640103285Sikob } 1641109890Ssimokawaout: 1642103285Sikob return err; 1643103285Sikob} 1644106790Ssimokawa 1645106790Ssimokawastatic int 1646113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1647103285Sikob{ 1648103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1649109890Ssimokawa int err = 0, s, ldesc; 1650103285Sikob unsigned short tag, ich; 1651129585Sdfr uint32_t stat; 1652109890Ssimokawa struct fwohci_dbch *dbch; 1653113584Ssimokawa struct fwohcidb_tr *db_tr; 1654109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1655109890Ssimokawa struct fw_xferq *ir; 1656103285Sikob 1657109890Ssimokawa dbch = &sc->ir[dmach]; 1658109890Ssimokawa ir = &dbch->xferq; 1659109890Ssimokawa 1660109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1661109890Ssimokawa tag = (ir->flag >> 6) & 3; 1662109890Ssimokawa ich = ir->flag & 0x3f; 1663108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1664108995Ssimokawa 1665109890Ssimokawa ir->queued = 0; 1666109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1667109890Ssimokawa dbch->ndesc = 2; 1668113584Ssimokawa fwohci_db_init(sc, dbch); 1669109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1670109179Ssimokawa return ENOMEM; 1671109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1672103285Sikob } 1673103285Sikob if(err) 1674103285Sikob return err; 1675103285Sikob 1676109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1677109890Ssimokawa if (first == NULL) { 1678109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1679109890Ssimokawa return 0; 1680109890Ssimokawa } 1681109890Ssimokawa 1682111892Ssimokawa ldesc = dbch->ndesc - 1; 1683111892Ssimokawa s = splfw(); 1684170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 1685170374Ssimokawa FW_GLOCK(fc); 1686109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1687109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1688120660Ssimokawa struct fwohcidb *db; 1689109890Ssimokawa 1690111942Ssimokawa#if 1 /* XXX for if_fwe */ 1691113584Ssimokawa if (chunk->mbuf != NULL) { 1692113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1693113584Ssimokawa db_tr->dbcnt = 1; 1694113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1695113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1696113584Ssimokawa /* flags */0); 1697113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1698113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1699113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1700113584Ssimokawa } 1701111942Ssimokawa#endif 1702109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1703113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1704113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1705109890Ssimokawa if (prev != NULL) { 1706109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1707113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1708103285Sikob } 1709109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1710109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1711109890Ssimokawa prev = chunk; 1712103285Sikob } 1713170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 1714170374Ssimokawa FW_GUNLOCK(fc); 1715113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1716113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1717109890Ssimokawa splx(s); 1718109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1719109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1720109890Ssimokawa return 0; 1721109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1722109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1723109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1724109890Ssimokawa } 1725109890Ssimokawa 1726113584Ssimokawa if (firewire_debug) 1727113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1728109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1729109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1730109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1731109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1732109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1733109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1734113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1735109890Ssimokawa | dbch->ndesc); 1736109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1737109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1738113584Ssimokawa#if 0 1739113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1740113584Ssimokawa#endif 1741103285Sikob return err; 1742103285Sikob} 1743106790Ssimokawa 1744106790Ssimokawaint 1745110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1746103285Sikob{ 1747103285Sikob u_int i; 1748103285Sikob 1749178911Ssimokawa fwohci_set_intr(&sc->fc, 0); 1750178911Ssimokawa 1751103285Sikob/* Now stopping all DMA channel */ 1752103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1753103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1754103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1755103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1756103285Sikob 1757103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1758103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1759103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1760103285Sikob } 1761103285Sikob 1762170374Ssimokawa#if 0 /* Let dcons(4) be accessed */ 1763103285Sikob/* Stop interrupt */ 1764103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1765103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1766103285Sikob | OHCI_INT_PHY_INT 1767103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1768103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1769103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1770103285Sikob | OHCI_INT_PHY_BUS_R); 1771116978Ssimokawa 1772170374Ssimokawa/* FLUSH FIFO and reset Transmitter/Reciever */ 1773170374Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1774170374Ssimokawa#endif 1775116978Ssimokawa 1776108642Ssimokawa/* XXX Link down? Bus reset? */ 1777103285Sikob return 0; 1778103285Sikob} 1779103285Sikob 1780108642Ssimokawaint 1781108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1782108642Ssimokawa{ 1783108642Ssimokawa int i; 1784116978Ssimokawa struct fw_xferq *ir; 1785116978Ssimokawa struct fw_bulkxfer *chunk; 1786108642Ssimokawa 1787108642Ssimokawa fwohci_reset(sc, dev); 1788129541Sdfr /* XXX resume isochronous receive automatically. (how about TX?) */ 1789108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1790116978Ssimokawa ir = &sc->ir[i].xferq; 1791116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1792108642Ssimokawa device_printf(sc->fc.dev, 1793108642Ssimokawa "resume iso receive ch: %d\n", i); 1794116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1795116978Ssimokawa /* requeue stdma to stfree */ 1796116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1797116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1798116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1799116978Ssimokawa } 1800108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1801108642Ssimokawa } 1802108642Ssimokawa } 1803108642Ssimokawa 1804108642Ssimokawa bus_generic_resume(dev); 1805108642Ssimokawa sc->fc.ibr(&sc->fc); 1806108642Ssimokawa return 0; 1807108642Ssimokawa} 1808108642Ssimokawa 1809170374Ssimokawa#ifdef OHCI_DEBUG 1810103285Sikobstatic void 1811170374Ssimokawafwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat) 1812103285Sikob{ 1813103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1814103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1815103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1816103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1817103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1818103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1819103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1820103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1821103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1822103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1823103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1824103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1825103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1826103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1827103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1828103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1829103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1830103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1831103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1832103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1833103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1834103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1835103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1836103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1837103285Sikob ); 1838170374Ssimokawa} 1839103285Sikob#endif 1840170374Ssimokawastatic void 1841170374Ssimokawafwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count) 1842170374Ssimokawa{ 1843170374Ssimokawa struct firewire_comm *fc = (struct firewire_comm *)sc; 1844170374Ssimokawa uint32_t node_id, plen; 1845170374Ssimokawa 1846187993Ssbruno FW_GLOCK_ASSERT(fc); 1847170374Ssimokawa if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) { 1848170374Ssimokawa fc->status = FWBUSRESET; 1849111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1850111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1851111074Ssimokawa 1852188509Ssbruno device_printf(fc->dev, "%s: BUS reset\n", __func__); 1853103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1854103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1855103285Sikob 1856103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1857103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1858103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1859103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1860103285Sikob 1861170374Ssimokawa if (!kdb_active) 1862170374Ssimokawa taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset); 1863170374Ssimokawa } 1864170374Ssimokawa if (stat & OHCI_INT_PHY_SID) { 1865170374Ssimokawa /* Enable bus reset interrupt */ 1866103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1867170374Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1868170374Ssimokawa 1869170374Ssimokawa /* Allow async. request to us */ 1870170374Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1871170400Ssimokawa if (firewire_phydma_enable) { 1872170400Ssimokawa /* allow from all nodes */ 1873170400Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1874170400Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1875170400Ssimokawa /* 0 to 4GB region */ 1876170400Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1877170400Ssimokawa } 1878170374Ssimokawa /* Set ATRetries register */ 1879170374Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1880170374Ssimokawa 1881170374Ssimokawa /* 1882170374Ssimokawa * Checking whether the node is root or not. If root, turn on 1883170374Ssimokawa * cycle master. 1884170374Ssimokawa */ 1885170374Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1886170374Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1887170374Ssimokawa 1888170374Ssimokawa fc->nodeid = node_id & 0x3f; 1889188509Ssbruno device_printf(fc->dev, "%s: node_id=0x%08x, SelfID Count=%d, ", 1890188509Ssbruno __func__, fc->nodeid, (plen >> 16) & 0xff); 1891170374Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1892188509Ssbruno device_printf(fc->dev, "%s: Bus reset failure\n", 1893188509Ssbruno __func__); 1894170374Ssimokawa goto sidout; 1895170374Ssimokawa } 1896170374Ssimokawa 1897170374Ssimokawa /* cycle timer */ 1898170374Ssimokawa sc->cycle_lost = 0; 1899170374Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 1900170374Ssimokawa if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 1901170374Ssimokawa printf("CYCLEMASTER mode\n"); 1902170374Ssimokawa OWRITE(sc, OHCI_LNKCTL, 1903170374Ssimokawa OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1904170374Ssimokawa } else { 1905170374Ssimokawa printf("non CYCLEMASTER mode\n"); 1906170374Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1907170374Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1908170374Ssimokawa } 1909170374Ssimokawa 1910170374Ssimokawa fc->status = FWBUSINIT; 1911170374Ssimokawa 1912170374Ssimokawa if (!kdb_active) 1913170374Ssimokawa taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid); 1914103285Sikob } 1915170374Ssimokawasidout: 1916170374Ssimokawa if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active)) 1917170374Ssimokawa taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma); 1918170374Ssimokawa} 1919170374Ssimokawa 1920170374Ssimokawastatic void 1921170374Ssimokawafwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count) 1922170374Ssimokawa{ 1923170374Ssimokawa uint32_t irstat, itstat; 1924170374Ssimokawa u_int i; 1925170374Ssimokawa struct firewire_comm *fc = (struct firewire_comm *)sc; 1926170374Ssimokawa 1927170374Ssimokawa if (stat & OHCI_INT_DMA_IR) { 1928127468Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1929103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1930109644Ssimokawa struct fwohci_dbch *dbch; 1931109644Ssimokawa 1932103285Sikob if((irstat & (1 << i)) != 0){ 1933109644Ssimokawa dbch = &sc->ir[i]; 1934109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1935109644Ssimokawa device_printf(sc->fc.dev, 1936109644Ssimokawa "dma(%d) not active\n", i); 1937109644Ssimokawa continue; 1938109644Ssimokawa } 1939113584Ssimokawa fwohci_rbuf_update(sc, i); 1940103285Sikob } 1941103285Sikob } 1942103285Sikob } 1943170374Ssimokawa if (stat & OHCI_INT_DMA_IT) { 1944127468Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1945103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1946103285Sikob if((itstat & (1 << i)) != 0){ 1947103285Sikob fwohci_tbuf_update(sc, i); 1948103285Sikob } 1949103285Sikob } 1950103285Sikob } 1951170374Ssimokawa if (stat & OHCI_INT_DMA_PRRS) { 1952103285Sikob#if 0 1953103285Sikob dump_dma(sc, ARRS_CH); 1954103285Sikob dump_db(sc, ARRS_CH); 1955103285Sikob#endif 1956106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1957103285Sikob } 1958170374Ssimokawa if (stat & OHCI_INT_DMA_PRRQ) { 1959103285Sikob#if 0 1960103285Sikob dump_dma(sc, ARRQ_CH); 1961103285Sikob dump_db(sc, ARRQ_CH); 1962103285Sikob#endif 1963106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1964103285Sikob } 1965167628Ssimokawa if (stat & OHCI_INT_CYC_LOST) { 1966167628Ssimokawa if (sc->cycle_lost >= 0) 1967167628Ssimokawa sc->cycle_lost ++; 1968167628Ssimokawa if (sc->cycle_lost > 10) { 1969167628Ssimokawa sc->cycle_lost = -1; 1970167628Ssimokawa#if 0 1971167628Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1972167628Ssimokawa#endif 1973167628Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1974214021Sbrucec device_printf(fc->dev, "too many cycles lost, " 1975214021Sbrucec "no cycle master present?\n"); 1976167628Ssimokawa } 1977167628Ssimokawa } 1978170374Ssimokawa if (stat & OHCI_INT_DMA_ATRQ) { 1979103285Sikob fwohci_txd(sc, &(sc->atrq)); 1980103285Sikob } 1981170374Ssimokawa if (stat & OHCI_INT_DMA_ATRS) { 1982103285Sikob fwohci_txd(sc, &(sc->atrs)); 1983103285Sikob } 1984170374Ssimokawa if (stat & OHCI_INT_PW_ERR) { 1985103285Sikob device_printf(fc->dev, "posted write error\n"); 1986103285Sikob } 1987170374Ssimokawa if (stat & OHCI_INT_ERR) { 1988103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1989103285Sikob } 1990170374Ssimokawa if (stat & OHCI_INT_PHY_INT) { 1991103285Sikob device_printf(fc->dev, "phy int\n"); 1992103285Sikob } 1993103285Sikob 1994103285Sikob return; 1995103285Sikob} 1996103285Sikob 1997113584Ssimokawastatic void 1998170374Ssimokawafwohci_task_busreset(void *arg, int pending) 1999113584Ssimokawa{ 2000113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2001170374Ssimokawa 2002187993Ssbruno FW_GLOCK(&sc->fc); 2003170374Ssimokawa fw_busreset(&sc->fc, FWBUSRESET); 2004170374Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2005170374Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2006187993Ssbruno FW_GUNLOCK(&sc->fc); 2007170374Ssimokawa} 2008170374Ssimokawa 2009170374Ssimokawastatic void 2010170374Ssimokawafwohci_task_sid(void *arg, int pending) 2011170374Ssimokawa{ 2012170374Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2013170374Ssimokawa struct firewire_comm *fc = &sc->fc; 2014170374Ssimokawa uint32_t *buf; 2015170374Ssimokawa int i, plen; 2016170374Ssimokawa 2017170374Ssimokawa 2018187993Ssbruno /* 2019187993Ssbruno * We really should have locking 2020187993Ssbruno * here. Not sure why it's not 2021187993Ssbruno */ 2022170374Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 2023170374Ssimokawa 2024170374Ssimokawa if (plen & OHCI_SID_ERR) { 2025170374Ssimokawa device_printf(fc->dev, "SID Error\n"); 2026170374Ssimokawa return; 2027170374Ssimokawa } 2028170374Ssimokawa plen &= OHCI_SID_CNT_MASK; 2029170374Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 2030170374Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 2031170374Ssimokawa return; 2032170374Ssimokawa } 2033170374Ssimokawa plen -= 4; /* chop control info */ 2034170374Ssimokawa buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2035170374Ssimokawa if (buf == NULL) { 2036170374Ssimokawa device_printf(fc->dev, "malloc failed\n"); 2037170374Ssimokawa return; 2038170374Ssimokawa } 2039170374Ssimokawa for (i = 0; i < plen / 4; i ++) 2040170374Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2041187993Ssbruno 2042170374Ssimokawa /* pending all pre-bus_reset packets */ 2043170374Ssimokawa fwohci_txd(sc, &sc->atrq); 2044170374Ssimokawa fwohci_txd(sc, &sc->atrs); 2045170374Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 2046170374Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 2047170374Ssimokawa fw_drain_txq(fc); 2048170374Ssimokawa fw_sidrcv(fc, buf, plen); 2049170374Ssimokawa free(buf, M_FW); 2050170374Ssimokawa} 2051170374Ssimokawa 2052170374Ssimokawastatic void 2053170374Ssimokawafwohci_task_dma(void *arg, int pending) 2054170374Ssimokawa{ 2055170374Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2056129585Sdfr uint32_t stat; 2057113584Ssimokawa 2058113584Ssimokawaagain: 2059113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 2060113584Ssimokawa if (stat) 2061170374Ssimokawa fwohci_intr_dma(sc, stat, -1); 2062113584Ssimokawa else 2063113584Ssimokawa return; 2064113584Ssimokawa goto again; 2065113584Ssimokawa} 2066113584Ssimokawa 2067170374Ssimokawastatic int 2068170374Ssimokawafwohci_check_stat(struct fwohci_softc *sc) 2069113584Ssimokawa{ 2070129585Sdfr uint32_t stat, irstat, itstat; 2071113584Ssimokawa 2072187993Ssbruno FW_GLOCK_ASSERT(&sc->fc); 2073113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 2074113584Ssimokawa if (stat == 0xffffffff) { 2075113584Ssimokawa device_printf(sc->fc.dev, 2076113584Ssimokawa "device physically ejected?\n"); 2077170374Ssimokawa return (FILTER_STRAY); 2078113584Ssimokawa } 2079113584Ssimokawa if (stat) 2080170374Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R); 2081170374Ssimokawa 2082170374Ssimokawa stat &= sc->intmask; 2083170374Ssimokawa if (stat == 0) 2084170374Ssimokawa return (FILTER_STRAY); 2085170374Ssimokawa 2086170374Ssimokawa atomic_set_int(&sc->intstat, stat); 2087113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2088113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2089113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2090113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2091113584Ssimokawa } 2092113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2093113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2094113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2095113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2096113584Ssimokawa } 2097170374Ssimokawa 2098170374Ssimokawa fwohci_intr_core(sc, stat, -1); 2099170374Ssimokawa return (FILTER_HANDLED); 2100113584Ssimokawa} 2101113584Ssimokawa 2102187993Ssbrunovoid 2103187993Ssbrunofwohci_intr(void *arg) 2104103285Sikob{ 2105103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2106103285Sikob 2107187993Ssbruno FW_GLOCK(&sc->fc); 2108187993Ssbruno fwohci_check_stat(sc); 2109187993Ssbruno FW_GUNLOCK(&sc->fc); 2110170374Ssimokawa} 2111103285Sikob 2112170374Ssimokawavoid 2113103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2114103285Sikob{ 2115170374Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2116187993Ssbruno 2117187993Ssbruno FW_GLOCK(fc); 2118170374Ssimokawa fwohci_check_stat(sc); 2119187993Ssbruno FW_GUNLOCK(fc); 2120103285Sikob} 2121103285Sikob 2122103285Sikobstatic void 2123103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2124103285Sikob{ 2125103285Sikob struct fwohci_softc *sc; 2126103285Sikob 2127103285Sikob sc = (struct fwohci_softc *)fc; 2128132432Ssimokawa if (firewire_debug) 2129108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2130103285Sikob if (enable) { 2131103285Sikob sc->intmask |= OHCI_INT_EN; 2132103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2133103285Sikob } else { 2134103285Sikob sc->intmask &= ~OHCI_INT_EN; 2135103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2136103285Sikob } 2137103285Sikob} 2138103285Sikob 2139106790Ssimokawastatic void 2140106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2141103285Sikob{ 2142103285Sikob struct firewire_comm *fc = &sc->fc; 2143120660Ssimokawa struct fwohcidb *db; 2144109890Ssimokawa struct fw_bulkxfer *chunk; 2145109890Ssimokawa struct fw_xferq *it; 2146129585Sdfr uint32_t stat, count; 2147113584Ssimokawa int s, w=0, ldesc; 2148103285Sikob 2149109890Ssimokawa it = fc->it[dmach]; 2150113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2151109890Ssimokawa s = splfw(); /* unnecessary ? */ 2152170374Ssimokawa FW_GLOCK(fc); 2153113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2154119155Ssimokawa if (firewire_debug) 2155119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2156109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2157109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2158113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2159113584Ssimokawa >> OHCI_STATUS_SHIFT; 2160109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2161119155Ssimokawa /* timestamp */ 2162113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2163113584Ssimokawa & OHCI_COUNT_MASK; 2164109890Ssimokawa if (stat == 0) 2165109890Ssimokawa break; 2166109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2167109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2168109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2169109890Ssimokawa#if 0 2170109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2171109179Ssimokawa#endif 2172109890Ssimokawa break; 2173109890Ssimokawa default: 2174109423Ssimokawa device_printf(fc->dev, 2175113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2176113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2177109890Ssimokawa } 2178109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2179109890Ssimokawa w++; 2180109403Ssimokawa } 2181170374Ssimokawa FW_GUNLOCK(fc); 2182109890Ssimokawa splx(s); 2183109890Ssimokawa if (w) 2184109890Ssimokawa wakeup(it); 2185103285Sikob} 2186106790Ssimokawa 2187106790Ssimokawastatic void 2188106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2189103285Sikob{ 2190109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2191120660Ssimokawa struct fwohcidb_tr *db_tr; 2192109890Ssimokawa struct fw_bulkxfer *chunk; 2193109890Ssimokawa struct fw_xferq *ir; 2194129585Sdfr uint32_t stat; 2195170374Ssimokawa int s, w = 0, ldesc; 2196109179Ssimokawa 2197109890Ssimokawa ir = fc->ir[dmach]; 2198113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2199170374Ssimokawa 2200113584Ssimokawa#if 0 2201113584Ssimokawa dump_db(sc, dmach); 2202113584Ssimokawa#endif 2203109890Ssimokawa s = splfw(); 2204170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 2205170374Ssimokawa FW_GLOCK(fc); 2206113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2207109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2208113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2209113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2210113584Ssimokawa >> OHCI_STATUS_SHIFT; 2211109890Ssimokawa if (stat == 0) 2212109890Ssimokawa break; 2213113584Ssimokawa 2214113584Ssimokawa if (chunk->mbuf != NULL) { 2215113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2216113584Ssimokawa BUS_DMASYNC_POSTREAD); 2217113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2218113584Ssimokawa } else if (ir->buf != NULL) { 2219113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2220113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2221113584Ssimokawa } else { 2222113584Ssimokawa /* XXX */ 2223113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2224113584Ssimokawa } 2225113584Ssimokawa 2226109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2227109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2228109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2229109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2230111942Ssimokawa chunk->resp = 0; 2231109890Ssimokawa break; 2232109890Ssimokawa default: 2233111942Ssimokawa chunk->resp = EINVAL; 2234109890Ssimokawa device_printf(fc->dev, 2235113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2236113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2237109890Ssimokawa } 2238109890Ssimokawa w++; 2239103285Sikob } 2240170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 2241170374Ssimokawa FW_GUNLOCK(fc); 2242109890Ssimokawa splx(s); 2243170374Ssimokawa if (w == 0) 2244170374Ssimokawa return; 2245170374Ssimokawa 2246170374Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2247170374Ssimokawa ir->hand(ir); 2248170374Ssimokawa else 2249170374Ssimokawa wakeup(ir); 2250103285Sikob} 2251106790Ssimokawa 2252106790Ssimokawavoid 2253129585Sdfrdump_dma(struct fwohci_softc *sc, uint32_t ch) 2254106790Ssimokawa{ 2255129585Sdfr uint32_t off, cntl, stat, cmd, match; 2256103285Sikob 2257103285Sikob if(ch == 0){ 2258103285Sikob off = OHCI_ATQOFF; 2259103285Sikob }else if(ch == 1){ 2260103285Sikob off = OHCI_ATSOFF; 2261103285Sikob }else if(ch == 2){ 2262103285Sikob off = OHCI_ARQOFF; 2263103285Sikob }else if(ch == 3){ 2264103285Sikob off = OHCI_ARSOFF; 2265103285Sikob }else if(ch < IRX_CH){ 2266103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2267103285Sikob }else{ 2268103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2269103285Sikob } 2270103285Sikob cntl = stat = OREAD(sc, off); 2271103285Sikob cmd = OREAD(sc, off + 0xc); 2272103285Sikob match = OREAD(sc, off + 0x10); 2273103285Sikob 2274113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2275103285Sikob ch, 2276103285Sikob cntl, 2277103285Sikob cmd, 2278103285Sikob match); 2279103285Sikob stat &= 0xffff ; 2280113584Ssimokawa if (stat) { 2281103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2282103285Sikob ch, 2283103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2284103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2285103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2286103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2287103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2288103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2289103285Sikob fwohcicode[stat & 0x1f], 2290103285Sikob stat & 0x1f 2291103285Sikob ); 2292103285Sikob }else{ 2293103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2294103285Sikob } 2295103285Sikob} 2296106790Ssimokawa 2297106790Ssimokawavoid 2298129585Sdfrdump_db(struct fwohci_softc *sc, uint32_t ch) 2299106790Ssimokawa{ 2300103285Sikob struct fwohci_dbch *dbch; 2301113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2302120660Ssimokawa struct fwohcidb *curr = NULL, *prev, *next = NULL; 2303103285Sikob int idb, jdb; 2304129585Sdfr uint32_t cmd, off; 2305103285Sikob if(ch == 0){ 2306103285Sikob off = OHCI_ATQOFF; 2307103285Sikob dbch = &sc->atrq; 2308103285Sikob }else if(ch == 1){ 2309103285Sikob off = OHCI_ATSOFF; 2310103285Sikob dbch = &sc->atrs; 2311103285Sikob }else if(ch == 2){ 2312103285Sikob off = OHCI_ARQOFF; 2313103285Sikob dbch = &sc->arrq; 2314103285Sikob }else if(ch == 3){ 2315103285Sikob off = OHCI_ARSOFF; 2316103285Sikob dbch = &sc->arrs; 2317103285Sikob }else if(ch < IRX_CH){ 2318103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2319103285Sikob dbch = &sc->it[ch - ITX_CH]; 2320103285Sikob }else { 2321103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2322103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2323103285Sikob } 2324103285Sikob cmd = OREAD(sc, off + 0xc); 2325103285Sikob 2326103285Sikob if( dbch->ndb == 0 ){ 2327103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2328103285Sikob return; 2329103285Sikob } 2330103285Sikob pp = dbch->top; 2331103285Sikob prev = pp->db; 2332103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2333103285Sikob cp = STAILQ_NEXT(pp, link); 2334103285Sikob if(cp == NULL){ 2335103285Sikob curr = NULL; 2336103285Sikob goto outdb; 2337103285Sikob } 2338103285Sikob np = STAILQ_NEXT(cp, link); 2339103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2340113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2341103285Sikob curr = cp->db; 2342103285Sikob if(np != NULL){ 2343103285Sikob next = np->db; 2344103285Sikob }else{ 2345103285Sikob next = NULL; 2346103285Sikob } 2347103285Sikob goto outdb; 2348103285Sikob } 2349103285Sikob } 2350103285Sikob pp = STAILQ_NEXT(pp, link); 2351144263Ssam if(pp == NULL){ 2352144263Ssam curr = NULL; 2353144263Ssam goto outdb; 2354144263Ssam } 2355103285Sikob prev = pp->db; 2356103285Sikob } 2357103285Sikoboutdb: 2358103285Sikob if( curr != NULL){ 2359113584Ssimokawa#if 0 2360103285Sikob printf("Prev DB %d\n", ch); 2361113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2362113584Ssimokawa#endif 2363103285Sikob printf("Current DB %d\n", ch); 2364113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2365113584Ssimokawa#if 0 2366103285Sikob printf("Next DB %d\n", ch); 2367113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2368113584Ssimokawa#endif 2369103285Sikob }else{ 2370103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2371103285Sikob } 2372103285Sikob return; 2373103285Sikob} 2374106790Ssimokawa 2375106790Ssimokawavoid 2376120660Ssimokawaprint_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2377129585Sdfr uint32_t ch, uint32_t max) 2378106790Ssimokawa{ 2379103285Sikob fwohcireg_t stat; 2380103285Sikob int i, key; 2381129585Sdfr uint32_t cmd, res; 2382103285Sikob 2383103285Sikob if(db == NULL){ 2384103285Sikob printf("No Descriptor is found\n"); 2385103285Sikob return; 2386103285Sikob } 2387103285Sikob 2388103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2389103285Sikob ch, 2390103285Sikob "Current", 2391103285Sikob "OP ", 2392103285Sikob "KEY", 2393103285Sikob "INT", 2394103285Sikob "BR ", 2395103285Sikob "len", 2396103285Sikob "Addr", 2397103285Sikob "Depend", 2398103285Sikob "Stat", 2399103285Sikob "Cnt"); 2400103285Sikob for( i = 0 ; i <= max ; i ++){ 2401113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2402113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2403113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2404113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2405127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 2406127468Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2407127468Ssimokawa db_tr->bus_addr, 2408127468Ssimokawa#else 2409113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2410114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2411108712Ssimokawa#endif 2412113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2413113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2414113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2415113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2416113584Ssimokawa cmd & OHCI_COUNT_MASK, 2417113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2418113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2419113584Ssimokawa stat, 2420113584Ssimokawa res & OHCI_COUNT_MASK); 2421103285Sikob if(stat & 0xff00){ 2422103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2423103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2424103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2425103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2426103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2427103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2428103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2429103285Sikob fwohcicode[stat & 0x1f], 2430103285Sikob stat & 0x1f 2431103285Sikob ); 2432103285Sikob }else{ 2433103285Sikob printf(" Nostat\n"); 2434103285Sikob } 2435103285Sikob if(key == OHCI_KEY_ST2 ){ 2436103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2437113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2438113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2439113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2440113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2441103285Sikob } 2442103285Sikob if(key == OHCI_KEY_DEVICE){ 2443103285Sikob return; 2444103285Sikob } 2445113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2446103285Sikob == OHCI_BRANCH_ALWAYS){ 2447103285Sikob return; 2448103285Sikob } 2449113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2450103285Sikob == OHCI_OUTPUT_LAST){ 2451103285Sikob return; 2452103285Sikob } 2453113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2454103285Sikob == OHCI_INPUT_LAST){ 2455103285Sikob return; 2456103285Sikob } 2457103285Sikob if(key == OHCI_KEY_ST2 ){ 2458103285Sikob i++; 2459103285Sikob } 2460103285Sikob } 2461103285Sikob return; 2462103285Sikob} 2463106790Ssimokawa 2464106790Ssimokawavoid 2465106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2466103285Sikob{ 2467103285Sikob struct fwohci_softc *sc; 2468129585Sdfr uint32_t fun; 2469103285Sikob 2470110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2471103285Sikob sc = (struct fwohci_softc *)fc; 2472108276Ssimokawa 2473187993Ssbruno FW_GLOCK(fc); 2474108276Ssimokawa /* 2475129611Sdfr * Make sure our cached values from the config rom are 2476129611Sdfr * initialised. 2477129611Sdfr */ 2478129611Sdfr OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2479129611Sdfr OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2480129611Sdfr 2481129611Sdfr /* 2482108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2483108276Ssimokawa * shouldn't became the root node. 2484108276Ssimokawa */ 2485103285Sikob#if 1 2486103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2487109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2488103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2489109280Ssimokawa#else /* Short bus reset */ 2490103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2491109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2492103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2493103285Sikob#endif 2494187993Ssbruno FW_GUNLOCK(fc); 2495103285Sikob} 2496106790Ssimokawa 2497106790Ssimokawavoid 2498106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2499103285Sikob{ 2500103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2501103285Sikob struct fwohci_dbch *dbch; 2502120660Ssimokawa struct fwohcidb *db; 2503103285Sikob struct fw_pkt *fp; 2504120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 2505103285Sikob unsigned short chtag; 2506103285Sikob int idb; 2507103285Sikob 2508170374Ssimokawa FW_GLOCK_ASSERT(&sc->fc); 2509170374Ssimokawa 2510103285Sikob dbch = &sc->it[dmach]; 2511103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2512103285Sikob 2513103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2514103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2515103285Sikob/* 2516113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2517103285Sikob*/ 2518113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2519109892Ssimokawa db = db_tr->db; 2520103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2521120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2522113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2523119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2524113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2525103285Sikob ohcifp->mode.stream.chtag = chtag; 2526103285Sikob ohcifp->mode.stream.tcode = 0xa; 2527113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2528113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2529113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2530113584Ssimokawa#endif 2531103285Sikob 2532113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2533113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2534113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2535109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2536113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2537103285Sikob | OHCI_UPDATE 2538109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2539109892Ssimokawa db[0].db.desc.depend = 2540109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2541113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2542109892Ssimokawa#else 2543113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2544113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2545109892Ssimokawa#endif 2546103285Sikob bulkxfer->end = (caddr_t)db_tr; 2547103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2548103285Sikob } 2549109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2550113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2551113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2552109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2553109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2554109280Ssimokawa /* OHCI 1.1 and above */ 2555109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2556109892Ssimokawa#endif 2557109892Ssimokawa/* 2558103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2559103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2560113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2561103285Sikob*/ 2562103285Sikob return; 2563103285Sikob} 2564106790Ssimokawa 2565106790Ssimokawastatic int 2566113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2567113584Ssimokawa int poffset) 2568103285Sikob{ 2569120660Ssimokawa struct fwohcidb *db = db_tr->db; 2570113584Ssimokawa struct fw_xferq *it; 2571103285Sikob int err = 0; 2572113584Ssimokawa 2573113584Ssimokawa it = &dbch->xferq; 2574113584Ssimokawa if(it->buf == 0){ 2575103285Sikob err = EINVAL; 2576103285Sikob return err; 2577103285Sikob } 2578113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2579103285Sikob db_tr->dbcnt = 3; 2580103285Sikob 2581113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2582113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2583119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2584120660Ssimokawa bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2585113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2586129585Sdfr fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2587113584Ssimokawa 2588113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2589113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2590109892Ssimokawa#if 1 2591113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2592113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2593109892Ssimokawa#endif 2594113584Ssimokawa return 0; 2595103285Sikob} 2596106790Ssimokawa 2597106790Ssimokawaint 2598113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2599113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2600103285Sikob{ 2601120660Ssimokawa struct fwohcidb *db = db_tr->db; 2602113584Ssimokawa struct fw_xferq *ir; 2603113584Ssimokawa int i, ldesc; 2604113584Ssimokawa bus_addr_t dbuf[2]; 2605103285Sikob int dsiz[2]; 2606103285Sikob 2607113584Ssimokawa ir = &dbch->xferq; 2608113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2609178911Ssimokawa if (db_tr->buf == NULL) { 2610178911Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, 2611178911Ssimokawa &db_tr->dma_map, ir->psize, &dbuf[0], 2612178911Ssimokawa BUS_DMA_NOWAIT); 2613178911Ssimokawa if (db_tr->buf == NULL) 2614178911Ssimokawa return(ENOMEM); 2615178911Ssimokawa } 2616103285Sikob db_tr->dbcnt = 1; 2617113584Ssimokawa dsiz[0] = ir->psize; 2618113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2619113584Ssimokawa BUS_DMASYNC_PREREAD); 2620113584Ssimokawa } else { 2621113584Ssimokawa db_tr->dbcnt = 0; 2622113584Ssimokawa if (dummy_dma != NULL) { 2623129585Sdfr dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2624113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2625113584Ssimokawa } 2626113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2627113584Ssimokawa if (ir->buf != NULL) { 2628113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2629113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2630113584Ssimokawa } 2631113584Ssimokawa db_tr->dbcnt++; 2632103285Sikob } 2633103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2634113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2635113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2636113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2637113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2638103285Sikob } 2639113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2640103285Sikob } 2641113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2642113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2643113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2644103285Sikob } 2645113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2646113584Ssimokawa return 0; 2647103285Sikob} 2648106790Ssimokawa 2649113584Ssimokawa 2650113584Ssimokawastatic int 2651113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2652103285Sikob{ 2653113584Ssimokawa struct fw_pkt *fp0; 2654129585Sdfr uint32_t ld0; 2655120660Ssimokawa int slen, hlen; 2656113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2657113584Ssimokawa int i; 2658113584Ssimokawa#endif 2659103285Sikob 2660113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2661113584Ssimokawa#if 0 2662113584Ssimokawa printf("ld0: x%08x\n", ld0); 2663113584Ssimokawa#endif 2664113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2665120660Ssimokawa /* determine length to swap */ 2666113584Ssimokawa switch (fp0->mode.common.tcode) { 2667113584Ssimokawa case FWTCODE_RREQQ: 2668113584Ssimokawa case FWTCODE_WRES: 2669113584Ssimokawa case FWTCODE_WREQQ: 2670113584Ssimokawa case FWTCODE_RRESQ: 2671113584Ssimokawa case FWOHCITCODE_PHY: 2672113584Ssimokawa slen = 12; 2673113584Ssimokawa break; 2674113584Ssimokawa case FWTCODE_RREQB: 2675113584Ssimokawa case FWTCODE_WREQB: 2676113584Ssimokawa case FWTCODE_LREQ: 2677113584Ssimokawa case FWTCODE_RRESB: 2678113584Ssimokawa case FWTCODE_LRES: 2679113584Ssimokawa slen = 16; 2680113584Ssimokawa break; 2681113584Ssimokawa default: 2682113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2683113584Ssimokawa return(0); 2684103285Sikob } 2685120660Ssimokawa hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2686120660Ssimokawa if (hlen > len) { 2687113584Ssimokawa if (firewire_debug) 2688113584Ssimokawa printf("splitted header\n"); 2689120660Ssimokawa return(-hlen); 2690103285Sikob } 2691113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2692113584Ssimokawa for(i = 0; i < slen/4; i ++) 2693113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2694113584Ssimokawa#endif 2695120660Ssimokawa return(hlen); 2696103285Sikob} 2697103285Sikob 2698103285Sikobstatic int 2699113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2700103285Sikob{ 2701120660Ssimokawa struct tcode_info *info; 2702113584Ssimokawa int r; 2703103285Sikob 2704120660Ssimokawa info = &tinfo[fp->mode.common.tcode]; 2705129585Sdfr r = info->hdr_len + sizeof(uint32_t); 2706120660Ssimokawa if ((info->flag & FWTI_BLOCK_ASY) != 0) 2707129585Sdfr r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2708120660Ssimokawa 2709169132Ssimokawa if (r == sizeof(uint32_t)) { 2710120660Ssimokawa /* XXX */ 2711110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2712110798Ssimokawa fp->mode.common.tcode); 2713169132Ssimokawa return (-1); 2714169132Ssimokawa } 2715120660Ssimokawa 2716110798Ssimokawa if (r > dbch->xferq.psize) { 2717110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2718169132Ssimokawa return (-1); 2719110798Ssimokawa /* panic ? */ 2720110798Ssimokawa } 2721120660Ssimokawa 2722110798Ssimokawa return r; 2723103285Sikob} 2724103285Sikob 2725106790Ssimokawastatic void 2726169132Ssimokawafwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2727169132Ssimokawa struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2728113584Ssimokawa{ 2729120660Ssimokawa struct fwohcidb *db = &db_tr->db[0]; 2730113584Ssimokawa 2731113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2732113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2733113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2734113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2735113584Ssimokawa dbch->bottom = db_tr; 2736169132Ssimokawa 2737169132Ssimokawa if (wake) 2738169132Ssimokawa OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2739113584Ssimokawa} 2740113584Ssimokawa 2741113584Ssimokawastatic void 2742106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2743103285Sikob{ 2744103285Sikob struct fwohcidb_tr *db_tr; 2745113584Ssimokawa struct iovec vec[2]; 2746113584Ssimokawa struct fw_pkt pktbuf; 2747113584Ssimokawa int nvec; 2748103285Sikob struct fw_pkt *fp; 2749129585Sdfr uint8_t *ld; 2750169132Ssimokawa uint32_t stat, off, status, event; 2751103285Sikob u_int spd; 2752113584Ssimokawa int len, plen, hlen, pcnt, offset; 2753103285Sikob int s; 2754103285Sikob caddr_t buf; 2755103285Sikob int resCount; 2756103285Sikob 2757103285Sikob if(&sc->arrq == dbch){ 2758103285Sikob off = OHCI_ARQOFF; 2759103285Sikob }else if(&sc->arrs == dbch){ 2760103285Sikob off = OHCI_ARSOFF; 2761103285Sikob }else{ 2762103285Sikob return; 2763103285Sikob } 2764103285Sikob 2765103285Sikob s = splfw(); 2766103285Sikob db_tr = dbch->top; 2767103285Sikob pcnt = 0; 2768103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2769113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2770113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2771113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2772113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2773169132Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2774113584Ssimokawa#if 0 2775169132Ssimokawa 2776169132Ssimokawa if (off == OHCI_ARQOFF) 2777169132Ssimokawa printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2778169132Ssimokawa db_tr->bus_addr, status, resCount); 2779113584Ssimokawa#endif 2780113584Ssimokawa len = dbch->xferq.psize - resCount; 2781129585Sdfr ld = (uint8_t *)db_tr->buf; 2782113584Ssimokawa if (dbch->pdb_tr == NULL) { 2783113584Ssimokawa len -= dbch->buf_offset; 2784113584Ssimokawa ld += dbch->buf_offset; 2785113584Ssimokawa } 2786113584Ssimokawa if (len > 0) 2787113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2788113584Ssimokawa BUS_DMASYNC_POSTREAD); 2789103285Sikob while (len > 0 ) { 2790106789Ssimokawa if (count >= 0 && count-- == 0) 2791106789Ssimokawa goto out; 2792113584Ssimokawa if(dbch->pdb_tr != NULL){ 2793113584Ssimokawa /* we have a fragment in previous buffer */ 2794113584Ssimokawa int rlen; 2795103285Sikob 2796113584Ssimokawa offset = dbch->buf_offset; 2797113584Ssimokawa if (offset < 0) 2798113584Ssimokawa offset = - offset; 2799113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2800113584Ssimokawa rlen = dbch->xferq.psize - offset; 2801113584Ssimokawa if (firewire_debug) 2802113584Ssimokawa printf("rlen=%d, offset=%d\n", 2803113584Ssimokawa rlen, dbch->buf_offset); 2804113584Ssimokawa if (dbch->buf_offset < 0) { 2805113584Ssimokawa /* splitted in header, pull up */ 2806113584Ssimokawa char *p; 2807113584Ssimokawa 2808113584Ssimokawa p = (char *)&pktbuf; 2809113584Ssimokawa bcopy(buf, p, rlen); 2810113584Ssimokawa p += rlen; 2811113584Ssimokawa /* this must be too long but harmless */ 2812113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2813113584Ssimokawa if (rlen < 0) 2814113584Ssimokawa printf("why rlen < 0\n"); 2815113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2816103285Sikob ld += rlen; 2817103285Sikob len -= rlen; 2818113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2819169132Ssimokawa if (hlen <= 0) { 2820169132Ssimokawa printf("hlen should be positive."); 2821169132Ssimokawa goto err; 2822113584Ssimokawa } 2823113584Ssimokawa offset = sizeof(pktbuf); 2824113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2825113584Ssimokawa vec[0].iov_len = offset; 2826113584Ssimokawa } else { 2827113584Ssimokawa /* splitted in payload */ 2828113584Ssimokawa offset = rlen; 2829113584Ssimokawa vec[0].iov_base = buf; 2830113584Ssimokawa vec[0].iov_len = rlen; 2831103285Sikob } 2832113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2833113584Ssimokawa nvec = 1; 2834113584Ssimokawa } else { 2835113584Ssimokawa /* no fragment in previous buffer */ 2836103285Sikob fp=(struct fw_pkt *)ld; 2837113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2838113584Ssimokawa if (hlen == 0) 2839169132Ssimokawa goto err; 2840113584Ssimokawa if (hlen < 0) { 2841113584Ssimokawa dbch->pdb_tr = db_tr; 2842113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2843113584Ssimokawa /* sanity check */ 2844169132Ssimokawa if (resCount != 0) { 2845169132Ssimokawa printf("resCount=%d hlen=%d\n", 2846169132Ssimokawa resCount, hlen); 2847169132Ssimokawa goto err; 2848169132Ssimokawa } 2849113584Ssimokawa goto out; 2850103285Sikob } 2851113584Ssimokawa offset = 0; 2852113584Ssimokawa nvec = 0; 2853113584Ssimokawa } 2854113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2855113584Ssimokawa if (plen < 0) { 2856113584Ssimokawa /* minimum header size + trailer 2857113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2858120660Ssimokawa printf("plen(%d) is negative! offset=%d\n", 2859120660Ssimokawa plen, offset); 2860169132Ssimokawa goto err; 2861113584Ssimokawa } 2862113584Ssimokawa if (plen > 0) { 2863113584Ssimokawa len -= plen; 2864113584Ssimokawa if (len < 0) { 2865113584Ssimokawa dbch->pdb_tr = db_tr; 2866113584Ssimokawa if (firewire_debug) 2867113584Ssimokawa printf("splitted payload\n"); 2868113584Ssimokawa /* sanity check */ 2869169132Ssimokawa if (resCount != 0) { 2870169132Ssimokawa printf("resCount=%d plen=%d" 2871169132Ssimokawa " len=%d\n", 2872169132Ssimokawa resCount, plen, len); 2873169132Ssimokawa goto err; 2874169132Ssimokawa } 2875113584Ssimokawa goto out; 2876103285Sikob } 2877113584Ssimokawa vec[nvec].iov_base = ld; 2878113584Ssimokawa vec[nvec].iov_len = plen; 2879113584Ssimokawa nvec ++; 2880103285Sikob ld += plen; 2881103285Sikob } 2882129585Sdfr dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2883113584Ssimokawa if (nvec == 0) 2884113584Ssimokawa printf("nvec == 0\n"); 2885113584Ssimokawa 2886103285Sikob/* DMA result-code will be written at the tail of packet */ 2887169132Ssimokawa stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 2888110577Ssimokawa#if 0 2889120660Ssimokawa printf("plen: %d, stat %x\n", 2890120660Ssimokawa plen ,stat); 2891103285Sikob#endif 2892169132Ssimokawa spd = (stat >> 21) & 0x3; 2893169132Ssimokawa event = (stat >> 16) & 0x1f; 2894169132Ssimokawa switch (event) { 2895113584Ssimokawa case FWOHCIEV_ACKPEND: 2896113584Ssimokawa#if 0 2897113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2898113584Ssimokawa#endif 2899113584Ssimokawa /* fall through */ 2900113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2901120660Ssimokawa { 2902120660Ssimokawa struct fw_rcv_buf rb; 2903120660Ssimokawa 2904113584Ssimokawa if ((vec[nvec-1].iov_len -= 2905113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2906113584Ssimokawa nvec--; 2907120660Ssimokawa rb.fc = &sc->fc; 2908120660Ssimokawa rb.vec = vec; 2909120660Ssimokawa rb.nvec = nvec; 2910120660Ssimokawa rb.spd = spd; 2911120660Ssimokawa fw_rcv(&rb); 2912120660Ssimokawa break; 2913120660Ssimokawa } 2914113584Ssimokawa case FWOHCIEV_BUSRST: 2915170425Ssimokawa if ((sc->fc.status != FWBUSRESET) && 2916170425Ssimokawa (sc->fc.status != FWBUSINIT)) 2917113584Ssimokawa printf("got BUSRST packet!?\n"); 2918113584Ssimokawa break; 2919113584Ssimokawa default: 2920169132Ssimokawa device_printf(sc->fc.dev, 2921169132Ssimokawa "Async DMA Receive error err=%02x %s" 2922169132Ssimokawa " plen=%d offset=%d len=%d status=0x%08x" 2923169132Ssimokawa " tcode=0x%x, stat=0x%08x\n", 2924169132Ssimokawa event, fwohcicode[event], plen, 2925169132Ssimokawa dbch->buf_offset, len, 2926169132Ssimokawa OREAD(sc, OHCI_DMACTL(off)), 2927169132Ssimokawa fp->mode.common.tcode, stat); 2928169132Ssimokawa#if 1 /* XXX */ 2929169132Ssimokawa goto err; 2930103285Sikob#endif 2931113584Ssimokawa break; 2932103285Sikob } 2933103285Sikob pcnt ++; 2934113584Ssimokawa if (dbch->pdb_tr != NULL) { 2935169132Ssimokawa fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 2936169132Ssimokawa off, 1); 2937113584Ssimokawa dbch->pdb_tr = NULL; 2938113584Ssimokawa } 2939113584Ssimokawa 2940113584Ssimokawa } 2941103285Sikobout: 2942103285Sikob if (resCount == 0) { 2943103285Sikob /* done on this buffer */ 2944113584Ssimokawa if (dbch->pdb_tr == NULL) { 2945169132Ssimokawa fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 2946113584Ssimokawa dbch->buf_offset = 0; 2947113584Ssimokawa } else 2948113584Ssimokawa if (dbch->pdb_tr != db_tr) 2949113584Ssimokawa printf("pdb_tr != db_tr\n"); 2950103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2951113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2952113584Ssimokawa >> OHCI_STATUS_SHIFT; 2953113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2954113584Ssimokawa & OHCI_COUNT_MASK; 2955113584Ssimokawa /* XXX check buffer overrun */ 2956103285Sikob dbch->top = db_tr; 2957103285Sikob } else { 2958103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2959103285Sikob break; 2960103285Sikob } 2961103285Sikob /* XXX make sure DMA is not dead */ 2962103285Sikob } 2963103285Sikob#if 0 2964103285Sikob if (pcnt < 1) 2965103285Sikob printf("fwohci_arcv: no packets\n"); 2966103285Sikob#endif 2967103285Sikob splx(s); 2968169132Ssimokawa return; 2969169132Ssimokawa 2970169132Ssimokawaerr: 2971169132Ssimokawa device_printf(sc->fc.dev, "AR DMA status=%x, ", 2972169132Ssimokawa OREAD(sc, OHCI_DMACTL(off))); 2973169132Ssimokawa dbch->pdb_tr = NULL; 2974169132Ssimokawa /* skip until resCount != 0 */ 2975169132Ssimokawa printf(" skip buffer"); 2976169132Ssimokawa while (resCount == 0) { 2977169132Ssimokawa printf(" #"); 2978169132Ssimokawa fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 2979169132Ssimokawa db_tr = STAILQ_NEXT(db_tr, link); 2980169132Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2981169132Ssimokawa & OHCI_COUNT_MASK; 2982188584Ssbruno } 2983169132Ssimokawa printf(" done\n"); 2984169132Ssimokawa dbch->top = db_tr; 2985169132Ssimokawa dbch->buf_offset = dbch->xferq.psize - resCount; 2986169132Ssimokawa OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2987169132Ssimokawa splx(s); 2988103285Sikob} 2989