fwohci.c revision 187993
1139749Simp/*- 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 187993 2009-02-01 23:28:52Z sbruno $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50169123Ssimokawa#include <sys/sysctl.h> 51103285Sikob#include <sys/bus.h> 52103285Sikob#include <sys/kernel.h> 53103285Sikob#include <sys/conf.h> 54113584Ssimokawa#include <sys/endian.h> 55170374Ssimokawa#include <sys/kdb.h> 56103285Sikob 57103285Sikob#include <machine/bus.h> 58103285Sikob 59127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 60117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 61117067Ssimokawa#endif 62117067Ssimokawa 63127468Ssimokawa#ifdef __DragonFly__ 64127468Ssimokawa#include "firewire.h" 65127468Ssimokawa#include "firewirereg.h" 66127468Ssimokawa#include "fwdma.h" 67127468Ssimokawa#include "fwohcireg.h" 68127468Ssimokawa#include "fwohcivar.h" 69127468Ssimokawa#include "firewire_phy.h" 70127468Ssimokawa#else 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirereg.h> 73113584Ssimokawa#include <dev/firewire/fwdma.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77127468Ssimokawa#endif 78103285Sikob 79103285Sikob#undef OHCI_DEBUG 80106802Ssimokawa 81169123Ssimokawastatic int nocyclemaster = 0; 82170400Ssimokawaint firewire_phydma_enable = 1; 83169123SsimokawaSYSCTL_DECL(_hw_firewire); 84169123SsimokawaSYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 85169123Ssimokawa "Do not send cycle start packets"); 86170400SsimokawaSYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW, 87170400Ssimokawa &firewire_phydma_enable, 1, "Allow physical request DMA from firewire"); 88170400SsimokawaTUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable); 89169123Ssimokawa 90103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 91103285Sikob "STOR","LOAD","NOP ","STOP",}; 92113584Ssimokawa 93103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 94103285Sikob "UNDEF","REG","SYS","DEV"}; 95113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 96103285Sikobchar fwohcicode[32][0x20]={ 97103285Sikob "No stat","Undef","long","miss Ack err", 98170374Ssimokawa "FIFO underrun","FIFO overrun","desc err", "data read err", 99103285Sikob "data write err","bus reset","timeout","tcode err", 100103285Sikob "Undef","Undef","unknown event","flushed", 101103285Sikob "Undef","ack complete","ack pend","Undef", 102103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 103103285Sikob "Undef","Undef","Undef","ack tardy", 104103285Sikob "Undef","ack data_err","ack type_err",""}; 105113584Ssimokawa 106116376Ssimokawa#define MAX_SPEED 3 107124378Ssimokawaextern char *linkspeed[]; 108129585Sdfruint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 109103285Sikob 110103285Sikobstatic struct tcode_info tinfo[] = { 111170374Ssimokawa/* hdr_len block flag valid_response */ 112170374Ssimokawa/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES}, 113170374Ssimokawa/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES}, 114170374Ssimokawa/* 2 WRES */ {12, FWTI_RES, 0xff}, 115170374Ssimokawa/* 3 XXX */ { 0, 0, 0xff}, 116170374Ssimokawa/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ}, 117170374Ssimokawa/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB}, 118170374Ssimokawa/* 6 RRESQ */ {16, FWTI_RES, 0xff}, 119170374Ssimokawa/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 120170374Ssimokawa/* 8 CYCS */ { 0, 0, 0xff}, 121170374Ssimokawa/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES}, 122170374Ssimokawa/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff}, 123170374Ssimokawa/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff}, 124170374Ssimokawa/* c XXX */ { 0, 0, 0xff}, 125170374Ssimokawa/* d XXX */ { 0, 0, 0xff}, 126170374Ssimokawa/* e PHY */ {12, FWTI_REQ, 0xff}, 127170374Ssimokawa/* f XXX */ { 0, 0, 0xff} 128103285Sikob}; 129103285Sikob 130103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 131103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 132103285Sikob 133103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 134103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 135103285Sikob 136124169Ssimokawastatic void fwohci_ibr (struct firewire_comm *); 137124169Ssimokawastatic void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 138124169Ssimokawastatic void fwohci_db_free (struct fwohci_dbch *); 139124169Ssimokawastatic void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 140124169Ssimokawastatic void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 141124169Ssimokawastatic void fwohci_start_atq (struct firewire_comm *); 142124169Ssimokawastatic void fwohci_start_ats (struct firewire_comm *); 143124169Ssimokawastatic void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 144129585Sdfrstatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 145129585Sdfrstatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 146124169Ssimokawastatic int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 147124169Ssimokawastatic int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 148124169Ssimokawastatic int fwohci_irx_enable (struct firewire_comm *, int); 149124169Ssimokawastatic int fwohci_irx_disable (struct firewire_comm *, int); 150113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 151129585Sdfrstatic void fwohci_irx_post (struct firewire_comm *, uint32_t *); 152113584Ssimokawa#endif 153124169Ssimokawastatic int fwohci_itxbuf_enable (struct firewire_comm *, int); 154124169Ssimokawastatic int fwohci_itx_disable (struct firewire_comm *, int); 155124169Ssimokawastatic void fwohci_timeout (void *); 156124169Ssimokawastatic void fwohci_set_intr (struct firewire_comm *, int); 157113584Ssimokawa 158124169Ssimokawastatic int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 159124169Ssimokawastatic int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 160129585Sdfrstatic void dump_db (struct fwohci_softc *, uint32_t); 161129585Sdfrstatic void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 162129585Sdfrstatic void dump_dma (struct fwohci_softc *, uint32_t); 163129585Sdfrstatic uint32_t fwohci_cyctimer (struct firewire_comm *); 164124169Ssimokawastatic void fwohci_rbuf_update (struct fwohci_softc *, int); 165124169Ssimokawastatic void fwohci_tbuf_update (struct fwohci_softc *, int); 166124169Ssimokawavoid fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 167170374Ssimokawastatic void fwohci_task_busreset(void *, int); 168170374Ssimokawastatic void fwohci_task_sid(void *, int); 169170374Ssimokawastatic void fwohci_task_dma(void *, int); 170103285Sikob 171103285Sikob/* 172103285Sikob * memory allocated for DMA programs 173103285Sikob */ 174103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 175103285Sikob 176103285Sikob#define NDB FWMAXQUEUE 177103285Sikob 178103285Sikob#define OHCI_VERSION 0x00 179112523Ssimokawa#define OHCI_ATRETRY 0x08 180103285Sikob#define OHCI_CROMHDR 0x18 181103285Sikob#define OHCI_BUS_OPT 0x20 182103285Sikob#define OHCI_BUSIRMC (1 << 31) 183103285Sikob#define OHCI_BUSCMC (1 << 30) 184103285Sikob#define OHCI_BUSISC (1 << 29) 185103285Sikob#define OHCI_BUSBMC (1 << 28) 186103285Sikob#define OHCI_BUSPMC (1 << 27) 187103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 188103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 189103285Sikob 190103285Sikob#define OHCI_EUID_HI 0x24 191103285Sikob#define OHCI_EUID_LO 0x28 192103285Sikob 193103285Sikob#define OHCI_CROMPTR 0x34 194103285Sikob#define OHCI_HCCCTL 0x50 195103285Sikob#define OHCI_HCCCTLCLR 0x54 196103285Sikob#define OHCI_AREQHI 0x100 197103285Sikob#define OHCI_AREQHICLR 0x104 198103285Sikob#define OHCI_AREQLO 0x108 199103285Sikob#define OHCI_AREQLOCLR 0x10c 200103285Sikob#define OHCI_PREQHI 0x110 201103285Sikob#define OHCI_PREQHICLR 0x114 202103285Sikob#define OHCI_PREQLO 0x118 203103285Sikob#define OHCI_PREQLOCLR 0x11c 204103285Sikob#define OHCI_PREQUPPER 0x120 205103285Sikob 206103285Sikob#define OHCI_SID_BUF 0x64 207103285Sikob#define OHCI_SID_CNT 0x68 208113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 209103285Sikob#define OHCI_SID_CNT_MASK 0xffc 210103285Sikob 211103285Sikob#define OHCI_IT_STAT 0x90 212103285Sikob#define OHCI_IT_STATCLR 0x94 213103285Sikob#define OHCI_IT_MASK 0x98 214103285Sikob#define OHCI_IT_MASKCLR 0x9c 215103285Sikob 216103285Sikob#define OHCI_IR_STAT 0xa0 217103285Sikob#define OHCI_IR_STATCLR 0xa4 218103285Sikob#define OHCI_IR_MASK 0xa8 219103285Sikob#define OHCI_IR_MASKCLR 0xac 220103285Sikob 221103285Sikob#define OHCI_LNKCTL 0xe0 222103285Sikob#define OHCI_LNKCTLCLR 0xe4 223103285Sikob 224103285Sikob#define OHCI_PHYACCESS 0xec 225103285Sikob#define OHCI_CYCLETIMER 0xf0 226103285Sikob 227103285Sikob#define OHCI_DMACTL(off) (off) 228103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 229103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 230103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 231103285Sikob 232103285Sikob#define OHCI_ATQOFF 0x180 233103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 234103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 235103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 236103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 237103285Sikob 238103285Sikob#define OHCI_ATSOFF 0x1a0 239103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 240103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 241103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 242103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 243103285Sikob 244103285Sikob#define OHCI_ARQOFF 0x1c0 245103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 246103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 247103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 248103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 249103285Sikob 250103285Sikob#define OHCI_ARSOFF 0x1e0 251103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 252103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 253103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 254103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 255103285Sikob 256103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 257103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 258103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 259103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 260103285Sikob 261103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 262103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 263103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 264103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 265103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 266103285Sikob 267103285Sikobd_ioctl_t fwohci_ioctl; 268103285Sikob 269103285Sikob/* 270103285Sikob * Communication with PHY device 271103285Sikob */ 272170374Ssimokawa/* XXX need lock for phy access */ 273129585Sdfrstatic uint32_t 274129585Sdfrfwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 275103285Sikob{ 276129585Sdfr uint32_t fun; 277103285Sikob 278103285Sikob addr &= 0xf; 279103285Sikob data &= 0xff; 280103285Sikob 281103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 282103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 283103285Sikob DELAY(100); 284103285Sikob 285103285Sikob return(fwphy_rddata( sc, addr)); 286103285Sikob} 287103285Sikob 288129585Sdfrstatic uint32_t 289103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 290103285Sikob{ 291103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 292103285Sikob int i; 293129585Sdfr uint32_t bm; 294103285Sikob 295103285Sikob#define OHCI_CSR_DATA 0x0c 296103285Sikob#define OHCI_CSR_COMP 0x10 297103285Sikob#define OHCI_CSR_CONT 0x14 298103285Sikob#define OHCI_BUS_MANAGER_ID 0 299103285Sikob 300103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 301103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 302103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 303103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 304109280Ssimokawa DELAY(10); 305103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 306107653Ssimokawa if((bm & 0x3f) == 0x3f) 307103285Sikob bm = node; 308132432Ssimokawa if (firewire_debug) 309107653Ssimokawa device_printf(sc->fc.dev, 310107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 311103285Sikob 312103285Sikob return(bm); 313103285Sikob} 314103285Sikob 315129585Sdfrstatic uint32_t 316106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 317103285Sikob{ 318129585Sdfr uint32_t fun, stat; 319108500Ssimokawa u_int i, retry = 0; 320103285Sikob 321103285Sikob addr &= 0xf; 322108500Ssimokawa#define MAX_RETRY 100 323108500Ssimokawaagain: 324108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 325103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 326103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 327108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 328103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 329103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 330103285Sikob break; 331109280Ssimokawa DELAY(100); 332103285Sikob } 333108500Ssimokawa if(i >= MAX_RETRY) { 334132432Ssimokawa if (firewire_debug) 335109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 336108527Ssimokawa if (++retry < MAX_RETRY) { 337109280Ssimokawa DELAY(100); 338108527Ssimokawa goto again; 339108527Ssimokawa } 340108500Ssimokawa } 341108500Ssimokawa /* Make sure that SCLK is started */ 342108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 343108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 344108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 345132432Ssimokawa if (firewire_debug) 346109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 347108500Ssimokawa if (++retry < MAX_RETRY) { 348109280Ssimokawa DELAY(100); 349108500Ssimokawa goto again; 350108500Ssimokawa } 351108500Ssimokawa } 352132432Ssimokawa if (firewire_debug || retry >= MAX_RETRY) 353108500Ssimokawa device_printf(sc->fc.dev, 354119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 355108500Ssimokawa#undef MAX_RETRY 356103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 357103285Sikob} 358103285Sikob/* Device specific ioctl. */ 359103285Sikobint 360130585Sphkfwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 361103285Sikob{ 362103285Sikob struct firewire_softc *sc; 363103285Sikob struct fwohci_softc *fc; 364103285Sikob int unit = DEV2UNIT(dev); 365103285Sikob int err = 0; 366103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 367129585Sdfr uint32_t *dmach = (uint32_t *) data; 368103285Sikob 369103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 370103285Sikob if(sc == NULL){ 371103285Sikob return(EINVAL); 372103285Sikob } 373103285Sikob fc = (struct fwohci_softc *)sc->fc; 374103285Sikob 375103285Sikob if (!data) 376103285Sikob return(EINVAL); 377103285Sikob 378103285Sikob switch (cmd) { 379103285Sikob case FWOHCI_WRREG: 380103285Sikob#define OHCI_MAX_REG 0x800 381103285Sikob if(reg->addr <= OHCI_MAX_REG){ 382103285Sikob OWRITE(fc, reg->addr, reg->data); 383103285Sikob reg->data = OREAD(fc, reg->addr); 384103285Sikob }else{ 385103285Sikob err = EINVAL; 386103285Sikob } 387103285Sikob break; 388103285Sikob case FWOHCI_RDREG: 389103285Sikob if(reg->addr <= OHCI_MAX_REG){ 390103285Sikob reg->data = OREAD(fc, reg->addr); 391103285Sikob }else{ 392103285Sikob err = EINVAL; 393103285Sikob } 394103285Sikob break; 395103285Sikob/* Read DMA descriptors for debug */ 396103285Sikob case DUMPDMA: 397103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 398103285Sikob dump_dma(fc, *dmach); 399103285Sikob dump_db(fc, *dmach); 400103285Sikob }else{ 401103285Sikob err = EINVAL; 402103285Sikob } 403103285Sikob break; 404119118Ssimokawa/* Read/Write Phy registers */ 405119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 406119118Ssimokawa case FWOHCI_RDPHYREG: 407119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 408119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 409119118Ssimokawa else 410119118Ssimokawa err = EINVAL; 411119118Ssimokawa break; 412119118Ssimokawa case FWOHCI_WRPHYREG: 413119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 414119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 415119118Ssimokawa else 416119118Ssimokawa err = EINVAL; 417119118Ssimokawa break; 418103285Sikob default: 419119118Ssimokawa err = EINVAL; 420103285Sikob break; 421103285Sikob } 422103285Sikob return err; 423103285Sikob} 424106790Ssimokawa 425108530Ssimokawastatic int 426108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 427103285Sikob{ 428129585Sdfr uint32_t reg, reg2; 429108530Ssimokawa int e1394a = 1; 430108530Ssimokawa/* 431108530Ssimokawa * probe PHY parameters 432108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 433108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 434108530Ssimokawa * number of port supported by core-logic. 435108530Ssimokawa * It is not actually available port on your PC . 436108530Ssimokawa */ 437108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 438167685Ssimokawa DELAY(500); 439167685Ssimokawa 440108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 441108530Ssimokawa 442108530Ssimokawa if((reg >> 5) != 7 ){ 443108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 444108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 445108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 446108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 447108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 448108530Ssimokawa sc->fc.speed, MAX_SPEED); 449108530Ssimokawa sc->fc.speed = MAX_SPEED; 450108530Ssimokawa } 451108530Ssimokawa device_printf(dev, 452108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 453108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 454108530Ssimokawa }else{ 455108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 456108530Ssimokawa sc->fc.mode |= FWPHYASYST; 457108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 458108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 459108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 460108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 461108530Ssimokawa sc->fc.speed, MAX_SPEED); 462108530Ssimokawa sc->fc.speed = MAX_SPEED; 463108530Ssimokawa } 464108530Ssimokawa device_printf(dev, 465108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 466108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 467108530Ssimokawa 468108530Ssimokawa /* check programPhyEnable */ 469108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 470108530Ssimokawa#if 0 471108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 472108530Ssimokawa#else /* XXX force to enable 1394a */ 473108530Ssimokawa if (e1394a) { 474108530Ssimokawa#endif 475132432Ssimokawa if (firewire_debug) 476108530Ssimokawa device_printf(dev, 477108530Ssimokawa "Enable 1394a Enhancements\n"); 478108530Ssimokawa /* enable EAA EMC */ 479108530Ssimokawa reg2 |= 0x03; 480108530Ssimokawa /* set aPhyEnhanceEnable */ 481108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 482108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 483108530Ssimokawa } else { 484108530Ssimokawa /* for safe */ 485108530Ssimokawa reg2 &= ~0x83; 486108530Ssimokawa } 487108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 488108530Ssimokawa } 489108530Ssimokawa 490108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 491108530Ssimokawa if((reg >> 5) == 7 ){ 492108530Ssimokawa reg = fwphy_rddata(sc, 4); 493108530Ssimokawa reg |= 1 << 6; 494108530Ssimokawa fwphy_wrdata(sc, 4, reg); 495108530Ssimokawa reg = fwphy_rddata(sc, 4); 496108530Ssimokawa } 497108530Ssimokawa return 0; 498108530Ssimokawa} 499108530Ssimokawa 500108530Ssimokawa 501108530Ssimokawavoid 502108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 503108530Ssimokawa{ 504108701Ssimokawa int i, max_rec, speed; 505129585Sdfr uint32_t reg, reg2; 506103285Sikob struct fwohcidb_tr *db_tr; 507103285Sikob 508129541Sdfr /* Disable interrupts */ 509108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 510108530Ssimokawa 511129541Sdfr /* Now stopping all DMA channels */ 512108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 513108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 514108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 515108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 516108530Ssimokawa 517108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 518108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 519108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 520108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 521108530Ssimokawa } 522108530Ssimokawa 523108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 524108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 525132432Ssimokawa if (firewire_debug) 526108530Ssimokawa device_printf(dev, "resetting OHCI..."); 527108530Ssimokawa i = 0; 528108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 529108530Ssimokawa if (i++ > 100) break; 530108530Ssimokawa DELAY(1000); 531108530Ssimokawa } 532132432Ssimokawa if (firewire_debug) 533108530Ssimokawa printf("done (loop=%d)\n", i); 534108530Ssimokawa 535108701Ssimokawa /* Probe phy */ 536108701Ssimokawa fwohci_probe_phy(sc, dev); 537108701Ssimokawa 538108701Ssimokawa /* Probe link */ 539108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 540108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 541108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 542108701Ssimokawa speed = (reg & 0x00000007); 543108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 544108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 545108701Ssimokawa /* XXX fix max_rec */ 546108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 547108701Ssimokawa if (max_rec != sc->fc.maxrec) { 548108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 549108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 550108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 551108701Ssimokawa } 552132432Ssimokawa if (firewire_debug) 553108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 554108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 555108530Ssimokawa 556108701Ssimokawa /* Initialize registers */ 557108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 558113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 559108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 560108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 561113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 562108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 563108530Ssimokawa 564108701Ssimokawa /* Enable link */ 565108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 566108642Ssimokawa 567108701Ssimokawa /* Force to start async RX DMA */ 568108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 569108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 570108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 571108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 572108530Ssimokawa 573108701Ssimokawa /* Initialize async TX */ 574108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 575108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 576116978Ssimokawa 577108701Ssimokawa /* AT Retries */ 578108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 579108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 580108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 581116978Ssimokawa 582116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 583116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 584116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 585116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 586116978Ssimokawa 587108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 588108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 589108530Ssimokawa db_tr->xfer = NULL; 590108530Ssimokawa } 591108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 592108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 593108530Ssimokawa db_tr->xfer = NULL; 594108530Ssimokawa } 595108530Ssimokawa 596108701Ssimokawa 597129541Sdfr /* Enable interrupts */ 598170374Ssimokawa sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID 599108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 600108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 601108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 602170374Ssimokawa sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT; 603170374Ssimokawa sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT; 604170374Ssimokawa OWRITE(sc, FWOHCI_INTMASK, sc->intmask); 605108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 606108530Ssimokawa 607108530Ssimokawa} 608108530Ssimokawa 609108530Ssimokawaint 610108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 611108530Ssimokawa{ 612121781Ssimokawa int i, mver; 613129585Sdfr uint32_t reg; 614129585Sdfr uint8_t ui[8]; 615108530Ssimokawa 616121781Ssimokawa/* OHCI version */ 617103285Sikob reg = OREAD(sc, OHCI_VERSION); 618121781Ssimokawa mver = (reg >> 16) & 0xff; 619103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 620121781Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 621121781Ssimokawa if (mver < 1 || mver > 9) { 622118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 623118416Ssimokawa return (ENXIO); 624118416Ssimokawa } 625118416Ssimokawa 626129541Sdfr/* Available Isochronous DMA channel probe */ 627110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 628110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 629110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 630110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 631110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 632110045Ssimokawa for (i = 0; i < 0x20; i++) 633110045Ssimokawa if ((reg & (1 << i)) == 0) 634110045Ssimokawa break; 635103285Sikob sc->fc.nisodma = i; 636129541Sdfr device_printf(dev, "No. of Isochronous channels is %d.\n", i); 637118820Ssimokawa if (i == 0) 638118820Ssimokawa return (ENXIO); 639103285Sikob 640103285Sikob sc->fc.arq = &sc->arrq.xferq; 641103285Sikob sc->fc.ars = &sc->arrs.xferq; 642103285Sikob sc->fc.atq = &sc->atrq.xferq; 643103285Sikob sc->fc.ats = &sc->atrs.xferq; 644103285Sikob 645113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 646113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 647113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 648113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 649113584Ssimokawa 650103285Sikob sc->arrq.xferq.start = NULL; 651103285Sikob sc->arrs.xferq.start = NULL; 652103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 653103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 654103285Sikob 655113584Ssimokawa sc->arrq.xferq.buf = NULL; 656113584Ssimokawa sc->arrs.xferq.buf = NULL; 657113584Ssimokawa sc->atrq.xferq.buf = NULL; 658113584Ssimokawa sc->atrs.xferq.buf = NULL; 659103285Sikob 660118293Ssimokawa sc->arrq.xferq.dmach = -1; 661118293Ssimokawa sc->arrs.xferq.dmach = -1; 662118293Ssimokawa sc->atrq.xferq.dmach = -1; 663118293Ssimokawa sc->atrs.xferq.dmach = -1; 664118293Ssimokawa 665103285Sikob sc->arrq.ndesc = 1; 666103285Sikob sc->arrs.ndesc = 1; 667110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 668110593Ssimokawa sc->atrs.ndesc = 2; 669103285Sikob 670103285Sikob sc->arrq.ndb = NDB; 671103285Sikob sc->arrs.ndb = NDB / 2; 672103285Sikob sc->atrq.ndb = NDB; 673103285Sikob sc->atrs.ndb = NDB / 2; 674103285Sikob 675103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 676103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 677103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 678118293Ssimokawa sc->it[i].xferq.dmach = i; 679118293Ssimokawa sc->ir[i].xferq.dmach = i; 680103285Sikob sc->it[i].ndb = 0; 681103285Sikob sc->ir[i].ndb = 0; 682103285Sikob } 683103285Sikob 684103285Sikob sc->fc.tcode = tinfo; 685113584Ssimokawa sc->fc.dev = dev; 686103285Sikob 687113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 688113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 689113584Ssimokawa if(sc->fc.config_rom == NULL){ 690113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 691103285Sikob return ENOMEM; 692103285Sikob } 693103285Sikob 694116376Ssimokawa#if 0 695116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 696103285Sikob sc->fc.config_rom[1] = 0x31333934; 697103285Sikob sc->fc.config_rom[2] = 0xf000a002; 698103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 699103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 700103285Sikob sc->fc.config_rom[5] = 0; 701103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 702103285Sikob 703103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 704113584Ssimokawa#endif 705103285Sikob 706103285Sikob 707129541Sdfr/* SID recieve buffer must align 2^11 */ 708103285Sikob#define OHCI_SIDSIZE (1 << 11) 709113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 710113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 711113584Ssimokawa if (sc->sid_buf == NULL) { 712113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 713108527Ssimokawa return ENOMEM; 714108527Ssimokawa } 715113584Ssimokawa 716129585Sdfr fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 717113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 718113584Ssimokawa 719113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 720113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 721109736Ssimokawa return ENOMEM; 722109736Ssimokawa } 723113584Ssimokawa 724113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 725108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 726108527Ssimokawa return ENOMEM; 727108527Ssimokawa 728113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 729108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 730108527Ssimokawa return ENOMEM; 731103285Sikob 732113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 733108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 734108527Ssimokawa return ENOMEM; 735108527Ssimokawa 736113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 737108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 738108527Ssimokawa return ENOMEM; 739103285Sikob 740109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 741109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 742109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 743109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 744103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 745109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 746109814Ssimokawa 747103285Sikob sc->fc.ioctl = fwohci_ioctl; 748103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 749103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 750103285Sikob sc->fc.ibr = fwohci_ibr; 751103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 752103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 753103285Sikob 754103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 755103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 756113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 757103285Sikob sc->fc.irx_post = fwohci_irx_post; 758113584Ssimokawa#else 759113584Ssimokawa sc->fc.irx_post = NULL; 760113584Ssimokawa#endif 761103285Sikob sc->fc.itx_post = NULL; 762103285Sikob sc->fc.timeout = fwohci_timeout; 763103285Sikob sc->fc.poll = fwohci_poll; 764103285Sikob sc->fc.set_intr = fwohci_set_intr; 765106790Ssimokawa 766113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 767113584Ssimokawa 768170374Ssimokawa /* Init task queue */ 769170374Ssimokawa sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK, 770170374Ssimokawa taskqueue_thread_enqueue, &sc->fc.taskqueue); 771170374Ssimokawa taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq", 772170374Ssimokawa device_get_unit(dev)); 773170374Ssimokawa TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc); 774170374Ssimokawa TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc); 775170374Ssimokawa TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc); 776170374Ssimokawa 777108530Ssimokawa fw_init(&sc->fc); 778108530Ssimokawa fwohci_reset(sc, dev); 779103285Sikob 780108530Ssimokawa return 0; 781103285Sikob} 782106790Ssimokawa 783106790Ssimokawavoid 784106790Ssimokawafwohci_timeout(void *arg) 785103285Sikob{ 786103285Sikob struct fwohci_softc *sc; 787103285Sikob 788103285Sikob sc = (struct fwohci_softc *)arg; 789103285Sikob} 790106790Ssimokawa 791129585Sdfruint32_t 792106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 793103285Sikob{ 794103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 795103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 796103285Sikob} 797103285Sikob 798108527Ssimokawaint 799108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 800108527Ssimokawa{ 801108527Ssimokawa int i; 802108527Ssimokawa 803113584Ssimokawa if (sc->sid_buf != NULL) 804113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 805113584Ssimokawa if (sc->fc.config_rom != NULL) 806113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 807108527Ssimokawa 808108527Ssimokawa fwohci_db_free(&sc->arrq); 809108527Ssimokawa fwohci_db_free(&sc->arrs); 810108527Ssimokawa 811108527Ssimokawa fwohci_db_free(&sc->atrq); 812108527Ssimokawa fwohci_db_free(&sc->atrs); 813108527Ssimokawa 814108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 815108527Ssimokawa fwohci_db_free(&sc->it[i]); 816108527Ssimokawa fwohci_db_free(&sc->ir[i]); 817108527Ssimokawa } 818170374Ssimokawa if (sc->fc.taskqueue != NULL) { 819170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset); 820170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid); 821170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma); 822170374Ssimokawa taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout); 823170374Ssimokawa taskqueue_free(sc->fc.taskqueue); 824170374Ssimokawa sc->fc.taskqueue = NULL; 825170374Ssimokawa } 826108527Ssimokawa 827108527Ssimokawa return 0; 828108527Ssimokawa} 829108527Ssimokawa 830108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 831108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 832108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 833108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 834108655Ssimokawa} while (0) 835108655Ssimokawa 836106790Ssimokawastatic void 837113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 838113584Ssimokawa{ 839113584Ssimokawa struct fwohcidb_tr *db_tr; 840120660Ssimokawa struct fwohcidb *db; 841113584Ssimokawa bus_dma_segment_t *s; 842113584Ssimokawa int i; 843113584Ssimokawa 844113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 845113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 846113584Ssimokawa if (error) { 847113584Ssimokawa if (firewire_debug || error != EFBIG) 848113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 849113584Ssimokawa return; 850113584Ssimokawa } 851113584Ssimokawa for (i = 0; i < nseg; i++) { 852113584Ssimokawa s = &segs[i]; 853113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 854113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 855113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 856113584Ssimokawa db++; 857113584Ssimokawa db_tr->dbcnt++; 858113584Ssimokawa } 859113584Ssimokawa} 860113584Ssimokawa 861113584Ssimokawastatic void 862113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 863113584Ssimokawa bus_size_t size, int error) 864113584Ssimokawa{ 865113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 866113584Ssimokawa} 867113584Ssimokawa 868113584Ssimokawastatic void 869106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 870103285Sikob{ 871103285Sikob int i, s; 872120660Ssimokawa int tcode, hdr_len, pl_off; 873103285Sikob int fsegment = -1; 874129585Sdfr uint32_t off; 875103285Sikob struct fw_xfer *xfer; 876103285Sikob struct fw_pkt *fp; 877120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 878103285Sikob struct fwohcidb_tr *db_tr; 879120660Ssimokawa struct fwohcidb *db; 880129585Sdfr uint32_t *ld; 881103285Sikob struct tcode_info *info; 882108655Ssimokawa static int maxdesc=0; 883103285Sikob 884170374Ssimokawa FW_GLOCK_ASSERT(&sc->fc); 885170374Ssimokawa 886103285Sikob if(&sc->atrq == dbch){ 887103285Sikob off = OHCI_ATQOFF; 888103285Sikob }else if(&sc->atrs == dbch){ 889103285Sikob off = OHCI_ATSOFF; 890103285Sikob }else{ 891103285Sikob return; 892103285Sikob } 893103285Sikob 894103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 895103285Sikob return; 896103285Sikob 897103285Sikob s = splfw(); 898103285Sikob db_tr = dbch->top; 899103285Sikobtxloop: 900103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 901103285Sikob if(xfer == NULL){ 902103285Sikob goto kick; 903103285Sikob } 904170374Ssimokawa#if 0 905103285Sikob if(dbch->xferq.queued == 0 ){ 906103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 907103285Sikob } 908170374Ssimokawa#endif 909103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 910103285Sikob db_tr->xfer = xfer; 911170374Ssimokawa xfer->flag = FWXF_START; 912103285Sikob 913120660Ssimokawa fp = &xfer->send.hdr; 914103285Sikob tcode = fp->mode.common.tcode; 915103285Sikob 916120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 917103285Sikob info = &tinfo[tcode]; 918113584Ssimokawa hdr_len = pl_off = info->hdr_len; 919119155Ssimokawa 920119155Ssimokawa ld = &ohcifp->mode.ld[0]; 921119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 922119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 923119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 924119155Ssimokawa 925120660Ssimokawa ohcifp->mode.common.spd = xfer->send.spd & 0x7; 926103285Sikob if (tcode == FWTCODE_STREAM ){ 927103285Sikob hdr_len = 8; 928113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 929103285Sikob } else if (tcode == FWTCODE_PHY) { 930103285Sikob hdr_len = 12; 931119155Ssimokawa ld[1] = fp->mode.ld[1]; 932119155Ssimokawa ld[2] = fp->mode.ld[2]; 933103285Sikob ohcifp->mode.common.spd = 0; 934103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 935103285Sikob } else { 936113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 937103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 938103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 939103285Sikob } 940103285Sikob db = &db_tr->db[0]; 941113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 942113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 943119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 944113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 945103285Sikob/* Specify bound timer of asy. responce */ 946103285Sikob if(&sc->atrs == dbch){ 947113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 948113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 949103285Sikob } 950113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 951113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 952113584Ssimokawa hdr_len = 12; 953113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 954119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 955113584Ssimokawa#endif 956103285Sikob 957111942Ssimokawaagain: 958103285Sikob db_tr->dbcnt = 2; 959103285Sikob db = &db_tr->db[db_tr->dbcnt]; 960120660Ssimokawa if (xfer->send.pay_len > 0) { 961113584Ssimokawa int err; 962113584Ssimokawa /* handle payload */ 963103285Sikob if (xfer->mbuf == NULL) { 964113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 965120660Ssimokawa &xfer->send.payload[0], xfer->send.pay_len, 966113584Ssimokawa fwohci_execute_db, db_tr, 967113584Ssimokawa /*flags*/0); 968103285Sikob } else { 969111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 970113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 971113584Ssimokawa xfer->mbuf, 972113584Ssimokawa fwohci_execute_db2, db_tr, 973113584Ssimokawa /* flags */0); 974113584Ssimokawa if (err == EFBIG) { 975113584Ssimokawa struct mbuf *m0; 976113584Ssimokawa 977113584Ssimokawa if (firewire_debug) 978113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 979113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 980113584Ssimokawa if (m0 != NULL) { 981111942Ssimokawa m_copydata(xfer->mbuf, 0, 982111942Ssimokawa xfer->mbuf->m_pkthdr.len, 983113584Ssimokawa mtod(m0, caddr_t)); 984113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 985111942Ssimokawa xfer->mbuf->m_pkthdr.len; 986111942Ssimokawa m_freem(xfer->mbuf); 987113584Ssimokawa xfer->mbuf = m0; 988111942Ssimokawa goto again; 989111942Ssimokawa } 990111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 991111942Ssimokawa } 992103285Sikob } 993113584Ssimokawa if (err) 994113584Ssimokawa printf("dmamap_load: err=%d\n", err); 995113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 996113584Ssimokawa BUS_DMASYNC_PREWRITE); 997113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 998113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 999113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1000113584Ssimokawa OHCI_OUTPUT_MORE); 1001113584Ssimokawa#endif 1002103285Sikob } 1003108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 1004108655Ssimokawa maxdesc = db_tr->dbcnt; 1005132432Ssimokawa if (firewire_debug) 1006187993Ssbruno device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc); 1007108655Ssimokawa } 1008103285Sikob /* last db */ 1009103285Sikob LAST_DB(db_tr, db); 1010113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 1011113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1012113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 1013113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 1014103285Sikob 1015103285Sikob if(fsegment == -1 ) 1016103285Sikob fsegment = db_tr->dbcnt; 1017103285Sikob if (dbch->pdb_tr != NULL) { 1018103285Sikob LAST_DB(dbch->pdb_tr, db); 1019113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1020103285Sikob } 1021170374Ssimokawa dbch->xferq.queued ++; 1022103285Sikob dbch->pdb_tr = db_tr; 1023103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1024103285Sikob if(db_tr != dbch->bottom){ 1025103285Sikob goto txloop; 1026103285Sikob } else { 1027107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1028103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 1029103285Sikob } 1030103285Sikobkick: 1031103285Sikob /* kick asy q */ 1032113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1033113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1034103285Sikob 1035103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1036103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1037103285Sikob } else { 1038132432Ssimokawa if (firewire_debug) 1039107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1040103285Sikob OREAD(sc, OHCI_DMACTL(off))); 1041113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1042103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1043103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1044103285Sikob } 1045106790Ssimokawa 1046103285Sikob dbch->top = db_tr; 1047103285Sikob splx(s); 1048103285Sikob return; 1049103285Sikob} 1050106790Ssimokawa 1051106790Ssimokawastatic void 1052106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1053103285Sikob{ 1054103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1055170374Ssimokawa FW_GLOCK(&sc->fc); 1056103285Sikob fwohci_start( sc, &(sc->atrq)); 1057170374Ssimokawa FW_GUNLOCK(&sc->fc); 1058103285Sikob return; 1059103285Sikob} 1060106790Ssimokawa 1061106790Ssimokawastatic void 1062106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1063103285Sikob{ 1064103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1065170374Ssimokawa FW_GLOCK(&sc->fc); 1066103285Sikob fwohci_start( sc, &(sc->atrs)); 1067170374Ssimokawa FW_GUNLOCK(&sc->fc); 1068103285Sikob return; 1069103285Sikob} 1070106790Ssimokawa 1071106790Ssimokawavoid 1072106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1073103285Sikob{ 1074113584Ssimokawa int s, ch, err = 0; 1075103285Sikob struct fwohcidb_tr *tr; 1076120660Ssimokawa struct fwohcidb *db; 1077103285Sikob struct fw_xfer *xfer; 1078129585Sdfr uint32_t off; 1079113584Ssimokawa u_int stat, status; 1080103285Sikob int packets; 1081103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1082113584Ssimokawa 1083103285Sikob if(&sc->atrq == dbch){ 1084103285Sikob off = OHCI_ATQOFF; 1085113584Ssimokawa ch = ATRQ_CH; 1086103285Sikob }else if(&sc->atrs == dbch){ 1087103285Sikob off = OHCI_ATSOFF; 1088113584Ssimokawa ch = ATRS_CH; 1089103285Sikob }else{ 1090103285Sikob return; 1091103285Sikob } 1092103285Sikob s = splfw(); 1093103285Sikob tr = dbch->bottom; 1094103285Sikob packets = 0; 1095113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1096113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1097103285Sikob while(dbch->xferq.queued > 0){ 1098103285Sikob LAST_DB(tr, db); 1099113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1100113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1101170425Ssimokawa if (fc->status != FWBUSINIT) 1102103285Sikob /* maybe out of order?? */ 1103103285Sikob goto out; 1104103285Sikob } 1105113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1106113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1107113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1108119155Ssimokawa#if 1 1109167629Ssimokawa if (firewire_debug > 1) 1110119155Ssimokawa dump_db(sc, ch); 1111103285Sikob#endif 1112113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1113113584Ssimokawa /* Stop DMA */ 1114103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1115103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1116103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1117103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1118103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1119103285Sikob } 1120113584Ssimokawa stat = status & FWOHCIEV_MASK; 1121103285Sikob switch(stat){ 1122110577Ssimokawa case FWOHCIEV_ACKPEND: 1123103285Sikob case FWOHCIEV_ACKCOMPL: 1124103285Sikob err = 0; 1125103285Sikob break; 1126103285Sikob case FWOHCIEV_ACKBSA: 1127103285Sikob case FWOHCIEV_ACKBSB: 1128110577Ssimokawa case FWOHCIEV_ACKBSX: 1129103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1130103285Sikob err = EBUSY; 1131103285Sikob break; 1132103285Sikob case FWOHCIEV_FLUSHED: 1133103285Sikob case FWOHCIEV_ACKTARD: 1134103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1135103285Sikob err = EAGAIN; 1136103285Sikob break; 1137103285Sikob case FWOHCIEV_MISSACK: 1138103285Sikob case FWOHCIEV_UNDRRUN: 1139103285Sikob case FWOHCIEV_OVRRUN: 1140103285Sikob case FWOHCIEV_DESCERR: 1141103285Sikob case FWOHCIEV_DTRDERR: 1142103285Sikob case FWOHCIEV_TIMEOUT: 1143103285Sikob case FWOHCIEV_TCODERR: 1144103285Sikob case FWOHCIEV_UNKNOWN: 1145103285Sikob case FWOHCIEV_ACKDERR: 1146103285Sikob case FWOHCIEV_ACKTERR: 1147103285Sikob default: 1148103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1149103285Sikob stat, fwohcicode[stat]); 1150103285Sikob err = EINVAL; 1151103285Sikob break; 1152103285Sikob } 1153110577Ssimokawa if (tr->xfer != NULL) { 1154103285Sikob xfer = tr->xfer; 1155170374Ssimokawa if (xfer->flag & FWXF_RCVD) { 1156119289Ssimokawa#if 0 1157113584Ssimokawa if (firewire_debug) 1158113584Ssimokawa printf("already rcvd\n"); 1159119289Ssimokawa#endif 1160113584Ssimokawa fw_xfer_done(xfer); 1161113584Ssimokawa } else { 1162170427Ssimokawa microtime(&xfer->tv); 1163170374Ssimokawa xfer->flag = FWXF_SENT; 1164170425Ssimokawa if (err == EBUSY) { 1165170374Ssimokawa xfer->flag = FWXF_BUSY; 1166114218Ssimokawa xfer->resp = err; 1167167630Ssimokawa xfer->recv.pay_len = 0; 1168167630Ssimokawa fw_xfer_done(xfer); 1169114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1170114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1171170374Ssimokawa xfer->flag = FWXF_SENTERR; 1172114218Ssimokawa xfer->resp = err; 1173120660Ssimokawa xfer->recv.pay_len = 0; 1174113584Ssimokawa fw_xfer_done(xfer); 1175114218Ssimokawa } 1176103285Sikob } 1177110577Ssimokawa /* 1178110577Ssimokawa * The watchdog timer takes care of split 1179110577Ssimokawa * transcation timeout for ACKPEND case. 1180110577Ssimokawa */ 1181113584Ssimokawa } else { 1182113584Ssimokawa printf("this shouldn't happen\n"); 1183103285Sikob } 1184170374Ssimokawa FW_GLOCK(fc); 1185110269Ssimokawa dbch->xferq.queued --; 1186170374Ssimokawa FW_GUNLOCK(fc); 1187103285Sikob tr->xfer = NULL; 1188103285Sikob 1189103285Sikob packets ++; 1190103285Sikob tr = STAILQ_NEXT(tr, link); 1191103285Sikob dbch->bottom = tr; 1192111956Ssimokawa if (dbch->bottom == dbch->top) { 1193111956Ssimokawa /* we reaches the end of context program */ 1194111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1195111956Ssimokawa printf("queued > 0\n"); 1196111956Ssimokawa break; 1197111956Ssimokawa } 1198103285Sikob } 1199103285Sikobout: 1200103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1201103285Sikob printf("make free slot\n"); 1202103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1203170374Ssimokawa FW_GLOCK(fc); 1204103285Sikob fwohci_start(sc, dbch); 1205170374Ssimokawa FW_GUNLOCK(fc); 1206103285Sikob } 1207103285Sikob splx(s); 1208103285Sikob} 1209106790Ssimokawa 1210106790Ssimokawastatic void 1211106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1212103285Sikob{ 1213103285Sikob struct fwohcidb_tr *db_tr; 1214113584Ssimokawa int idb; 1215103285Sikob 1216108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1217108527Ssimokawa return; 1218108527Ssimokawa 1219113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1220103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1221113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1222113584Ssimokawa db_tr->buf != NULL) { 1223113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1224113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1225113584Ssimokawa db_tr->buf = NULL; 1226113584Ssimokawa } else if (db_tr->dma_map != NULL) 1227113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1228103285Sikob } 1229103285Sikob dbch->ndb = 0; 1230103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1231113584Ssimokawa fwdma_free_multiseg(dbch->am); 1232110195Ssimokawa free(db_tr, M_FW); 1233103285Sikob STAILQ_INIT(&dbch->db_trq); 1234108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1235103285Sikob} 1236106790Ssimokawa 1237106790Ssimokawastatic void 1238113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1239103285Sikob{ 1240103285Sikob int idb; 1241103285Sikob struct fwohcidb_tr *db_tr; 1242108642Ssimokawa 1243108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1244108642Ssimokawa goto out; 1245108642Ssimokawa 1246113584Ssimokawa /* create dma_tag for buffers */ 1247113584Ssimokawa#define MAX_REQCOUNT 0xffff 1248113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1249113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1250113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1251113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1252113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1253113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1254113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1255113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1256117126Sscottl /*flags*/ 0, 1257127468Ssimokawa#if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1258117126Sscottl /*lockfunc*/busdma_lock_mutex, 1259170374Ssimokawa /*lockarg*/FW_GMTX(&sc->fc), 1260117228Ssimokawa#endif 1261117228Ssimokawa &dbch->dmat)) 1262113584Ssimokawa return; 1263113584Ssimokawa 1264103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1265103285Sikob /* DB entry must start at 16 bytes bounary. */ 1266103285Sikob STAILQ_INIT(&dbch->db_trq); 1267103285Sikob db_tr = (struct fwohcidb_tr *) 1268103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1269113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1270103285Sikob if(db_tr == NULL){ 1271109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1272103285Sikob return; 1273103285Sikob } 1274109379Ssimokawa 1275113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1276113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1277113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1278113584Ssimokawa if (dbch->am == NULL) { 1279113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1280124836Ssimokawa free(db_tr, M_FW); 1281103285Sikob return; 1282103285Sikob } 1283103285Sikob /* Attach DB to DMA ch. */ 1284103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1285103285Sikob db_tr->dbcnt = 0; 1286113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1287113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1288113584Ssimokawa /* create dmamap for buffers */ 1289113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1290113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1291113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1292113584Ssimokawa printf("bus_dmamap_create failed\n"); 1293113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1294113584Ssimokawa fwohci_db_free(dbch); 1295113584Ssimokawa return; 1296113584Ssimokawa } 1297103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1298113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1299108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1300108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1301108530Ssimokawa ].start = (caddr_t)db_tr; 1302108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1303108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1304108530Ssimokawa ].end = (caddr_t)db_tr; 1305103285Sikob } 1306103285Sikob db_tr++; 1307103285Sikob } 1308103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1309103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1310108642Ssimokawaout: 1311108642Ssimokawa dbch->xferq.queued = 0; 1312108642Ssimokawa dbch->pdb_tr = NULL; 1313103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1314103285Sikob dbch->bottom = dbch->top; 1315108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1316103285Sikob} 1317106790Ssimokawa 1318106790Ssimokawastatic int 1319106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1320103285Sikob{ 1321103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1322109890Ssimokawa 1323113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1324113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1325103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1326103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1327109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1328167086Sjhb pause("fwitxd", hz); 1329103285Sikob fwohci_db_free(&sc->it[dmach]); 1330103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1331103285Sikob return 0; 1332103285Sikob} 1333106790Ssimokawa 1334106790Ssimokawastatic int 1335106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1336103285Sikob{ 1337103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1338103285Sikob 1339103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1340103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1341103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1342109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1343167086Sjhb pause("fwirxd", hz); 1344103285Sikob fwohci_db_free(&sc->ir[dmach]); 1345103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1346103285Sikob return 0; 1347103285Sikob} 1348106790Ssimokawa 1349113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1350106790Ssimokawastatic void 1351129585Sdfrfwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1352103285Sikob{ 1353113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1354103285Sikob return; 1355103285Sikob} 1356103285Sikob#endif 1357103285Sikob 1358106790Ssimokawastatic int 1359106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1360103285Sikob{ 1361103285Sikob int err = 0; 1362113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1363129585Sdfr uint32_t off = 0; 1364103285Sikob struct fwohcidb_tr *db_tr; 1365120660Ssimokawa struct fwohcidb *db; 1366103285Sikob 1367103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1368103285Sikob err = EINVAL; 1369103285Sikob return err; 1370103285Sikob } 1371103285Sikob z = dbch->ndesc; 1372103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1373103285Sikob if( &sc->it[dmach] == dbch){ 1374103285Sikob off = OHCI_ITOFF(dmach); 1375103285Sikob break; 1376103285Sikob } 1377103285Sikob } 1378123740Speter if(off == 0){ 1379103285Sikob err = EINVAL; 1380103285Sikob return err; 1381103285Sikob } 1382103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1383103285Sikob return err; 1384103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1385103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1386103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1387103285Sikob } 1388103285Sikob db_tr = dbch->top; 1389113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1390113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1391103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1392103285Sikob break; 1393103285Sikob } 1394109892Ssimokawa db = db_tr->db; 1395113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1396113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1397113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1398113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1399103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1400103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1401113584Ssimokawa FWOHCI_DMA_SET( 1402113584Ssimokawa db[ldesc].db.desc.cmd, 1403113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1404109280Ssimokawa /* OHCI 1.1 and above */ 1405113584Ssimokawa FWOHCI_DMA_SET( 1406113584Ssimokawa db[0].db.desc.cmd, 1407113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1408103285Sikob } 1409103285Sikob } 1410103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1411103285Sikob } 1412113584Ssimokawa FWOHCI_DMA_CLEAR( 1413113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1414103285Sikob return err; 1415103285Sikob} 1416106790Ssimokawa 1417106790Ssimokawastatic int 1418106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1419103285Sikob{ 1420103285Sikob int err = 0; 1421109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1422129585Sdfr uint32_t off = 0; 1423103285Sikob struct fwohcidb_tr *db_tr; 1424120660Ssimokawa struct fwohcidb *db; 1425103285Sikob 1426103285Sikob z = dbch->ndesc; 1427103285Sikob if(&sc->arrq == dbch){ 1428103285Sikob off = OHCI_ARQOFF; 1429103285Sikob }else if(&sc->arrs == dbch){ 1430103285Sikob off = OHCI_ARSOFF; 1431103285Sikob }else{ 1432103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1433103285Sikob if( &sc->ir[dmach] == dbch){ 1434103285Sikob off = OHCI_IROFF(dmach); 1435103285Sikob break; 1436103285Sikob } 1437103285Sikob } 1438103285Sikob } 1439123740Speter if(off == 0){ 1440103285Sikob err = EINVAL; 1441103285Sikob return err; 1442103285Sikob } 1443103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1444103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1445103285Sikob return err; 1446103285Sikob }else{ 1447103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1448103285Sikob err = EBUSY; 1449103285Sikob return err; 1450103285Sikob } 1451103285Sikob } 1452103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1453108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1454103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1455103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1456103285Sikob } 1457103285Sikob db_tr = dbch->top; 1458113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1459113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1460113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1461103285Sikob break; 1462109892Ssimokawa db = db_tr->db; 1463109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1464113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1465113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1466103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1467103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1468113584Ssimokawa FWOHCI_DMA_SET( 1469113584Ssimokawa db[ldesc].db.desc.cmd, 1470113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1471113584Ssimokawa FWOHCI_DMA_CLEAR( 1472113584Ssimokawa db[ldesc].db.desc.depend, 1473113584Ssimokawa 0xf); 1474103285Sikob } 1475103285Sikob } 1476103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1477103285Sikob } 1478113584Ssimokawa FWOHCI_DMA_CLEAR( 1479113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1480103285Sikob dbch->buf_offset = 0; 1481113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1482113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1483103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1484103285Sikob return err; 1485103285Sikob }else{ 1486113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1487103285Sikob } 1488103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1489103285Sikob return err; 1490103285Sikob} 1491106790Ssimokawa 1492106790Ssimokawastatic int 1493113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1494109890Ssimokawa{ 1495109890Ssimokawa int sec, cycle, cycle_match; 1496109890Ssimokawa 1497109890Ssimokawa cycle = cycle_now & 0x1fff; 1498109890Ssimokawa sec = cycle_now >> 13; 1499109890Ssimokawa#define CYCLE_MOD 0x10 1500113584Ssimokawa#if 1 1501109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1502113584Ssimokawa#else 1503113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1504113584Ssimokawa#endif 1505109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1506109890Ssimokawa if (cycle >= 8000) { 1507109890Ssimokawa sec ++; 1508109890Ssimokawa cycle -= 8000; 1509109890Ssimokawa } 1510113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1511109890Ssimokawa if (cycle >= 8000) { 1512109890Ssimokawa sec ++; 1513109890Ssimokawa if (cycle == 8000) 1514109890Ssimokawa cycle = 0; 1515109890Ssimokawa else 1516109890Ssimokawa cycle = CYCLE_MOD; 1517109890Ssimokawa } 1518109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1519109890Ssimokawa 1520109890Ssimokawa return(cycle_match); 1521109890Ssimokawa} 1522109890Ssimokawa 1523109890Ssimokawastatic int 1524106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1525103285Sikob{ 1526103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1527103285Sikob int err = 0; 1528103285Sikob unsigned short tag, ich; 1529103285Sikob struct fwohci_dbch *dbch; 1530109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1531129585Sdfr uint32_t stat; 1532109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1533109890Ssimokawa struct fw_xferq *it; 1534103285Sikob 1535103285Sikob dbch = &sc->it[dmach]; 1536109890Ssimokawa it = &dbch->xferq; 1537109890Ssimokawa 1538109890Ssimokawa tag = (it->flag >> 6) & 3; 1539109890Ssimokawa ich = it->flag & 0x3f; 1540109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1541109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1542103285Sikob dbch->ndesc = 3; 1543113584Ssimokawa fwohci_db_init(sc, dbch); 1544109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1545109179Ssimokawa return ENOMEM; 1546170374Ssimokawa 1547103285Sikob err = fwohci_tx_enable(sc, dbch); 1548103285Sikob } 1549103285Sikob if(err) 1550103285Sikob return err; 1551109890Ssimokawa 1552109892Ssimokawa ldesc = dbch->ndesc - 1; 1553109890Ssimokawa s = splfw(); 1554170374Ssimokawa FW_GLOCK(fc); 1555109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1556109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1557120660Ssimokawa struct fwohcidb *db; 1558109890Ssimokawa 1559113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1560113584Ssimokawa BUS_DMASYNC_PREWRITE); 1561109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1562109890Ssimokawa if (prev != NULL) { 1563109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1564113584Ssimokawa#if 0 /* XXX necessary? */ 1565113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1566113584Ssimokawa OHCI_BRANCH_ALWAYS); 1567113584Ssimokawa#endif 1568109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1569109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1570113584Ssimokawa ((struct fwohcidb_tr *) 1571113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1572109892Ssimokawa#else 1573113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1574113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1575109892Ssimokawa#endif 1576103285Sikob } 1577109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1578109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1579109890Ssimokawa prev = chunk; 1580109403Ssimokawa } 1581170374Ssimokawa FW_GUNLOCK(fc); 1582113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1583113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1584109890Ssimokawa splx(s); 1585109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1586113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1587113584Ssimokawa printf("stat 0x%x\n", stat); 1588113584Ssimokawa 1589109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1590109890Ssimokawa return 0; 1591109890Ssimokawa 1592113584Ssimokawa#if 0 1593109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1594113584Ssimokawa#endif 1595109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1596109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1597109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1598113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1599109890Ssimokawa 1600109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1601113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1602113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1603167629Ssimokawa if (firewire_debug > 1) { 1604109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1605113584Ssimokawa#if 1 1606113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1607113584Ssimokawa#endif 1608113584Ssimokawa } 1609109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1610109890Ssimokawa#if 1 1611109890Ssimokawa /* Don't start until all chunks are buffered */ 1612109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1613109890Ssimokawa goto out; 1614109890Ssimokawa#endif 1615113584Ssimokawa#if 1 1616109890Ssimokawa /* Clear cycle match counter bits */ 1617109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1618109890Ssimokawa 1619109356Ssimokawa /* 2bit second + 13bit cycle */ 1620109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1621113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1622109890Ssimokawa 1623109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1624109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1625109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1626113584Ssimokawa#else 1627113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1628113584Ssimokawa#endif 1629167629Ssimokawa if (firewire_debug > 1) { 1630109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1631109403Ssimokawa cycle_now, cycle_match); 1632113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1633113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1634113584Ssimokawa } 1635109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1636109890Ssimokawa device_printf(sc->fc.dev, 1637109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1638113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1639103285Sikob } 1640109890Ssimokawaout: 1641103285Sikob return err; 1642103285Sikob} 1643106790Ssimokawa 1644106790Ssimokawastatic int 1645113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1646103285Sikob{ 1647103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1648109890Ssimokawa int err = 0, s, ldesc; 1649103285Sikob unsigned short tag, ich; 1650129585Sdfr uint32_t stat; 1651109890Ssimokawa struct fwohci_dbch *dbch; 1652113584Ssimokawa struct fwohcidb_tr *db_tr; 1653109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1654109890Ssimokawa struct fw_xferq *ir; 1655103285Sikob 1656109890Ssimokawa dbch = &sc->ir[dmach]; 1657109890Ssimokawa ir = &dbch->xferq; 1658109890Ssimokawa 1659109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1660109890Ssimokawa tag = (ir->flag >> 6) & 3; 1661109890Ssimokawa ich = ir->flag & 0x3f; 1662108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1663108995Ssimokawa 1664109890Ssimokawa ir->queued = 0; 1665109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1666109890Ssimokawa dbch->ndesc = 2; 1667113584Ssimokawa fwohci_db_init(sc, dbch); 1668109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1669109179Ssimokawa return ENOMEM; 1670109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1671103285Sikob } 1672103285Sikob if(err) 1673103285Sikob return err; 1674103285Sikob 1675109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1676109890Ssimokawa if (first == NULL) { 1677109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1678109890Ssimokawa return 0; 1679109890Ssimokawa } 1680109890Ssimokawa 1681111892Ssimokawa ldesc = dbch->ndesc - 1; 1682111892Ssimokawa s = splfw(); 1683170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 1684170374Ssimokawa FW_GLOCK(fc); 1685109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1686109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1687120660Ssimokawa struct fwohcidb *db; 1688109890Ssimokawa 1689111942Ssimokawa#if 1 /* XXX for if_fwe */ 1690113584Ssimokawa if (chunk->mbuf != NULL) { 1691113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1692113584Ssimokawa db_tr->dbcnt = 1; 1693113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1694113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1695113584Ssimokawa /* flags */0); 1696113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1697113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1698113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1699113584Ssimokawa } 1700111942Ssimokawa#endif 1701109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1702113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1703113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1704109890Ssimokawa if (prev != NULL) { 1705109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1706113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1707103285Sikob } 1708109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1709109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1710109890Ssimokawa prev = chunk; 1711103285Sikob } 1712170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 1713170374Ssimokawa FW_GUNLOCK(fc); 1714113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1715113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1716109890Ssimokawa splx(s); 1717109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1718109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1719109890Ssimokawa return 0; 1720109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1721109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1722109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1723109890Ssimokawa } 1724109890Ssimokawa 1725113584Ssimokawa if (firewire_debug) 1726113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1727109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1728109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1729109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1730109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1731109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1732109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1733113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1734109890Ssimokawa | dbch->ndesc); 1735109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1736109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1737113584Ssimokawa#if 0 1738113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1739113584Ssimokawa#endif 1740103285Sikob return err; 1741103285Sikob} 1742106790Ssimokawa 1743106790Ssimokawaint 1744110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1745103285Sikob{ 1746103285Sikob u_int i; 1747103285Sikob 1748178911Ssimokawa fwohci_set_intr(&sc->fc, 0); 1749178911Ssimokawa 1750103285Sikob/* Now stopping all DMA channel */ 1751103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1752103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1753103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1754103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1755103285Sikob 1756103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1757103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1758103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1759103285Sikob } 1760103285Sikob 1761170374Ssimokawa#if 0 /* Let dcons(4) be accessed */ 1762103285Sikob/* Stop interrupt */ 1763103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1764103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1765103285Sikob | OHCI_INT_PHY_INT 1766103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1767103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1768103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1769103285Sikob | OHCI_INT_PHY_BUS_R); 1770116978Ssimokawa 1771170374Ssimokawa/* FLUSH FIFO and reset Transmitter/Reciever */ 1772170374Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1773170374Ssimokawa#endif 1774116978Ssimokawa 1775108642Ssimokawa/* XXX Link down? Bus reset? */ 1776103285Sikob return 0; 1777103285Sikob} 1778103285Sikob 1779108642Ssimokawaint 1780108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1781108642Ssimokawa{ 1782108642Ssimokawa int i; 1783116978Ssimokawa struct fw_xferq *ir; 1784116978Ssimokawa struct fw_bulkxfer *chunk; 1785108642Ssimokawa 1786108642Ssimokawa fwohci_reset(sc, dev); 1787129541Sdfr /* XXX resume isochronous receive automatically. (how about TX?) */ 1788108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1789116978Ssimokawa ir = &sc->ir[i].xferq; 1790116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1791108642Ssimokawa device_printf(sc->fc.dev, 1792108642Ssimokawa "resume iso receive ch: %d\n", i); 1793116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1794116978Ssimokawa /* requeue stdma to stfree */ 1795116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1796116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1797116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1798116978Ssimokawa } 1799108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1800108642Ssimokawa } 1801108642Ssimokawa } 1802108642Ssimokawa 1803108642Ssimokawa bus_generic_resume(dev); 1804108642Ssimokawa sc->fc.ibr(&sc->fc); 1805108642Ssimokawa return 0; 1806108642Ssimokawa} 1807108642Ssimokawa 1808170374Ssimokawa#ifdef OHCI_DEBUG 1809103285Sikobstatic void 1810170374Ssimokawafwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat) 1811103285Sikob{ 1812103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1813103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1814103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1815103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1816103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1817103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1818103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1819103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1820103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1821103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1822103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1823103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1824103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1825103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1826103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1827103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1828103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1829103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1830103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1831103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1832103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1833103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1834103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1835103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1836103285Sikob ); 1837170374Ssimokawa} 1838103285Sikob#endif 1839170374Ssimokawastatic void 1840170374Ssimokawafwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count) 1841170374Ssimokawa{ 1842170374Ssimokawa struct firewire_comm *fc = (struct firewire_comm *)sc; 1843170374Ssimokawa uint32_t node_id, plen; 1844170374Ssimokawa 1845187993Ssbruno FW_GLOCK_ASSERT(fc); 1846170374Ssimokawa if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) { 1847170374Ssimokawa fc->status = FWBUSRESET; 1848111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1849111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1850111074Ssimokawa 1851103285Sikob device_printf(fc->dev, "BUS reset\n"); 1852103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1853103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1854103285Sikob 1855103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1856103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1857103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1858103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1859103285Sikob 1860170374Ssimokawa if (!kdb_active) 1861170374Ssimokawa taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset); 1862170374Ssimokawa } 1863170374Ssimokawa if (stat & OHCI_INT_PHY_SID) { 1864170374Ssimokawa /* Enable bus reset interrupt */ 1865103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1866170374Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1867170374Ssimokawa 1868170374Ssimokawa /* Allow async. request to us */ 1869170374Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1870170400Ssimokawa if (firewire_phydma_enable) { 1871170400Ssimokawa /* allow from all nodes */ 1872170400Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1873170400Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1874170400Ssimokawa /* 0 to 4GB region */ 1875170400Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1876170400Ssimokawa } 1877170374Ssimokawa /* Set ATRetries register */ 1878170374Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1879170374Ssimokawa 1880170374Ssimokawa /* 1881170374Ssimokawa * Checking whether the node is root or not. If root, turn on 1882170374Ssimokawa * cycle master. 1883170374Ssimokawa */ 1884170374Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1885170374Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1886170374Ssimokawa 1887170374Ssimokawa fc->nodeid = node_id & 0x3f; 1888187993Ssbruno device_printf(fc->dev, "node_id=0x%08x, SelfID Count=%d, ", 1889187993Ssbruno fc->nodeid, (plen >> 16) & 0xff); 1890170374Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1891170374Ssimokawa printf("Bus reset failure\n"); 1892170374Ssimokawa goto sidout; 1893170374Ssimokawa } 1894170374Ssimokawa 1895170374Ssimokawa /* cycle timer */ 1896170374Ssimokawa sc->cycle_lost = 0; 1897170374Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 1898170374Ssimokawa if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 1899170374Ssimokawa printf("CYCLEMASTER mode\n"); 1900170374Ssimokawa OWRITE(sc, OHCI_LNKCTL, 1901170374Ssimokawa OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1902170374Ssimokawa } else { 1903170374Ssimokawa printf("non CYCLEMASTER mode\n"); 1904170374Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1905170374Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1906170374Ssimokawa } 1907170374Ssimokawa 1908170374Ssimokawa fc->status = FWBUSINIT; 1909170374Ssimokawa 1910170374Ssimokawa if (!kdb_active) 1911170374Ssimokawa taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid); 1912103285Sikob } 1913170374Ssimokawasidout: 1914170374Ssimokawa if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active)) 1915170374Ssimokawa taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma); 1916170374Ssimokawa} 1917170374Ssimokawa 1918170374Ssimokawastatic void 1919170374Ssimokawafwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count) 1920170374Ssimokawa{ 1921170374Ssimokawa uint32_t irstat, itstat; 1922170374Ssimokawa u_int i; 1923170374Ssimokawa struct firewire_comm *fc = (struct firewire_comm *)sc; 1924170374Ssimokawa 1925170374Ssimokawa if (stat & OHCI_INT_DMA_IR) { 1926127468Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1927103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1928109644Ssimokawa struct fwohci_dbch *dbch; 1929109644Ssimokawa 1930103285Sikob if((irstat & (1 << i)) != 0){ 1931109644Ssimokawa dbch = &sc->ir[i]; 1932109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1933109644Ssimokawa device_printf(sc->fc.dev, 1934109644Ssimokawa "dma(%d) not active\n", i); 1935109644Ssimokawa continue; 1936109644Ssimokawa } 1937113584Ssimokawa fwohci_rbuf_update(sc, i); 1938103285Sikob } 1939103285Sikob } 1940103285Sikob } 1941170374Ssimokawa if (stat & OHCI_INT_DMA_IT) { 1942127468Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1943103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1944103285Sikob if((itstat & (1 << i)) != 0){ 1945103285Sikob fwohci_tbuf_update(sc, i); 1946103285Sikob } 1947103285Sikob } 1948103285Sikob } 1949170374Ssimokawa if (stat & OHCI_INT_DMA_PRRS) { 1950103285Sikob#if 0 1951103285Sikob dump_dma(sc, ARRS_CH); 1952103285Sikob dump_db(sc, ARRS_CH); 1953103285Sikob#endif 1954106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1955103285Sikob } 1956170374Ssimokawa if (stat & OHCI_INT_DMA_PRRQ) { 1957103285Sikob#if 0 1958103285Sikob dump_dma(sc, ARRQ_CH); 1959103285Sikob dump_db(sc, ARRQ_CH); 1960103285Sikob#endif 1961106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1962103285Sikob } 1963167628Ssimokawa if (stat & OHCI_INT_CYC_LOST) { 1964167628Ssimokawa if (sc->cycle_lost >= 0) 1965167628Ssimokawa sc->cycle_lost ++; 1966167628Ssimokawa if (sc->cycle_lost > 10) { 1967167628Ssimokawa sc->cycle_lost = -1; 1968167628Ssimokawa#if 0 1969167628Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1970167628Ssimokawa#endif 1971167628Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1972167628Ssimokawa device_printf(fc->dev, "too many cycle lost, " 1973167628Ssimokawa "no cycle master presents?\n"); 1974167628Ssimokawa } 1975167628Ssimokawa } 1976170374Ssimokawa if (stat & OHCI_INT_DMA_ATRQ) { 1977103285Sikob fwohci_txd(sc, &(sc->atrq)); 1978103285Sikob } 1979170374Ssimokawa if (stat & OHCI_INT_DMA_ATRS) { 1980103285Sikob fwohci_txd(sc, &(sc->atrs)); 1981103285Sikob } 1982170374Ssimokawa if (stat & OHCI_INT_PW_ERR) { 1983103285Sikob device_printf(fc->dev, "posted write error\n"); 1984103285Sikob } 1985170374Ssimokawa if (stat & OHCI_INT_ERR) { 1986103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1987103285Sikob } 1988170374Ssimokawa if (stat & OHCI_INT_PHY_INT) { 1989103285Sikob device_printf(fc->dev, "phy int\n"); 1990103285Sikob } 1991103285Sikob 1992103285Sikob return; 1993103285Sikob} 1994103285Sikob 1995113584Ssimokawastatic void 1996170374Ssimokawafwohci_task_busreset(void *arg, int pending) 1997113584Ssimokawa{ 1998113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1999170374Ssimokawa 2000187993Ssbruno FW_GLOCK(&sc->fc); 2001170374Ssimokawa fw_busreset(&sc->fc, FWBUSRESET); 2002170374Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2003170374Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2004187993Ssbruno FW_GUNLOCK(&sc->fc); 2005170374Ssimokawa} 2006170374Ssimokawa 2007170374Ssimokawastatic void 2008170374Ssimokawafwohci_task_sid(void *arg, int pending) 2009170374Ssimokawa{ 2010170374Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2011170374Ssimokawa struct firewire_comm *fc = &sc->fc; 2012170374Ssimokawa uint32_t *buf; 2013170374Ssimokawa int i, plen; 2014170374Ssimokawa 2015170374Ssimokawa 2016187993Ssbruno /* 2017187993Ssbruno * We really should have locking 2018187993Ssbruno * here. Not sure why it's not 2019187993Ssbruno */ 2020170374Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 2021170374Ssimokawa 2022170374Ssimokawa if (plen & OHCI_SID_ERR) { 2023170374Ssimokawa device_printf(fc->dev, "SID Error\n"); 2024170374Ssimokawa return; 2025170374Ssimokawa } 2026170374Ssimokawa plen &= OHCI_SID_CNT_MASK; 2027170374Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 2028170374Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 2029170374Ssimokawa return; 2030170374Ssimokawa } 2031170374Ssimokawa plen -= 4; /* chop control info */ 2032170374Ssimokawa buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2033170374Ssimokawa if (buf == NULL) { 2034170374Ssimokawa device_printf(fc->dev, "malloc failed\n"); 2035170374Ssimokawa return; 2036170374Ssimokawa } 2037170374Ssimokawa for (i = 0; i < plen / 4; i ++) 2038170374Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2039187993Ssbruno 2040170374Ssimokawa /* pending all pre-bus_reset packets */ 2041170374Ssimokawa fwohci_txd(sc, &sc->atrq); 2042170374Ssimokawa fwohci_txd(sc, &sc->atrs); 2043170374Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 2044170374Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 2045170374Ssimokawa fw_drain_txq(fc); 2046170374Ssimokawa fw_sidrcv(fc, buf, plen); 2047170374Ssimokawa free(buf, M_FW); 2048170374Ssimokawa} 2049170374Ssimokawa 2050170374Ssimokawastatic void 2051170374Ssimokawafwohci_task_dma(void *arg, int pending) 2052170374Ssimokawa{ 2053170374Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2054129585Sdfr uint32_t stat; 2055113584Ssimokawa 2056113584Ssimokawaagain: 2057113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 2058113584Ssimokawa if (stat) 2059170374Ssimokawa fwohci_intr_dma(sc, stat, -1); 2060113584Ssimokawa else 2061113584Ssimokawa return; 2062113584Ssimokawa goto again; 2063113584Ssimokawa} 2064113584Ssimokawa 2065170374Ssimokawastatic int 2066170374Ssimokawafwohci_check_stat(struct fwohci_softc *sc) 2067113584Ssimokawa{ 2068129585Sdfr uint32_t stat, irstat, itstat; 2069113584Ssimokawa 2070187993Ssbruno FW_GLOCK_ASSERT(&sc->fc); 2071113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 2072113584Ssimokawa if (stat == 0xffffffff) { 2073113584Ssimokawa device_printf(sc->fc.dev, 2074113584Ssimokawa "device physically ejected?\n"); 2075170374Ssimokawa return (FILTER_STRAY); 2076113584Ssimokawa } 2077113584Ssimokawa if (stat) 2078170374Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R); 2079170374Ssimokawa 2080170374Ssimokawa stat &= sc->intmask; 2081170374Ssimokawa if (stat == 0) 2082170374Ssimokawa return (FILTER_STRAY); 2083170374Ssimokawa 2084170374Ssimokawa atomic_set_int(&sc->intstat, stat); 2085113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2086113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2087113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2088113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2089113584Ssimokawa } 2090113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2091113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2092113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2093113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2094113584Ssimokawa } 2095170374Ssimokawa 2096170374Ssimokawa fwohci_intr_core(sc, stat, -1); 2097170374Ssimokawa return (FILTER_HANDLED); 2098113584Ssimokawa} 2099113584Ssimokawa 2100187993Ssbrunovoid 2101187993Ssbrunofwohci_intr(void *arg) 2102103285Sikob{ 2103103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2104103285Sikob 2105187993Ssbruno FW_GLOCK(&sc->fc); 2106187993Ssbruno fwohci_check_stat(sc); 2107187993Ssbruno FW_GUNLOCK(&sc->fc); 2108170374Ssimokawa} 2109103285Sikob 2110170374Ssimokawavoid 2111103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2112103285Sikob{ 2113170374Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)fc; 2114187993Ssbruno 2115187993Ssbruno FW_GLOCK(fc); 2116170374Ssimokawa fwohci_check_stat(sc); 2117187993Ssbruno FW_GUNLOCK(fc); 2118103285Sikob} 2119103285Sikob 2120103285Sikobstatic void 2121103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2122103285Sikob{ 2123103285Sikob struct fwohci_softc *sc; 2124103285Sikob 2125103285Sikob sc = (struct fwohci_softc *)fc; 2126132432Ssimokawa if (firewire_debug) 2127108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2128103285Sikob if (enable) { 2129103285Sikob sc->intmask |= OHCI_INT_EN; 2130103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2131103285Sikob } else { 2132103285Sikob sc->intmask &= ~OHCI_INT_EN; 2133103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2134103285Sikob } 2135103285Sikob} 2136103285Sikob 2137106790Ssimokawastatic void 2138106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2139103285Sikob{ 2140103285Sikob struct firewire_comm *fc = &sc->fc; 2141120660Ssimokawa struct fwohcidb *db; 2142109890Ssimokawa struct fw_bulkxfer *chunk; 2143109890Ssimokawa struct fw_xferq *it; 2144129585Sdfr uint32_t stat, count; 2145113584Ssimokawa int s, w=0, ldesc; 2146103285Sikob 2147109890Ssimokawa it = fc->it[dmach]; 2148113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2149109890Ssimokawa s = splfw(); /* unnecessary ? */ 2150170374Ssimokawa FW_GLOCK(fc); 2151113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2152119155Ssimokawa if (firewire_debug) 2153119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2154109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2155109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2156113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2157113584Ssimokawa >> OHCI_STATUS_SHIFT; 2158109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2159119155Ssimokawa /* timestamp */ 2160113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2161113584Ssimokawa & OHCI_COUNT_MASK; 2162109890Ssimokawa if (stat == 0) 2163109890Ssimokawa break; 2164109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2165109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2166109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2167109890Ssimokawa#if 0 2168109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2169109179Ssimokawa#endif 2170109890Ssimokawa break; 2171109890Ssimokawa default: 2172109423Ssimokawa device_printf(fc->dev, 2173113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2174113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2175109890Ssimokawa } 2176109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2177109890Ssimokawa w++; 2178109403Ssimokawa } 2179170374Ssimokawa FW_GUNLOCK(fc); 2180109890Ssimokawa splx(s); 2181109890Ssimokawa if (w) 2182109890Ssimokawa wakeup(it); 2183103285Sikob} 2184106790Ssimokawa 2185106790Ssimokawastatic void 2186106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2187103285Sikob{ 2188109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2189120660Ssimokawa struct fwohcidb_tr *db_tr; 2190109890Ssimokawa struct fw_bulkxfer *chunk; 2191109890Ssimokawa struct fw_xferq *ir; 2192129585Sdfr uint32_t stat; 2193170374Ssimokawa int s, w = 0, ldesc; 2194109179Ssimokawa 2195109890Ssimokawa ir = fc->ir[dmach]; 2196113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2197170374Ssimokawa 2198113584Ssimokawa#if 0 2199113584Ssimokawa dump_db(sc, dmach); 2200113584Ssimokawa#endif 2201109890Ssimokawa s = splfw(); 2202170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 2203170374Ssimokawa FW_GLOCK(fc); 2204113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2205109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2206113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2207113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2208113584Ssimokawa >> OHCI_STATUS_SHIFT; 2209109890Ssimokawa if (stat == 0) 2210109890Ssimokawa break; 2211113584Ssimokawa 2212113584Ssimokawa if (chunk->mbuf != NULL) { 2213113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2214113584Ssimokawa BUS_DMASYNC_POSTREAD); 2215113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2216113584Ssimokawa } else if (ir->buf != NULL) { 2217113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2218113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2219113584Ssimokawa } else { 2220113584Ssimokawa /* XXX */ 2221113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2222113584Ssimokawa } 2223113584Ssimokawa 2224109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2225109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2226109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2227109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2228111942Ssimokawa chunk->resp = 0; 2229109890Ssimokawa break; 2230109890Ssimokawa default: 2231111942Ssimokawa chunk->resp = EINVAL; 2232109890Ssimokawa device_printf(fc->dev, 2233113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2234113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2235109890Ssimokawa } 2236109890Ssimokawa w++; 2237103285Sikob } 2238170374Ssimokawa if ((ir->flag & FWXFERQ_HANDLER) == 0) 2239170374Ssimokawa FW_GUNLOCK(fc); 2240109890Ssimokawa splx(s); 2241170374Ssimokawa if (w == 0) 2242170374Ssimokawa return; 2243170374Ssimokawa 2244170374Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2245170374Ssimokawa ir->hand(ir); 2246170374Ssimokawa else 2247170374Ssimokawa wakeup(ir); 2248103285Sikob} 2249106790Ssimokawa 2250106790Ssimokawavoid 2251129585Sdfrdump_dma(struct fwohci_softc *sc, uint32_t ch) 2252106790Ssimokawa{ 2253129585Sdfr uint32_t off, cntl, stat, cmd, match; 2254103285Sikob 2255103285Sikob if(ch == 0){ 2256103285Sikob off = OHCI_ATQOFF; 2257103285Sikob }else if(ch == 1){ 2258103285Sikob off = OHCI_ATSOFF; 2259103285Sikob }else if(ch == 2){ 2260103285Sikob off = OHCI_ARQOFF; 2261103285Sikob }else if(ch == 3){ 2262103285Sikob off = OHCI_ARSOFF; 2263103285Sikob }else if(ch < IRX_CH){ 2264103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2265103285Sikob }else{ 2266103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2267103285Sikob } 2268103285Sikob cntl = stat = OREAD(sc, off); 2269103285Sikob cmd = OREAD(sc, off + 0xc); 2270103285Sikob match = OREAD(sc, off + 0x10); 2271103285Sikob 2272113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2273103285Sikob ch, 2274103285Sikob cntl, 2275103285Sikob cmd, 2276103285Sikob match); 2277103285Sikob stat &= 0xffff ; 2278113584Ssimokawa if (stat) { 2279103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2280103285Sikob ch, 2281103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2282103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2283103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2284103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2285103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2286103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2287103285Sikob fwohcicode[stat & 0x1f], 2288103285Sikob stat & 0x1f 2289103285Sikob ); 2290103285Sikob }else{ 2291103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2292103285Sikob } 2293103285Sikob} 2294106790Ssimokawa 2295106790Ssimokawavoid 2296129585Sdfrdump_db(struct fwohci_softc *sc, uint32_t ch) 2297106790Ssimokawa{ 2298103285Sikob struct fwohci_dbch *dbch; 2299113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2300120660Ssimokawa struct fwohcidb *curr = NULL, *prev, *next = NULL; 2301103285Sikob int idb, jdb; 2302129585Sdfr uint32_t cmd, off; 2303103285Sikob if(ch == 0){ 2304103285Sikob off = OHCI_ATQOFF; 2305103285Sikob dbch = &sc->atrq; 2306103285Sikob }else if(ch == 1){ 2307103285Sikob off = OHCI_ATSOFF; 2308103285Sikob dbch = &sc->atrs; 2309103285Sikob }else if(ch == 2){ 2310103285Sikob off = OHCI_ARQOFF; 2311103285Sikob dbch = &sc->arrq; 2312103285Sikob }else if(ch == 3){ 2313103285Sikob off = OHCI_ARSOFF; 2314103285Sikob dbch = &sc->arrs; 2315103285Sikob }else if(ch < IRX_CH){ 2316103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2317103285Sikob dbch = &sc->it[ch - ITX_CH]; 2318103285Sikob }else { 2319103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2320103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2321103285Sikob } 2322103285Sikob cmd = OREAD(sc, off + 0xc); 2323103285Sikob 2324103285Sikob if( dbch->ndb == 0 ){ 2325103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2326103285Sikob return; 2327103285Sikob } 2328103285Sikob pp = dbch->top; 2329103285Sikob prev = pp->db; 2330103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2331103285Sikob cp = STAILQ_NEXT(pp, link); 2332103285Sikob if(cp == NULL){ 2333103285Sikob curr = NULL; 2334103285Sikob goto outdb; 2335103285Sikob } 2336103285Sikob np = STAILQ_NEXT(cp, link); 2337103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2338113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2339103285Sikob curr = cp->db; 2340103285Sikob if(np != NULL){ 2341103285Sikob next = np->db; 2342103285Sikob }else{ 2343103285Sikob next = NULL; 2344103285Sikob } 2345103285Sikob goto outdb; 2346103285Sikob } 2347103285Sikob } 2348103285Sikob pp = STAILQ_NEXT(pp, link); 2349144263Ssam if(pp == NULL){ 2350144263Ssam curr = NULL; 2351144263Ssam goto outdb; 2352144263Ssam } 2353103285Sikob prev = pp->db; 2354103285Sikob } 2355103285Sikoboutdb: 2356103285Sikob if( curr != NULL){ 2357113584Ssimokawa#if 0 2358103285Sikob printf("Prev DB %d\n", ch); 2359113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2360113584Ssimokawa#endif 2361103285Sikob printf("Current DB %d\n", ch); 2362113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2363113584Ssimokawa#if 0 2364103285Sikob printf("Next DB %d\n", ch); 2365113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2366113584Ssimokawa#endif 2367103285Sikob }else{ 2368103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2369103285Sikob } 2370103285Sikob return; 2371103285Sikob} 2372106790Ssimokawa 2373106790Ssimokawavoid 2374120660Ssimokawaprint_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2375129585Sdfr uint32_t ch, uint32_t max) 2376106790Ssimokawa{ 2377103285Sikob fwohcireg_t stat; 2378103285Sikob int i, key; 2379129585Sdfr uint32_t cmd, res; 2380103285Sikob 2381103285Sikob if(db == NULL){ 2382103285Sikob printf("No Descriptor is found\n"); 2383103285Sikob return; 2384103285Sikob } 2385103285Sikob 2386103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2387103285Sikob ch, 2388103285Sikob "Current", 2389103285Sikob "OP ", 2390103285Sikob "KEY", 2391103285Sikob "INT", 2392103285Sikob "BR ", 2393103285Sikob "len", 2394103285Sikob "Addr", 2395103285Sikob "Depend", 2396103285Sikob "Stat", 2397103285Sikob "Cnt"); 2398103285Sikob for( i = 0 ; i <= max ; i ++){ 2399113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2400113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2401113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2402113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2403127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 2404127468Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2405127468Ssimokawa db_tr->bus_addr, 2406127468Ssimokawa#else 2407113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2408114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2409108712Ssimokawa#endif 2410113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2411113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2412113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2413113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2414113584Ssimokawa cmd & OHCI_COUNT_MASK, 2415113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2416113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2417113584Ssimokawa stat, 2418113584Ssimokawa res & OHCI_COUNT_MASK); 2419103285Sikob if(stat & 0xff00){ 2420103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2421103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2422103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2423103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2424103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2425103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2426103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2427103285Sikob fwohcicode[stat & 0x1f], 2428103285Sikob stat & 0x1f 2429103285Sikob ); 2430103285Sikob }else{ 2431103285Sikob printf(" Nostat\n"); 2432103285Sikob } 2433103285Sikob if(key == OHCI_KEY_ST2 ){ 2434103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2435113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2436113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2437113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2438113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2439103285Sikob } 2440103285Sikob if(key == OHCI_KEY_DEVICE){ 2441103285Sikob return; 2442103285Sikob } 2443113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2444103285Sikob == OHCI_BRANCH_ALWAYS){ 2445103285Sikob return; 2446103285Sikob } 2447113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2448103285Sikob == OHCI_OUTPUT_LAST){ 2449103285Sikob return; 2450103285Sikob } 2451113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2452103285Sikob == OHCI_INPUT_LAST){ 2453103285Sikob return; 2454103285Sikob } 2455103285Sikob if(key == OHCI_KEY_ST2 ){ 2456103285Sikob i++; 2457103285Sikob } 2458103285Sikob } 2459103285Sikob return; 2460103285Sikob} 2461106790Ssimokawa 2462106790Ssimokawavoid 2463106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2464103285Sikob{ 2465103285Sikob struct fwohci_softc *sc; 2466129585Sdfr uint32_t fun; 2467103285Sikob 2468110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2469103285Sikob sc = (struct fwohci_softc *)fc; 2470108276Ssimokawa 2471187993Ssbruno FW_GLOCK(fc); 2472108276Ssimokawa /* 2473129611Sdfr * Make sure our cached values from the config rom are 2474129611Sdfr * initialised. 2475129611Sdfr */ 2476129611Sdfr OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2477129611Sdfr OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2478129611Sdfr 2479129611Sdfr /* 2480108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2481108276Ssimokawa * shouldn't became the root node. 2482108276Ssimokawa */ 2483103285Sikob#if 1 2484103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2485109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2486103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2487109280Ssimokawa#else /* Short bus reset */ 2488103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2489109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2490103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2491103285Sikob#endif 2492187993Ssbruno FW_GUNLOCK(fc); 2493103285Sikob} 2494106790Ssimokawa 2495106790Ssimokawavoid 2496106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2497103285Sikob{ 2498103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2499103285Sikob struct fwohci_dbch *dbch; 2500120660Ssimokawa struct fwohcidb *db; 2501103285Sikob struct fw_pkt *fp; 2502120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 2503103285Sikob unsigned short chtag; 2504103285Sikob int idb; 2505103285Sikob 2506170374Ssimokawa FW_GLOCK_ASSERT(&sc->fc); 2507170374Ssimokawa 2508103285Sikob dbch = &sc->it[dmach]; 2509103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2510103285Sikob 2511103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2512103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2513103285Sikob/* 2514113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2515103285Sikob*/ 2516113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2517109892Ssimokawa db = db_tr->db; 2518103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2519120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2520113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2521119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2522113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2523103285Sikob ohcifp->mode.stream.chtag = chtag; 2524103285Sikob ohcifp->mode.stream.tcode = 0xa; 2525113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2526113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2527113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2528113584Ssimokawa#endif 2529103285Sikob 2530113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2531113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2532113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2533109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2534113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2535103285Sikob | OHCI_UPDATE 2536109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2537109892Ssimokawa db[0].db.desc.depend = 2538109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2539113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2540109892Ssimokawa#else 2541113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2542113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2543109892Ssimokawa#endif 2544103285Sikob bulkxfer->end = (caddr_t)db_tr; 2545103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2546103285Sikob } 2547109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2548113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2549113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2550109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2551109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2552109280Ssimokawa /* OHCI 1.1 and above */ 2553109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2554109892Ssimokawa#endif 2555109892Ssimokawa/* 2556103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2557103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2558113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2559103285Sikob*/ 2560103285Sikob return; 2561103285Sikob} 2562106790Ssimokawa 2563106790Ssimokawastatic int 2564113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2565113584Ssimokawa int poffset) 2566103285Sikob{ 2567120660Ssimokawa struct fwohcidb *db = db_tr->db; 2568113584Ssimokawa struct fw_xferq *it; 2569103285Sikob int err = 0; 2570113584Ssimokawa 2571113584Ssimokawa it = &dbch->xferq; 2572113584Ssimokawa if(it->buf == 0){ 2573103285Sikob err = EINVAL; 2574103285Sikob return err; 2575103285Sikob } 2576113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2577103285Sikob db_tr->dbcnt = 3; 2578103285Sikob 2579113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2580113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2581119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2582120660Ssimokawa bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2583113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2584129585Sdfr fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2585113584Ssimokawa 2586113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2587113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2588109892Ssimokawa#if 1 2589113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2590113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2591109892Ssimokawa#endif 2592113584Ssimokawa return 0; 2593103285Sikob} 2594106790Ssimokawa 2595106790Ssimokawaint 2596113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2597113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2598103285Sikob{ 2599120660Ssimokawa struct fwohcidb *db = db_tr->db; 2600113584Ssimokawa struct fw_xferq *ir; 2601113584Ssimokawa int i, ldesc; 2602113584Ssimokawa bus_addr_t dbuf[2]; 2603103285Sikob int dsiz[2]; 2604103285Sikob 2605113584Ssimokawa ir = &dbch->xferq; 2606113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2607178911Ssimokawa if (db_tr->buf == NULL) { 2608178911Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, 2609178911Ssimokawa &db_tr->dma_map, ir->psize, &dbuf[0], 2610178911Ssimokawa BUS_DMA_NOWAIT); 2611178911Ssimokawa if (db_tr->buf == NULL) 2612178911Ssimokawa return(ENOMEM); 2613178911Ssimokawa } 2614103285Sikob db_tr->dbcnt = 1; 2615113584Ssimokawa dsiz[0] = ir->psize; 2616113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2617113584Ssimokawa BUS_DMASYNC_PREREAD); 2618113584Ssimokawa } else { 2619113584Ssimokawa db_tr->dbcnt = 0; 2620113584Ssimokawa if (dummy_dma != NULL) { 2621129585Sdfr dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2622113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2623113584Ssimokawa } 2624113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2625113584Ssimokawa if (ir->buf != NULL) { 2626113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2627113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2628113584Ssimokawa } 2629113584Ssimokawa db_tr->dbcnt++; 2630103285Sikob } 2631103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2632113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2633113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2634113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2635113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2636103285Sikob } 2637113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2638103285Sikob } 2639113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2640113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2641113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2642103285Sikob } 2643113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2644113584Ssimokawa return 0; 2645103285Sikob} 2646106790Ssimokawa 2647113584Ssimokawa 2648113584Ssimokawastatic int 2649113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2650103285Sikob{ 2651113584Ssimokawa struct fw_pkt *fp0; 2652129585Sdfr uint32_t ld0; 2653120660Ssimokawa int slen, hlen; 2654113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2655113584Ssimokawa int i; 2656113584Ssimokawa#endif 2657103285Sikob 2658113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2659113584Ssimokawa#if 0 2660113584Ssimokawa printf("ld0: x%08x\n", ld0); 2661113584Ssimokawa#endif 2662113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2663120660Ssimokawa /* determine length to swap */ 2664113584Ssimokawa switch (fp0->mode.common.tcode) { 2665113584Ssimokawa case FWTCODE_RREQQ: 2666113584Ssimokawa case FWTCODE_WRES: 2667113584Ssimokawa case FWTCODE_WREQQ: 2668113584Ssimokawa case FWTCODE_RRESQ: 2669113584Ssimokawa case FWOHCITCODE_PHY: 2670113584Ssimokawa slen = 12; 2671113584Ssimokawa break; 2672113584Ssimokawa case FWTCODE_RREQB: 2673113584Ssimokawa case FWTCODE_WREQB: 2674113584Ssimokawa case FWTCODE_LREQ: 2675113584Ssimokawa case FWTCODE_RRESB: 2676113584Ssimokawa case FWTCODE_LRES: 2677113584Ssimokawa slen = 16; 2678113584Ssimokawa break; 2679113584Ssimokawa default: 2680113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2681113584Ssimokawa return(0); 2682103285Sikob } 2683120660Ssimokawa hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2684120660Ssimokawa if (hlen > len) { 2685113584Ssimokawa if (firewire_debug) 2686113584Ssimokawa printf("splitted header\n"); 2687120660Ssimokawa return(-hlen); 2688103285Sikob } 2689113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2690113584Ssimokawa for(i = 0; i < slen/4; i ++) 2691113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2692113584Ssimokawa#endif 2693120660Ssimokawa return(hlen); 2694103285Sikob} 2695103285Sikob 2696103285Sikobstatic int 2697113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2698103285Sikob{ 2699120660Ssimokawa struct tcode_info *info; 2700113584Ssimokawa int r; 2701103285Sikob 2702120660Ssimokawa info = &tinfo[fp->mode.common.tcode]; 2703129585Sdfr r = info->hdr_len + sizeof(uint32_t); 2704120660Ssimokawa if ((info->flag & FWTI_BLOCK_ASY) != 0) 2705129585Sdfr r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2706120660Ssimokawa 2707169132Ssimokawa if (r == sizeof(uint32_t)) { 2708120660Ssimokawa /* XXX */ 2709110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2710110798Ssimokawa fp->mode.common.tcode); 2711169132Ssimokawa return (-1); 2712169132Ssimokawa } 2713120660Ssimokawa 2714110798Ssimokawa if (r > dbch->xferq.psize) { 2715110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2716169132Ssimokawa return (-1); 2717110798Ssimokawa /* panic ? */ 2718110798Ssimokawa } 2719120660Ssimokawa 2720110798Ssimokawa return r; 2721103285Sikob} 2722103285Sikob 2723106790Ssimokawastatic void 2724169132Ssimokawafwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2725169132Ssimokawa struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2726113584Ssimokawa{ 2727120660Ssimokawa struct fwohcidb *db = &db_tr->db[0]; 2728113584Ssimokawa 2729113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2730113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2731113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2732113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2733113584Ssimokawa dbch->bottom = db_tr; 2734169132Ssimokawa 2735169132Ssimokawa if (wake) 2736169132Ssimokawa OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2737113584Ssimokawa} 2738113584Ssimokawa 2739113584Ssimokawastatic void 2740106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2741103285Sikob{ 2742103285Sikob struct fwohcidb_tr *db_tr; 2743113584Ssimokawa struct iovec vec[2]; 2744113584Ssimokawa struct fw_pkt pktbuf; 2745113584Ssimokawa int nvec; 2746103285Sikob struct fw_pkt *fp; 2747129585Sdfr uint8_t *ld; 2748169132Ssimokawa uint32_t stat, off, status, event; 2749103285Sikob u_int spd; 2750113584Ssimokawa int len, plen, hlen, pcnt, offset; 2751103285Sikob int s; 2752103285Sikob caddr_t buf; 2753103285Sikob int resCount; 2754103285Sikob 2755103285Sikob if(&sc->arrq == dbch){ 2756103285Sikob off = OHCI_ARQOFF; 2757103285Sikob }else if(&sc->arrs == dbch){ 2758103285Sikob off = OHCI_ARSOFF; 2759103285Sikob }else{ 2760103285Sikob return; 2761103285Sikob } 2762103285Sikob 2763103285Sikob s = splfw(); 2764103285Sikob db_tr = dbch->top; 2765103285Sikob pcnt = 0; 2766103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2767113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2768113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2769113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2770113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2771169132Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2772113584Ssimokawa#if 0 2773169132Ssimokawa 2774169132Ssimokawa if (off == OHCI_ARQOFF) 2775169132Ssimokawa printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2776169132Ssimokawa db_tr->bus_addr, status, resCount); 2777113584Ssimokawa#endif 2778113584Ssimokawa len = dbch->xferq.psize - resCount; 2779129585Sdfr ld = (uint8_t *)db_tr->buf; 2780113584Ssimokawa if (dbch->pdb_tr == NULL) { 2781113584Ssimokawa len -= dbch->buf_offset; 2782113584Ssimokawa ld += dbch->buf_offset; 2783113584Ssimokawa } 2784113584Ssimokawa if (len > 0) 2785113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2786113584Ssimokawa BUS_DMASYNC_POSTREAD); 2787103285Sikob while (len > 0 ) { 2788106789Ssimokawa if (count >= 0 && count-- == 0) 2789106789Ssimokawa goto out; 2790113584Ssimokawa if(dbch->pdb_tr != NULL){ 2791113584Ssimokawa /* we have a fragment in previous buffer */ 2792113584Ssimokawa int rlen; 2793103285Sikob 2794113584Ssimokawa offset = dbch->buf_offset; 2795113584Ssimokawa if (offset < 0) 2796113584Ssimokawa offset = - offset; 2797113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2798113584Ssimokawa rlen = dbch->xferq.psize - offset; 2799113584Ssimokawa if (firewire_debug) 2800113584Ssimokawa printf("rlen=%d, offset=%d\n", 2801113584Ssimokawa rlen, dbch->buf_offset); 2802113584Ssimokawa if (dbch->buf_offset < 0) { 2803113584Ssimokawa /* splitted in header, pull up */ 2804113584Ssimokawa char *p; 2805113584Ssimokawa 2806113584Ssimokawa p = (char *)&pktbuf; 2807113584Ssimokawa bcopy(buf, p, rlen); 2808113584Ssimokawa p += rlen; 2809113584Ssimokawa /* this must be too long but harmless */ 2810113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2811113584Ssimokawa if (rlen < 0) 2812113584Ssimokawa printf("why rlen < 0\n"); 2813113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2814103285Sikob ld += rlen; 2815103285Sikob len -= rlen; 2816113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2817169132Ssimokawa if (hlen <= 0) { 2818169132Ssimokawa printf("hlen should be positive."); 2819169132Ssimokawa goto err; 2820113584Ssimokawa } 2821113584Ssimokawa offset = sizeof(pktbuf); 2822113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2823113584Ssimokawa vec[0].iov_len = offset; 2824113584Ssimokawa } else { 2825113584Ssimokawa /* splitted in payload */ 2826113584Ssimokawa offset = rlen; 2827113584Ssimokawa vec[0].iov_base = buf; 2828113584Ssimokawa vec[0].iov_len = rlen; 2829103285Sikob } 2830113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2831113584Ssimokawa nvec = 1; 2832113584Ssimokawa } else { 2833113584Ssimokawa /* no fragment in previous buffer */ 2834103285Sikob fp=(struct fw_pkt *)ld; 2835113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2836113584Ssimokawa if (hlen == 0) 2837169132Ssimokawa goto err; 2838113584Ssimokawa if (hlen < 0) { 2839113584Ssimokawa dbch->pdb_tr = db_tr; 2840113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2841113584Ssimokawa /* sanity check */ 2842169132Ssimokawa if (resCount != 0) { 2843169132Ssimokawa printf("resCount=%d hlen=%d\n", 2844169132Ssimokawa resCount, hlen); 2845169132Ssimokawa goto err; 2846169132Ssimokawa } 2847113584Ssimokawa goto out; 2848103285Sikob } 2849113584Ssimokawa offset = 0; 2850113584Ssimokawa nvec = 0; 2851113584Ssimokawa } 2852113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2853113584Ssimokawa if (plen < 0) { 2854113584Ssimokawa /* minimum header size + trailer 2855113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2856120660Ssimokawa printf("plen(%d) is negative! offset=%d\n", 2857120660Ssimokawa plen, offset); 2858169132Ssimokawa goto err; 2859113584Ssimokawa } 2860113584Ssimokawa if (plen > 0) { 2861113584Ssimokawa len -= plen; 2862113584Ssimokawa if (len < 0) { 2863113584Ssimokawa dbch->pdb_tr = db_tr; 2864113584Ssimokawa if (firewire_debug) 2865113584Ssimokawa printf("splitted payload\n"); 2866113584Ssimokawa /* sanity check */ 2867169132Ssimokawa if (resCount != 0) { 2868169132Ssimokawa printf("resCount=%d plen=%d" 2869169132Ssimokawa " len=%d\n", 2870169132Ssimokawa resCount, plen, len); 2871169132Ssimokawa goto err; 2872169132Ssimokawa } 2873113584Ssimokawa goto out; 2874103285Sikob } 2875113584Ssimokawa vec[nvec].iov_base = ld; 2876113584Ssimokawa vec[nvec].iov_len = plen; 2877113584Ssimokawa nvec ++; 2878103285Sikob ld += plen; 2879103285Sikob } 2880129585Sdfr dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2881113584Ssimokawa if (nvec == 0) 2882113584Ssimokawa printf("nvec == 0\n"); 2883113584Ssimokawa 2884103285Sikob/* DMA result-code will be written at the tail of packet */ 2885169132Ssimokawa stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 2886110577Ssimokawa#if 0 2887120660Ssimokawa printf("plen: %d, stat %x\n", 2888120660Ssimokawa plen ,stat); 2889103285Sikob#endif 2890169132Ssimokawa spd = (stat >> 21) & 0x3; 2891169132Ssimokawa event = (stat >> 16) & 0x1f; 2892169132Ssimokawa switch (event) { 2893113584Ssimokawa case FWOHCIEV_ACKPEND: 2894113584Ssimokawa#if 0 2895113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2896113584Ssimokawa#endif 2897113584Ssimokawa /* fall through */ 2898113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2899120660Ssimokawa { 2900120660Ssimokawa struct fw_rcv_buf rb; 2901120660Ssimokawa 2902113584Ssimokawa if ((vec[nvec-1].iov_len -= 2903113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2904113584Ssimokawa nvec--; 2905120660Ssimokawa rb.fc = &sc->fc; 2906120660Ssimokawa rb.vec = vec; 2907120660Ssimokawa rb.nvec = nvec; 2908120660Ssimokawa rb.spd = spd; 2909120660Ssimokawa fw_rcv(&rb); 2910120660Ssimokawa break; 2911120660Ssimokawa } 2912113584Ssimokawa case FWOHCIEV_BUSRST: 2913170425Ssimokawa if ((sc->fc.status != FWBUSRESET) && 2914170425Ssimokawa (sc->fc.status != FWBUSINIT)) 2915113584Ssimokawa printf("got BUSRST packet!?\n"); 2916113584Ssimokawa break; 2917113584Ssimokawa default: 2918169132Ssimokawa device_printf(sc->fc.dev, 2919169132Ssimokawa "Async DMA Receive error err=%02x %s" 2920169132Ssimokawa " plen=%d offset=%d len=%d status=0x%08x" 2921169132Ssimokawa " tcode=0x%x, stat=0x%08x\n", 2922169132Ssimokawa event, fwohcicode[event], plen, 2923169132Ssimokawa dbch->buf_offset, len, 2924169132Ssimokawa OREAD(sc, OHCI_DMACTL(off)), 2925169132Ssimokawa fp->mode.common.tcode, stat); 2926169132Ssimokawa#if 1 /* XXX */ 2927169132Ssimokawa goto err; 2928103285Sikob#endif 2929113584Ssimokawa break; 2930103285Sikob } 2931103285Sikob pcnt ++; 2932113584Ssimokawa if (dbch->pdb_tr != NULL) { 2933169132Ssimokawa fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 2934169132Ssimokawa off, 1); 2935113584Ssimokawa dbch->pdb_tr = NULL; 2936113584Ssimokawa } 2937113584Ssimokawa 2938113584Ssimokawa } 2939103285Sikobout: 2940103285Sikob if (resCount == 0) { 2941103285Sikob /* done on this buffer */ 2942113584Ssimokawa if (dbch->pdb_tr == NULL) { 2943169132Ssimokawa fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 2944113584Ssimokawa dbch->buf_offset = 0; 2945113584Ssimokawa } else 2946113584Ssimokawa if (dbch->pdb_tr != db_tr) 2947113584Ssimokawa printf("pdb_tr != db_tr\n"); 2948103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2949113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2950113584Ssimokawa >> OHCI_STATUS_SHIFT; 2951113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2952113584Ssimokawa & OHCI_COUNT_MASK; 2953113584Ssimokawa /* XXX check buffer overrun */ 2954103285Sikob dbch->top = db_tr; 2955103285Sikob } else { 2956103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2957103285Sikob break; 2958103285Sikob } 2959103285Sikob /* XXX make sure DMA is not dead */ 2960103285Sikob } 2961103285Sikob#if 0 2962103285Sikob if (pcnt < 1) 2963103285Sikob printf("fwohci_arcv: no packets\n"); 2964103285Sikob#endif 2965103285Sikob splx(s); 2966169132Ssimokawa return; 2967169132Ssimokawa 2968169132Ssimokawaerr: 2969169132Ssimokawa device_printf(sc->fc.dev, "AR DMA status=%x, ", 2970169132Ssimokawa OREAD(sc, OHCI_DMACTL(off))); 2971169132Ssimokawa dbch->pdb_tr = NULL; 2972169132Ssimokawa /* skip until resCount != 0 */ 2973169132Ssimokawa printf(" skip buffer"); 2974169132Ssimokawa while (resCount == 0) { 2975169132Ssimokawa printf(" #"); 2976169132Ssimokawa fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 2977169132Ssimokawa db_tr = STAILQ_NEXT(db_tr, link); 2978169132Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2979169132Ssimokawa & OHCI_COUNT_MASK; 2980169132Ssimokawa } while (resCount == 0) 2981169132Ssimokawa printf(" done\n"); 2982169132Ssimokawa dbch->top = db_tr; 2983169132Ssimokawa dbch->buf_offset = dbch->xferq.psize - resCount; 2984169132Ssimokawa OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2985169132Ssimokawa splx(s); 2986103285Sikob} 2987