fwohci.c revision 130585
1103285Sikob/* 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 130585 2004-06-16 09:47:26Z phk $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50103285Sikob#include <sys/bus.h> 51103285Sikob#include <sys/kernel.h> 52103285Sikob#include <sys/conf.h> 53113584Ssimokawa#include <sys/endian.h> 54103285Sikob 55103285Sikob#include <machine/bus.h> 56103285Sikob 57127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 58117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 59117067Ssimokawa#endif 60117067Ssimokawa 61127468Ssimokawa#ifdef __DragonFly__ 62127468Ssimokawa#include "firewire.h" 63127468Ssimokawa#include "firewirereg.h" 64127468Ssimokawa#include "fwdma.h" 65127468Ssimokawa#include "fwohcireg.h" 66127468Ssimokawa#include "fwohcivar.h" 67127468Ssimokawa#include "firewire_phy.h" 68127468Ssimokawa#else 69103285Sikob#include <dev/firewire/firewire.h> 70103285Sikob#include <dev/firewire/firewirereg.h> 71113584Ssimokawa#include <dev/firewire/fwdma.h> 72103285Sikob#include <dev/firewire/fwohcireg.h> 73103285Sikob#include <dev/firewire/fwohcivar.h> 74103285Sikob#include <dev/firewire/firewire_phy.h> 75127468Ssimokawa#endif 76103285Sikob 77103285Sikob#undef OHCI_DEBUG 78106802Ssimokawa 79103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 80103285Sikob "STOR","LOAD","NOP ","STOP",}; 81113584Ssimokawa 82103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83103285Sikob "UNDEF","REG","SYS","DEV"}; 84113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 85103285Sikobchar fwohcicode[32][0x20]={ 86103285Sikob "No stat","Undef","long","miss Ack err", 87103285Sikob "underrun","overrun","desc err", "data read err", 88103285Sikob "data write err","bus reset","timeout","tcode err", 89103285Sikob "Undef","Undef","unknown event","flushed", 90103285Sikob "Undef","ack complete","ack pend","Undef", 91103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 92103285Sikob "Undef","Undef","Undef","ack tardy", 93103285Sikob "Undef","ack data_err","ack type_err",""}; 94113584Ssimokawa 95116376Ssimokawa#define MAX_SPEED 3 96124378Ssimokawaextern char *linkspeed[]; 97129585Sdfruint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125124169Ssimokawastatic void fwohci_ibr (struct firewire_comm *); 126124169Ssimokawastatic void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 127124169Ssimokawastatic void fwohci_db_free (struct fwohci_dbch *); 128124169Ssimokawastatic void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 129124169Ssimokawastatic void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 130124169Ssimokawastatic void fwohci_start_atq (struct firewire_comm *); 131124169Ssimokawastatic void fwohci_start_ats (struct firewire_comm *); 132124169Ssimokawastatic void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 133129585Sdfrstatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 134129585Sdfrstatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 135124169Ssimokawastatic int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 136124169Ssimokawastatic int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 137124169Ssimokawastatic int fwohci_irx_enable (struct firewire_comm *, int); 138124169Ssimokawastatic int fwohci_irx_disable (struct firewire_comm *, int); 139113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 140129585Sdfrstatic void fwohci_irx_post (struct firewire_comm *, uint32_t *); 141113584Ssimokawa#endif 142124169Ssimokawastatic int fwohci_itxbuf_enable (struct firewire_comm *, int); 143124169Ssimokawastatic int fwohci_itx_disable (struct firewire_comm *, int); 144124169Ssimokawastatic void fwohci_timeout (void *); 145124169Ssimokawastatic void fwohci_set_intr (struct firewire_comm *, int); 146113584Ssimokawa 147124169Ssimokawastatic int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 148124169Ssimokawastatic int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 149129585Sdfrstatic void dump_db (struct fwohci_softc *, uint32_t); 150129585Sdfrstatic void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 151129585Sdfrstatic void dump_dma (struct fwohci_softc *, uint32_t); 152129585Sdfrstatic uint32_t fwohci_cyctimer (struct firewire_comm *); 153124169Ssimokawastatic void fwohci_rbuf_update (struct fwohci_softc *, int); 154124169Ssimokawastatic void fwohci_tbuf_update (struct fwohci_softc *, int); 155124169Ssimokawavoid fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 156113584Ssimokawa#if FWOHCI_TASKQUEUE 157113584Ssimokawastatic void fwohci_complete(void *, int); 158113584Ssimokawa#endif 159103285Sikob 160103285Sikob/* 161103285Sikob * memory allocated for DMA programs 162103285Sikob */ 163103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 164103285Sikob 165103285Sikob#define NDB FWMAXQUEUE 166103285Sikob 167103285Sikob#define OHCI_VERSION 0x00 168112523Ssimokawa#define OHCI_ATRETRY 0x08 169103285Sikob#define OHCI_CROMHDR 0x18 170103285Sikob#define OHCI_BUS_OPT 0x20 171103285Sikob#define OHCI_BUSIRMC (1 << 31) 172103285Sikob#define OHCI_BUSCMC (1 << 30) 173103285Sikob#define OHCI_BUSISC (1 << 29) 174103285Sikob#define OHCI_BUSBMC (1 << 28) 175103285Sikob#define OHCI_BUSPMC (1 << 27) 176103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 177103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 178103285Sikob 179103285Sikob#define OHCI_EUID_HI 0x24 180103285Sikob#define OHCI_EUID_LO 0x28 181103285Sikob 182103285Sikob#define OHCI_CROMPTR 0x34 183103285Sikob#define OHCI_HCCCTL 0x50 184103285Sikob#define OHCI_HCCCTLCLR 0x54 185103285Sikob#define OHCI_AREQHI 0x100 186103285Sikob#define OHCI_AREQHICLR 0x104 187103285Sikob#define OHCI_AREQLO 0x108 188103285Sikob#define OHCI_AREQLOCLR 0x10c 189103285Sikob#define OHCI_PREQHI 0x110 190103285Sikob#define OHCI_PREQHICLR 0x114 191103285Sikob#define OHCI_PREQLO 0x118 192103285Sikob#define OHCI_PREQLOCLR 0x11c 193103285Sikob#define OHCI_PREQUPPER 0x120 194103285Sikob 195103285Sikob#define OHCI_SID_BUF 0x64 196103285Sikob#define OHCI_SID_CNT 0x68 197113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 198103285Sikob#define OHCI_SID_CNT_MASK 0xffc 199103285Sikob 200103285Sikob#define OHCI_IT_STAT 0x90 201103285Sikob#define OHCI_IT_STATCLR 0x94 202103285Sikob#define OHCI_IT_MASK 0x98 203103285Sikob#define OHCI_IT_MASKCLR 0x9c 204103285Sikob 205103285Sikob#define OHCI_IR_STAT 0xa0 206103285Sikob#define OHCI_IR_STATCLR 0xa4 207103285Sikob#define OHCI_IR_MASK 0xa8 208103285Sikob#define OHCI_IR_MASKCLR 0xac 209103285Sikob 210103285Sikob#define OHCI_LNKCTL 0xe0 211103285Sikob#define OHCI_LNKCTLCLR 0xe4 212103285Sikob 213103285Sikob#define OHCI_PHYACCESS 0xec 214103285Sikob#define OHCI_CYCLETIMER 0xf0 215103285Sikob 216103285Sikob#define OHCI_DMACTL(off) (off) 217103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 218103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 219103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 220103285Sikob 221103285Sikob#define OHCI_ATQOFF 0x180 222103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 223103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 224103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 225103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 226103285Sikob 227103285Sikob#define OHCI_ATSOFF 0x1a0 228103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 229103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 230103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 231103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 232103285Sikob 233103285Sikob#define OHCI_ARQOFF 0x1c0 234103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 235103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 236103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 237103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 238103285Sikob 239103285Sikob#define OHCI_ARSOFF 0x1e0 240103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 241103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 242103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 243103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 244103285Sikob 245103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 246103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 247103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 248103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 249103285Sikob 250103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 251103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 252103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 253103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 254103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 255103285Sikob 256103285Sikobd_ioctl_t fwohci_ioctl; 257103285Sikob 258103285Sikob/* 259103285Sikob * Communication with PHY device 260103285Sikob */ 261129585Sdfrstatic uint32_t 262129585Sdfrfwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 263103285Sikob{ 264129585Sdfr uint32_t fun; 265103285Sikob 266103285Sikob addr &= 0xf; 267103285Sikob data &= 0xff; 268103285Sikob 269103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 270103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 271103285Sikob DELAY(100); 272103285Sikob 273103285Sikob return(fwphy_rddata( sc, addr)); 274103285Sikob} 275103285Sikob 276129585Sdfrstatic uint32_t 277103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 278103285Sikob{ 279103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 280103285Sikob int i; 281129585Sdfr uint32_t bm; 282103285Sikob 283103285Sikob#define OHCI_CSR_DATA 0x0c 284103285Sikob#define OHCI_CSR_COMP 0x10 285103285Sikob#define OHCI_CSR_CONT 0x14 286103285Sikob#define OHCI_BUS_MANAGER_ID 0 287103285Sikob 288103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 289103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 290103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 291103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 292109280Ssimokawa DELAY(10); 293103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 294107653Ssimokawa if((bm & 0x3f) == 0x3f) 295103285Sikob bm = node; 296107653Ssimokawa if (bootverbose) 297107653Ssimokawa device_printf(sc->fc.dev, 298107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 299103285Sikob 300103285Sikob return(bm); 301103285Sikob} 302103285Sikob 303129585Sdfrstatic uint32_t 304106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 305103285Sikob{ 306129585Sdfr uint32_t fun, stat; 307108500Ssimokawa u_int i, retry = 0; 308103285Sikob 309103285Sikob addr &= 0xf; 310108500Ssimokawa#define MAX_RETRY 100 311108500Ssimokawaagain: 312108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 313103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 314103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 315108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 316103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 317103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 318103285Sikob break; 319109280Ssimokawa DELAY(100); 320103285Sikob } 321108500Ssimokawa if(i >= MAX_RETRY) { 322109280Ssimokawa if (bootverbose) 323109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 324108527Ssimokawa if (++retry < MAX_RETRY) { 325109280Ssimokawa DELAY(100); 326108527Ssimokawa goto again; 327108527Ssimokawa } 328108500Ssimokawa } 329108500Ssimokawa /* Make sure that SCLK is started */ 330108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 331108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 332108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 333109280Ssimokawa if (bootverbose) 334109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 335108500Ssimokawa if (++retry < MAX_RETRY) { 336109280Ssimokawa DELAY(100); 337108500Ssimokawa goto again; 338108500Ssimokawa } 339108500Ssimokawa } 340108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 341108500Ssimokawa device_printf(sc->fc.dev, 342119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 343108500Ssimokawa#undef MAX_RETRY 344103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 345103285Sikob} 346103285Sikob/* Device specific ioctl. */ 347103285Sikobint 348130585Sphkfwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 349103285Sikob{ 350103285Sikob struct firewire_softc *sc; 351103285Sikob struct fwohci_softc *fc; 352103285Sikob int unit = DEV2UNIT(dev); 353103285Sikob int err = 0; 354103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 355129585Sdfr uint32_t *dmach = (uint32_t *) data; 356103285Sikob 357103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 358103285Sikob if(sc == NULL){ 359103285Sikob return(EINVAL); 360103285Sikob } 361103285Sikob fc = (struct fwohci_softc *)sc->fc; 362103285Sikob 363103285Sikob if (!data) 364103285Sikob return(EINVAL); 365103285Sikob 366103285Sikob switch (cmd) { 367103285Sikob case FWOHCI_WRREG: 368103285Sikob#define OHCI_MAX_REG 0x800 369103285Sikob if(reg->addr <= OHCI_MAX_REG){ 370103285Sikob OWRITE(fc, reg->addr, reg->data); 371103285Sikob reg->data = OREAD(fc, reg->addr); 372103285Sikob }else{ 373103285Sikob err = EINVAL; 374103285Sikob } 375103285Sikob break; 376103285Sikob case FWOHCI_RDREG: 377103285Sikob if(reg->addr <= OHCI_MAX_REG){ 378103285Sikob reg->data = OREAD(fc, reg->addr); 379103285Sikob }else{ 380103285Sikob err = EINVAL; 381103285Sikob } 382103285Sikob break; 383103285Sikob/* Read DMA descriptors for debug */ 384103285Sikob case DUMPDMA: 385103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 386103285Sikob dump_dma(fc, *dmach); 387103285Sikob dump_db(fc, *dmach); 388103285Sikob }else{ 389103285Sikob err = EINVAL; 390103285Sikob } 391103285Sikob break; 392119118Ssimokawa/* Read/Write Phy registers */ 393119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 394119118Ssimokawa case FWOHCI_RDPHYREG: 395119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 396119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 397119118Ssimokawa else 398119118Ssimokawa err = EINVAL; 399119118Ssimokawa break; 400119118Ssimokawa case FWOHCI_WRPHYREG: 401119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 402119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 403119118Ssimokawa else 404119118Ssimokawa err = EINVAL; 405119118Ssimokawa break; 406103285Sikob default: 407119118Ssimokawa err = EINVAL; 408103285Sikob break; 409103285Sikob } 410103285Sikob return err; 411103285Sikob} 412106790Ssimokawa 413108530Ssimokawastatic int 414108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 415103285Sikob{ 416129585Sdfr uint32_t reg, reg2; 417108530Ssimokawa int e1394a = 1; 418108530Ssimokawa/* 419108530Ssimokawa * probe PHY parameters 420108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 421108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 422108530Ssimokawa * number of port supported by core-logic. 423108530Ssimokawa * It is not actually available port on your PC . 424108530Ssimokawa */ 425108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 426108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 427108530Ssimokawa 428108530Ssimokawa if((reg >> 5) != 7 ){ 429108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 430108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 431108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 432108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 433108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 434108530Ssimokawa sc->fc.speed, MAX_SPEED); 435108530Ssimokawa sc->fc.speed = MAX_SPEED; 436108530Ssimokawa } 437108530Ssimokawa device_printf(dev, 438108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 439108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 440108530Ssimokawa }else{ 441108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 442108530Ssimokawa sc->fc.mode |= FWPHYASYST; 443108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 444108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 445108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 446108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 447108530Ssimokawa sc->fc.speed, MAX_SPEED); 448108530Ssimokawa sc->fc.speed = MAX_SPEED; 449108530Ssimokawa } 450108530Ssimokawa device_printf(dev, 451108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 452108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 453108530Ssimokawa 454108530Ssimokawa /* check programPhyEnable */ 455108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 456108530Ssimokawa#if 0 457108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 458108530Ssimokawa#else /* XXX force to enable 1394a */ 459108530Ssimokawa if (e1394a) { 460108530Ssimokawa#endif 461108530Ssimokawa if (bootverbose) 462108530Ssimokawa device_printf(dev, 463108530Ssimokawa "Enable 1394a Enhancements\n"); 464108530Ssimokawa /* enable EAA EMC */ 465108530Ssimokawa reg2 |= 0x03; 466108530Ssimokawa /* set aPhyEnhanceEnable */ 467108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 468108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 469108530Ssimokawa } else { 470108530Ssimokawa /* for safe */ 471108530Ssimokawa reg2 &= ~0x83; 472108530Ssimokawa } 473108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 474108530Ssimokawa } 475108530Ssimokawa 476108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 477108530Ssimokawa if((reg >> 5) == 7 ){ 478108530Ssimokawa reg = fwphy_rddata(sc, 4); 479108530Ssimokawa reg |= 1 << 6; 480108530Ssimokawa fwphy_wrdata(sc, 4, reg); 481108530Ssimokawa reg = fwphy_rddata(sc, 4); 482108530Ssimokawa } 483108530Ssimokawa return 0; 484108530Ssimokawa} 485108530Ssimokawa 486108530Ssimokawa 487108530Ssimokawavoid 488108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 489108530Ssimokawa{ 490108701Ssimokawa int i, max_rec, speed; 491129585Sdfr uint32_t reg, reg2; 492103285Sikob struct fwohcidb_tr *db_tr; 493103285Sikob 494129541Sdfr /* Disable interrupts */ 495108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 496108530Ssimokawa 497129541Sdfr /* Now stopping all DMA channels */ 498108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 499108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 500108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 501108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 502108530Ssimokawa 503108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 504108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 505108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 506108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 507108530Ssimokawa } 508108530Ssimokawa 509108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 510108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 511108530Ssimokawa if (bootverbose) 512108530Ssimokawa device_printf(dev, "resetting OHCI..."); 513108530Ssimokawa i = 0; 514108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 515108530Ssimokawa if (i++ > 100) break; 516108530Ssimokawa DELAY(1000); 517108530Ssimokawa } 518108530Ssimokawa if (bootverbose) 519108530Ssimokawa printf("done (loop=%d)\n", i); 520108530Ssimokawa 521108701Ssimokawa /* Probe phy */ 522108701Ssimokawa fwohci_probe_phy(sc, dev); 523108701Ssimokawa 524108701Ssimokawa /* Probe link */ 525108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 526108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 527108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 528108701Ssimokawa speed = (reg & 0x00000007); 529108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 530108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 531108701Ssimokawa /* XXX fix max_rec */ 532108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 533108701Ssimokawa if (max_rec != sc->fc.maxrec) { 534108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 535108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 536108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 537108701Ssimokawa } 538108530Ssimokawa if (bootverbose) 539108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 540108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 541108530Ssimokawa 542108701Ssimokawa /* Initialize registers */ 543108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 544113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 545108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 546108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 547113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 548108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 549108530Ssimokawa 550108701Ssimokawa /* Enable link */ 551108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 552108642Ssimokawa 553108701Ssimokawa /* Force to start async RX DMA */ 554108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 555108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 556108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 557108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 558108530Ssimokawa 559108701Ssimokawa /* Initialize async TX */ 560108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 561108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562116978Ssimokawa 563108701Ssimokawa /* AT Retries */ 564108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 565108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 566108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 567116978Ssimokawa 568116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 569116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 570116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 571116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 572116978Ssimokawa 573108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 574108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 575108530Ssimokawa db_tr->xfer = NULL; 576108530Ssimokawa } 577108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 578108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 579108530Ssimokawa db_tr->xfer = NULL; 580108530Ssimokawa } 581108530Ssimokawa 582108701Ssimokawa 583129541Sdfr /* Enable interrupts */ 584108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 585108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 586108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 587108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 588108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 589108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 590108530Ssimokawa 591108530Ssimokawa} 592108530Ssimokawa 593108530Ssimokawaint 594108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 595108530Ssimokawa{ 596121781Ssimokawa int i, mver; 597129585Sdfr uint32_t reg; 598129585Sdfr uint8_t ui[8]; 599108530Ssimokawa 600113584Ssimokawa#if FWOHCI_TASKQUEUE 601113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 602113584Ssimokawa#endif 603113584Ssimokawa 604121781Ssimokawa/* OHCI version */ 605103285Sikob reg = OREAD(sc, OHCI_VERSION); 606121781Ssimokawa mver = (reg >> 16) & 0xff; 607103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 608121781Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 609121781Ssimokawa if (mver < 1 || mver > 9) { 610118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 611118416Ssimokawa return (ENXIO); 612118416Ssimokawa } 613118416Ssimokawa 614129541Sdfr/* Available Isochronous DMA channel probe */ 615110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 616110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 617110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 618110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 619110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 620110045Ssimokawa for (i = 0; i < 0x20; i++) 621110045Ssimokawa if ((reg & (1 << i)) == 0) 622110045Ssimokawa break; 623103285Sikob sc->fc.nisodma = i; 624129541Sdfr device_printf(dev, "No. of Isochronous channels is %d.\n", i); 625118820Ssimokawa if (i == 0) 626118820Ssimokawa return (ENXIO); 627103285Sikob 628103285Sikob sc->fc.arq = &sc->arrq.xferq; 629103285Sikob sc->fc.ars = &sc->arrs.xferq; 630103285Sikob sc->fc.atq = &sc->atrq.xferq; 631103285Sikob sc->fc.ats = &sc->atrs.xferq; 632103285Sikob 633113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 634113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 635113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 636113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 637113584Ssimokawa 638103285Sikob sc->arrq.xferq.start = NULL; 639103285Sikob sc->arrs.xferq.start = NULL; 640103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 641103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 642103285Sikob 643113584Ssimokawa sc->arrq.xferq.buf = NULL; 644113584Ssimokawa sc->arrs.xferq.buf = NULL; 645113584Ssimokawa sc->atrq.xferq.buf = NULL; 646113584Ssimokawa sc->atrs.xferq.buf = NULL; 647103285Sikob 648118293Ssimokawa sc->arrq.xferq.dmach = -1; 649118293Ssimokawa sc->arrs.xferq.dmach = -1; 650118293Ssimokawa sc->atrq.xferq.dmach = -1; 651118293Ssimokawa sc->atrs.xferq.dmach = -1; 652118293Ssimokawa 653103285Sikob sc->arrq.ndesc = 1; 654103285Sikob sc->arrs.ndesc = 1; 655110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 656110593Ssimokawa sc->atrs.ndesc = 2; 657103285Sikob 658103285Sikob sc->arrq.ndb = NDB; 659103285Sikob sc->arrs.ndb = NDB / 2; 660103285Sikob sc->atrq.ndb = NDB; 661103285Sikob sc->atrs.ndb = NDB / 2; 662103285Sikob 663103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 664103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 665103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 666118293Ssimokawa sc->it[i].xferq.dmach = i; 667118293Ssimokawa sc->ir[i].xferq.dmach = i; 668103285Sikob sc->it[i].ndb = 0; 669103285Sikob sc->ir[i].ndb = 0; 670103285Sikob } 671103285Sikob 672103285Sikob sc->fc.tcode = tinfo; 673113584Ssimokawa sc->fc.dev = dev; 674103285Sikob 675113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 676113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 677113584Ssimokawa if(sc->fc.config_rom == NULL){ 678113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 679103285Sikob return ENOMEM; 680103285Sikob } 681103285Sikob 682116376Ssimokawa#if 0 683116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 684103285Sikob sc->fc.config_rom[1] = 0x31333934; 685103285Sikob sc->fc.config_rom[2] = 0xf000a002; 686103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 687103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 688103285Sikob sc->fc.config_rom[5] = 0; 689103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 690103285Sikob 691103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 692113584Ssimokawa#endif 693103285Sikob 694103285Sikob 695129541Sdfr/* SID recieve buffer must align 2^11 */ 696103285Sikob#define OHCI_SIDSIZE (1 << 11) 697113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 698113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 699113584Ssimokawa if (sc->sid_buf == NULL) { 700113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 701108527Ssimokawa return ENOMEM; 702108527Ssimokawa } 703113584Ssimokawa 704129585Sdfr fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 705113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 706113584Ssimokawa 707113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 708113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 709109736Ssimokawa return ENOMEM; 710109736Ssimokawa } 711113584Ssimokawa 712113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 713108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 714108527Ssimokawa return ENOMEM; 715108527Ssimokawa 716113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 717108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 718108527Ssimokawa return ENOMEM; 719103285Sikob 720113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 721108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 722108527Ssimokawa return ENOMEM; 723108527Ssimokawa 724113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 725108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 726108527Ssimokawa return ENOMEM; 727103285Sikob 728109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 729109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 730109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 731109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 732103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 733109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 734109814Ssimokawa 735103285Sikob sc->fc.ioctl = fwohci_ioctl; 736103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 737103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 738103285Sikob sc->fc.ibr = fwohci_ibr; 739103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 740103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 741103285Sikob 742103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 743103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 744113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 745103285Sikob sc->fc.irx_post = fwohci_irx_post; 746113584Ssimokawa#else 747113584Ssimokawa sc->fc.irx_post = NULL; 748113584Ssimokawa#endif 749103285Sikob sc->fc.itx_post = NULL; 750103285Sikob sc->fc.timeout = fwohci_timeout; 751103285Sikob sc->fc.poll = fwohci_poll; 752103285Sikob sc->fc.set_intr = fwohci_set_intr; 753106790Ssimokawa 754113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 755113584Ssimokawa 756108530Ssimokawa fw_init(&sc->fc); 757108530Ssimokawa fwohci_reset(sc, dev); 758103285Sikob 759108530Ssimokawa return 0; 760103285Sikob} 761106790Ssimokawa 762106790Ssimokawavoid 763106790Ssimokawafwohci_timeout(void *arg) 764103285Sikob{ 765103285Sikob struct fwohci_softc *sc; 766103285Sikob 767103285Sikob sc = (struct fwohci_softc *)arg; 768103285Sikob} 769106790Ssimokawa 770129585Sdfruint32_t 771106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 772103285Sikob{ 773103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 774103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 775103285Sikob} 776103285Sikob 777108527Ssimokawaint 778108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 779108527Ssimokawa{ 780108527Ssimokawa int i; 781108527Ssimokawa 782113584Ssimokawa if (sc->sid_buf != NULL) 783113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 784113584Ssimokawa if (sc->fc.config_rom != NULL) 785113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 786108527Ssimokawa 787108527Ssimokawa fwohci_db_free(&sc->arrq); 788108527Ssimokawa fwohci_db_free(&sc->arrs); 789108527Ssimokawa 790108527Ssimokawa fwohci_db_free(&sc->atrq); 791108527Ssimokawa fwohci_db_free(&sc->atrs); 792108527Ssimokawa 793108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 794108527Ssimokawa fwohci_db_free(&sc->it[i]); 795108527Ssimokawa fwohci_db_free(&sc->ir[i]); 796108527Ssimokawa } 797108527Ssimokawa 798108527Ssimokawa return 0; 799108527Ssimokawa} 800108527Ssimokawa 801108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 802108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 803108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 804108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 805108655Ssimokawa} while (0) 806108655Ssimokawa 807106790Ssimokawastatic void 808113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 809113584Ssimokawa{ 810113584Ssimokawa struct fwohcidb_tr *db_tr; 811120660Ssimokawa struct fwohcidb *db; 812113584Ssimokawa bus_dma_segment_t *s; 813113584Ssimokawa int i; 814113584Ssimokawa 815113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 816113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 817113584Ssimokawa if (error) { 818113584Ssimokawa if (firewire_debug || error != EFBIG) 819113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 820113584Ssimokawa return; 821113584Ssimokawa } 822113584Ssimokawa for (i = 0; i < nseg; i++) { 823113584Ssimokawa s = &segs[i]; 824113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 825113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 826113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 827113584Ssimokawa db++; 828113584Ssimokawa db_tr->dbcnt++; 829113584Ssimokawa } 830113584Ssimokawa} 831113584Ssimokawa 832113584Ssimokawastatic void 833113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 834113584Ssimokawa bus_size_t size, int error) 835113584Ssimokawa{ 836113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 837113584Ssimokawa} 838113584Ssimokawa 839113584Ssimokawastatic void 840106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 841103285Sikob{ 842103285Sikob int i, s; 843120660Ssimokawa int tcode, hdr_len, pl_off; 844103285Sikob int fsegment = -1; 845129585Sdfr uint32_t off; 846103285Sikob struct fw_xfer *xfer; 847103285Sikob struct fw_pkt *fp; 848120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 849103285Sikob struct fwohcidb_tr *db_tr; 850120660Ssimokawa struct fwohcidb *db; 851129585Sdfr uint32_t *ld; 852103285Sikob struct tcode_info *info; 853108655Ssimokawa static int maxdesc=0; 854103285Sikob 855103285Sikob if(&sc->atrq == dbch){ 856103285Sikob off = OHCI_ATQOFF; 857103285Sikob }else if(&sc->atrs == dbch){ 858103285Sikob off = OHCI_ATSOFF; 859103285Sikob }else{ 860103285Sikob return; 861103285Sikob } 862103285Sikob 863103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 864103285Sikob return; 865103285Sikob 866103285Sikob s = splfw(); 867103285Sikob db_tr = dbch->top; 868103285Sikobtxloop: 869103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 870103285Sikob if(xfer == NULL){ 871103285Sikob goto kick; 872103285Sikob } 873103285Sikob if(dbch->xferq.queued == 0 ){ 874103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 875103285Sikob } 876103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 877103285Sikob db_tr->xfer = xfer; 878103285Sikob xfer->state = FWXF_START; 879103285Sikob 880120660Ssimokawa fp = &xfer->send.hdr; 881103285Sikob tcode = fp->mode.common.tcode; 882103285Sikob 883120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 884103285Sikob info = &tinfo[tcode]; 885113584Ssimokawa hdr_len = pl_off = info->hdr_len; 886119155Ssimokawa 887119155Ssimokawa ld = &ohcifp->mode.ld[0]; 888119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 889119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 890119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 891119155Ssimokawa 892120660Ssimokawa ohcifp->mode.common.spd = xfer->send.spd & 0x7; 893103285Sikob if (tcode == FWTCODE_STREAM ){ 894103285Sikob hdr_len = 8; 895113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 896103285Sikob } else if (tcode == FWTCODE_PHY) { 897103285Sikob hdr_len = 12; 898119155Ssimokawa ld[1] = fp->mode.ld[1]; 899119155Ssimokawa ld[2] = fp->mode.ld[2]; 900103285Sikob ohcifp->mode.common.spd = 0; 901103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 902103285Sikob } else { 903113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 904103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 905103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 906103285Sikob } 907103285Sikob db = &db_tr->db[0]; 908113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 909113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 910119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 911113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 912103285Sikob/* Specify bound timer of asy. responce */ 913103285Sikob if(&sc->atrs == dbch){ 914113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 915113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 916103285Sikob } 917113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 918113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 919113584Ssimokawa hdr_len = 12; 920113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 921119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 922113584Ssimokawa#endif 923103285Sikob 924111942Ssimokawaagain: 925103285Sikob db_tr->dbcnt = 2; 926103285Sikob db = &db_tr->db[db_tr->dbcnt]; 927120660Ssimokawa if (xfer->send.pay_len > 0) { 928113584Ssimokawa int err; 929113584Ssimokawa /* handle payload */ 930103285Sikob if (xfer->mbuf == NULL) { 931113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 932120660Ssimokawa &xfer->send.payload[0], xfer->send.pay_len, 933113584Ssimokawa fwohci_execute_db, db_tr, 934113584Ssimokawa /*flags*/0); 935103285Sikob } else { 936111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 937113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 938113584Ssimokawa xfer->mbuf, 939113584Ssimokawa fwohci_execute_db2, db_tr, 940113584Ssimokawa /* flags */0); 941113584Ssimokawa if (err == EFBIG) { 942113584Ssimokawa struct mbuf *m0; 943113584Ssimokawa 944113584Ssimokawa if (firewire_debug) 945113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 946113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 947113584Ssimokawa if (m0 != NULL) { 948111942Ssimokawa m_copydata(xfer->mbuf, 0, 949111942Ssimokawa xfer->mbuf->m_pkthdr.len, 950113584Ssimokawa mtod(m0, caddr_t)); 951113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 952111942Ssimokawa xfer->mbuf->m_pkthdr.len; 953111942Ssimokawa m_freem(xfer->mbuf); 954113584Ssimokawa xfer->mbuf = m0; 955111942Ssimokawa goto again; 956111942Ssimokawa } 957111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 958111942Ssimokawa } 959103285Sikob } 960113584Ssimokawa if (err) 961113584Ssimokawa printf("dmamap_load: err=%d\n", err); 962113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 963113584Ssimokawa BUS_DMASYNC_PREWRITE); 964113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 965113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 966113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 967113584Ssimokawa OHCI_OUTPUT_MORE); 968113584Ssimokawa#endif 969103285Sikob } 970108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 971108655Ssimokawa maxdesc = db_tr->dbcnt; 972108655Ssimokawa if (bootverbose) 973108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 974108655Ssimokawa } 975103285Sikob /* last db */ 976103285Sikob LAST_DB(db_tr, db); 977113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 978113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 979113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 980113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 981103285Sikob 982103285Sikob if(fsegment == -1 ) 983103285Sikob fsegment = db_tr->dbcnt; 984103285Sikob if (dbch->pdb_tr != NULL) { 985103285Sikob LAST_DB(dbch->pdb_tr, db); 986113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 987103285Sikob } 988103285Sikob dbch->pdb_tr = db_tr; 989103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 990103285Sikob if(db_tr != dbch->bottom){ 991103285Sikob goto txloop; 992103285Sikob } else { 993107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 994103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 995103285Sikob } 996103285Sikobkick: 997103285Sikob /* kick asy q */ 998113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 999113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1000103285Sikob 1001103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1002103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1003103285Sikob } else { 1004107653Ssimokawa if (bootverbose) 1005107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1006103285Sikob OREAD(sc, OHCI_DMACTL(off))); 1007113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1008103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1009103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1010103285Sikob } 1011106790Ssimokawa 1012103285Sikob dbch->top = db_tr; 1013103285Sikob splx(s); 1014103285Sikob return; 1015103285Sikob} 1016106790Ssimokawa 1017106790Ssimokawastatic void 1018106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1019103285Sikob{ 1020103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021103285Sikob fwohci_start( sc, &(sc->atrq)); 1022103285Sikob return; 1023103285Sikob} 1024106790Ssimokawa 1025106790Ssimokawastatic void 1026106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1027103285Sikob{ 1028103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1029103285Sikob fwohci_start( sc, &(sc->atrs)); 1030103285Sikob return; 1031103285Sikob} 1032106790Ssimokawa 1033106790Ssimokawavoid 1034106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1035103285Sikob{ 1036113584Ssimokawa int s, ch, err = 0; 1037103285Sikob struct fwohcidb_tr *tr; 1038120660Ssimokawa struct fwohcidb *db; 1039103285Sikob struct fw_xfer *xfer; 1040129585Sdfr uint32_t off; 1041113584Ssimokawa u_int stat, status; 1042103285Sikob int packets; 1043103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1044113584Ssimokawa 1045103285Sikob if(&sc->atrq == dbch){ 1046103285Sikob off = OHCI_ATQOFF; 1047113584Ssimokawa ch = ATRQ_CH; 1048103285Sikob }else if(&sc->atrs == dbch){ 1049103285Sikob off = OHCI_ATSOFF; 1050113584Ssimokawa ch = ATRS_CH; 1051103285Sikob }else{ 1052103285Sikob return; 1053103285Sikob } 1054103285Sikob s = splfw(); 1055103285Sikob tr = dbch->bottom; 1056103285Sikob packets = 0; 1057113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1058113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1059103285Sikob while(dbch->xferq.queued > 0){ 1060103285Sikob LAST_DB(tr, db); 1061113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1062113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1063103285Sikob if (fc->status != FWBUSRESET) 1064103285Sikob /* maybe out of order?? */ 1065103285Sikob goto out; 1066103285Sikob } 1067113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1068113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1069113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1070119155Ssimokawa#if 1 1071119155Ssimokawa if (firewire_debug) 1072119155Ssimokawa dump_db(sc, ch); 1073103285Sikob#endif 1074113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1075113584Ssimokawa /* Stop DMA */ 1076103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1077103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1078103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1079103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1080103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1081103285Sikob } 1082113584Ssimokawa stat = status & FWOHCIEV_MASK; 1083103285Sikob switch(stat){ 1084110577Ssimokawa case FWOHCIEV_ACKPEND: 1085103285Sikob case FWOHCIEV_ACKCOMPL: 1086103285Sikob err = 0; 1087103285Sikob break; 1088103285Sikob case FWOHCIEV_ACKBSA: 1089103285Sikob case FWOHCIEV_ACKBSB: 1090110577Ssimokawa case FWOHCIEV_ACKBSX: 1091103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1092103285Sikob err = EBUSY; 1093103285Sikob break; 1094103285Sikob case FWOHCIEV_FLUSHED: 1095103285Sikob case FWOHCIEV_ACKTARD: 1096103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1097103285Sikob err = EAGAIN; 1098103285Sikob break; 1099103285Sikob case FWOHCIEV_MISSACK: 1100103285Sikob case FWOHCIEV_UNDRRUN: 1101103285Sikob case FWOHCIEV_OVRRUN: 1102103285Sikob case FWOHCIEV_DESCERR: 1103103285Sikob case FWOHCIEV_DTRDERR: 1104103285Sikob case FWOHCIEV_TIMEOUT: 1105103285Sikob case FWOHCIEV_TCODERR: 1106103285Sikob case FWOHCIEV_UNKNOWN: 1107103285Sikob case FWOHCIEV_ACKDERR: 1108103285Sikob case FWOHCIEV_ACKTERR: 1109103285Sikob default: 1110103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1111103285Sikob stat, fwohcicode[stat]); 1112103285Sikob err = EINVAL; 1113103285Sikob break; 1114103285Sikob } 1115110577Ssimokawa if (tr->xfer != NULL) { 1116103285Sikob xfer = tr->xfer; 1117113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1118119289Ssimokawa#if 0 1119113584Ssimokawa if (firewire_debug) 1120113584Ssimokawa printf("already rcvd\n"); 1121119289Ssimokawa#endif 1122113584Ssimokawa fw_xfer_done(xfer); 1123113584Ssimokawa } else { 1124114218Ssimokawa xfer->state = FWXF_SENT; 1125114218Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1126114218Ssimokawa xfer->state = FWXF_BUSY; 1127114218Ssimokawa xfer->resp = err; 1128114218Ssimokawa if (xfer->retry_req != NULL) 1129114218Ssimokawa xfer->retry_req(xfer); 1130114224Ssimokawa else { 1131120660Ssimokawa xfer->recv.pay_len = 0; 1132114218Ssimokawa fw_xfer_done(xfer); 1133114224Ssimokawa } 1134114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1135114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1136114218Ssimokawa xfer->state = FWXF_SENTERR; 1137114218Ssimokawa xfer->resp = err; 1138120660Ssimokawa xfer->recv.pay_len = 0; 1139113584Ssimokawa fw_xfer_done(xfer); 1140114218Ssimokawa } 1141103285Sikob } 1142110577Ssimokawa /* 1143110577Ssimokawa * The watchdog timer takes care of split 1144110577Ssimokawa * transcation timeout for ACKPEND case. 1145110577Ssimokawa */ 1146113584Ssimokawa } else { 1147113584Ssimokawa printf("this shouldn't happen\n"); 1148103285Sikob } 1149110269Ssimokawa dbch->xferq.queued --; 1150103285Sikob tr->xfer = NULL; 1151103285Sikob 1152103285Sikob packets ++; 1153103285Sikob tr = STAILQ_NEXT(tr, link); 1154103285Sikob dbch->bottom = tr; 1155111956Ssimokawa if (dbch->bottom == dbch->top) { 1156111956Ssimokawa /* we reaches the end of context program */ 1157111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1158111956Ssimokawa printf("queued > 0\n"); 1159111956Ssimokawa break; 1160111956Ssimokawa } 1161103285Sikob } 1162103285Sikobout: 1163103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1164103285Sikob printf("make free slot\n"); 1165103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1166103285Sikob fwohci_start(sc, dbch); 1167103285Sikob } 1168103285Sikob splx(s); 1169103285Sikob} 1170106790Ssimokawa 1171106790Ssimokawastatic void 1172106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1173103285Sikob{ 1174103285Sikob struct fwohcidb_tr *db_tr; 1175113584Ssimokawa int idb; 1176103285Sikob 1177108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1178108527Ssimokawa return; 1179108527Ssimokawa 1180113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1181103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1182113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1183113584Ssimokawa db_tr->buf != NULL) { 1184113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1185113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1186113584Ssimokawa db_tr->buf = NULL; 1187113584Ssimokawa } else if (db_tr->dma_map != NULL) 1188113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1189103285Sikob } 1190103285Sikob dbch->ndb = 0; 1191103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1192113584Ssimokawa fwdma_free_multiseg(dbch->am); 1193110195Ssimokawa free(db_tr, M_FW); 1194103285Sikob STAILQ_INIT(&dbch->db_trq); 1195108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1196103285Sikob} 1197106790Ssimokawa 1198106790Ssimokawastatic void 1199113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1200103285Sikob{ 1201103285Sikob int idb; 1202103285Sikob struct fwohcidb_tr *db_tr; 1203108642Ssimokawa 1204108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1205108642Ssimokawa goto out; 1206108642Ssimokawa 1207113584Ssimokawa /* create dma_tag for buffers */ 1208113584Ssimokawa#define MAX_REQCOUNT 0xffff 1209113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1210113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1211113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1212113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1213113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1214113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1215113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1216113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1217117126Sscottl /*flags*/ 0, 1218127468Ssimokawa#if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1219117126Sscottl /*lockfunc*/busdma_lock_mutex, 1220117228Ssimokawa /*lockarg*/&Giant, 1221117228Ssimokawa#endif 1222117228Ssimokawa &dbch->dmat)) 1223113584Ssimokawa return; 1224113584Ssimokawa 1225103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1226103285Sikob /* DB entry must start at 16 bytes bounary. */ 1227103285Sikob STAILQ_INIT(&dbch->db_trq); 1228103285Sikob db_tr = (struct fwohcidb_tr *) 1229103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1230113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1231103285Sikob if(db_tr == NULL){ 1232109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1233103285Sikob return; 1234103285Sikob } 1235109379Ssimokawa 1236113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1237113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1238113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1239113584Ssimokawa if (dbch->am == NULL) { 1240113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1241124836Ssimokawa free(db_tr, M_FW); 1242103285Sikob return; 1243103285Sikob } 1244103285Sikob /* Attach DB to DMA ch. */ 1245103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1246103285Sikob db_tr->dbcnt = 0; 1247113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1248113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1249113584Ssimokawa /* create dmamap for buffers */ 1250113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1251113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1252113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1253113584Ssimokawa printf("bus_dmamap_create failed\n"); 1254113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1255113584Ssimokawa fwohci_db_free(dbch); 1256113584Ssimokawa return; 1257113584Ssimokawa } 1258103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1259113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1260108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1261108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1262108530Ssimokawa ].start = (caddr_t)db_tr; 1263108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1264108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1265108530Ssimokawa ].end = (caddr_t)db_tr; 1266103285Sikob } 1267103285Sikob db_tr++; 1268103285Sikob } 1269103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1270103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1271108642Ssimokawaout: 1272108642Ssimokawa dbch->xferq.queued = 0; 1273108642Ssimokawa dbch->pdb_tr = NULL; 1274103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1275103285Sikob dbch->bottom = dbch->top; 1276108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1277103285Sikob} 1278106790Ssimokawa 1279106790Ssimokawastatic int 1280106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1281103285Sikob{ 1282103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1283113584Ssimokawa int sleepch; 1284109890Ssimokawa 1285113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1286113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1287103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1288103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1289109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1290113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1291103285Sikob fwohci_db_free(&sc->it[dmach]); 1292103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1293103285Sikob return 0; 1294103285Sikob} 1295106790Ssimokawa 1296106790Ssimokawastatic int 1297106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1298103285Sikob{ 1299103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1300113584Ssimokawa int sleepch; 1301103285Sikob 1302103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1303103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1304103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1305109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1306113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1307103285Sikob fwohci_db_free(&sc->ir[dmach]); 1308103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1309103285Sikob return 0; 1310103285Sikob} 1311106790Ssimokawa 1312113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1313106790Ssimokawastatic void 1314129585Sdfrfwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1315103285Sikob{ 1316113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1317103285Sikob return; 1318103285Sikob} 1319103285Sikob#endif 1320103285Sikob 1321106790Ssimokawastatic int 1322106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1323103285Sikob{ 1324103285Sikob int err = 0; 1325113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1326129585Sdfr uint32_t off = 0; 1327103285Sikob struct fwohcidb_tr *db_tr; 1328120660Ssimokawa struct fwohcidb *db; 1329103285Sikob 1330103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1331103285Sikob err = EINVAL; 1332103285Sikob return err; 1333103285Sikob } 1334103285Sikob z = dbch->ndesc; 1335103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1336103285Sikob if( &sc->it[dmach] == dbch){ 1337103285Sikob off = OHCI_ITOFF(dmach); 1338103285Sikob break; 1339103285Sikob } 1340103285Sikob } 1341123740Speter if(off == 0){ 1342103285Sikob err = EINVAL; 1343103285Sikob return err; 1344103285Sikob } 1345103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1346103285Sikob return err; 1347103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1348103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1349103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1350103285Sikob } 1351103285Sikob db_tr = dbch->top; 1352113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1353113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1354103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1355103285Sikob break; 1356103285Sikob } 1357109892Ssimokawa db = db_tr->db; 1358113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1359113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1360113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1361113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1362103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1363103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1364113584Ssimokawa FWOHCI_DMA_SET( 1365113584Ssimokawa db[ldesc].db.desc.cmd, 1366113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1367109280Ssimokawa /* OHCI 1.1 and above */ 1368113584Ssimokawa FWOHCI_DMA_SET( 1369113584Ssimokawa db[0].db.desc.cmd, 1370113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1371103285Sikob } 1372103285Sikob } 1373103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1374103285Sikob } 1375113584Ssimokawa FWOHCI_DMA_CLEAR( 1376113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1377103285Sikob return err; 1378103285Sikob} 1379106790Ssimokawa 1380106790Ssimokawastatic int 1381106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1382103285Sikob{ 1383103285Sikob int err = 0; 1384109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1385129585Sdfr uint32_t off = 0; 1386103285Sikob struct fwohcidb_tr *db_tr; 1387120660Ssimokawa struct fwohcidb *db; 1388103285Sikob 1389103285Sikob z = dbch->ndesc; 1390103285Sikob if(&sc->arrq == dbch){ 1391103285Sikob off = OHCI_ARQOFF; 1392103285Sikob }else if(&sc->arrs == dbch){ 1393103285Sikob off = OHCI_ARSOFF; 1394103285Sikob }else{ 1395103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1396103285Sikob if( &sc->ir[dmach] == dbch){ 1397103285Sikob off = OHCI_IROFF(dmach); 1398103285Sikob break; 1399103285Sikob } 1400103285Sikob } 1401103285Sikob } 1402123740Speter if(off == 0){ 1403103285Sikob err = EINVAL; 1404103285Sikob return err; 1405103285Sikob } 1406103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1407103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1408103285Sikob return err; 1409103285Sikob }else{ 1410103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1411103285Sikob err = EBUSY; 1412103285Sikob return err; 1413103285Sikob } 1414103285Sikob } 1415103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1416108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1417103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1418103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1419103285Sikob } 1420103285Sikob db_tr = dbch->top; 1421113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1422113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1423113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1424103285Sikob break; 1425109892Ssimokawa db = db_tr->db; 1426109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1427113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1428113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1429103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1430103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1431113584Ssimokawa FWOHCI_DMA_SET( 1432113584Ssimokawa db[ldesc].db.desc.cmd, 1433113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1434113584Ssimokawa FWOHCI_DMA_CLEAR( 1435113584Ssimokawa db[ldesc].db.desc.depend, 1436113584Ssimokawa 0xf); 1437103285Sikob } 1438103285Sikob } 1439103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1440103285Sikob } 1441113584Ssimokawa FWOHCI_DMA_CLEAR( 1442113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1443103285Sikob dbch->buf_offset = 0; 1444113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1445113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1446103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1447103285Sikob return err; 1448103285Sikob }else{ 1449113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1450103285Sikob } 1451103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1452103285Sikob return err; 1453103285Sikob} 1454106790Ssimokawa 1455106790Ssimokawastatic int 1456113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1457109890Ssimokawa{ 1458109890Ssimokawa int sec, cycle, cycle_match; 1459109890Ssimokawa 1460109890Ssimokawa cycle = cycle_now & 0x1fff; 1461109890Ssimokawa sec = cycle_now >> 13; 1462109890Ssimokawa#define CYCLE_MOD 0x10 1463113584Ssimokawa#if 1 1464109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1465113584Ssimokawa#else 1466113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1467113584Ssimokawa#endif 1468109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1469109890Ssimokawa if (cycle >= 8000) { 1470109890Ssimokawa sec ++; 1471109890Ssimokawa cycle -= 8000; 1472109890Ssimokawa } 1473113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1474109890Ssimokawa if (cycle >= 8000) { 1475109890Ssimokawa sec ++; 1476109890Ssimokawa if (cycle == 8000) 1477109890Ssimokawa cycle = 0; 1478109890Ssimokawa else 1479109890Ssimokawa cycle = CYCLE_MOD; 1480109890Ssimokawa } 1481109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1482109890Ssimokawa 1483109890Ssimokawa return(cycle_match); 1484109890Ssimokawa} 1485109890Ssimokawa 1486109890Ssimokawastatic int 1487106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1488103285Sikob{ 1489103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1490103285Sikob int err = 0; 1491103285Sikob unsigned short tag, ich; 1492103285Sikob struct fwohci_dbch *dbch; 1493109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1494129585Sdfr uint32_t stat; 1495109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1496109890Ssimokawa struct fw_xferq *it; 1497103285Sikob 1498103285Sikob dbch = &sc->it[dmach]; 1499109890Ssimokawa it = &dbch->xferq; 1500109890Ssimokawa 1501109890Ssimokawa tag = (it->flag >> 6) & 3; 1502109890Ssimokawa ich = it->flag & 0x3f; 1503109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1504109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1505103285Sikob dbch->ndesc = 3; 1506113584Ssimokawa fwohci_db_init(sc, dbch); 1507109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1508109179Ssimokawa return ENOMEM; 1509103285Sikob err = fwohci_tx_enable(sc, dbch); 1510103285Sikob } 1511103285Sikob if(err) 1512103285Sikob return err; 1513109890Ssimokawa 1514109892Ssimokawa ldesc = dbch->ndesc - 1; 1515109890Ssimokawa s = splfw(); 1516109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1517109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1518120660Ssimokawa struct fwohcidb *db; 1519109890Ssimokawa 1520113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1521113584Ssimokawa BUS_DMASYNC_PREWRITE); 1522109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1523109890Ssimokawa if (prev != NULL) { 1524109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1525113584Ssimokawa#if 0 /* XXX necessary? */ 1526113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1527113584Ssimokawa OHCI_BRANCH_ALWAYS); 1528113584Ssimokawa#endif 1529109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1530109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1531113584Ssimokawa ((struct fwohcidb_tr *) 1532113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1533109892Ssimokawa#else 1534113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1535113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1536109892Ssimokawa#endif 1537103285Sikob } 1538109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1539109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1540109890Ssimokawa prev = chunk; 1541109403Ssimokawa } 1542113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1543113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1544109890Ssimokawa splx(s); 1545109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1546113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1547113584Ssimokawa printf("stat 0x%x\n", stat); 1548113584Ssimokawa 1549109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1550109890Ssimokawa return 0; 1551109890Ssimokawa 1552113584Ssimokawa#if 0 1553109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1554113584Ssimokawa#endif 1555109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1556109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1557109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1558113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1559109890Ssimokawa 1560109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1561113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1562113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1563113584Ssimokawa if (firewire_debug) { 1564109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1565113584Ssimokawa#if 1 1566113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1567113584Ssimokawa#endif 1568113584Ssimokawa } 1569109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1570109890Ssimokawa#if 1 1571109890Ssimokawa /* Don't start until all chunks are buffered */ 1572109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1573109890Ssimokawa goto out; 1574109890Ssimokawa#endif 1575113584Ssimokawa#if 1 1576109890Ssimokawa /* Clear cycle match counter bits */ 1577109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1578109890Ssimokawa 1579109356Ssimokawa /* 2bit second + 13bit cycle */ 1580109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1581113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1582109890Ssimokawa 1583109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1584109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1585109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1586113584Ssimokawa#else 1587113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1588113584Ssimokawa#endif 1589113584Ssimokawa if (firewire_debug) { 1590109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1591109403Ssimokawa cycle_now, cycle_match); 1592113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1593113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1594113584Ssimokawa } 1595109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1596109890Ssimokawa device_printf(sc->fc.dev, 1597109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1598113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1599103285Sikob } 1600109890Ssimokawaout: 1601103285Sikob return err; 1602103285Sikob} 1603106790Ssimokawa 1604106790Ssimokawastatic int 1605113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1606103285Sikob{ 1607103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1608109890Ssimokawa int err = 0, s, ldesc; 1609103285Sikob unsigned short tag, ich; 1610129585Sdfr uint32_t stat; 1611109890Ssimokawa struct fwohci_dbch *dbch; 1612113584Ssimokawa struct fwohcidb_tr *db_tr; 1613109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1614109890Ssimokawa struct fw_xferq *ir; 1615103285Sikob 1616109890Ssimokawa dbch = &sc->ir[dmach]; 1617109890Ssimokawa ir = &dbch->xferq; 1618109890Ssimokawa 1619109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1620109890Ssimokawa tag = (ir->flag >> 6) & 3; 1621109890Ssimokawa ich = ir->flag & 0x3f; 1622108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1623108995Ssimokawa 1624109890Ssimokawa ir->queued = 0; 1625109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1626109890Ssimokawa dbch->ndesc = 2; 1627113584Ssimokawa fwohci_db_init(sc, dbch); 1628109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1629109179Ssimokawa return ENOMEM; 1630109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1631103285Sikob } 1632103285Sikob if(err) 1633103285Sikob return err; 1634103285Sikob 1635109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1636109890Ssimokawa if (first == NULL) { 1637109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1638109890Ssimokawa return 0; 1639109890Ssimokawa } 1640109890Ssimokawa 1641111892Ssimokawa ldesc = dbch->ndesc - 1; 1642111892Ssimokawa s = splfw(); 1643109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1644109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1645120660Ssimokawa struct fwohcidb *db; 1646109890Ssimokawa 1647111942Ssimokawa#if 1 /* XXX for if_fwe */ 1648113584Ssimokawa if (chunk->mbuf != NULL) { 1649113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1650113584Ssimokawa db_tr->dbcnt = 1; 1651113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1652113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1653113584Ssimokawa /* flags */0); 1654113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1655113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1656113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1657113584Ssimokawa } 1658111942Ssimokawa#endif 1659109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1660113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1661113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1662109890Ssimokawa if (prev != NULL) { 1663109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1664113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1665103285Sikob } 1666109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1667109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1668109890Ssimokawa prev = chunk; 1669103285Sikob } 1670113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1671113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1672109890Ssimokawa splx(s); 1673109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1674109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1675109890Ssimokawa return 0; 1676109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1677109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1678109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1679109890Ssimokawa } 1680109890Ssimokawa 1681113584Ssimokawa if (firewire_debug) 1682113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1683109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1684109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1685109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1686109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1687109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1688109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1689113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1690109890Ssimokawa | dbch->ndesc); 1691109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1692109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1693113584Ssimokawa#if 0 1694113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1695113584Ssimokawa#endif 1696103285Sikob return err; 1697103285Sikob} 1698106790Ssimokawa 1699106790Ssimokawaint 1700110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1701103285Sikob{ 1702103285Sikob u_int i; 1703103285Sikob 1704103285Sikob/* Now stopping all DMA channel */ 1705103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1706103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1707103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1708103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1709103285Sikob 1710103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1711103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1712103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1713103285Sikob } 1714103285Sikob 1715103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1716103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1717103285Sikob 1718103285Sikob/* Stop interrupt */ 1719103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1720103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1721103285Sikob | OHCI_INT_PHY_INT 1722103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1723103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1724103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1725103285Sikob | OHCI_INT_PHY_BUS_R); 1726116978Ssimokawa 1727118416Ssimokawa if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1728118416Ssimokawa fw_drain_txq(&sc->fc); 1729116978Ssimokawa 1730108642Ssimokawa/* XXX Link down? Bus reset? */ 1731103285Sikob return 0; 1732103285Sikob} 1733103285Sikob 1734108642Ssimokawaint 1735108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1736108642Ssimokawa{ 1737108642Ssimokawa int i; 1738116978Ssimokawa struct fw_xferq *ir; 1739116978Ssimokawa struct fw_bulkxfer *chunk; 1740108642Ssimokawa 1741108642Ssimokawa fwohci_reset(sc, dev); 1742129541Sdfr /* XXX resume isochronous receive automatically. (how about TX?) */ 1743108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1744116978Ssimokawa ir = &sc->ir[i].xferq; 1745116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1746108642Ssimokawa device_printf(sc->fc.dev, 1747108642Ssimokawa "resume iso receive ch: %d\n", i); 1748116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1749116978Ssimokawa /* requeue stdma to stfree */ 1750116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1751116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1752116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1753116978Ssimokawa } 1754108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1755108642Ssimokawa } 1756108642Ssimokawa } 1757108642Ssimokawa 1758108642Ssimokawa bus_generic_resume(dev); 1759108642Ssimokawa sc->fc.ibr(&sc->fc); 1760108642Ssimokawa return 0; 1761108642Ssimokawa} 1762108642Ssimokawa 1763103285Sikob#define ACK_ALL 1764103285Sikobstatic void 1765129585Sdfrfwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1766103285Sikob{ 1767129585Sdfr uint32_t irstat, itstat; 1768103285Sikob u_int i; 1769103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1770103285Sikob 1771103285Sikob#ifdef OHCI_DEBUG 1772103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1773103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1774103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1775103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1776103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1777103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1778103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1779103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1780103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1781103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1782103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1783103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1784103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1785103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1786103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1787103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1788103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1789103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1790103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1791103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1792103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1793103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1794103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1795103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1796103285Sikob ); 1797103285Sikob#endif 1798103285Sikob/* Bus reset */ 1799103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1800111074Ssimokawa if (fc->status == FWBUSRESET) 1801111074Ssimokawa goto busresetout; 1802111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1803111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1804111074Ssimokawa 1805103285Sikob device_printf(fc->dev, "BUS reset\n"); 1806103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1807103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1808103285Sikob 1809103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1810103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1811103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1812103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1813103285Sikob 1814103285Sikob#ifndef ACK_ALL 1815103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1816103285Sikob#endif 1817110798Ssimokawa fw_busreset(fc); 1818116376Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1819116376Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1820103285Sikob } 1821111074Ssimokawabusresetout: 1822103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1823103285Sikob#ifndef ACK_ALL 1824103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1825103285Sikob#endif 1826127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 1827113584Ssimokawa irstat = sc->irstat; 1828113584Ssimokawa sc->irstat = 0; 1829127468Ssimokawa#else 1830127468Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1831113584Ssimokawa#endif 1832103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1833109644Ssimokawa struct fwohci_dbch *dbch; 1834109644Ssimokawa 1835103285Sikob if((irstat & (1 << i)) != 0){ 1836109644Ssimokawa dbch = &sc->ir[i]; 1837109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1838109644Ssimokawa device_printf(sc->fc.dev, 1839109644Ssimokawa "dma(%d) not active\n", i); 1840109644Ssimokawa continue; 1841109644Ssimokawa } 1842113584Ssimokawa fwohci_rbuf_update(sc, i); 1843103285Sikob } 1844103285Sikob } 1845103285Sikob } 1846103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1847103285Sikob#ifndef ACK_ALL 1848103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1849103285Sikob#endif 1850127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 1851113584Ssimokawa itstat = sc->itstat; 1852113584Ssimokawa sc->itstat = 0; 1853127468Ssimokawa#else 1854127468Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1855113584Ssimokawa#endif 1856103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1857103285Sikob if((itstat & (1 << i)) != 0){ 1858103285Sikob fwohci_tbuf_update(sc, i); 1859103285Sikob } 1860103285Sikob } 1861103285Sikob } 1862103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1863103285Sikob#ifndef ACK_ALL 1864103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1865103285Sikob#endif 1866103285Sikob#if 0 1867103285Sikob dump_dma(sc, ARRS_CH); 1868103285Sikob dump_db(sc, ARRS_CH); 1869103285Sikob#endif 1870106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1871103285Sikob } 1872103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1873103285Sikob#ifndef ACK_ALL 1874103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1875103285Sikob#endif 1876103285Sikob#if 0 1877103285Sikob dump_dma(sc, ARRQ_CH); 1878103285Sikob dump_db(sc, ARRQ_CH); 1879103285Sikob#endif 1880106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1881103285Sikob } 1882103285Sikob if(stat & OHCI_INT_PHY_SID){ 1883129585Sdfr uint32_t *buf, node_id; 1884103285Sikob int plen; 1885103285Sikob 1886103285Sikob#ifndef ACK_ALL 1887103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1888103285Sikob#endif 1889111074Ssimokawa /* Enable bus reset interrupt */ 1890111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1891111787Ssimokawa /* Allow async. request to us */ 1892111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1893111787Ssimokawa /* XXX insecure ?? */ 1894111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1895111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1896111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1897112523Ssimokawa /* Set ATRetries register */ 1898112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1899103285Sikob/* 1900103285Sikob** Checking whether the node is root or not. If root, turn on 1901103285Sikob** cycle master. 1902103285Sikob*/ 1903113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1904113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1905113584Ssimokawa 1906113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1907113584Ssimokawa node_id, (plen >> 16) & 0xff); 1908113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1909103285Sikob printf("Bus reset failure\n"); 1910103285Sikob goto sidout; 1911103285Sikob } 1912113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1913103285Sikob printf("CYCLEMASTER mode\n"); 1914103285Sikob OWRITE(sc, OHCI_LNKCTL, 1915103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1916113584Ssimokawa } else { 1917103285Sikob printf("non CYCLEMASTER mode\n"); 1918103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1919103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1920103285Sikob } 1921113584Ssimokawa fc->nodeid = node_id & 0x3f; 1922103285Sikob 1923113584Ssimokawa if (plen & OHCI_SID_ERR) { 1924113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1925113584Ssimokawa goto sidout; 1926113584Ssimokawa } 1927113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1928109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1929109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1930109736Ssimokawa goto sidout; 1931109736Ssimokawa } 1932103285Sikob plen -= 4; /* chop control info */ 1933129585Sdfr buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1934113584Ssimokawa if (buf == NULL) { 1935113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1936113584Ssimokawa goto sidout; 1937113584Ssimokawa } 1938113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1939113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1940127468Ssimokawa#if 1 /* XXX needed?? */ 1941110269Ssimokawa /* pending all pre-bus_reset packets */ 1942110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1943110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1944110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1945110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1946110798Ssimokawa fw_drain_txq(fc); 1947110269Ssimokawa#endif 1948113584Ssimokawa fw_sidrcv(fc, buf, plen); 1949113584Ssimokawa free(buf, M_FW); 1950103285Sikob } 1951103285Sikobsidout: 1952103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1953103285Sikob#ifndef ACK_ALL 1954103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1955103285Sikob#endif 1956103285Sikob fwohci_txd(sc, &(sc->atrq)); 1957103285Sikob } 1958103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1959103285Sikob#ifndef ACK_ALL 1960103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1961103285Sikob#endif 1962103285Sikob fwohci_txd(sc, &(sc->atrs)); 1963103285Sikob } 1964103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1965103285Sikob#ifndef ACK_ALL 1966103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1967103285Sikob#endif 1968103285Sikob device_printf(fc->dev, "posted write error\n"); 1969103285Sikob } 1970103285Sikob if((stat & OHCI_INT_ERR )){ 1971103285Sikob#ifndef ACK_ALL 1972103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1973103285Sikob#endif 1974103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1975103285Sikob } 1976103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1977103285Sikob#ifndef ACK_ALL 1978103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1979103285Sikob#endif 1980103285Sikob device_printf(fc->dev, "phy int\n"); 1981103285Sikob } 1982103285Sikob 1983103285Sikob return; 1984103285Sikob} 1985103285Sikob 1986113584Ssimokawa#if FWOHCI_TASKQUEUE 1987113584Ssimokawastatic void 1988113584Ssimokawafwohci_complete(void *arg, int pending) 1989113584Ssimokawa{ 1990113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1991129585Sdfr uint32_t stat; 1992113584Ssimokawa 1993113584Ssimokawaagain: 1994113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 1995113584Ssimokawa if (stat) 1996113584Ssimokawa fwohci_intr_body(sc, stat, -1); 1997113584Ssimokawa else 1998113584Ssimokawa return; 1999113584Ssimokawa goto again; 2000113584Ssimokawa} 2001113584Ssimokawa#endif 2002113584Ssimokawa 2003129585Sdfrstatic uint32_t 2004113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 2005113584Ssimokawa{ 2006129585Sdfr uint32_t stat, irstat, itstat; 2007113584Ssimokawa 2008113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 2009113584Ssimokawa if (stat == 0xffffffff) { 2010113584Ssimokawa device_printf(sc->fc.dev, 2011113584Ssimokawa "device physically ejected?\n"); 2012113584Ssimokawa return(stat); 2013113584Ssimokawa } 2014113584Ssimokawa#ifdef ACK_ALL 2015113584Ssimokawa if (stat) 2016113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2017113584Ssimokawa#endif 2018113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2019113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2020113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2021113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2022113584Ssimokawa } 2023113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2024113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2025113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2026113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2027113584Ssimokawa } 2028113584Ssimokawa return(stat); 2029113584Ssimokawa} 2030113584Ssimokawa 2031103285Sikobvoid 2032103285Sikobfwohci_intr(void *arg) 2033103285Sikob{ 2034103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2035129585Sdfr uint32_t stat; 2036113584Ssimokawa#if !FWOHCI_TASKQUEUE 2037129585Sdfr uint32_t bus_reset = 0; 2038113584Ssimokawa#endif 2039103285Sikob 2040103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 2041103285Sikob /* polling mode */ 2042103285Sikob return; 2043103285Sikob } 2044103285Sikob 2045113584Ssimokawa#if !FWOHCI_TASKQUEUE 2046113584Ssimokawaagain: 2047103285Sikob#endif 2048113584Ssimokawa stat = fwochi_check_stat(sc); 2049113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2050113584Ssimokawa return; 2051113584Ssimokawa#if FWOHCI_TASKQUEUE 2052113584Ssimokawa atomic_set_int(&sc->intstat, stat); 2053113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 2054113584Ssimokawa if (stat) 2055113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2056113584Ssimokawa#else 2057113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 2058113584Ssimokawa if ((stat & ~bus_reset) == 0) 2059113584Ssimokawa return; 2060113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2061113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2062113584Ssimokawa goto again; 2063113584Ssimokawa#endif 2064103285Sikob} 2065103285Sikob 2066116897Ssimokawavoid 2067103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2068103285Sikob{ 2069103285Sikob int s; 2070129585Sdfr uint32_t stat; 2071103285Sikob struct fwohci_softc *sc; 2072103285Sikob 2073103285Sikob 2074103285Sikob sc = (struct fwohci_softc *)fc; 2075103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2076103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2077103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2078103285Sikob#if 0 2079103285Sikob if (!quick) { 2080103285Sikob#else 2081103285Sikob if (1) { 2082103285Sikob#endif 2083113584Ssimokawa stat = fwochi_check_stat(sc); 2084113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2085103285Sikob return; 2086103285Sikob } 2087103285Sikob s = splfw(); 2088106789Ssimokawa fwohci_intr_body(sc, stat, count); 2089103285Sikob splx(s); 2090103285Sikob} 2091103285Sikob 2092103285Sikobstatic void 2093103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2094103285Sikob{ 2095103285Sikob struct fwohci_softc *sc; 2096103285Sikob 2097103285Sikob sc = (struct fwohci_softc *)fc; 2098107653Ssimokawa if (bootverbose) 2099108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2100103285Sikob if (enable) { 2101103285Sikob sc->intmask |= OHCI_INT_EN; 2102103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2103103285Sikob } else { 2104103285Sikob sc->intmask &= ~OHCI_INT_EN; 2105103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2106103285Sikob } 2107103285Sikob} 2108103285Sikob 2109106790Ssimokawastatic void 2110106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2111103285Sikob{ 2112103285Sikob struct firewire_comm *fc = &sc->fc; 2113120660Ssimokawa struct fwohcidb *db; 2114109890Ssimokawa struct fw_bulkxfer *chunk; 2115109890Ssimokawa struct fw_xferq *it; 2116129585Sdfr uint32_t stat, count; 2117113584Ssimokawa int s, w=0, ldesc; 2118103285Sikob 2119109890Ssimokawa it = fc->it[dmach]; 2120113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2121109890Ssimokawa s = splfw(); /* unnecessary ? */ 2122113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2123119155Ssimokawa if (firewire_debug) 2124119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2125109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2126109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2127113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2128113584Ssimokawa >> OHCI_STATUS_SHIFT; 2129109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2130119155Ssimokawa /* timestamp */ 2131113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2132113584Ssimokawa & OHCI_COUNT_MASK; 2133109890Ssimokawa if (stat == 0) 2134109890Ssimokawa break; 2135109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2136109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2137109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2138109890Ssimokawa#if 0 2139109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2140109179Ssimokawa#endif 2141109890Ssimokawa break; 2142109890Ssimokawa default: 2143109423Ssimokawa device_printf(fc->dev, 2144113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2145113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2146109890Ssimokawa } 2147109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2148109890Ssimokawa w++; 2149109403Ssimokawa } 2150109890Ssimokawa splx(s); 2151109890Ssimokawa if (w) 2152109890Ssimokawa wakeup(it); 2153103285Sikob} 2154106790Ssimokawa 2155106790Ssimokawastatic void 2156106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2157103285Sikob{ 2158109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2159120660Ssimokawa struct fwohcidb_tr *db_tr; 2160109890Ssimokawa struct fw_bulkxfer *chunk; 2161109890Ssimokawa struct fw_xferq *ir; 2162129585Sdfr uint32_t stat; 2163113584Ssimokawa int s, w=0, ldesc; 2164109179Ssimokawa 2165109890Ssimokawa ir = fc->ir[dmach]; 2166113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2167113584Ssimokawa#if 0 2168113584Ssimokawa dump_db(sc, dmach); 2169113584Ssimokawa#endif 2170109890Ssimokawa s = splfw(); 2171113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2172109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2173113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2174113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2175113584Ssimokawa >> OHCI_STATUS_SHIFT; 2176109890Ssimokawa if (stat == 0) 2177109890Ssimokawa break; 2178113584Ssimokawa 2179113584Ssimokawa if (chunk->mbuf != NULL) { 2180113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2181113584Ssimokawa BUS_DMASYNC_POSTREAD); 2182113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2183113584Ssimokawa } else if (ir->buf != NULL) { 2184113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2185113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2186113584Ssimokawa } else { 2187113584Ssimokawa /* XXX */ 2188113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2189113584Ssimokawa } 2190113584Ssimokawa 2191109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2192109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2193109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2194109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2195111942Ssimokawa chunk->resp = 0; 2196109890Ssimokawa break; 2197109890Ssimokawa default: 2198111942Ssimokawa chunk->resp = EINVAL; 2199109890Ssimokawa device_printf(fc->dev, 2200113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2201113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2202109890Ssimokawa } 2203109890Ssimokawa w++; 2204103285Sikob } 2205109890Ssimokawa splx(s); 2206111942Ssimokawa if (w) { 2207111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2208111942Ssimokawa ir->hand(ir); 2209111942Ssimokawa else 2210111942Ssimokawa wakeup(ir); 2211111942Ssimokawa } 2212103285Sikob} 2213106790Ssimokawa 2214106790Ssimokawavoid 2215129585Sdfrdump_dma(struct fwohci_softc *sc, uint32_t ch) 2216106790Ssimokawa{ 2217129585Sdfr uint32_t off, cntl, stat, cmd, match; 2218103285Sikob 2219103285Sikob if(ch == 0){ 2220103285Sikob off = OHCI_ATQOFF; 2221103285Sikob }else if(ch == 1){ 2222103285Sikob off = OHCI_ATSOFF; 2223103285Sikob }else if(ch == 2){ 2224103285Sikob off = OHCI_ARQOFF; 2225103285Sikob }else if(ch == 3){ 2226103285Sikob off = OHCI_ARSOFF; 2227103285Sikob }else if(ch < IRX_CH){ 2228103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2229103285Sikob }else{ 2230103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2231103285Sikob } 2232103285Sikob cntl = stat = OREAD(sc, off); 2233103285Sikob cmd = OREAD(sc, off + 0xc); 2234103285Sikob match = OREAD(sc, off + 0x10); 2235103285Sikob 2236113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2237103285Sikob ch, 2238103285Sikob cntl, 2239103285Sikob cmd, 2240103285Sikob match); 2241103285Sikob stat &= 0xffff ; 2242113584Ssimokawa if (stat) { 2243103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2244103285Sikob ch, 2245103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2246103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2247103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2248103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2249103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2250103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2251103285Sikob fwohcicode[stat & 0x1f], 2252103285Sikob stat & 0x1f 2253103285Sikob ); 2254103285Sikob }else{ 2255103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2256103285Sikob } 2257103285Sikob} 2258106790Ssimokawa 2259106790Ssimokawavoid 2260129585Sdfrdump_db(struct fwohci_softc *sc, uint32_t ch) 2261106790Ssimokawa{ 2262103285Sikob struct fwohci_dbch *dbch; 2263113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2264120660Ssimokawa struct fwohcidb *curr = NULL, *prev, *next = NULL; 2265103285Sikob int idb, jdb; 2266129585Sdfr uint32_t cmd, off; 2267103285Sikob if(ch == 0){ 2268103285Sikob off = OHCI_ATQOFF; 2269103285Sikob dbch = &sc->atrq; 2270103285Sikob }else if(ch == 1){ 2271103285Sikob off = OHCI_ATSOFF; 2272103285Sikob dbch = &sc->atrs; 2273103285Sikob }else if(ch == 2){ 2274103285Sikob off = OHCI_ARQOFF; 2275103285Sikob dbch = &sc->arrq; 2276103285Sikob }else if(ch == 3){ 2277103285Sikob off = OHCI_ARSOFF; 2278103285Sikob dbch = &sc->arrs; 2279103285Sikob }else if(ch < IRX_CH){ 2280103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2281103285Sikob dbch = &sc->it[ch - ITX_CH]; 2282103285Sikob }else { 2283103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2284103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2285103285Sikob } 2286103285Sikob cmd = OREAD(sc, off + 0xc); 2287103285Sikob 2288103285Sikob if( dbch->ndb == 0 ){ 2289103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2290103285Sikob return; 2291103285Sikob } 2292103285Sikob pp = dbch->top; 2293103285Sikob prev = pp->db; 2294103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2295103285Sikob if(pp == NULL){ 2296103285Sikob curr = NULL; 2297103285Sikob goto outdb; 2298103285Sikob } 2299103285Sikob cp = STAILQ_NEXT(pp, link); 2300103285Sikob if(cp == NULL){ 2301103285Sikob curr = NULL; 2302103285Sikob goto outdb; 2303103285Sikob } 2304103285Sikob np = STAILQ_NEXT(cp, link); 2305103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2306113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2307103285Sikob curr = cp->db; 2308103285Sikob if(np != NULL){ 2309103285Sikob next = np->db; 2310103285Sikob }else{ 2311103285Sikob next = NULL; 2312103285Sikob } 2313103285Sikob goto outdb; 2314103285Sikob } 2315103285Sikob } 2316103285Sikob pp = STAILQ_NEXT(pp, link); 2317103285Sikob prev = pp->db; 2318103285Sikob } 2319103285Sikoboutdb: 2320103285Sikob if( curr != NULL){ 2321113584Ssimokawa#if 0 2322103285Sikob printf("Prev DB %d\n", ch); 2323113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2324113584Ssimokawa#endif 2325103285Sikob printf("Current DB %d\n", ch); 2326113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2327113584Ssimokawa#if 0 2328103285Sikob printf("Next DB %d\n", ch); 2329113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2330113584Ssimokawa#endif 2331103285Sikob }else{ 2332103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2333103285Sikob } 2334103285Sikob return; 2335103285Sikob} 2336106790Ssimokawa 2337106790Ssimokawavoid 2338120660Ssimokawaprint_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2339129585Sdfr uint32_t ch, uint32_t max) 2340106790Ssimokawa{ 2341103285Sikob fwohcireg_t stat; 2342103285Sikob int i, key; 2343129585Sdfr uint32_t cmd, res; 2344103285Sikob 2345103285Sikob if(db == NULL){ 2346103285Sikob printf("No Descriptor is found\n"); 2347103285Sikob return; 2348103285Sikob } 2349103285Sikob 2350103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2351103285Sikob ch, 2352103285Sikob "Current", 2353103285Sikob "OP ", 2354103285Sikob "KEY", 2355103285Sikob "INT", 2356103285Sikob "BR ", 2357103285Sikob "len", 2358103285Sikob "Addr", 2359103285Sikob "Depend", 2360103285Sikob "Stat", 2361103285Sikob "Cnt"); 2362103285Sikob for( i = 0 ; i <= max ; i ++){ 2363113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2364113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2365113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2366113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2367127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 2368127468Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2369127468Ssimokawa db_tr->bus_addr, 2370127468Ssimokawa#else 2371113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2372114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2373108712Ssimokawa#endif 2374113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2375113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2376113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2377113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2378113584Ssimokawa cmd & OHCI_COUNT_MASK, 2379113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2380113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2381113584Ssimokawa stat, 2382113584Ssimokawa res & OHCI_COUNT_MASK); 2383103285Sikob if(stat & 0xff00){ 2384103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2385103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2386103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2387103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2388103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2389103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2390103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2391103285Sikob fwohcicode[stat & 0x1f], 2392103285Sikob stat & 0x1f 2393103285Sikob ); 2394103285Sikob }else{ 2395103285Sikob printf(" Nostat\n"); 2396103285Sikob } 2397103285Sikob if(key == OHCI_KEY_ST2 ){ 2398103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2399113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2400113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2401113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2402113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2403103285Sikob } 2404103285Sikob if(key == OHCI_KEY_DEVICE){ 2405103285Sikob return; 2406103285Sikob } 2407113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2408103285Sikob == OHCI_BRANCH_ALWAYS){ 2409103285Sikob return; 2410103285Sikob } 2411113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2412103285Sikob == OHCI_OUTPUT_LAST){ 2413103285Sikob return; 2414103285Sikob } 2415113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2416103285Sikob == OHCI_INPUT_LAST){ 2417103285Sikob return; 2418103285Sikob } 2419103285Sikob if(key == OHCI_KEY_ST2 ){ 2420103285Sikob i++; 2421103285Sikob } 2422103285Sikob } 2423103285Sikob return; 2424103285Sikob} 2425106790Ssimokawa 2426106790Ssimokawavoid 2427106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2428103285Sikob{ 2429103285Sikob struct fwohci_softc *sc; 2430129585Sdfr uint32_t fun; 2431103285Sikob 2432110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2433103285Sikob sc = (struct fwohci_softc *)fc; 2434108276Ssimokawa 2435108276Ssimokawa /* 2436129611Sdfr * Make sure our cached values from the config rom are 2437129611Sdfr * initialised. 2438129611Sdfr */ 2439129611Sdfr OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2440129611Sdfr OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2441129611Sdfr 2442129611Sdfr /* 2443108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2444108276Ssimokawa * shouldn't became the root node. 2445108276Ssimokawa */ 2446103285Sikob#if 1 2447103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2448109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2449103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2450109280Ssimokawa#else /* Short bus reset */ 2451103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2452109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2453103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2454103285Sikob#endif 2455103285Sikob} 2456106790Ssimokawa 2457106790Ssimokawavoid 2458106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2459103285Sikob{ 2460103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2461103285Sikob struct fwohci_dbch *dbch; 2462120660Ssimokawa struct fwohcidb *db; 2463103285Sikob struct fw_pkt *fp; 2464120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 2465103285Sikob unsigned short chtag; 2466103285Sikob int idb; 2467103285Sikob 2468103285Sikob dbch = &sc->it[dmach]; 2469103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2470103285Sikob 2471103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2472103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2473103285Sikob/* 2474113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2475103285Sikob*/ 2476113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2477109892Ssimokawa db = db_tr->db; 2478103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2479120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2480113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2481119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2482113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2483103285Sikob ohcifp->mode.stream.chtag = chtag; 2484103285Sikob ohcifp->mode.stream.tcode = 0xa; 2485113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2486113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2487113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2488113584Ssimokawa#endif 2489103285Sikob 2490113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2491113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2492113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2493109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2494113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2495103285Sikob | OHCI_UPDATE 2496109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2497109892Ssimokawa db[0].db.desc.depend = 2498109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2499113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2500109892Ssimokawa#else 2501113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2502113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2503109892Ssimokawa#endif 2504103285Sikob bulkxfer->end = (caddr_t)db_tr; 2505103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2506103285Sikob } 2507109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2508113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2509113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2510109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2511109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2512109280Ssimokawa /* OHCI 1.1 and above */ 2513109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2514109892Ssimokawa#endif 2515109892Ssimokawa/* 2516103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2517103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2518113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2519103285Sikob*/ 2520103285Sikob return; 2521103285Sikob} 2522106790Ssimokawa 2523106790Ssimokawastatic int 2524113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2525113584Ssimokawa int poffset) 2526103285Sikob{ 2527120660Ssimokawa struct fwohcidb *db = db_tr->db; 2528113584Ssimokawa struct fw_xferq *it; 2529103285Sikob int err = 0; 2530113584Ssimokawa 2531113584Ssimokawa it = &dbch->xferq; 2532113584Ssimokawa if(it->buf == 0){ 2533103285Sikob err = EINVAL; 2534103285Sikob return err; 2535103285Sikob } 2536113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2537103285Sikob db_tr->dbcnt = 3; 2538103285Sikob 2539113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2540113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2541119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2542120660Ssimokawa bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2543113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2544129585Sdfr fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2545113584Ssimokawa 2546113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2547113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2548109892Ssimokawa#if 1 2549113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2550113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2551109892Ssimokawa#endif 2552113584Ssimokawa return 0; 2553103285Sikob} 2554106790Ssimokawa 2555106790Ssimokawaint 2556113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2557113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2558103285Sikob{ 2559120660Ssimokawa struct fwohcidb *db = db_tr->db; 2560113584Ssimokawa struct fw_xferq *ir; 2561113584Ssimokawa int i, ldesc; 2562113584Ssimokawa bus_addr_t dbuf[2]; 2563103285Sikob int dsiz[2]; 2564103285Sikob 2565113584Ssimokawa ir = &dbch->xferq; 2566113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2567113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2568113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2569113584Ssimokawa if (db_tr->buf == NULL) 2570113584Ssimokawa return(ENOMEM); 2571103285Sikob db_tr->dbcnt = 1; 2572113584Ssimokawa dsiz[0] = ir->psize; 2573113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2574113584Ssimokawa BUS_DMASYNC_PREREAD); 2575113584Ssimokawa } else { 2576113584Ssimokawa db_tr->dbcnt = 0; 2577113584Ssimokawa if (dummy_dma != NULL) { 2578129585Sdfr dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2579113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2580113584Ssimokawa } 2581113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2582113584Ssimokawa if (ir->buf != NULL) { 2583113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2584113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2585113584Ssimokawa } 2586113584Ssimokawa db_tr->dbcnt++; 2587103285Sikob } 2588103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2589113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2590113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2591113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2592113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2593103285Sikob } 2594113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2595103285Sikob } 2596113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2597113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2598113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2599103285Sikob } 2600113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2601113584Ssimokawa return 0; 2602103285Sikob} 2603106790Ssimokawa 2604113584Ssimokawa 2605113584Ssimokawastatic int 2606113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2607103285Sikob{ 2608113584Ssimokawa struct fw_pkt *fp0; 2609129585Sdfr uint32_t ld0; 2610120660Ssimokawa int slen, hlen; 2611113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2612113584Ssimokawa int i; 2613113584Ssimokawa#endif 2614103285Sikob 2615113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2616113584Ssimokawa#if 0 2617113584Ssimokawa printf("ld0: x%08x\n", ld0); 2618113584Ssimokawa#endif 2619113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2620120660Ssimokawa /* determine length to swap */ 2621113584Ssimokawa switch (fp0->mode.common.tcode) { 2622113584Ssimokawa case FWTCODE_RREQQ: 2623113584Ssimokawa case FWTCODE_WRES: 2624113584Ssimokawa case FWTCODE_WREQQ: 2625113584Ssimokawa case FWTCODE_RRESQ: 2626113584Ssimokawa case FWOHCITCODE_PHY: 2627113584Ssimokawa slen = 12; 2628113584Ssimokawa break; 2629113584Ssimokawa case FWTCODE_RREQB: 2630113584Ssimokawa case FWTCODE_WREQB: 2631113584Ssimokawa case FWTCODE_LREQ: 2632113584Ssimokawa case FWTCODE_RRESB: 2633113584Ssimokawa case FWTCODE_LRES: 2634113584Ssimokawa slen = 16; 2635113584Ssimokawa break; 2636113584Ssimokawa default: 2637113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2638113584Ssimokawa return(0); 2639103285Sikob } 2640120660Ssimokawa hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2641120660Ssimokawa if (hlen > len) { 2642113584Ssimokawa if (firewire_debug) 2643113584Ssimokawa printf("splitted header\n"); 2644120660Ssimokawa return(-hlen); 2645103285Sikob } 2646113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2647113584Ssimokawa for(i = 0; i < slen/4; i ++) 2648113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2649113584Ssimokawa#endif 2650120660Ssimokawa return(hlen); 2651103285Sikob} 2652103285Sikob 2653103285Sikobstatic int 2654113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2655103285Sikob{ 2656120660Ssimokawa struct tcode_info *info; 2657113584Ssimokawa int r; 2658103285Sikob 2659120660Ssimokawa info = &tinfo[fp->mode.common.tcode]; 2660129585Sdfr r = info->hdr_len + sizeof(uint32_t); 2661120660Ssimokawa if ((info->flag & FWTI_BLOCK_ASY) != 0) 2662129585Sdfr r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2663120660Ssimokawa 2664129585Sdfr if (r == sizeof(uint32_t)) 2665120660Ssimokawa /* XXX */ 2666110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2667110798Ssimokawa fp->mode.common.tcode); 2668120660Ssimokawa 2669110798Ssimokawa if (r > dbch->xferq.psize) { 2670110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2671110798Ssimokawa /* panic ? */ 2672110798Ssimokawa } 2673120660Ssimokawa 2674110798Ssimokawa return r; 2675103285Sikob} 2676103285Sikob 2677106790Ssimokawastatic void 2678113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2679113584Ssimokawa{ 2680120660Ssimokawa struct fwohcidb *db = &db_tr->db[0]; 2681113584Ssimokawa 2682113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2683113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2684113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2685113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2686113584Ssimokawa dbch->bottom = db_tr; 2687113584Ssimokawa} 2688113584Ssimokawa 2689113584Ssimokawastatic void 2690106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2691103285Sikob{ 2692103285Sikob struct fwohcidb_tr *db_tr; 2693113584Ssimokawa struct iovec vec[2]; 2694113584Ssimokawa struct fw_pkt pktbuf; 2695113584Ssimokawa int nvec; 2696103285Sikob struct fw_pkt *fp; 2697129585Sdfr uint8_t *ld; 2698129585Sdfr uint32_t stat, off, status; 2699103285Sikob u_int spd; 2700113584Ssimokawa int len, plen, hlen, pcnt, offset; 2701103285Sikob int s; 2702103285Sikob caddr_t buf; 2703103285Sikob int resCount; 2704103285Sikob 2705103285Sikob if(&sc->arrq == dbch){ 2706103285Sikob off = OHCI_ARQOFF; 2707103285Sikob }else if(&sc->arrs == dbch){ 2708103285Sikob off = OHCI_ARSOFF; 2709103285Sikob }else{ 2710103285Sikob return; 2711103285Sikob } 2712103285Sikob 2713103285Sikob s = splfw(); 2714103285Sikob db_tr = dbch->top; 2715103285Sikob pcnt = 0; 2716103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2717113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2718113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2719113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2720113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2721113584Ssimokawa#if 0 2722113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2723113584Ssimokawa#endif 2724113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2725113584Ssimokawa len = dbch->xferq.psize - resCount; 2726129585Sdfr ld = (uint8_t *)db_tr->buf; 2727113584Ssimokawa if (dbch->pdb_tr == NULL) { 2728113584Ssimokawa len -= dbch->buf_offset; 2729113584Ssimokawa ld += dbch->buf_offset; 2730113584Ssimokawa } 2731113584Ssimokawa if (len > 0) 2732113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2733113584Ssimokawa BUS_DMASYNC_POSTREAD); 2734103285Sikob while (len > 0 ) { 2735106789Ssimokawa if (count >= 0 && count-- == 0) 2736106789Ssimokawa goto out; 2737113584Ssimokawa if(dbch->pdb_tr != NULL){ 2738113584Ssimokawa /* we have a fragment in previous buffer */ 2739113584Ssimokawa int rlen; 2740103285Sikob 2741113584Ssimokawa offset = dbch->buf_offset; 2742113584Ssimokawa if (offset < 0) 2743113584Ssimokawa offset = - offset; 2744113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2745113584Ssimokawa rlen = dbch->xferq.psize - offset; 2746113584Ssimokawa if (firewire_debug) 2747113584Ssimokawa printf("rlen=%d, offset=%d\n", 2748113584Ssimokawa rlen, dbch->buf_offset); 2749113584Ssimokawa if (dbch->buf_offset < 0) { 2750113584Ssimokawa /* splitted in header, pull up */ 2751113584Ssimokawa char *p; 2752113584Ssimokawa 2753113584Ssimokawa p = (char *)&pktbuf; 2754113584Ssimokawa bcopy(buf, p, rlen); 2755113584Ssimokawa p += rlen; 2756113584Ssimokawa /* this must be too long but harmless */ 2757113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2758113584Ssimokawa if (rlen < 0) 2759113584Ssimokawa printf("why rlen < 0\n"); 2760113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2761103285Sikob ld += rlen; 2762103285Sikob len -= rlen; 2763113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2764113584Ssimokawa if (hlen < 0) { 2765113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2766113584Ssimokawa } 2767113584Ssimokawa offset = sizeof(pktbuf); 2768113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2769113584Ssimokawa vec[0].iov_len = offset; 2770113584Ssimokawa } else { 2771113584Ssimokawa /* splitted in payload */ 2772113584Ssimokawa offset = rlen; 2773113584Ssimokawa vec[0].iov_base = buf; 2774113584Ssimokawa vec[0].iov_len = rlen; 2775103285Sikob } 2776113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2777113584Ssimokawa nvec = 1; 2778113584Ssimokawa } else { 2779113584Ssimokawa /* no fragment in previous buffer */ 2780103285Sikob fp=(struct fw_pkt *)ld; 2781113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2782113584Ssimokawa if (hlen == 0) 2783113584Ssimokawa /* XXX need reset */ 2784103285Sikob goto out; 2785113584Ssimokawa if (hlen < 0) { 2786113584Ssimokawa dbch->pdb_tr = db_tr; 2787113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2788113584Ssimokawa /* sanity check */ 2789113584Ssimokawa if (resCount != 0) 2790124145Ssimokawa printf("resCount = %d !?\n", 2791124145Ssimokawa resCount); 2792124145Ssimokawa /* XXX clear pdb_tr */ 2793113584Ssimokawa goto out; 2794103285Sikob } 2795113584Ssimokawa offset = 0; 2796113584Ssimokawa nvec = 0; 2797113584Ssimokawa } 2798113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2799113584Ssimokawa if (plen < 0) { 2800113584Ssimokawa /* minimum header size + trailer 2801113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2802120660Ssimokawa printf("plen(%d) is negative! offset=%d\n", 2803120660Ssimokawa plen, offset); 2804124145Ssimokawa /* XXX clear pdb_tr */ 2805113584Ssimokawa goto out; 2806113584Ssimokawa } 2807113584Ssimokawa if (plen > 0) { 2808113584Ssimokawa len -= plen; 2809113584Ssimokawa if (len < 0) { 2810113584Ssimokawa dbch->pdb_tr = db_tr; 2811113584Ssimokawa if (firewire_debug) 2812113584Ssimokawa printf("splitted payload\n"); 2813113584Ssimokawa /* sanity check */ 2814113584Ssimokawa if (resCount != 0) 2815124145Ssimokawa printf("resCount = %d !?\n", 2816124145Ssimokawa resCount); 2817124145Ssimokawa /* XXX clear pdb_tr */ 2818113584Ssimokawa goto out; 2819103285Sikob } 2820113584Ssimokawa vec[nvec].iov_base = ld; 2821113584Ssimokawa vec[nvec].iov_len = plen; 2822113584Ssimokawa nvec ++; 2823103285Sikob ld += plen; 2824103285Sikob } 2825129585Sdfr dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2826113584Ssimokawa if (nvec == 0) 2827113584Ssimokawa printf("nvec == 0\n"); 2828113584Ssimokawa 2829103285Sikob/* DMA result-code will be written at the tail of packet */ 2830113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2831113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2832113584Ssimokawa#else 2833113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2834113584Ssimokawa#endif 2835110577Ssimokawa#if 0 2836120660Ssimokawa printf("plen: %d, stat %x\n", 2837120660Ssimokawa plen ,stat); 2838103285Sikob#endif 2839113584Ssimokawa spd = (stat >> 5) & 0x3; 2840113584Ssimokawa stat &= 0x1f; 2841113584Ssimokawa switch(stat){ 2842113584Ssimokawa case FWOHCIEV_ACKPEND: 2843113584Ssimokawa#if 0 2844113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2845113584Ssimokawa#endif 2846113584Ssimokawa /* fall through */ 2847113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2848120660Ssimokawa { 2849120660Ssimokawa struct fw_rcv_buf rb; 2850120660Ssimokawa 2851113584Ssimokawa if ((vec[nvec-1].iov_len -= 2852113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2853113584Ssimokawa nvec--; 2854120660Ssimokawa rb.fc = &sc->fc; 2855120660Ssimokawa rb.vec = vec; 2856120660Ssimokawa rb.nvec = nvec; 2857120660Ssimokawa rb.spd = spd; 2858120660Ssimokawa fw_rcv(&rb); 2859120660Ssimokawa break; 2860120660Ssimokawa } 2861113584Ssimokawa case FWOHCIEV_BUSRST: 2862113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2863113584Ssimokawa printf("got BUSRST packet!?\n"); 2864113584Ssimokawa break; 2865113584Ssimokawa default: 2866113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2867103285Sikob#if 0 /* XXX */ 2868113584Ssimokawa goto out; 2869103285Sikob#endif 2870113584Ssimokawa break; 2871103285Sikob } 2872103285Sikob pcnt ++; 2873113584Ssimokawa if (dbch->pdb_tr != NULL) { 2874113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2875113584Ssimokawa dbch->pdb_tr = NULL; 2876113584Ssimokawa } 2877113584Ssimokawa 2878113584Ssimokawa } 2879103285Sikobout: 2880103285Sikob if (resCount == 0) { 2881103285Sikob /* done on this buffer */ 2882113584Ssimokawa if (dbch->pdb_tr == NULL) { 2883113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2884113584Ssimokawa dbch->buf_offset = 0; 2885113584Ssimokawa } else 2886113584Ssimokawa if (dbch->pdb_tr != db_tr) 2887113584Ssimokawa printf("pdb_tr != db_tr\n"); 2888103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2889113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2890113584Ssimokawa >> OHCI_STATUS_SHIFT; 2891113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2892113584Ssimokawa & OHCI_COUNT_MASK; 2893113584Ssimokawa /* XXX check buffer overrun */ 2894103285Sikob dbch->top = db_tr; 2895103285Sikob } else { 2896103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2897103285Sikob break; 2898103285Sikob } 2899103285Sikob /* XXX make sure DMA is not dead */ 2900103285Sikob } 2901103285Sikob#if 0 2902103285Sikob if (pcnt < 1) 2903103285Sikob printf("fwohci_arcv: no packets\n"); 2904103285Sikob#endif 2905103285Sikob splx(s); 2906103285Sikob} 2907