fwohci.c revision 120660
1103285Sikob/* 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 120660 2003-10-02 04:06:56Z simokawa $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50103285Sikob#include <sys/bus.h> 51103285Sikob#include <sys/kernel.h> 52103285Sikob#include <sys/conf.h> 53113584Ssimokawa#include <sys/endian.h> 54103285Sikob 55103285Sikob#include <machine/bus.h> 56103285Sikob 57117067Ssimokawa#if __FreeBSD_version < 500000 58117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 59117067Ssimokawa#endif 60117067Ssimokawa 61103285Sikob#include <dev/firewire/firewire.h> 62103285Sikob#include <dev/firewire/firewirereg.h> 63113584Ssimokawa#include <dev/firewire/fwdma.h> 64103285Sikob#include <dev/firewire/fwohcireg.h> 65103285Sikob#include <dev/firewire/fwohcivar.h> 66103285Sikob#include <dev/firewire/firewire_phy.h> 67103285Sikob 68103285Sikob#undef OHCI_DEBUG 69106802Ssimokawa 70103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71103285Sikob "STOR","LOAD","NOP ","STOP",}; 72113584Ssimokawa 73103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74103285Sikob "UNDEF","REG","SYS","DEV"}; 75113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76103285Sikobchar fwohcicode[32][0x20]={ 77103285Sikob "No stat","Undef","long","miss Ack err", 78103285Sikob "underrun","overrun","desc err", "data read err", 79103285Sikob "data write err","bus reset","timeout","tcode err", 80103285Sikob "Undef","Undef","unknown event","flushed", 81103285Sikob "Undef","ack complete","ack pend","Undef", 82103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 83103285Sikob "Undef","Undef","Undef","ack tardy", 84103285Sikob "Undef","ack data_err","ack type_err",""}; 85113584Ssimokawa 86116376Ssimokawa#define MAX_SPEED 3 87116376Ssimokawaextern char linkspeed[][0x10]; 88103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89103285Sikob 90103285Sikobstatic struct tcode_info tinfo[] = { 91103285Sikob/* hdr_len block flag*/ 92103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94103285Sikob/* 2 WRES */ {12, FWTI_RES}, 95103285Sikob/* 3 XXX */ { 0, 0}, 96103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 99103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100103285Sikob/* 8 CYCS */ { 0, 0}, 101103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104103285Sikob/* c XXX */ { 0, 0}, 105103285Sikob/* d XXX */ { 0, 0}, 106103285Sikob/* e PHY */ {12, FWTI_REQ}, 107103285Sikob/* f XXX */ { 0, 0} 108103285Sikob}; 109103285Sikob 110103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 111103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 112103285Sikob 113103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115103285Sikob 116103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 117113584Ssimokawastatic void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 119106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 122103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 123103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 129103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 130113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 131103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132113584Ssimokawa#endif 133103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 135103285Sikobstatic void fwohci_timeout __P((void *)); 136103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 137113584Ssimokawa 138113584Ssimokawastatic int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139113584Ssimokawastatic int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 141120660Ssimokawastatic void print_db __P((struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t)); 142103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147113584Ssimokawa#if FWOHCI_TASKQUEUE 148113584Ssimokawastatic void fwohci_complete(void *, int); 149113584Ssimokawa#endif 150103285Sikob 151103285Sikob/* 152103285Sikob * memory allocated for DMA programs 153103285Sikob */ 154103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155103285Sikob 156103285Sikob#define NDB FWMAXQUEUE 157103285Sikob 158103285Sikob#define OHCI_VERSION 0x00 159112523Ssimokawa#define OHCI_ATRETRY 0x08 160103285Sikob#define OHCI_CROMHDR 0x18 161103285Sikob#define OHCI_BUS_OPT 0x20 162103285Sikob#define OHCI_BUSIRMC (1 << 31) 163103285Sikob#define OHCI_BUSCMC (1 << 30) 164103285Sikob#define OHCI_BUSISC (1 << 29) 165103285Sikob#define OHCI_BUSBMC (1 << 28) 166103285Sikob#define OHCI_BUSPMC (1 << 27) 167103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 168103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 169103285Sikob 170103285Sikob#define OHCI_EUID_HI 0x24 171103285Sikob#define OHCI_EUID_LO 0x28 172103285Sikob 173103285Sikob#define OHCI_CROMPTR 0x34 174103285Sikob#define OHCI_HCCCTL 0x50 175103285Sikob#define OHCI_HCCCTLCLR 0x54 176103285Sikob#define OHCI_AREQHI 0x100 177103285Sikob#define OHCI_AREQHICLR 0x104 178103285Sikob#define OHCI_AREQLO 0x108 179103285Sikob#define OHCI_AREQLOCLR 0x10c 180103285Sikob#define OHCI_PREQHI 0x110 181103285Sikob#define OHCI_PREQHICLR 0x114 182103285Sikob#define OHCI_PREQLO 0x118 183103285Sikob#define OHCI_PREQLOCLR 0x11c 184103285Sikob#define OHCI_PREQUPPER 0x120 185103285Sikob 186103285Sikob#define OHCI_SID_BUF 0x64 187103285Sikob#define OHCI_SID_CNT 0x68 188113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 189103285Sikob#define OHCI_SID_CNT_MASK 0xffc 190103285Sikob 191103285Sikob#define OHCI_IT_STAT 0x90 192103285Sikob#define OHCI_IT_STATCLR 0x94 193103285Sikob#define OHCI_IT_MASK 0x98 194103285Sikob#define OHCI_IT_MASKCLR 0x9c 195103285Sikob 196103285Sikob#define OHCI_IR_STAT 0xa0 197103285Sikob#define OHCI_IR_STATCLR 0xa4 198103285Sikob#define OHCI_IR_MASK 0xa8 199103285Sikob#define OHCI_IR_MASKCLR 0xac 200103285Sikob 201103285Sikob#define OHCI_LNKCTL 0xe0 202103285Sikob#define OHCI_LNKCTLCLR 0xe4 203103285Sikob 204103285Sikob#define OHCI_PHYACCESS 0xec 205103285Sikob#define OHCI_CYCLETIMER 0xf0 206103285Sikob 207103285Sikob#define OHCI_DMACTL(off) (off) 208103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 209103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 210103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 211103285Sikob 212103285Sikob#define OHCI_ATQOFF 0x180 213103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 214103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 215103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 216103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 217103285Sikob 218103285Sikob#define OHCI_ATSOFF 0x1a0 219103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 220103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 221103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 222103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 223103285Sikob 224103285Sikob#define OHCI_ARQOFF 0x1c0 225103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 226103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 227103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 228103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 229103285Sikob 230103285Sikob#define OHCI_ARSOFF 0x1e0 231103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 232103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 233103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 234103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 235103285Sikob 236103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 237103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 238103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 239103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 240103285Sikob 241103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 242103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 243103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 244103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 245103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 246103285Sikob 247103285Sikobd_ioctl_t fwohci_ioctl; 248103285Sikob 249103285Sikob/* 250103285Sikob * Communication with PHY device 251103285Sikob */ 252106790Ssimokawastatic u_int32_t 253106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 254103285Sikob{ 255103285Sikob u_int32_t fun; 256103285Sikob 257103285Sikob addr &= 0xf; 258103285Sikob data &= 0xff; 259103285Sikob 260103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 261103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 262103285Sikob DELAY(100); 263103285Sikob 264103285Sikob return(fwphy_rddata( sc, addr)); 265103285Sikob} 266103285Sikob 267103285Sikobstatic u_int32_t 268103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 269103285Sikob{ 270103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 271103285Sikob int i; 272103285Sikob u_int32_t bm; 273103285Sikob 274103285Sikob#define OHCI_CSR_DATA 0x0c 275103285Sikob#define OHCI_CSR_COMP 0x10 276103285Sikob#define OHCI_CSR_CONT 0x14 277103285Sikob#define OHCI_BUS_MANAGER_ID 0 278103285Sikob 279103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 280103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 281103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 282103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 283109280Ssimokawa DELAY(10); 284103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 285107653Ssimokawa if((bm & 0x3f) == 0x3f) 286103285Sikob bm = node; 287107653Ssimokawa if (bootverbose) 288107653Ssimokawa device_printf(sc->fc.dev, 289107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 290103285Sikob 291103285Sikob return(bm); 292103285Sikob} 293103285Sikob 294106790Ssimokawastatic u_int32_t 295106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 296103285Sikob{ 297108500Ssimokawa u_int32_t fun, stat; 298108500Ssimokawa u_int i, retry = 0; 299103285Sikob 300103285Sikob addr &= 0xf; 301108500Ssimokawa#define MAX_RETRY 100 302108500Ssimokawaagain: 303108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 304103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 305103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 306108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 307103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 308103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 309103285Sikob break; 310109280Ssimokawa DELAY(100); 311103285Sikob } 312108500Ssimokawa if(i >= MAX_RETRY) { 313109280Ssimokawa if (bootverbose) 314109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 315108527Ssimokawa if (++retry < MAX_RETRY) { 316109280Ssimokawa DELAY(100); 317108527Ssimokawa goto again; 318108527Ssimokawa } 319108500Ssimokawa } 320108500Ssimokawa /* Make sure that SCLK is started */ 321108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 322108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 323108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 324109280Ssimokawa if (bootverbose) 325109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 326108500Ssimokawa if (++retry < MAX_RETRY) { 327109280Ssimokawa DELAY(100); 328108500Ssimokawa goto again; 329108500Ssimokawa } 330108500Ssimokawa } 331108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 332108500Ssimokawa device_printf(sc->fc.dev, 333119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 334108500Ssimokawa#undef MAX_RETRY 335103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 336103285Sikob} 337103285Sikob/* Device specific ioctl. */ 338103285Sikobint 339103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 340103285Sikob{ 341103285Sikob struct firewire_softc *sc; 342103285Sikob struct fwohci_softc *fc; 343103285Sikob int unit = DEV2UNIT(dev); 344103285Sikob int err = 0; 345103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 346103285Sikob u_int32_t *dmach = (u_int32_t *) data; 347103285Sikob 348103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 349103285Sikob if(sc == NULL){ 350103285Sikob return(EINVAL); 351103285Sikob } 352103285Sikob fc = (struct fwohci_softc *)sc->fc; 353103285Sikob 354103285Sikob if (!data) 355103285Sikob return(EINVAL); 356103285Sikob 357103285Sikob switch (cmd) { 358103285Sikob case FWOHCI_WRREG: 359103285Sikob#define OHCI_MAX_REG 0x800 360103285Sikob if(reg->addr <= OHCI_MAX_REG){ 361103285Sikob OWRITE(fc, reg->addr, reg->data); 362103285Sikob reg->data = OREAD(fc, reg->addr); 363103285Sikob }else{ 364103285Sikob err = EINVAL; 365103285Sikob } 366103285Sikob break; 367103285Sikob case FWOHCI_RDREG: 368103285Sikob if(reg->addr <= OHCI_MAX_REG){ 369103285Sikob reg->data = OREAD(fc, reg->addr); 370103285Sikob }else{ 371103285Sikob err = EINVAL; 372103285Sikob } 373103285Sikob break; 374103285Sikob/* Read DMA descriptors for debug */ 375103285Sikob case DUMPDMA: 376103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 377103285Sikob dump_dma(fc, *dmach); 378103285Sikob dump_db(fc, *dmach); 379103285Sikob }else{ 380103285Sikob err = EINVAL; 381103285Sikob } 382103285Sikob break; 383119118Ssimokawa/* Read/Write Phy registers */ 384119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 385119118Ssimokawa case FWOHCI_RDPHYREG: 386119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 387119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 388119118Ssimokawa else 389119118Ssimokawa err = EINVAL; 390119118Ssimokawa break; 391119118Ssimokawa case FWOHCI_WRPHYREG: 392119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 393119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 394119118Ssimokawa else 395119118Ssimokawa err = EINVAL; 396119118Ssimokawa break; 397103285Sikob default: 398119118Ssimokawa err = EINVAL; 399103285Sikob break; 400103285Sikob } 401103285Sikob return err; 402103285Sikob} 403106790Ssimokawa 404108530Ssimokawastatic int 405108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406103285Sikob{ 407108530Ssimokawa u_int32_t reg, reg2; 408108530Ssimokawa int e1394a = 1; 409108530Ssimokawa/* 410108530Ssimokawa * probe PHY parameters 411108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 412108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 413108530Ssimokawa * number of port supported by core-logic. 414108530Ssimokawa * It is not actually available port on your PC . 415108530Ssimokawa */ 416108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa device_printf(dev, 429108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 430108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 431108530Ssimokawa }else{ 432108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433108530Ssimokawa sc->fc.mode |= FWPHYASYST; 434108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 435108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 437108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 438108530Ssimokawa sc->fc.speed, MAX_SPEED); 439108530Ssimokawa sc->fc.speed = MAX_SPEED; 440108530Ssimokawa } 441108530Ssimokawa device_printf(dev, 442108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 443108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 444108530Ssimokawa 445108530Ssimokawa /* check programPhyEnable */ 446108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 447108530Ssimokawa#if 0 448108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449108530Ssimokawa#else /* XXX force to enable 1394a */ 450108530Ssimokawa if (e1394a) { 451108530Ssimokawa#endif 452108530Ssimokawa if (bootverbose) 453108530Ssimokawa device_printf(dev, 454108530Ssimokawa "Enable 1394a Enhancements\n"); 455108530Ssimokawa /* enable EAA EMC */ 456108530Ssimokawa reg2 |= 0x03; 457108530Ssimokawa /* set aPhyEnhanceEnable */ 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460108530Ssimokawa } else { 461108530Ssimokawa /* for safe */ 462108530Ssimokawa reg2 &= ~0x83; 463108530Ssimokawa } 464108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 465108530Ssimokawa } 466108530Ssimokawa 467108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468108530Ssimokawa if((reg >> 5) == 7 ){ 469108530Ssimokawa reg = fwphy_rddata(sc, 4); 470108530Ssimokawa reg |= 1 << 6; 471108530Ssimokawa fwphy_wrdata(sc, 4, reg); 472108530Ssimokawa reg = fwphy_rddata(sc, 4); 473108530Ssimokawa } 474108530Ssimokawa return 0; 475108530Ssimokawa} 476108530Ssimokawa 477108530Ssimokawa 478108530Ssimokawavoid 479108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 480108530Ssimokawa{ 481108701Ssimokawa int i, max_rec, speed; 482103285Sikob u_int32_t reg, reg2; 483103285Sikob struct fwohcidb_tr *db_tr; 484103285Sikob 485108701Ssimokawa /* Disable interrupt */ 486108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487108530Ssimokawa 488108701Ssimokawa /* Now stopping all DMA channel */ 489108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa 494108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa } 499108530Ssimokawa 500108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 501108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502108530Ssimokawa if (bootverbose) 503108530Ssimokawa device_printf(dev, "resetting OHCI..."); 504108530Ssimokawa i = 0; 505108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506108530Ssimokawa if (i++ > 100) break; 507108530Ssimokawa DELAY(1000); 508108530Ssimokawa } 509108530Ssimokawa if (bootverbose) 510108530Ssimokawa printf("done (loop=%d)\n", i); 511108530Ssimokawa 512108701Ssimokawa /* Probe phy */ 513108701Ssimokawa fwohci_probe_phy(sc, dev); 514108701Ssimokawa 515108701Ssimokawa /* Probe link */ 516108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 517108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 518108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 519108701Ssimokawa speed = (reg & 0x00000007); 520108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 521108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 522108701Ssimokawa /* XXX fix max_rec */ 523108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 524108701Ssimokawa if (max_rec != sc->fc.maxrec) { 525108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 527108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528108701Ssimokawa } 529108530Ssimokawa if (bootverbose) 530108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 532108530Ssimokawa 533108701Ssimokawa /* Initialize registers */ 534108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540108701Ssimokawa fw_busreset(&sc->fc); 541108530Ssimokawa 542108701Ssimokawa /* Enable link */ 543108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544108642Ssimokawa 545108701Ssimokawa /* Force to start async RX DMA */ 546108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 550108530Ssimokawa 551108701Ssimokawa /* Initialize async TX */ 552108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554116978Ssimokawa 555108701Ssimokawa /* AT Retries */ 556108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 557108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559116978Ssimokawa 560116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 563116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 564116978Ssimokawa 565108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567108530Ssimokawa db_tr->xfer = NULL; 568108530Ssimokawa } 569108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571108530Ssimokawa db_tr->xfer = NULL; 572108530Ssimokawa } 573108530Ssimokawa 574108701Ssimokawa 575108701Ssimokawa /* Enable interrupt */ 576108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 577108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 578108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 582108530Ssimokawa 583108530Ssimokawa} 584108530Ssimokawa 585108530Ssimokawaint 586108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 587108530Ssimokawa{ 588108530Ssimokawa int i; 589108530Ssimokawa u_int32_t reg; 590109814Ssimokawa u_int8_t ui[8]; 591108530Ssimokawa 592113584Ssimokawa#if FWOHCI_TASKQUEUE 593113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594113584Ssimokawa#endif 595113584Ssimokawa 596103285Sikob reg = OREAD(sc, OHCI_VERSION); 597103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 598103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 599103285Sikob 600118416Ssimokawa if (((reg>>16) & 0xff) < 1) { 601118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 602118416Ssimokawa return (ENXIO); 603118416Ssimokawa } 604118416Ssimokawa 605110045Ssimokawa/* Available Isochrounous DMA channel probe */ 606110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 607110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 608110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 609110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 610110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 611110045Ssimokawa for (i = 0; i < 0x20; i++) 612110045Ssimokawa if ((reg & (1 << i)) == 0) 613110045Ssimokawa break; 614103285Sikob sc->fc.nisodma = i; 615103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 616118820Ssimokawa if (i == 0) 617118820Ssimokawa return (ENXIO); 618103285Sikob 619103285Sikob sc->fc.arq = &sc->arrq.xferq; 620103285Sikob sc->fc.ars = &sc->arrs.xferq; 621103285Sikob sc->fc.atq = &sc->atrq.xferq; 622103285Sikob sc->fc.ats = &sc->atrs.xferq; 623103285Sikob 624113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 625113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 626113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628113584Ssimokawa 629103285Sikob sc->arrq.xferq.start = NULL; 630103285Sikob sc->arrs.xferq.start = NULL; 631103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 632103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 633103285Sikob 634113584Ssimokawa sc->arrq.xferq.buf = NULL; 635113584Ssimokawa sc->arrs.xferq.buf = NULL; 636113584Ssimokawa sc->atrq.xferq.buf = NULL; 637113584Ssimokawa sc->atrs.xferq.buf = NULL; 638103285Sikob 639118293Ssimokawa sc->arrq.xferq.dmach = -1; 640118293Ssimokawa sc->arrs.xferq.dmach = -1; 641118293Ssimokawa sc->atrq.xferq.dmach = -1; 642118293Ssimokawa sc->atrs.xferq.dmach = -1; 643118293Ssimokawa 644103285Sikob sc->arrq.ndesc = 1; 645103285Sikob sc->arrs.ndesc = 1; 646110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 647110593Ssimokawa sc->atrs.ndesc = 2; 648103285Sikob 649103285Sikob sc->arrq.ndb = NDB; 650103285Sikob sc->arrs.ndb = NDB / 2; 651103285Sikob sc->atrq.ndb = NDB; 652103285Sikob sc->atrs.ndb = NDB / 2; 653103285Sikob 654103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 655103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 656103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 657118293Ssimokawa sc->it[i].xferq.dmach = i; 658118293Ssimokawa sc->ir[i].xferq.dmach = i; 659103285Sikob sc->it[i].ndb = 0; 660103285Sikob sc->ir[i].ndb = 0; 661103285Sikob } 662103285Sikob 663103285Sikob sc->fc.tcode = tinfo; 664113584Ssimokawa sc->fc.dev = dev; 665103285Sikob 666113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 667113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 668113584Ssimokawa if(sc->fc.config_rom == NULL){ 669113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 670103285Sikob return ENOMEM; 671103285Sikob } 672103285Sikob 673116376Ssimokawa#if 0 674116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 675103285Sikob sc->fc.config_rom[1] = 0x31333934; 676103285Sikob sc->fc.config_rom[2] = 0xf000a002; 677103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 678103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 679103285Sikob sc->fc.config_rom[5] = 0; 680103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 681103285Sikob 682103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 683113584Ssimokawa#endif 684103285Sikob 685103285Sikob 686103285Sikob/* SID recieve buffer must allign 2^11 */ 687103285Sikob#define OHCI_SIDSIZE (1 << 11) 688113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 689113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 690113584Ssimokawa if (sc->sid_buf == NULL) { 691113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 692108527Ssimokawa return ENOMEM; 693108527Ssimokawa } 694113584Ssimokawa 695113584Ssimokawa fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 696113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 697113584Ssimokawa 698113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 699113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 700109736Ssimokawa return ENOMEM; 701109736Ssimokawa } 702113584Ssimokawa 703113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 704108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 705108527Ssimokawa return ENOMEM; 706108527Ssimokawa 707113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 708108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 709108527Ssimokawa return ENOMEM; 710103285Sikob 711113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 712108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 713108527Ssimokawa return ENOMEM; 714108527Ssimokawa 715113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 716108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 717108527Ssimokawa return ENOMEM; 718103285Sikob 719109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 720109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 721109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 722109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 723103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 724109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 725109814Ssimokawa 726103285Sikob sc->fc.ioctl = fwohci_ioctl; 727103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 728103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 729103285Sikob sc->fc.ibr = fwohci_ibr; 730103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 731103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 732103285Sikob 733103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 734103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 735113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 736103285Sikob sc->fc.irx_post = fwohci_irx_post; 737113584Ssimokawa#else 738113584Ssimokawa sc->fc.irx_post = NULL; 739113584Ssimokawa#endif 740103285Sikob sc->fc.itx_post = NULL; 741103285Sikob sc->fc.timeout = fwohci_timeout; 742103285Sikob sc->fc.poll = fwohci_poll; 743103285Sikob sc->fc.set_intr = fwohci_set_intr; 744106790Ssimokawa 745113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 746113584Ssimokawa 747108530Ssimokawa fw_init(&sc->fc); 748108530Ssimokawa fwohci_reset(sc, dev); 749103285Sikob 750108530Ssimokawa return 0; 751103285Sikob} 752106790Ssimokawa 753106790Ssimokawavoid 754106790Ssimokawafwohci_timeout(void *arg) 755103285Sikob{ 756103285Sikob struct fwohci_softc *sc; 757103285Sikob 758103285Sikob sc = (struct fwohci_softc *)arg; 759103285Sikob} 760106790Ssimokawa 761106790Ssimokawau_int32_t 762106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 763103285Sikob{ 764103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 765103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 766103285Sikob} 767103285Sikob 768108527Ssimokawaint 769108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 770108527Ssimokawa{ 771108527Ssimokawa int i; 772108527Ssimokawa 773113584Ssimokawa if (sc->sid_buf != NULL) 774113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 775113584Ssimokawa if (sc->fc.config_rom != NULL) 776113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 777108527Ssimokawa 778108527Ssimokawa fwohci_db_free(&sc->arrq); 779108527Ssimokawa fwohci_db_free(&sc->arrs); 780108527Ssimokawa 781108527Ssimokawa fwohci_db_free(&sc->atrq); 782108527Ssimokawa fwohci_db_free(&sc->atrs); 783108527Ssimokawa 784108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 785108527Ssimokawa fwohci_db_free(&sc->it[i]); 786108527Ssimokawa fwohci_db_free(&sc->ir[i]); 787108527Ssimokawa } 788108527Ssimokawa 789108527Ssimokawa return 0; 790108527Ssimokawa} 791108527Ssimokawa 792108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 793108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 794108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 795108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 796108655Ssimokawa} while (0) 797108655Ssimokawa 798106790Ssimokawastatic void 799113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 800113584Ssimokawa{ 801113584Ssimokawa struct fwohcidb_tr *db_tr; 802120660Ssimokawa struct fwohcidb *db; 803113584Ssimokawa bus_dma_segment_t *s; 804113584Ssimokawa int i; 805113584Ssimokawa 806113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 807113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 808113584Ssimokawa if (error) { 809113584Ssimokawa if (firewire_debug || error != EFBIG) 810113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 811113584Ssimokawa return; 812113584Ssimokawa } 813113584Ssimokawa for (i = 0; i < nseg; i++) { 814113584Ssimokawa s = &segs[i]; 815113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 816113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 817113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 818113584Ssimokawa db++; 819113584Ssimokawa db_tr->dbcnt++; 820113584Ssimokawa } 821113584Ssimokawa} 822113584Ssimokawa 823113584Ssimokawastatic void 824113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 825113584Ssimokawa bus_size_t size, int error) 826113584Ssimokawa{ 827113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 828113584Ssimokawa} 829113584Ssimokawa 830113584Ssimokawastatic void 831106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 832103285Sikob{ 833103285Sikob int i, s; 834120660Ssimokawa int tcode, hdr_len, pl_off; 835103285Sikob int fsegment = -1; 836103285Sikob u_int32_t off; 837103285Sikob struct fw_xfer *xfer; 838103285Sikob struct fw_pkt *fp; 839120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 840103285Sikob struct fwohcidb_tr *db_tr; 841120660Ssimokawa struct fwohcidb *db; 842120660Ssimokawa u_int32_t *ld; 843103285Sikob struct tcode_info *info; 844108655Ssimokawa static int maxdesc=0; 845103285Sikob 846103285Sikob if(&sc->atrq == dbch){ 847103285Sikob off = OHCI_ATQOFF; 848103285Sikob }else if(&sc->atrs == dbch){ 849103285Sikob off = OHCI_ATSOFF; 850103285Sikob }else{ 851103285Sikob return; 852103285Sikob } 853103285Sikob 854103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 855103285Sikob return; 856103285Sikob 857103285Sikob s = splfw(); 858103285Sikob db_tr = dbch->top; 859103285Sikobtxloop: 860103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 861103285Sikob if(xfer == NULL){ 862103285Sikob goto kick; 863103285Sikob } 864103285Sikob if(dbch->xferq.queued == 0 ){ 865103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 866103285Sikob } 867103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 868103285Sikob db_tr->xfer = xfer; 869103285Sikob xfer->state = FWXF_START; 870103285Sikob 871120660Ssimokawa fp = &xfer->send.hdr; 872103285Sikob tcode = fp->mode.common.tcode; 873103285Sikob 874120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 875103285Sikob info = &tinfo[tcode]; 876113584Ssimokawa hdr_len = pl_off = info->hdr_len; 877119155Ssimokawa 878119155Ssimokawa ld = &ohcifp->mode.ld[0]; 879119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 880119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 881119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 882119155Ssimokawa 883120660Ssimokawa ohcifp->mode.common.spd = xfer->send.spd & 0x7; 884103285Sikob if (tcode == FWTCODE_STREAM ){ 885103285Sikob hdr_len = 8; 886113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 887103285Sikob } else if (tcode == FWTCODE_PHY) { 888103285Sikob hdr_len = 12; 889119155Ssimokawa ld[1] = fp->mode.ld[1]; 890119155Ssimokawa ld[2] = fp->mode.ld[2]; 891103285Sikob ohcifp->mode.common.spd = 0; 892103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 893103285Sikob } else { 894113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 895103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 896103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 897103285Sikob } 898103285Sikob db = &db_tr->db[0]; 899113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 900113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 901119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 902113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 903103285Sikob/* Specify bound timer of asy. responce */ 904103285Sikob if(&sc->atrs == dbch){ 905113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 906113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 907103285Sikob } 908113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 909113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 910113584Ssimokawa hdr_len = 12; 911113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 912119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 913113584Ssimokawa#endif 914103285Sikob 915111942Ssimokawaagain: 916103285Sikob db_tr->dbcnt = 2; 917103285Sikob db = &db_tr->db[db_tr->dbcnt]; 918120660Ssimokawa if (xfer->send.pay_len > 0) { 919113584Ssimokawa int err; 920113584Ssimokawa /* handle payload */ 921103285Sikob if (xfer->mbuf == NULL) { 922113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 923120660Ssimokawa &xfer->send.payload[0], xfer->send.pay_len, 924113584Ssimokawa fwohci_execute_db, db_tr, 925113584Ssimokawa /*flags*/0); 926103285Sikob } else { 927111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 928113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 929113584Ssimokawa xfer->mbuf, 930113584Ssimokawa fwohci_execute_db2, db_tr, 931113584Ssimokawa /* flags */0); 932113584Ssimokawa if (err == EFBIG) { 933113584Ssimokawa struct mbuf *m0; 934113584Ssimokawa 935113584Ssimokawa if (firewire_debug) 936113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 937113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 938113584Ssimokawa if (m0 != NULL) { 939111942Ssimokawa m_copydata(xfer->mbuf, 0, 940111942Ssimokawa xfer->mbuf->m_pkthdr.len, 941113584Ssimokawa mtod(m0, caddr_t)); 942113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 943111942Ssimokawa xfer->mbuf->m_pkthdr.len; 944111942Ssimokawa m_freem(xfer->mbuf); 945113584Ssimokawa xfer->mbuf = m0; 946111942Ssimokawa goto again; 947111942Ssimokawa } 948111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 949111942Ssimokawa } 950103285Sikob } 951113584Ssimokawa if (err) 952113584Ssimokawa printf("dmamap_load: err=%d\n", err); 953113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 954113584Ssimokawa BUS_DMASYNC_PREWRITE); 955113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 956113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 957113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 958113584Ssimokawa OHCI_OUTPUT_MORE); 959113584Ssimokawa#endif 960103285Sikob } 961108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 962108655Ssimokawa maxdesc = db_tr->dbcnt; 963108655Ssimokawa if (bootverbose) 964108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 965108655Ssimokawa } 966103285Sikob /* last db */ 967103285Sikob LAST_DB(db_tr, db); 968113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 969113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 970113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 971113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 972103285Sikob 973103285Sikob if(fsegment == -1 ) 974103285Sikob fsegment = db_tr->dbcnt; 975103285Sikob if (dbch->pdb_tr != NULL) { 976103285Sikob LAST_DB(dbch->pdb_tr, db); 977113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 978103285Sikob } 979103285Sikob dbch->pdb_tr = db_tr; 980103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 981103285Sikob if(db_tr != dbch->bottom){ 982103285Sikob goto txloop; 983103285Sikob } else { 984107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 985103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 986103285Sikob } 987103285Sikobkick: 988103285Sikob /* kick asy q */ 989113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 990113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 991103285Sikob 992103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 993103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 994103285Sikob } else { 995107653Ssimokawa if (bootverbose) 996107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 997103285Sikob OREAD(sc, OHCI_DMACTL(off))); 998113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 999103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1000103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1001103285Sikob } 1002106790Ssimokawa 1003103285Sikob dbch->top = db_tr; 1004103285Sikob splx(s); 1005103285Sikob return; 1006103285Sikob} 1007106790Ssimokawa 1008106790Ssimokawastatic void 1009106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1010103285Sikob{ 1011103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1012103285Sikob fwohci_start( sc, &(sc->atrq)); 1013103285Sikob return; 1014103285Sikob} 1015106790Ssimokawa 1016106790Ssimokawastatic void 1017106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1018103285Sikob{ 1019103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1020103285Sikob fwohci_start( sc, &(sc->atrs)); 1021103285Sikob return; 1022103285Sikob} 1023106790Ssimokawa 1024106790Ssimokawavoid 1025106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1026103285Sikob{ 1027113584Ssimokawa int s, ch, err = 0; 1028103285Sikob struct fwohcidb_tr *tr; 1029120660Ssimokawa struct fwohcidb *db; 1030103285Sikob struct fw_xfer *xfer; 1031103285Sikob u_int32_t off; 1032113584Ssimokawa u_int stat, status; 1033103285Sikob int packets; 1034103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1035113584Ssimokawa 1036103285Sikob if(&sc->atrq == dbch){ 1037103285Sikob off = OHCI_ATQOFF; 1038113584Ssimokawa ch = ATRQ_CH; 1039103285Sikob }else if(&sc->atrs == dbch){ 1040103285Sikob off = OHCI_ATSOFF; 1041113584Ssimokawa ch = ATRS_CH; 1042103285Sikob }else{ 1043103285Sikob return; 1044103285Sikob } 1045103285Sikob s = splfw(); 1046103285Sikob tr = dbch->bottom; 1047103285Sikob packets = 0; 1048113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1049113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1050103285Sikob while(dbch->xferq.queued > 0){ 1051103285Sikob LAST_DB(tr, db); 1052113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1053113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1054103285Sikob if (fc->status != FWBUSRESET) 1055103285Sikob /* maybe out of order?? */ 1056103285Sikob goto out; 1057103285Sikob } 1058113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1059113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1060113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1061119155Ssimokawa#if 1 1062119155Ssimokawa if (firewire_debug) 1063119155Ssimokawa dump_db(sc, ch); 1064103285Sikob#endif 1065113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1066113584Ssimokawa /* Stop DMA */ 1067103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1068103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1069103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1070103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1071103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1072103285Sikob } 1073113584Ssimokawa stat = status & FWOHCIEV_MASK; 1074103285Sikob switch(stat){ 1075110577Ssimokawa case FWOHCIEV_ACKPEND: 1076103285Sikob case FWOHCIEV_ACKCOMPL: 1077103285Sikob err = 0; 1078103285Sikob break; 1079103285Sikob case FWOHCIEV_ACKBSA: 1080103285Sikob case FWOHCIEV_ACKBSB: 1081110577Ssimokawa case FWOHCIEV_ACKBSX: 1082103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1083103285Sikob err = EBUSY; 1084103285Sikob break; 1085103285Sikob case FWOHCIEV_FLUSHED: 1086103285Sikob case FWOHCIEV_ACKTARD: 1087103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1088103285Sikob err = EAGAIN; 1089103285Sikob break; 1090103285Sikob case FWOHCIEV_MISSACK: 1091103285Sikob case FWOHCIEV_UNDRRUN: 1092103285Sikob case FWOHCIEV_OVRRUN: 1093103285Sikob case FWOHCIEV_DESCERR: 1094103285Sikob case FWOHCIEV_DTRDERR: 1095103285Sikob case FWOHCIEV_TIMEOUT: 1096103285Sikob case FWOHCIEV_TCODERR: 1097103285Sikob case FWOHCIEV_UNKNOWN: 1098103285Sikob case FWOHCIEV_ACKDERR: 1099103285Sikob case FWOHCIEV_ACKTERR: 1100103285Sikob default: 1101103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1102103285Sikob stat, fwohcicode[stat]); 1103103285Sikob err = EINVAL; 1104103285Sikob break; 1105103285Sikob } 1106110577Ssimokawa if (tr->xfer != NULL) { 1107103285Sikob xfer = tr->xfer; 1108113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1109119289Ssimokawa#if 0 1110113584Ssimokawa if (firewire_debug) 1111113584Ssimokawa printf("already rcvd\n"); 1112119289Ssimokawa#endif 1113113584Ssimokawa fw_xfer_done(xfer); 1114113584Ssimokawa } else { 1115114218Ssimokawa xfer->state = FWXF_SENT; 1116114218Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1117114218Ssimokawa xfer->state = FWXF_BUSY; 1118114218Ssimokawa xfer->resp = err; 1119114218Ssimokawa if (xfer->retry_req != NULL) 1120114218Ssimokawa xfer->retry_req(xfer); 1121114224Ssimokawa else { 1122120660Ssimokawa xfer->recv.pay_len = 0; 1123114218Ssimokawa fw_xfer_done(xfer); 1124114224Ssimokawa } 1125114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1126114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1127114218Ssimokawa xfer->state = FWXF_SENTERR; 1128114218Ssimokawa xfer->resp = err; 1129120660Ssimokawa xfer->recv.pay_len = 0; 1130113584Ssimokawa fw_xfer_done(xfer); 1131114218Ssimokawa } 1132103285Sikob } 1133110577Ssimokawa /* 1134110577Ssimokawa * The watchdog timer takes care of split 1135110577Ssimokawa * transcation timeout for ACKPEND case. 1136110577Ssimokawa */ 1137113584Ssimokawa } else { 1138113584Ssimokawa printf("this shouldn't happen\n"); 1139103285Sikob } 1140110269Ssimokawa dbch->xferq.queued --; 1141103285Sikob tr->xfer = NULL; 1142103285Sikob 1143103285Sikob packets ++; 1144103285Sikob tr = STAILQ_NEXT(tr, link); 1145103285Sikob dbch->bottom = tr; 1146111956Ssimokawa if (dbch->bottom == dbch->top) { 1147111956Ssimokawa /* we reaches the end of context program */ 1148111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1149111956Ssimokawa printf("queued > 0\n"); 1150111956Ssimokawa break; 1151111956Ssimokawa } 1152103285Sikob } 1153103285Sikobout: 1154103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1155103285Sikob printf("make free slot\n"); 1156103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1157103285Sikob fwohci_start(sc, dbch); 1158103285Sikob } 1159103285Sikob splx(s); 1160103285Sikob} 1161106790Ssimokawa 1162106790Ssimokawastatic void 1163106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1164103285Sikob{ 1165103285Sikob struct fwohcidb_tr *db_tr; 1166113584Ssimokawa int idb; 1167103285Sikob 1168108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1169108527Ssimokawa return; 1170108527Ssimokawa 1171113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1172103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1173113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1174113584Ssimokawa db_tr->buf != NULL) { 1175113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1176113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1177113584Ssimokawa db_tr->buf = NULL; 1178113584Ssimokawa } else if (db_tr->dma_map != NULL) 1179113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1180103285Sikob } 1181103285Sikob dbch->ndb = 0; 1182103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1183113584Ssimokawa fwdma_free_multiseg(dbch->am); 1184110195Ssimokawa free(db_tr, M_FW); 1185103285Sikob STAILQ_INIT(&dbch->db_trq); 1186108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1187103285Sikob} 1188106790Ssimokawa 1189106790Ssimokawastatic void 1190113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1191103285Sikob{ 1192103285Sikob int idb; 1193103285Sikob struct fwohcidb_tr *db_tr; 1194108642Ssimokawa 1195108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1196108642Ssimokawa goto out; 1197108642Ssimokawa 1198113584Ssimokawa /* create dma_tag for buffers */ 1199113584Ssimokawa#define MAX_REQCOUNT 0xffff 1200113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1201113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1202113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1203113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1204113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1205113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1206113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1207113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1208117126Sscottl /*flags*/ 0, 1209117228Ssimokawa#if __FreeBSD_version >= 501102 1210117126Sscottl /*lockfunc*/busdma_lock_mutex, 1211117228Ssimokawa /*lockarg*/&Giant, 1212117228Ssimokawa#endif 1213117228Ssimokawa &dbch->dmat)) 1214113584Ssimokawa return; 1215113584Ssimokawa 1216103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1217103285Sikob /* DB entry must start at 16 bytes bounary. */ 1218103285Sikob STAILQ_INIT(&dbch->db_trq); 1219103285Sikob db_tr = (struct fwohcidb_tr *) 1220103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1221113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1222103285Sikob if(db_tr == NULL){ 1223109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1224103285Sikob return; 1225103285Sikob } 1226109379Ssimokawa 1227113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1228113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1229113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1230113584Ssimokawa if (dbch->am == NULL) { 1231113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1232103285Sikob return; 1233103285Sikob } 1234103285Sikob /* Attach DB to DMA ch. */ 1235103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1236103285Sikob db_tr->dbcnt = 0; 1237113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1238113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1239113584Ssimokawa /* create dmamap for buffers */ 1240113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1241113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1242113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1243113584Ssimokawa printf("bus_dmamap_create failed\n"); 1244113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1245113584Ssimokawa fwohci_db_free(dbch); 1246113584Ssimokawa return; 1247113584Ssimokawa } 1248103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1249113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1250108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1251108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1252108530Ssimokawa ].start = (caddr_t)db_tr; 1253108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1254108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1255108530Ssimokawa ].end = (caddr_t)db_tr; 1256103285Sikob } 1257103285Sikob db_tr++; 1258103285Sikob } 1259103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1260103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1261108642Ssimokawaout: 1262108642Ssimokawa dbch->xferq.queued = 0; 1263108642Ssimokawa dbch->pdb_tr = NULL; 1264103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1265103285Sikob dbch->bottom = dbch->top; 1266108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1267103285Sikob} 1268106790Ssimokawa 1269106790Ssimokawastatic int 1270106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1271103285Sikob{ 1272103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1273113584Ssimokawa int sleepch; 1274109890Ssimokawa 1275113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1276113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1277103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1278103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1279109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1280113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1281103285Sikob fwohci_db_free(&sc->it[dmach]); 1282103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1283103285Sikob return 0; 1284103285Sikob} 1285106790Ssimokawa 1286106790Ssimokawastatic int 1287106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1288103285Sikob{ 1289103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1290113584Ssimokawa int sleepch; 1291103285Sikob 1292103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1293103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1294103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1295109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1296113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1297103285Sikob fwohci_db_free(&sc->ir[dmach]); 1298103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1299103285Sikob return 0; 1300103285Sikob} 1301106790Ssimokawa 1302113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1303106790Ssimokawastatic void 1304106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1305103285Sikob{ 1306113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1307103285Sikob return; 1308103285Sikob} 1309103285Sikob#endif 1310103285Sikob 1311106790Ssimokawastatic int 1312106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1313103285Sikob{ 1314103285Sikob int err = 0; 1315113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1316103285Sikob u_int32_t off = NULL; 1317103285Sikob struct fwohcidb_tr *db_tr; 1318120660Ssimokawa struct fwohcidb *db; 1319103285Sikob 1320103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1321103285Sikob err = EINVAL; 1322103285Sikob return err; 1323103285Sikob } 1324103285Sikob z = dbch->ndesc; 1325103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1326103285Sikob if( &sc->it[dmach] == dbch){ 1327103285Sikob off = OHCI_ITOFF(dmach); 1328103285Sikob break; 1329103285Sikob } 1330103285Sikob } 1331103285Sikob if(off == NULL){ 1332103285Sikob err = EINVAL; 1333103285Sikob return err; 1334103285Sikob } 1335103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1336103285Sikob return err; 1337103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1338103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1339103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1340103285Sikob } 1341103285Sikob db_tr = dbch->top; 1342113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1343113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1344103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1345103285Sikob break; 1346103285Sikob } 1347109892Ssimokawa db = db_tr->db; 1348113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1349113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1350113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1351113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1352103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1353103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1354113584Ssimokawa FWOHCI_DMA_SET( 1355113584Ssimokawa db[ldesc].db.desc.cmd, 1356113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1357109280Ssimokawa /* OHCI 1.1 and above */ 1358113584Ssimokawa FWOHCI_DMA_SET( 1359113584Ssimokawa db[0].db.desc.cmd, 1360113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1361103285Sikob } 1362103285Sikob } 1363103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1364103285Sikob } 1365113584Ssimokawa FWOHCI_DMA_CLEAR( 1366113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1367103285Sikob return err; 1368103285Sikob} 1369106790Ssimokawa 1370106790Ssimokawastatic int 1371106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1372103285Sikob{ 1373103285Sikob int err = 0; 1374109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1375103285Sikob u_int32_t off = NULL; 1376103285Sikob struct fwohcidb_tr *db_tr; 1377120660Ssimokawa struct fwohcidb *db; 1378103285Sikob 1379103285Sikob z = dbch->ndesc; 1380103285Sikob if(&sc->arrq == dbch){ 1381103285Sikob off = OHCI_ARQOFF; 1382103285Sikob }else if(&sc->arrs == dbch){ 1383103285Sikob off = OHCI_ARSOFF; 1384103285Sikob }else{ 1385103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1386103285Sikob if( &sc->ir[dmach] == dbch){ 1387103285Sikob off = OHCI_IROFF(dmach); 1388103285Sikob break; 1389103285Sikob } 1390103285Sikob } 1391103285Sikob } 1392103285Sikob if(off == NULL){ 1393103285Sikob err = EINVAL; 1394103285Sikob return err; 1395103285Sikob } 1396103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1397103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1398103285Sikob return err; 1399103285Sikob }else{ 1400103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1401103285Sikob err = EBUSY; 1402103285Sikob return err; 1403103285Sikob } 1404103285Sikob } 1405103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1406108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1407103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1408103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1409103285Sikob } 1410103285Sikob db_tr = dbch->top; 1411113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1412113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1413113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1414103285Sikob break; 1415109892Ssimokawa db = db_tr->db; 1416109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1417113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1418113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1419103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1420103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1421113584Ssimokawa FWOHCI_DMA_SET( 1422113584Ssimokawa db[ldesc].db.desc.cmd, 1423113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1424113584Ssimokawa FWOHCI_DMA_CLEAR( 1425113584Ssimokawa db[ldesc].db.desc.depend, 1426113584Ssimokawa 0xf); 1427103285Sikob } 1428103285Sikob } 1429103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1430103285Sikob } 1431113584Ssimokawa FWOHCI_DMA_CLEAR( 1432113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1433103285Sikob dbch->buf_offset = 0; 1434113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1435113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1436103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1437103285Sikob return err; 1438103285Sikob }else{ 1439113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1440103285Sikob } 1441103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1442103285Sikob return err; 1443103285Sikob} 1444106790Ssimokawa 1445106790Ssimokawastatic int 1446113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1447109890Ssimokawa{ 1448109890Ssimokawa int sec, cycle, cycle_match; 1449109890Ssimokawa 1450109890Ssimokawa cycle = cycle_now & 0x1fff; 1451109890Ssimokawa sec = cycle_now >> 13; 1452109890Ssimokawa#define CYCLE_MOD 0x10 1453113584Ssimokawa#if 1 1454109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1455113584Ssimokawa#else 1456113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1457113584Ssimokawa#endif 1458109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1459109890Ssimokawa if (cycle >= 8000) { 1460109890Ssimokawa sec ++; 1461109890Ssimokawa cycle -= 8000; 1462109890Ssimokawa } 1463113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1464109890Ssimokawa if (cycle >= 8000) { 1465109890Ssimokawa sec ++; 1466109890Ssimokawa if (cycle == 8000) 1467109890Ssimokawa cycle = 0; 1468109890Ssimokawa else 1469109890Ssimokawa cycle = CYCLE_MOD; 1470109890Ssimokawa } 1471109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1472109890Ssimokawa 1473109890Ssimokawa return(cycle_match); 1474109890Ssimokawa} 1475109890Ssimokawa 1476109890Ssimokawastatic int 1477106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1478103285Sikob{ 1479103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1480103285Sikob int err = 0; 1481103285Sikob unsigned short tag, ich; 1482103285Sikob struct fwohci_dbch *dbch; 1483109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1484109356Ssimokawa u_int32_t stat; 1485109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1486109890Ssimokawa struct fw_xferq *it; 1487103285Sikob 1488103285Sikob dbch = &sc->it[dmach]; 1489109890Ssimokawa it = &dbch->xferq; 1490109890Ssimokawa 1491109890Ssimokawa tag = (it->flag >> 6) & 3; 1492109890Ssimokawa ich = it->flag & 0x3f; 1493109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1494109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1495103285Sikob dbch->ndesc = 3; 1496113584Ssimokawa fwohci_db_init(sc, dbch); 1497109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1498109179Ssimokawa return ENOMEM; 1499103285Sikob err = fwohci_tx_enable(sc, dbch); 1500103285Sikob } 1501103285Sikob if(err) 1502103285Sikob return err; 1503109890Ssimokawa 1504109892Ssimokawa ldesc = dbch->ndesc - 1; 1505109890Ssimokawa s = splfw(); 1506109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1507109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1508120660Ssimokawa struct fwohcidb *db; 1509109890Ssimokawa 1510113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1511113584Ssimokawa BUS_DMASYNC_PREWRITE); 1512109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1513109890Ssimokawa if (prev != NULL) { 1514109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1515113584Ssimokawa#if 0 /* XXX necessary? */ 1516113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1517113584Ssimokawa OHCI_BRANCH_ALWAYS); 1518113584Ssimokawa#endif 1519109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1520109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1521113584Ssimokawa ((struct fwohcidb_tr *) 1522113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1523109892Ssimokawa#else 1524113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1525113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1526109892Ssimokawa#endif 1527103285Sikob } 1528109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1529109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1530109890Ssimokawa prev = chunk; 1531109403Ssimokawa } 1532113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1533113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1534109890Ssimokawa splx(s); 1535109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1536113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1537113584Ssimokawa printf("stat 0x%x\n", stat); 1538113584Ssimokawa 1539109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1540109890Ssimokawa return 0; 1541109890Ssimokawa 1542113584Ssimokawa#if 0 1543109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1544113584Ssimokawa#endif 1545109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1546109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1547109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1548113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1549109890Ssimokawa 1550109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1551113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1552113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1553113584Ssimokawa if (firewire_debug) { 1554109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1555113584Ssimokawa#if 1 1556113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1557113584Ssimokawa#endif 1558113584Ssimokawa } 1559109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1560109890Ssimokawa#if 1 1561109890Ssimokawa /* Don't start until all chunks are buffered */ 1562109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1563109890Ssimokawa goto out; 1564109890Ssimokawa#endif 1565113584Ssimokawa#if 1 1566109890Ssimokawa /* Clear cycle match counter bits */ 1567109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1568109890Ssimokawa 1569109356Ssimokawa /* 2bit second + 13bit cycle */ 1570109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1571113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1572109890Ssimokawa 1573109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1574109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1575109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1576113584Ssimokawa#else 1577113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1578113584Ssimokawa#endif 1579113584Ssimokawa if (firewire_debug) { 1580109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1581109403Ssimokawa cycle_now, cycle_match); 1582113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1583113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1584113584Ssimokawa } 1585109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1586109890Ssimokawa device_printf(sc->fc.dev, 1587109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1588113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1589103285Sikob } 1590109890Ssimokawaout: 1591103285Sikob return err; 1592103285Sikob} 1593106790Ssimokawa 1594106790Ssimokawastatic int 1595113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1596103285Sikob{ 1597103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1598109890Ssimokawa int err = 0, s, ldesc; 1599103285Sikob unsigned short tag, ich; 1600109736Ssimokawa u_int32_t stat; 1601109890Ssimokawa struct fwohci_dbch *dbch; 1602113584Ssimokawa struct fwohcidb_tr *db_tr; 1603109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1604109890Ssimokawa struct fw_xferq *ir; 1605103285Sikob 1606109890Ssimokawa dbch = &sc->ir[dmach]; 1607109890Ssimokawa ir = &dbch->xferq; 1608109890Ssimokawa 1609109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1610109890Ssimokawa tag = (ir->flag >> 6) & 3; 1611109890Ssimokawa ich = ir->flag & 0x3f; 1612108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1613108995Ssimokawa 1614109890Ssimokawa ir->queued = 0; 1615109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1616109890Ssimokawa dbch->ndesc = 2; 1617113584Ssimokawa fwohci_db_init(sc, dbch); 1618109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1619109179Ssimokawa return ENOMEM; 1620109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1621103285Sikob } 1622103285Sikob if(err) 1623103285Sikob return err; 1624103285Sikob 1625109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1626109890Ssimokawa if (first == NULL) { 1627109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1628109890Ssimokawa return 0; 1629109890Ssimokawa } 1630109890Ssimokawa 1631111892Ssimokawa ldesc = dbch->ndesc - 1; 1632111892Ssimokawa s = splfw(); 1633109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1634109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1635120660Ssimokawa struct fwohcidb *db; 1636109890Ssimokawa 1637111942Ssimokawa#if 1 /* XXX for if_fwe */ 1638113584Ssimokawa if (chunk->mbuf != NULL) { 1639113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1640113584Ssimokawa db_tr->dbcnt = 1; 1641113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1642113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1643113584Ssimokawa /* flags */0); 1644113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1645113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1646113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1647113584Ssimokawa } 1648111942Ssimokawa#endif 1649109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1650113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1651113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1652109890Ssimokawa if (prev != NULL) { 1653109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1654113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1655103285Sikob } 1656109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1657109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1658109890Ssimokawa prev = chunk; 1659103285Sikob } 1660113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1661113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1662109890Ssimokawa splx(s); 1663109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1664109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1665109890Ssimokawa return 0; 1666109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1667109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1668109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1669109890Ssimokawa } 1670109890Ssimokawa 1671113584Ssimokawa if (firewire_debug) 1672113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1673109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1674109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1675109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1676109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1677109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1678109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1679113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1680109890Ssimokawa | dbch->ndesc); 1681109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1682109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1683113584Ssimokawa#if 0 1684113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1685113584Ssimokawa#endif 1686103285Sikob return err; 1687103285Sikob} 1688106790Ssimokawa 1689106790Ssimokawaint 1690110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1691103285Sikob{ 1692103285Sikob u_int i; 1693103285Sikob 1694103285Sikob/* Now stopping all DMA channel */ 1695103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1696103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1697103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1698103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1699103285Sikob 1700103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1701103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1702103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1703103285Sikob } 1704103285Sikob 1705103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1706103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1707103285Sikob 1708103285Sikob/* Stop interrupt */ 1709103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1710103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1711103285Sikob | OHCI_INT_PHY_INT 1712103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1713103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1714103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1715103285Sikob | OHCI_INT_PHY_BUS_R); 1716116978Ssimokawa 1717118416Ssimokawa if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1718118416Ssimokawa fw_drain_txq(&sc->fc); 1719116978Ssimokawa 1720108642Ssimokawa/* XXX Link down? Bus reset? */ 1721103285Sikob return 0; 1722103285Sikob} 1723103285Sikob 1724108642Ssimokawaint 1725108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1726108642Ssimokawa{ 1727108642Ssimokawa int i; 1728116978Ssimokawa struct fw_xferq *ir; 1729116978Ssimokawa struct fw_bulkxfer *chunk; 1730108642Ssimokawa 1731108642Ssimokawa fwohci_reset(sc, dev); 1732108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1733108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1734116978Ssimokawa ir = &sc->ir[i].xferq; 1735116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1736108642Ssimokawa device_printf(sc->fc.dev, 1737108642Ssimokawa "resume iso receive ch: %d\n", i); 1738116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1739116978Ssimokawa /* requeue stdma to stfree */ 1740116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1741116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1742116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1743116978Ssimokawa } 1744108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1745108642Ssimokawa } 1746108642Ssimokawa } 1747108642Ssimokawa 1748108642Ssimokawa bus_generic_resume(dev); 1749108642Ssimokawa sc->fc.ibr(&sc->fc); 1750108642Ssimokawa return 0; 1751108642Ssimokawa} 1752108642Ssimokawa 1753103285Sikob#define ACK_ALL 1754103285Sikobstatic void 1755106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1756103285Sikob{ 1757103285Sikob u_int32_t irstat, itstat; 1758103285Sikob u_int i; 1759103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1760103285Sikob 1761103285Sikob#ifdef OHCI_DEBUG 1762103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1763103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1764103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1765103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1766103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1767103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1768103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1769103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1770103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1771103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1772103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1773103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1774103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1775103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1776103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1777103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1778103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1779103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1780103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1781103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1782103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1783103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1784103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1785103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1786103285Sikob ); 1787103285Sikob#endif 1788103285Sikob/* Bus reset */ 1789103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1790111074Ssimokawa if (fc->status == FWBUSRESET) 1791111074Ssimokawa goto busresetout; 1792111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1793111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1794111074Ssimokawa 1795103285Sikob device_printf(fc->dev, "BUS reset\n"); 1796103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1797103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1798103285Sikob 1799103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1800103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1801103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1802103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1803103285Sikob 1804103285Sikob#ifndef ACK_ALL 1805103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1806103285Sikob#endif 1807110798Ssimokawa fw_busreset(fc); 1808116376Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1809116376Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1810103285Sikob } 1811111074Ssimokawabusresetout: 1812103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1813103285Sikob#ifndef ACK_ALL 1814103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1815103285Sikob#endif 1816113584Ssimokawa#if __FreeBSD_version >= 500000 1817113584Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1818113584Ssimokawa#else 1819113584Ssimokawa irstat = sc->irstat; 1820113584Ssimokawa sc->irstat = 0; 1821113584Ssimokawa#endif 1822103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1823109644Ssimokawa struct fwohci_dbch *dbch; 1824109644Ssimokawa 1825103285Sikob if((irstat & (1 << i)) != 0){ 1826109644Ssimokawa dbch = &sc->ir[i]; 1827109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1828109644Ssimokawa device_printf(sc->fc.dev, 1829109644Ssimokawa "dma(%d) not active\n", i); 1830109644Ssimokawa continue; 1831109644Ssimokawa } 1832113584Ssimokawa fwohci_rbuf_update(sc, i); 1833103285Sikob } 1834103285Sikob } 1835103285Sikob } 1836103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1837103285Sikob#ifndef ACK_ALL 1838103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1839103285Sikob#endif 1840113584Ssimokawa#if __FreeBSD_version >= 500000 1841113584Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1842113584Ssimokawa#else 1843113584Ssimokawa itstat = sc->itstat; 1844113584Ssimokawa sc->itstat = 0; 1845113584Ssimokawa#endif 1846103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1847103285Sikob if((itstat & (1 << i)) != 0){ 1848103285Sikob fwohci_tbuf_update(sc, i); 1849103285Sikob } 1850103285Sikob } 1851103285Sikob } 1852103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1853103285Sikob#ifndef ACK_ALL 1854103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1855103285Sikob#endif 1856103285Sikob#if 0 1857103285Sikob dump_dma(sc, ARRS_CH); 1858103285Sikob dump_db(sc, ARRS_CH); 1859103285Sikob#endif 1860106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1861103285Sikob } 1862103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1863103285Sikob#ifndef ACK_ALL 1864103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1865103285Sikob#endif 1866103285Sikob#if 0 1867103285Sikob dump_dma(sc, ARRQ_CH); 1868103285Sikob dump_db(sc, ARRQ_CH); 1869103285Sikob#endif 1870106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1871103285Sikob } 1872103285Sikob if(stat & OHCI_INT_PHY_SID){ 1873113584Ssimokawa u_int32_t *buf, node_id; 1874103285Sikob int plen; 1875103285Sikob 1876103285Sikob#ifndef ACK_ALL 1877103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1878103285Sikob#endif 1879111074Ssimokawa /* Enable bus reset interrupt */ 1880111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1881111787Ssimokawa /* Allow async. request to us */ 1882111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1883111787Ssimokawa /* XXX insecure ?? */ 1884111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1885111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1886111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1887112523Ssimokawa /* Set ATRetries register */ 1888112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1889103285Sikob/* 1890103285Sikob** Checking whether the node is root or not. If root, turn on 1891103285Sikob** cycle master. 1892103285Sikob*/ 1893113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1894113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1895113584Ssimokawa 1896113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1897113584Ssimokawa node_id, (plen >> 16) & 0xff); 1898113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1899103285Sikob printf("Bus reset failure\n"); 1900103285Sikob goto sidout; 1901103285Sikob } 1902113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1903103285Sikob printf("CYCLEMASTER mode\n"); 1904103285Sikob OWRITE(sc, OHCI_LNKCTL, 1905103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1906113584Ssimokawa } else { 1907103285Sikob printf("non CYCLEMASTER mode\n"); 1908103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1909103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1910103285Sikob } 1911113584Ssimokawa fc->nodeid = node_id & 0x3f; 1912103285Sikob 1913113584Ssimokawa if (plen & OHCI_SID_ERR) { 1914113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1915113584Ssimokawa goto sidout; 1916113584Ssimokawa } 1917113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1918109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1919109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1920109736Ssimokawa goto sidout; 1921109736Ssimokawa } 1922103285Sikob plen -= 4; /* chop control info */ 1923113584Ssimokawa buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1924113584Ssimokawa if (buf == NULL) { 1925113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1926113584Ssimokawa goto sidout; 1927113584Ssimokawa } 1928113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1929113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1930110269Ssimokawa#if 1 1931110269Ssimokawa /* pending all pre-bus_reset packets */ 1932110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1933110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1934110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1935110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1936110798Ssimokawa fw_drain_txq(fc); 1937110269Ssimokawa#endif 1938113584Ssimokawa fw_sidrcv(fc, buf, plen); 1939113584Ssimokawa free(buf, M_FW); 1940103285Sikob } 1941103285Sikobsidout: 1942103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1943103285Sikob#ifndef ACK_ALL 1944103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1945103285Sikob#endif 1946103285Sikob fwohci_txd(sc, &(sc->atrq)); 1947103285Sikob } 1948103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1949103285Sikob#ifndef ACK_ALL 1950103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1951103285Sikob#endif 1952103285Sikob fwohci_txd(sc, &(sc->atrs)); 1953103285Sikob } 1954103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1955103285Sikob#ifndef ACK_ALL 1956103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1957103285Sikob#endif 1958103285Sikob device_printf(fc->dev, "posted write error\n"); 1959103285Sikob } 1960103285Sikob if((stat & OHCI_INT_ERR )){ 1961103285Sikob#ifndef ACK_ALL 1962103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1963103285Sikob#endif 1964103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1965103285Sikob } 1966103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1967103285Sikob#ifndef ACK_ALL 1968103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1969103285Sikob#endif 1970103285Sikob device_printf(fc->dev, "phy int\n"); 1971103285Sikob } 1972103285Sikob 1973103285Sikob return; 1974103285Sikob} 1975103285Sikob 1976113584Ssimokawa#if FWOHCI_TASKQUEUE 1977113584Ssimokawastatic void 1978113584Ssimokawafwohci_complete(void *arg, int pending) 1979113584Ssimokawa{ 1980113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1981113584Ssimokawa u_int32_t stat; 1982113584Ssimokawa 1983113584Ssimokawaagain: 1984113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 1985113584Ssimokawa if (stat) 1986113584Ssimokawa fwohci_intr_body(sc, stat, -1); 1987113584Ssimokawa else 1988113584Ssimokawa return; 1989113584Ssimokawa goto again; 1990113584Ssimokawa} 1991113584Ssimokawa#endif 1992113584Ssimokawa 1993113584Ssimokawastatic u_int32_t 1994113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 1995113584Ssimokawa{ 1996113584Ssimokawa u_int32_t stat, irstat, itstat; 1997113584Ssimokawa 1998113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 1999113584Ssimokawa if (stat == 0xffffffff) { 2000113584Ssimokawa device_printf(sc->fc.dev, 2001113584Ssimokawa "device physically ejected?\n"); 2002113584Ssimokawa return(stat); 2003113584Ssimokawa } 2004113584Ssimokawa#ifdef ACK_ALL 2005113584Ssimokawa if (stat) 2006113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2007113584Ssimokawa#endif 2008113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2009113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2010113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2011113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2012113584Ssimokawa } 2013113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2014113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2015113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2016113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2017113584Ssimokawa } 2018113584Ssimokawa return(stat); 2019113584Ssimokawa} 2020113584Ssimokawa 2021103285Sikobvoid 2022103285Sikobfwohci_intr(void *arg) 2023103285Sikob{ 2024103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2025113584Ssimokawa u_int32_t stat; 2026113584Ssimokawa#if !FWOHCI_TASKQUEUE 2027113584Ssimokawa u_int32_t bus_reset = 0; 2028113584Ssimokawa#endif 2029103285Sikob 2030103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 2031103285Sikob /* polling mode */ 2032103285Sikob return; 2033103285Sikob } 2034103285Sikob 2035113584Ssimokawa#if !FWOHCI_TASKQUEUE 2036113584Ssimokawaagain: 2037103285Sikob#endif 2038113584Ssimokawa stat = fwochi_check_stat(sc); 2039113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2040113584Ssimokawa return; 2041113584Ssimokawa#if FWOHCI_TASKQUEUE 2042113584Ssimokawa atomic_set_int(&sc->intstat, stat); 2043113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 2044113584Ssimokawa if (stat) 2045113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2046113584Ssimokawa#else 2047113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 2048113584Ssimokawa if ((stat & ~bus_reset) == 0) 2049113584Ssimokawa return; 2050113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2051113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2052113584Ssimokawa goto again; 2053113584Ssimokawa#endif 2054103285Sikob} 2055103285Sikob 2056116897Ssimokawavoid 2057103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2058103285Sikob{ 2059103285Sikob int s; 2060103285Sikob u_int32_t stat; 2061103285Sikob struct fwohci_softc *sc; 2062103285Sikob 2063103285Sikob 2064103285Sikob sc = (struct fwohci_softc *)fc; 2065103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2066103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2067103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2068103285Sikob#if 0 2069103285Sikob if (!quick) { 2070103285Sikob#else 2071103285Sikob if (1) { 2072103285Sikob#endif 2073113584Ssimokawa stat = fwochi_check_stat(sc); 2074113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2075103285Sikob return; 2076103285Sikob } 2077103285Sikob s = splfw(); 2078106789Ssimokawa fwohci_intr_body(sc, stat, count); 2079103285Sikob splx(s); 2080103285Sikob} 2081103285Sikob 2082103285Sikobstatic void 2083103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2084103285Sikob{ 2085103285Sikob struct fwohci_softc *sc; 2086103285Sikob 2087103285Sikob sc = (struct fwohci_softc *)fc; 2088107653Ssimokawa if (bootverbose) 2089108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2090103285Sikob if (enable) { 2091103285Sikob sc->intmask |= OHCI_INT_EN; 2092103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2093103285Sikob } else { 2094103285Sikob sc->intmask &= ~OHCI_INT_EN; 2095103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2096103285Sikob } 2097103285Sikob} 2098103285Sikob 2099106790Ssimokawastatic void 2100106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2101103285Sikob{ 2102103285Sikob struct firewire_comm *fc = &sc->fc; 2103120660Ssimokawa struct fwohcidb *db; 2104109890Ssimokawa struct fw_bulkxfer *chunk; 2105109890Ssimokawa struct fw_xferq *it; 2106109890Ssimokawa u_int32_t stat, count; 2107113584Ssimokawa int s, w=0, ldesc; 2108103285Sikob 2109109890Ssimokawa it = fc->it[dmach]; 2110113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2111109890Ssimokawa s = splfw(); /* unnecessary ? */ 2112113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2113119155Ssimokawa if (firewire_debug) 2114119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2115109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2116109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2117113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2118113584Ssimokawa >> OHCI_STATUS_SHIFT; 2119109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2120119155Ssimokawa /* timestamp */ 2121113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2122113584Ssimokawa & OHCI_COUNT_MASK; 2123109890Ssimokawa if (stat == 0) 2124109890Ssimokawa break; 2125109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2126109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2127109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2128109890Ssimokawa#if 0 2129109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2130109179Ssimokawa#endif 2131109890Ssimokawa break; 2132109890Ssimokawa default: 2133109423Ssimokawa device_printf(fc->dev, 2134113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2135113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2136109890Ssimokawa } 2137109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2138109890Ssimokawa w++; 2139109403Ssimokawa } 2140109890Ssimokawa splx(s); 2141109890Ssimokawa if (w) 2142109890Ssimokawa wakeup(it); 2143103285Sikob} 2144106790Ssimokawa 2145106790Ssimokawastatic void 2146106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2147103285Sikob{ 2148109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2149120660Ssimokawa struct fwohcidb_tr *db_tr; 2150109890Ssimokawa struct fw_bulkxfer *chunk; 2151109890Ssimokawa struct fw_xferq *ir; 2152109890Ssimokawa u_int32_t stat; 2153113584Ssimokawa int s, w=0, ldesc; 2154109179Ssimokawa 2155109890Ssimokawa ir = fc->ir[dmach]; 2156113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2157113584Ssimokawa#if 0 2158113584Ssimokawa dump_db(sc, dmach); 2159113584Ssimokawa#endif 2160109890Ssimokawa s = splfw(); 2161113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2162109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2163113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2164113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2165113584Ssimokawa >> OHCI_STATUS_SHIFT; 2166109890Ssimokawa if (stat == 0) 2167109890Ssimokawa break; 2168113584Ssimokawa 2169113584Ssimokawa if (chunk->mbuf != NULL) { 2170113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2171113584Ssimokawa BUS_DMASYNC_POSTREAD); 2172113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2173113584Ssimokawa } else if (ir->buf != NULL) { 2174113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2175113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2176113584Ssimokawa } else { 2177113584Ssimokawa /* XXX */ 2178113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2179113584Ssimokawa } 2180113584Ssimokawa 2181109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2182109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2183109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2184109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2185111942Ssimokawa chunk->resp = 0; 2186109890Ssimokawa break; 2187109890Ssimokawa default: 2188111942Ssimokawa chunk->resp = EINVAL; 2189109890Ssimokawa device_printf(fc->dev, 2190113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2191113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2192109890Ssimokawa } 2193109890Ssimokawa w++; 2194103285Sikob } 2195109890Ssimokawa splx(s); 2196111942Ssimokawa if (w) { 2197111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2198111942Ssimokawa ir->hand(ir); 2199111942Ssimokawa else 2200111942Ssimokawa wakeup(ir); 2201111942Ssimokawa } 2202103285Sikob} 2203106790Ssimokawa 2204106790Ssimokawavoid 2205106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2206106790Ssimokawa{ 2207103285Sikob u_int32_t off, cntl, stat, cmd, match; 2208103285Sikob 2209103285Sikob if(ch == 0){ 2210103285Sikob off = OHCI_ATQOFF; 2211103285Sikob }else if(ch == 1){ 2212103285Sikob off = OHCI_ATSOFF; 2213103285Sikob }else if(ch == 2){ 2214103285Sikob off = OHCI_ARQOFF; 2215103285Sikob }else if(ch == 3){ 2216103285Sikob off = OHCI_ARSOFF; 2217103285Sikob }else if(ch < IRX_CH){ 2218103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2219103285Sikob }else{ 2220103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2221103285Sikob } 2222103285Sikob cntl = stat = OREAD(sc, off); 2223103285Sikob cmd = OREAD(sc, off + 0xc); 2224103285Sikob match = OREAD(sc, off + 0x10); 2225103285Sikob 2226113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2227103285Sikob ch, 2228103285Sikob cntl, 2229103285Sikob cmd, 2230103285Sikob match); 2231103285Sikob stat &= 0xffff ; 2232113584Ssimokawa if (stat) { 2233103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2234103285Sikob ch, 2235103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2236103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2237103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2238103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2239103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2240103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2241103285Sikob fwohcicode[stat & 0x1f], 2242103285Sikob stat & 0x1f 2243103285Sikob ); 2244103285Sikob }else{ 2245103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2246103285Sikob } 2247103285Sikob} 2248106790Ssimokawa 2249106790Ssimokawavoid 2250106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2251106790Ssimokawa{ 2252103285Sikob struct fwohci_dbch *dbch; 2253113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2254120660Ssimokawa struct fwohcidb *curr = NULL, *prev, *next = NULL; 2255103285Sikob int idb, jdb; 2256103285Sikob u_int32_t cmd, off; 2257103285Sikob if(ch == 0){ 2258103285Sikob off = OHCI_ATQOFF; 2259103285Sikob dbch = &sc->atrq; 2260103285Sikob }else if(ch == 1){ 2261103285Sikob off = OHCI_ATSOFF; 2262103285Sikob dbch = &sc->atrs; 2263103285Sikob }else if(ch == 2){ 2264103285Sikob off = OHCI_ARQOFF; 2265103285Sikob dbch = &sc->arrq; 2266103285Sikob }else if(ch == 3){ 2267103285Sikob off = OHCI_ARSOFF; 2268103285Sikob dbch = &sc->arrs; 2269103285Sikob }else if(ch < IRX_CH){ 2270103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2271103285Sikob dbch = &sc->it[ch - ITX_CH]; 2272103285Sikob }else { 2273103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2274103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2275103285Sikob } 2276103285Sikob cmd = OREAD(sc, off + 0xc); 2277103285Sikob 2278103285Sikob if( dbch->ndb == 0 ){ 2279103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2280103285Sikob return; 2281103285Sikob } 2282103285Sikob pp = dbch->top; 2283103285Sikob prev = pp->db; 2284103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2285103285Sikob if(pp == NULL){ 2286103285Sikob curr = NULL; 2287103285Sikob goto outdb; 2288103285Sikob } 2289103285Sikob cp = STAILQ_NEXT(pp, link); 2290103285Sikob if(cp == NULL){ 2291103285Sikob curr = NULL; 2292103285Sikob goto outdb; 2293103285Sikob } 2294103285Sikob np = STAILQ_NEXT(cp, link); 2295103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2296113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2297103285Sikob curr = cp->db; 2298103285Sikob if(np != NULL){ 2299103285Sikob next = np->db; 2300103285Sikob }else{ 2301103285Sikob next = NULL; 2302103285Sikob } 2303103285Sikob goto outdb; 2304103285Sikob } 2305103285Sikob } 2306103285Sikob pp = STAILQ_NEXT(pp, link); 2307103285Sikob prev = pp->db; 2308103285Sikob } 2309103285Sikoboutdb: 2310103285Sikob if( curr != NULL){ 2311113584Ssimokawa#if 0 2312103285Sikob printf("Prev DB %d\n", ch); 2313113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2314113584Ssimokawa#endif 2315103285Sikob printf("Current DB %d\n", ch); 2316113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2317113584Ssimokawa#if 0 2318103285Sikob printf("Next DB %d\n", ch); 2319113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2320113584Ssimokawa#endif 2321103285Sikob }else{ 2322103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2323103285Sikob } 2324103285Sikob return; 2325103285Sikob} 2326106790Ssimokawa 2327106790Ssimokawavoid 2328120660Ssimokawaprint_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2329113584Ssimokawa u_int32_t ch, u_int32_t max) 2330106790Ssimokawa{ 2331103285Sikob fwohcireg_t stat; 2332103285Sikob int i, key; 2333113584Ssimokawa u_int32_t cmd, res; 2334103285Sikob 2335103285Sikob if(db == NULL){ 2336103285Sikob printf("No Descriptor is found\n"); 2337103285Sikob return; 2338103285Sikob } 2339103285Sikob 2340103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2341103285Sikob ch, 2342103285Sikob "Current", 2343103285Sikob "OP ", 2344103285Sikob "KEY", 2345103285Sikob "INT", 2346103285Sikob "BR ", 2347103285Sikob "len", 2348103285Sikob "Addr", 2349103285Sikob "Depend", 2350103285Sikob "Stat", 2351103285Sikob "Cnt"); 2352103285Sikob for( i = 0 ; i <= max ; i ++){ 2353113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2354113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2355113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2356113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2357108712Ssimokawa#if __FreeBSD_version >= 500000 2358113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2359114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2360108712Ssimokawa#else 2361108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2362114142Ssimokawa db_tr->bus_addr, 2363108712Ssimokawa#endif 2364113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2365113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2366113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2367113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2368113584Ssimokawa cmd & OHCI_COUNT_MASK, 2369113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2370113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2371113584Ssimokawa stat, 2372113584Ssimokawa res & OHCI_COUNT_MASK); 2373103285Sikob if(stat & 0xff00){ 2374103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2375103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2376103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2377103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2378103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2379103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2380103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2381103285Sikob fwohcicode[stat & 0x1f], 2382103285Sikob stat & 0x1f 2383103285Sikob ); 2384103285Sikob }else{ 2385103285Sikob printf(" Nostat\n"); 2386103285Sikob } 2387103285Sikob if(key == OHCI_KEY_ST2 ){ 2388103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2389113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2390113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2391113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2392113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2393103285Sikob } 2394103285Sikob if(key == OHCI_KEY_DEVICE){ 2395103285Sikob return; 2396103285Sikob } 2397113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2398103285Sikob == OHCI_BRANCH_ALWAYS){ 2399103285Sikob return; 2400103285Sikob } 2401113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2402103285Sikob == OHCI_OUTPUT_LAST){ 2403103285Sikob return; 2404103285Sikob } 2405113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2406103285Sikob == OHCI_INPUT_LAST){ 2407103285Sikob return; 2408103285Sikob } 2409103285Sikob if(key == OHCI_KEY_ST2 ){ 2410103285Sikob i++; 2411103285Sikob } 2412103285Sikob } 2413103285Sikob return; 2414103285Sikob} 2415106790Ssimokawa 2416106790Ssimokawavoid 2417106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2418103285Sikob{ 2419103285Sikob struct fwohci_softc *sc; 2420103285Sikob u_int32_t fun; 2421103285Sikob 2422110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2423103285Sikob sc = (struct fwohci_softc *)fc; 2424108276Ssimokawa 2425108276Ssimokawa /* 2426108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2427108276Ssimokawa * shouldn't became the root node. 2428108276Ssimokawa */ 2429103285Sikob#if 1 2430103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2431109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2432103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2433109280Ssimokawa#else /* Short bus reset */ 2434103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2435109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2436103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2437103285Sikob#endif 2438103285Sikob} 2439106790Ssimokawa 2440106790Ssimokawavoid 2441106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2442103285Sikob{ 2443103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2444103285Sikob struct fwohci_dbch *dbch; 2445120660Ssimokawa struct fwohcidb *db; 2446103285Sikob struct fw_pkt *fp; 2447120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 2448103285Sikob unsigned short chtag; 2449103285Sikob int idb; 2450103285Sikob 2451103285Sikob dbch = &sc->it[dmach]; 2452103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2453103285Sikob 2454103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2455103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2456103285Sikob/* 2457113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2458103285Sikob*/ 2459113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2460109892Ssimokawa db = db_tr->db; 2461103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2462120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2463113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2464119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2465113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2466103285Sikob ohcifp->mode.stream.chtag = chtag; 2467103285Sikob ohcifp->mode.stream.tcode = 0xa; 2468113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2469113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2470113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2471113584Ssimokawa#endif 2472103285Sikob 2473113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2474113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2475113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2476109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2477113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2478103285Sikob | OHCI_UPDATE 2479109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2480109892Ssimokawa db[0].db.desc.depend = 2481109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2482113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2483109892Ssimokawa#else 2484113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2485113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2486109892Ssimokawa#endif 2487103285Sikob bulkxfer->end = (caddr_t)db_tr; 2488103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2489103285Sikob } 2490109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2491113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2492113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2493109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2494109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2495109280Ssimokawa /* OHCI 1.1 and above */ 2496109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2497109892Ssimokawa#endif 2498109892Ssimokawa/* 2499103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2500103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2501113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2502103285Sikob*/ 2503103285Sikob return; 2504103285Sikob} 2505106790Ssimokawa 2506106790Ssimokawastatic int 2507113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2508113584Ssimokawa int poffset) 2509103285Sikob{ 2510120660Ssimokawa struct fwohcidb *db = db_tr->db; 2511113584Ssimokawa struct fw_xferq *it; 2512103285Sikob int err = 0; 2513113584Ssimokawa 2514113584Ssimokawa it = &dbch->xferq; 2515113584Ssimokawa if(it->buf == 0){ 2516103285Sikob err = EINVAL; 2517103285Sikob return err; 2518103285Sikob } 2519113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2520103285Sikob db_tr->dbcnt = 3; 2521103285Sikob 2522113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2523113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2524119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2525120660Ssimokawa bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2526113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2527113584Ssimokawa fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2528113584Ssimokawa 2529113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2530113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2531109892Ssimokawa#if 1 2532113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2533113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2534109892Ssimokawa#endif 2535113584Ssimokawa return 0; 2536103285Sikob} 2537106790Ssimokawa 2538106790Ssimokawaint 2539113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2540113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2541103285Sikob{ 2542120660Ssimokawa struct fwohcidb *db = db_tr->db; 2543113584Ssimokawa struct fw_xferq *ir; 2544113584Ssimokawa int i, ldesc; 2545113584Ssimokawa bus_addr_t dbuf[2]; 2546103285Sikob int dsiz[2]; 2547103285Sikob 2548113584Ssimokawa ir = &dbch->xferq; 2549113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2550113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2551113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2552113584Ssimokawa if (db_tr->buf == NULL) 2553113584Ssimokawa return(ENOMEM); 2554103285Sikob db_tr->dbcnt = 1; 2555113584Ssimokawa dsiz[0] = ir->psize; 2556113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2557113584Ssimokawa BUS_DMASYNC_PREREAD); 2558113584Ssimokawa } else { 2559113584Ssimokawa db_tr->dbcnt = 0; 2560113584Ssimokawa if (dummy_dma != NULL) { 2561113584Ssimokawa dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2562113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2563113584Ssimokawa } 2564113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2565113584Ssimokawa if (ir->buf != NULL) { 2566113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2567113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2568113584Ssimokawa } 2569113584Ssimokawa db_tr->dbcnt++; 2570103285Sikob } 2571103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2572113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2573113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2574113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2575113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2576103285Sikob } 2577113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2578103285Sikob } 2579113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2580113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2581113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2582103285Sikob } 2583113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2584113584Ssimokawa return 0; 2585103285Sikob} 2586106790Ssimokawa 2587113584Ssimokawa 2588113584Ssimokawastatic int 2589113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2590103285Sikob{ 2591113584Ssimokawa struct fw_pkt *fp0; 2592113584Ssimokawa u_int32_t ld0; 2593120660Ssimokawa int slen, hlen; 2594113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2595113584Ssimokawa int i; 2596113584Ssimokawa#endif 2597103285Sikob 2598113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2599113584Ssimokawa#if 0 2600113584Ssimokawa printf("ld0: x%08x\n", ld0); 2601113584Ssimokawa#endif 2602113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2603120660Ssimokawa /* determine length to swap */ 2604113584Ssimokawa switch (fp0->mode.common.tcode) { 2605113584Ssimokawa case FWTCODE_RREQQ: 2606113584Ssimokawa case FWTCODE_WRES: 2607113584Ssimokawa case FWTCODE_WREQQ: 2608113584Ssimokawa case FWTCODE_RRESQ: 2609113584Ssimokawa case FWOHCITCODE_PHY: 2610113584Ssimokawa slen = 12; 2611113584Ssimokawa break; 2612113584Ssimokawa case FWTCODE_RREQB: 2613113584Ssimokawa case FWTCODE_WREQB: 2614113584Ssimokawa case FWTCODE_LREQ: 2615113584Ssimokawa case FWTCODE_RRESB: 2616113584Ssimokawa case FWTCODE_LRES: 2617113584Ssimokawa slen = 16; 2618113584Ssimokawa break; 2619113584Ssimokawa default: 2620113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2621113584Ssimokawa return(0); 2622103285Sikob } 2623120660Ssimokawa hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2624120660Ssimokawa if (hlen > len) { 2625113584Ssimokawa if (firewire_debug) 2626113584Ssimokawa printf("splitted header\n"); 2627120660Ssimokawa return(-hlen); 2628103285Sikob } 2629113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2630113584Ssimokawa for(i = 0; i < slen/4; i ++) 2631113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2632113584Ssimokawa#endif 2633120660Ssimokawa return(hlen); 2634103285Sikob} 2635103285Sikob 2636103285Sikobstatic int 2637113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2638103285Sikob{ 2639120660Ssimokawa struct tcode_info *info; 2640113584Ssimokawa int r; 2641103285Sikob 2642120660Ssimokawa info = &tinfo[fp->mode.common.tcode]; 2643120660Ssimokawa r = info->hdr_len + sizeof(u_int32_t); 2644120660Ssimokawa if ((info->flag & FWTI_BLOCK_ASY) != 0) 2645120660Ssimokawa r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); 2646120660Ssimokawa 2647120660Ssimokawa if (r == sizeof(u_int32_t)) 2648120660Ssimokawa /* XXX */ 2649110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2650110798Ssimokawa fp->mode.common.tcode); 2651120660Ssimokawa 2652110798Ssimokawa if (r > dbch->xferq.psize) { 2653110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2654110798Ssimokawa /* panic ? */ 2655110798Ssimokawa } 2656120660Ssimokawa 2657110798Ssimokawa return r; 2658103285Sikob} 2659103285Sikob 2660106790Ssimokawastatic void 2661113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2662113584Ssimokawa{ 2663120660Ssimokawa struct fwohcidb *db = &db_tr->db[0]; 2664113584Ssimokawa 2665113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2666113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2667113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2668113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2669113584Ssimokawa dbch->bottom = db_tr; 2670113584Ssimokawa} 2671113584Ssimokawa 2672113584Ssimokawastatic void 2673106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2674103285Sikob{ 2675103285Sikob struct fwohcidb_tr *db_tr; 2676113584Ssimokawa struct iovec vec[2]; 2677113584Ssimokawa struct fw_pkt pktbuf; 2678113584Ssimokawa int nvec; 2679103285Sikob struct fw_pkt *fp; 2680103285Sikob u_int8_t *ld; 2681113584Ssimokawa u_int32_t stat, off, status; 2682103285Sikob u_int spd; 2683113584Ssimokawa int len, plen, hlen, pcnt, offset; 2684103285Sikob int s; 2685103285Sikob caddr_t buf; 2686103285Sikob int resCount; 2687103285Sikob 2688103285Sikob if(&sc->arrq == dbch){ 2689103285Sikob off = OHCI_ARQOFF; 2690103285Sikob }else if(&sc->arrs == dbch){ 2691103285Sikob off = OHCI_ARSOFF; 2692103285Sikob }else{ 2693103285Sikob return; 2694103285Sikob } 2695103285Sikob 2696103285Sikob s = splfw(); 2697103285Sikob db_tr = dbch->top; 2698103285Sikob pcnt = 0; 2699103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2700113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2701113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2702113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2703113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2704113584Ssimokawa#if 0 2705113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2706113584Ssimokawa#endif 2707113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2708113584Ssimokawa len = dbch->xferq.psize - resCount; 2709113584Ssimokawa ld = (u_int8_t *)db_tr->buf; 2710113584Ssimokawa if (dbch->pdb_tr == NULL) { 2711113584Ssimokawa len -= dbch->buf_offset; 2712113584Ssimokawa ld += dbch->buf_offset; 2713113584Ssimokawa } 2714113584Ssimokawa if (len > 0) 2715113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2716113584Ssimokawa BUS_DMASYNC_POSTREAD); 2717103285Sikob while (len > 0 ) { 2718106789Ssimokawa if (count >= 0 && count-- == 0) 2719106789Ssimokawa goto out; 2720113584Ssimokawa if(dbch->pdb_tr != NULL){ 2721113584Ssimokawa /* we have a fragment in previous buffer */ 2722113584Ssimokawa int rlen; 2723103285Sikob 2724113584Ssimokawa offset = dbch->buf_offset; 2725113584Ssimokawa if (offset < 0) 2726113584Ssimokawa offset = - offset; 2727113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2728113584Ssimokawa rlen = dbch->xferq.psize - offset; 2729113584Ssimokawa if (firewire_debug) 2730113584Ssimokawa printf("rlen=%d, offset=%d\n", 2731113584Ssimokawa rlen, dbch->buf_offset); 2732113584Ssimokawa if (dbch->buf_offset < 0) { 2733113584Ssimokawa /* splitted in header, pull up */ 2734113584Ssimokawa char *p; 2735113584Ssimokawa 2736113584Ssimokawa p = (char *)&pktbuf; 2737113584Ssimokawa bcopy(buf, p, rlen); 2738113584Ssimokawa p += rlen; 2739113584Ssimokawa /* this must be too long but harmless */ 2740113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2741113584Ssimokawa if (rlen < 0) 2742113584Ssimokawa printf("why rlen < 0\n"); 2743113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2744103285Sikob ld += rlen; 2745103285Sikob len -= rlen; 2746113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2747113584Ssimokawa if (hlen < 0) { 2748113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2749113584Ssimokawa } 2750113584Ssimokawa offset = sizeof(pktbuf); 2751113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2752113584Ssimokawa vec[0].iov_len = offset; 2753113584Ssimokawa } else { 2754113584Ssimokawa /* splitted in payload */ 2755113584Ssimokawa offset = rlen; 2756113584Ssimokawa vec[0].iov_base = buf; 2757113584Ssimokawa vec[0].iov_len = rlen; 2758103285Sikob } 2759113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2760113584Ssimokawa nvec = 1; 2761113584Ssimokawa } else { 2762113584Ssimokawa /* no fragment in previous buffer */ 2763103285Sikob fp=(struct fw_pkt *)ld; 2764113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2765113584Ssimokawa if (hlen == 0) 2766113584Ssimokawa /* XXX need reset */ 2767103285Sikob goto out; 2768113584Ssimokawa if (hlen < 0) { 2769113584Ssimokawa dbch->pdb_tr = db_tr; 2770113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2771113584Ssimokawa /* sanity check */ 2772113584Ssimokawa if (resCount != 0) 2773113584Ssimokawa printf("resCount != 0 !?\n"); 2774113584Ssimokawa goto out; 2775103285Sikob } 2776113584Ssimokawa offset = 0; 2777113584Ssimokawa nvec = 0; 2778113584Ssimokawa } 2779113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2780113584Ssimokawa if (plen < 0) { 2781113584Ssimokawa /* minimum header size + trailer 2782113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2783120660Ssimokawa printf("plen(%d) is negative! offset=%d\n", 2784120660Ssimokawa plen, offset); 2785113584Ssimokawa goto out; 2786113584Ssimokawa } 2787113584Ssimokawa if (plen > 0) { 2788113584Ssimokawa len -= plen; 2789113584Ssimokawa if (len < 0) { 2790113584Ssimokawa dbch->pdb_tr = db_tr; 2791113584Ssimokawa if (firewire_debug) 2792113584Ssimokawa printf("splitted payload\n"); 2793113584Ssimokawa /* sanity check */ 2794113584Ssimokawa if (resCount != 0) 2795113584Ssimokawa printf("resCount != 0 !?\n"); 2796113584Ssimokawa goto out; 2797103285Sikob } 2798113584Ssimokawa vec[nvec].iov_base = ld; 2799113584Ssimokawa vec[nvec].iov_len = plen; 2800113584Ssimokawa nvec ++; 2801103285Sikob ld += plen; 2802103285Sikob } 2803113584Ssimokawa dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2804113584Ssimokawa if (nvec == 0) 2805113584Ssimokawa printf("nvec == 0\n"); 2806113584Ssimokawa 2807103285Sikob/* DMA result-code will be written at the tail of packet */ 2808113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2809113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2810113584Ssimokawa#else 2811113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2812113584Ssimokawa#endif 2813110577Ssimokawa#if 0 2814120660Ssimokawa printf("plen: %d, stat %x\n", 2815120660Ssimokawa plen ,stat); 2816103285Sikob#endif 2817113584Ssimokawa spd = (stat >> 5) & 0x3; 2818113584Ssimokawa stat &= 0x1f; 2819113584Ssimokawa switch(stat){ 2820113584Ssimokawa case FWOHCIEV_ACKPEND: 2821113584Ssimokawa#if 0 2822113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2823113584Ssimokawa#endif 2824113584Ssimokawa /* fall through */ 2825113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2826120660Ssimokawa { 2827120660Ssimokawa struct fw_rcv_buf rb; 2828120660Ssimokawa 2829113584Ssimokawa if ((vec[nvec-1].iov_len -= 2830113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2831113584Ssimokawa nvec--; 2832120660Ssimokawa rb.fc = &sc->fc; 2833120660Ssimokawa rb.vec = vec; 2834120660Ssimokawa rb.nvec = nvec; 2835120660Ssimokawa rb.spd = spd; 2836120660Ssimokawa fw_rcv(&rb); 2837120660Ssimokawa break; 2838120660Ssimokawa } 2839113584Ssimokawa case FWOHCIEV_BUSRST: 2840113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2841113584Ssimokawa printf("got BUSRST packet!?\n"); 2842113584Ssimokawa break; 2843113584Ssimokawa default: 2844113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2845103285Sikob#if 0 /* XXX */ 2846113584Ssimokawa goto out; 2847103285Sikob#endif 2848113584Ssimokawa break; 2849103285Sikob } 2850103285Sikob pcnt ++; 2851113584Ssimokawa if (dbch->pdb_tr != NULL) { 2852113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2853113584Ssimokawa dbch->pdb_tr = NULL; 2854113584Ssimokawa } 2855113584Ssimokawa 2856113584Ssimokawa } 2857103285Sikobout: 2858103285Sikob if (resCount == 0) { 2859103285Sikob /* done on this buffer */ 2860113584Ssimokawa if (dbch->pdb_tr == NULL) { 2861113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2862113584Ssimokawa dbch->buf_offset = 0; 2863113584Ssimokawa } else 2864113584Ssimokawa if (dbch->pdb_tr != db_tr) 2865113584Ssimokawa printf("pdb_tr != db_tr\n"); 2866103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2867113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2868113584Ssimokawa >> OHCI_STATUS_SHIFT; 2869113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2870113584Ssimokawa & OHCI_COUNT_MASK; 2871113584Ssimokawa /* XXX check buffer overrun */ 2872103285Sikob dbch->top = db_tr; 2873103285Sikob } else { 2874103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2875103285Sikob break; 2876103285Sikob } 2877103285Sikob /* XXX make sure DMA is not dead */ 2878103285Sikob } 2879103285Sikob#if 0 2880103285Sikob if (pcnt < 1) 2881103285Sikob printf("fwohci_arcv: no packets\n"); 2882103285Sikob#endif 2883103285Sikob splx(s); 2884103285Sikob} 2885