fwohci.c revision 119289
1103285Sikob/* 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 119289 2003-08-22 07:30:41Z simokawa $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50103285Sikob#include <sys/bus.h> 51103285Sikob#include <sys/kernel.h> 52103285Sikob#include <sys/conf.h> 53113584Ssimokawa#include <sys/endian.h> 54103285Sikob 55103285Sikob#include <machine/bus.h> 56103285Sikob 57117067Ssimokawa#if __FreeBSD_version < 500000 58117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 59117067Ssimokawa#endif 60117067Ssimokawa 61103285Sikob#include <dev/firewire/firewire.h> 62103285Sikob#include <dev/firewire/firewirereg.h> 63113584Ssimokawa#include <dev/firewire/fwdma.h> 64103285Sikob#include <dev/firewire/fwohcireg.h> 65103285Sikob#include <dev/firewire/fwohcivar.h> 66103285Sikob#include <dev/firewire/firewire_phy.h> 67103285Sikob 68103285Sikob#undef OHCI_DEBUG 69106802Ssimokawa 70103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71103285Sikob "STOR","LOAD","NOP ","STOP",}; 72113584Ssimokawa 73103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74103285Sikob "UNDEF","REG","SYS","DEV"}; 75113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76103285Sikobchar fwohcicode[32][0x20]={ 77103285Sikob "No stat","Undef","long","miss Ack err", 78103285Sikob "underrun","overrun","desc err", "data read err", 79103285Sikob "data write err","bus reset","timeout","tcode err", 80103285Sikob "Undef","Undef","unknown event","flushed", 81103285Sikob "Undef","ack complete","ack pend","Undef", 82103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 83103285Sikob "Undef","Undef","Undef","ack tardy", 84103285Sikob "Undef","ack data_err","ack type_err",""}; 85113584Ssimokawa 86116376Ssimokawa#define MAX_SPEED 3 87116376Ssimokawaextern char linkspeed[][0x10]; 88103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89103285Sikob 90103285Sikobstatic struct tcode_info tinfo[] = { 91103285Sikob/* hdr_len block flag*/ 92103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94103285Sikob/* 2 WRES */ {12, FWTI_RES}, 95103285Sikob/* 3 XXX */ { 0, 0}, 96103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 99103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100103285Sikob/* 8 CYCS */ { 0, 0}, 101103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104103285Sikob/* c XXX */ { 0, 0}, 105103285Sikob/* d XXX */ { 0, 0}, 106103285Sikob/* e PHY */ {12, FWTI_REQ}, 107103285Sikob/* f XXX */ { 0, 0} 108103285Sikob}; 109103285Sikob 110103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 111103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 112103285Sikob 113103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115103285Sikob 116103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 117113584Ssimokawastatic void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 119106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 122103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 123103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 129103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 130113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 131103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132113584Ssimokawa#endif 133103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 135103285Sikobstatic void fwohci_timeout __P((void *)); 136103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 137113584Ssimokawa 138113584Ssimokawastatic int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139113584Ssimokawastatic int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 141113584Ssimokawastatic void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147113584Ssimokawa#if FWOHCI_TASKQUEUE 148113584Ssimokawastatic void fwohci_complete(void *, int); 149113584Ssimokawa#endif 150103285Sikob 151103285Sikob/* 152103285Sikob * memory allocated for DMA programs 153103285Sikob */ 154103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155103285Sikob 156103285Sikob#define NDB FWMAXQUEUE 157103285Sikob 158103285Sikob#define OHCI_VERSION 0x00 159112523Ssimokawa#define OHCI_ATRETRY 0x08 160103285Sikob#define OHCI_CROMHDR 0x18 161103285Sikob#define OHCI_BUS_OPT 0x20 162103285Sikob#define OHCI_BUSIRMC (1 << 31) 163103285Sikob#define OHCI_BUSCMC (1 << 30) 164103285Sikob#define OHCI_BUSISC (1 << 29) 165103285Sikob#define OHCI_BUSBMC (1 << 28) 166103285Sikob#define OHCI_BUSPMC (1 << 27) 167103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 168103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 169103285Sikob 170103285Sikob#define OHCI_EUID_HI 0x24 171103285Sikob#define OHCI_EUID_LO 0x28 172103285Sikob 173103285Sikob#define OHCI_CROMPTR 0x34 174103285Sikob#define OHCI_HCCCTL 0x50 175103285Sikob#define OHCI_HCCCTLCLR 0x54 176103285Sikob#define OHCI_AREQHI 0x100 177103285Sikob#define OHCI_AREQHICLR 0x104 178103285Sikob#define OHCI_AREQLO 0x108 179103285Sikob#define OHCI_AREQLOCLR 0x10c 180103285Sikob#define OHCI_PREQHI 0x110 181103285Sikob#define OHCI_PREQHICLR 0x114 182103285Sikob#define OHCI_PREQLO 0x118 183103285Sikob#define OHCI_PREQLOCLR 0x11c 184103285Sikob#define OHCI_PREQUPPER 0x120 185103285Sikob 186103285Sikob#define OHCI_SID_BUF 0x64 187103285Sikob#define OHCI_SID_CNT 0x68 188113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 189103285Sikob#define OHCI_SID_CNT_MASK 0xffc 190103285Sikob 191103285Sikob#define OHCI_IT_STAT 0x90 192103285Sikob#define OHCI_IT_STATCLR 0x94 193103285Sikob#define OHCI_IT_MASK 0x98 194103285Sikob#define OHCI_IT_MASKCLR 0x9c 195103285Sikob 196103285Sikob#define OHCI_IR_STAT 0xa0 197103285Sikob#define OHCI_IR_STATCLR 0xa4 198103285Sikob#define OHCI_IR_MASK 0xa8 199103285Sikob#define OHCI_IR_MASKCLR 0xac 200103285Sikob 201103285Sikob#define OHCI_LNKCTL 0xe0 202103285Sikob#define OHCI_LNKCTLCLR 0xe4 203103285Sikob 204103285Sikob#define OHCI_PHYACCESS 0xec 205103285Sikob#define OHCI_CYCLETIMER 0xf0 206103285Sikob 207103285Sikob#define OHCI_DMACTL(off) (off) 208103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 209103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 210103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 211103285Sikob 212103285Sikob#define OHCI_ATQOFF 0x180 213103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 214103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 215103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 216103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 217103285Sikob 218103285Sikob#define OHCI_ATSOFF 0x1a0 219103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 220103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 221103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 222103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 223103285Sikob 224103285Sikob#define OHCI_ARQOFF 0x1c0 225103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 226103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 227103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 228103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 229103285Sikob 230103285Sikob#define OHCI_ARSOFF 0x1e0 231103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 232103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 233103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 234103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 235103285Sikob 236103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 237103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 238103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 239103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 240103285Sikob 241103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 242103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 243103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 244103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 245103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 246103285Sikob 247103285Sikobd_ioctl_t fwohci_ioctl; 248103285Sikob 249103285Sikob/* 250103285Sikob * Communication with PHY device 251103285Sikob */ 252106790Ssimokawastatic u_int32_t 253106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 254103285Sikob{ 255103285Sikob u_int32_t fun; 256103285Sikob 257103285Sikob addr &= 0xf; 258103285Sikob data &= 0xff; 259103285Sikob 260103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 261103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 262103285Sikob DELAY(100); 263103285Sikob 264103285Sikob return(fwphy_rddata( sc, addr)); 265103285Sikob} 266103285Sikob 267103285Sikobstatic u_int32_t 268103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 269103285Sikob{ 270103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 271103285Sikob int i; 272103285Sikob u_int32_t bm; 273103285Sikob 274103285Sikob#define OHCI_CSR_DATA 0x0c 275103285Sikob#define OHCI_CSR_COMP 0x10 276103285Sikob#define OHCI_CSR_CONT 0x14 277103285Sikob#define OHCI_BUS_MANAGER_ID 0 278103285Sikob 279103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 280103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 281103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 282103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 283109280Ssimokawa DELAY(10); 284103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 285107653Ssimokawa if((bm & 0x3f) == 0x3f) 286103285Sikob bm = node; 287107653Ssimokawa if (bootverbose) 288107653Ssimokawa device_printf(sc->fc.dev, 289107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 290103285Sikob 291103285Sikob return(bm); 292103285Sikob} 293103285Sikob 294106790Ssimokawastatic u_int32_t 295106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 296103285Sikob{ 297108500Ssimokawa u_int32_t fun, stat; 298108500Ssimokawa u_int i, retry = 0; 299103285Sikob 300103285Sikob addr &= 0xf; 301108500Ssimokawa#define MAX_RETRY 100 302108500Ssimokawaagain: 303108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 304103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 305103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 306108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 307103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 308103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 309103285Sikob break; 310109280Ssimokawa DELAY(100); 311103285Sikob } 312108500Ssimokawa if(i >= MAX_RETRY) { 313109280Ssimokawa if (bootverbose) 314109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 315108527Ssimokawa if (++retry < MAX_RETRY) { 316109280Ssimokawa DELAY(100); 317108527Ssimokawa goto again; 318108527Ssimokawa } 319108500Ssimokawa } 320108500Ssimokawa /* Make sure that SCLK is started */ 321108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 322108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 323108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 324109280Ssimokawa if (bootverbose) 325109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 326108500Ssimokawa if (++retry < MAX_RETRY) { 327109280Ssimokawa DELAY(100); 328108500Ssimokawa goto again; 329108500Ssimokawa } 330108500Ssimokawa } 331108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 332108500Ssimokawa device_printf(sc->fc.dev, 333119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 334108500Ssimokawa#undef MAX_RETRY 335103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 336103285Sikob} 337103285Sikob/* Device specific ioctl. */ 338103285Sikobint 339103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 340103285Sikob{ 341103285Sikob struct firewire_softc *sc; 342103285Sikob struct fwohci_softc *fc; 343103285Sikob int unit = DEV2UNIT(dev); 344103285Sikob int err = 0; 345103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 346103285Sikob u_int32_t *dmach = (u_int32_t *) data; 347103285Sikob 348103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 349103285Sikob if(sc == NULL){ 350103285Sikob return(EINVAL); 351103285Sikob } 352103285Sikob fc = (struct fwohci_softc *)sc->fc; 353103285Sikob 354103285Sikob if (!data) 355103285Sikob return(EINVAL); 356103285Sikob 357103285Sikob switch (cmd) { 358103285Sikob case FWOHCI_WRREG: 359103285Sikob#define OHCI_MAX_REG 0x800 360103285Sikob if(reg->addr <= OHCI_MAX_REG){ 361103285Sikob OWRITE(fc, reg->addr, reg->data); 362103285Sikob reg->data = OREAD(fc, reg->addr); 363103285Sikob }else{ 364103285Sikob err = EINVAL; 365103285Sikob } 366103285Sikob break; 367103285Sikob case FWOHCI_RDREG: 368103285Sikob if(reg->addr <= OHCI_MAX_REG){ 369103285Sikob reg->data = OREAD(fc, reg->addr); 370103285Sikob }else{ 371103285Sikob err = EINVAL; 372103285Sikob } 373103285Sikob break; 374103285Sikob/* Read DMA descriptors for debug */ 375103285Sikob case DUMPDMA: 376103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 377103285Sikob dump_dma(fc, *dmach); 378103285Sikob dump_db(fc, *dmach); 379103285Sikob }else{ 380103285Sikob err = EINVAL; 381103285Sikob } 382103285Sikob break; 383119118Ssimokawa/* Read/Write Phy registers */ 384119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 385119118Ssimokawa case FWOHCI_RDPHYREG: 386119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 387119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 388119118Ssimokawa else 389119118Ssimokawa err = EINVAL; 390119118Ssimokawa break; 391119118Ssimokawa case FWOHCI_WRPHYREG: 392119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 393119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 394119118Ssimokawa else 395119118Ssimokawa err = EINVAL; 396119118Ssimokawa break; 397103285Sikob default: 398119118Ssimokawa err = EINVAL; 399103285Sikob break; 400103285Sikob } 401103285Sikob return err; 402103285Sikob} 403106790Ssimokawa 404108530Ssimokawastatic int 405108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406103285Sikob{ 407108530Ssimokawa u_int32_t reg, reg2; 408108530Ssimokawa int e1394a = 1; 409108530Ssimokawa/* 410108530Ssimokawa * probe PHY parameters 411108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 412108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 413108530Ssimokawa * number of port supported by core-logic. 414108530Ssimokawa * It is not actually available port on your PC . 415108530Ssimokawa */ 416108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa device_printf(dev, 429108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 430108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 431108530Ssimokawa }else{ 432108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433108530Ssimokawa sc->fc.mode |= FWPHYASYST; 434108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 435108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 437108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 438108530Ssimokawa sc->fc.speed, MAX_SPEED); 439108530Ssimokawa sc->fc.speed = MAX_SPEED; 440108530Ssimokawa } 441108530Ssimokawa device_printf(dev, 442108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 443108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 444108530Ssimokawa 445108530Ssimokawa /* check programPhyEnable */ 446108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 447108530Ssimokawa#if 0 448108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449108530Ssimokawa#else /* XXX force to enable 1394a */ 450108530Ssimokawa if (e1394a) { 451108530Ssimokawa#endif 452108530Ssimokawa if (bootverbose) 453108530Ssimokawa device_printf(dev, 454108530Ssimokawa "Enable 1394a Enhancements\n"); 455108530Ssimokawa /* enable EAA EMC */ 456108530Ssimokawa reg2 |= 0x03; 457108530Ssimokawa /* set aPhyEnhanceEnable */ 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460108530Ssimokawa } else { 461108530Ssimokawa /* for safe */ 462108530Ssimokawa reg2 &= ~0x83; 463108530Ssimokawa } 464108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 465108530Ssimokawa } 466108530Ssimokawa 467108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468108530Ssimokawa if((reg >> 5) == 7 ){ 469108530Ssimokawa reg = fwphy_rddata(sc, 4); 470108530Ssimokawa reg |= 1 << 6; 471108530Ssimokawa fwphy_wrdata(sc, 4, reg); 472108530Ssimokawa reg = fwphy_rddata(sc, 4); 473108530Ssimokawa } 474108530Ssimokawa return 0; 475108530Ssimokawa} 476108530Ssimokawa 477108530Ssimokawa 478108530Ssimokawavoid 479108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 480108530Ssimokawa{ 481108701Ssimokawa int i, max_rec, speed; 482103285Sikob u_int32_t reg, reg2; 483103285Sikob struct fwohcidb_tr *db_tr; 484103285Sikob 485108701Ssimokawa /* Disable interrupt */ 486108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487108530Ssimokawa 488108701Ssimokawa /* Now stopping all DMA channel */ 489108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa 494108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa } 499108530Ssimokawa 500108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 501108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502108530Ssimokawa if (bootverbose) 503108530Ssimokawa device_printf(dev, "resetting OHCI..."); 504108530Ssimokawa i = 0; 505108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506108530Ssimokawa if (i++ > 100) break; 507108530Ssimokawa DELAY(1000); 508108530Ssimokawa } 509108530Ssimokawa if (bootverbose) 510108530Ssimokawa printf("done (loop=%d)\n", i); 511108530Ssimokawa 512108701Ssimokawa /* Probe phy */ 513108701Ssimokawa fwohci_probe_phy(sc, dev); 514108701Ssimokawa 515108701Ssimokawa /* Probe link */ 516108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 517108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 518108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 519108701Ssimokawa speed = (reg & 0x00000007); 520108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 521108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 522108701Ssimokawa /* XXX fix max_rec */ 523108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 524108701Ssimokawa if (max_rec != sc->fc.maxrec) { 525108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 527108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528108701Ssimokawa } 529108530Ssimokawa if (bootverbose) 530108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 532108530Ssimokawa 533108701Ssimokawa /* Initialize registers */ 534108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540108701Ssimokawa fw_busreset(&sc->fc); 541108530Ssimokawa 542108701Ssimokawa /* Enable link */ 543108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544108642Ssimokawa 545108701Ssimokawa /* Force to start async RX DMA */ 546108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 550108530Ssimokawa 551108701Ssimokawa /* Initialize async TX */ 552108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554116978Ssimokawa 555108701Ssimokawa /* AT Retries */ 556108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 557108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559116978Ssimokawa 560116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 563116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 564116978Ssimokawa 565108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567108530Ssimokawa db_tr->xfer = NULL; 568108530Ssimokawa } 569108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571108530Ssimokawa db_tr->xfer = NULL; 572108530Ssimokawa } 573108530Ssimokawa 574108701Ssimokawa 575108701Ssimokawa /* Enable interrupt */ 576108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 577108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 578108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 582108530Ssimokawa 583108530Ssimokawa} 584108530Ssimokawa 585108530Ssimokawaint 586108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 587108530Ssimokawa{ 588108530Ssimokawa int i; 589108530Ssimokawa u_int32_t reg; 590109814Ssimokawa u_int8_t ui[8]; 591108530Ssimokawa 592113584Ssimokawa#if FWOHCI_TASKQUEUE 593113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594113584Ssimokawa#endif 595113584Ssimokawa 596103285Sikob reg = OREAD(sc, OHCI_VERSION); 597103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 598103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 599103285Sikob 600118416Ssimokawa if (((reg>>16) & 0xff) < 1) { 601118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 602118416Ssimokawa return (ENXIO); 603118416Ssimokawa } 604118416Ssimokawa 605110045Ssimokawa/* Available Isochrounous DMA channel probe */ 606110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 607110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 608110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 609110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 610110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 611110045Ssimokawa for (i = 0; i < 0x20; i++) 612110045Ssimokawa if ((reg & (1 << i)) == 0) 613110045Ssimokawa break; 614103285Sikob sc->fc.nisodma = i; 615103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 616118820Ssimokawa if (i == 0) 617118820Ssimokawa return (ENXIO); 618103285Sikob 619103285Sikob sc->fc.arq = &sc->arrq.xferq; 620103285Sikob sc->fc.ars = &sc->arrs.xferq; 621103285Sikob sc->fc.atq = &sc->atrq.xferq; 622103285Sikob sc->fc.ats = &sc->atrs.xferq; 623103285Sikob 624113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 625113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 626113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628113584Ssimokawa 629103285Sikob sc->arrq.xferq.start = NULL; 630103285Sikob sc->arrs.xferq.start = NULL; 631103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 632103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 633103285Sikob 634113584Ssimokawa sc->arrq.xferq.buf = NULL; 635113584Ssimokawa sc->arrs.xferq.buf = NULL; 636113584Ssimokawa sc->atrq.xferq.buf = NULL; 637113584Ssimokawa sc->atrs.xferq.buf = NULL; 638103285Sikob 639118293Ssimokawa sc->arrq.xferq.dmach = -1; 640118293Ssimokawa sc->arrs.xferq.dmach = -1; 641118293Ssimokawa sc->atrq.xferq.dmach = -1; 642118293Ssimokawa sc->atrs.xferq.dmach = -1; 643118293Ssimokawa 644103285Sikob sc->arrq.ndesc = 1; 645103285Sikob sc->arrs.ndesc = 1; 646110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 647110593Ssimokawa sc->atrs.ndesc = 2; 648103285Sikob 649103285Sikob sc->arrq.ndb = NDB; 650103285Sikob sc->arrs.ndb = NDB / 2; 651103285Sikob sc->atrq.ndb = NDB; 652103285Sikob sc->atrs.ndb = NDB / 2; 653103285Sikob 654103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 655103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 656103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 657118293Ssimokawa sc->it[i].xferq.dmach = i; 658118293Ssimokawa sc->ir[i].xferq.dmach = i; 659103285Sikob sc->it[i].ndb = 0; 660103285Sikob sc->ir[i].ndb = 0; 661103285Sikob } 662103285Sikob 663103285Sikob sc->fc.tcode = tinfo; 664113584Ssimokawa sc->fc.dev = dev; 665103285Sikob 666113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 667113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 668113584Ssimokawa if(sc->fc.config_rom == NULL){ 669113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 670103285Sikob return ENOMEM; 671103285Sikob } 672103285Sikob 673116376Ssimokawa#if 0 674116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 675103285Sikob sc->fc.config_rom[1] = 0x31333934; 676103285Sikob sc->fc.config_rom[2] = 0xf000a002; 677103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 678103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 679103285Sikob sc->fc.config_rom[5] = 0; 680103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 681103285Sikob 682103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 683113584Ssimokawa#endif 684103285Sikob 685103285Sikob 686103285Sikob/* SID recieve buffer must allign 2^11 */ 687103285Sikob#define OHCI_SIDSIZE (1 << 11) 688113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 689113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 690113584Ssimokawa if (sc->sid_buf == NULL) { 691113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 692108527Ssimokawa return ENOMEM; 693108527Ssimokawa } 694113584Ssimokawa 695113584Ssimokawa fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 696113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 697113584Ssimokawa 698113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 699113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 700109736Ssimokawa return ENOMEM; 701109736Ssimokawa } 702113584Ssimokawa 703113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 704108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 705108527Ssimokawa return ENOMEM; 706108527Ssimokawa 707113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 708108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 709108527Ssimokawa return ENOMEM; 710103285Sikob 711113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 712108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 713108527Ssimokawa return ENOMEM; 714108527Ssimokawa 715113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 716108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 717108527Ssimokawa return ENOMEM; 718103285Sikob 719109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 720109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 721109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 722109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 723103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 724109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 725109814Ssimokawa 726103285Sikob sc->fc.ioctl = fwohci_ioctl; 727103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 728103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 729103285Sikob sc->fc.ibr = fwohci_ibr; 730103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 731103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 732103285Sikob 733103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 734103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 735113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 736103285Sikob sc->fc.irx_post = fwohci_irx_post; 737113584Ssimokawa#else 738113584Ssimokawa sc->fc.irx_post = NULL; 739113584Ssimokawa#endif 740103285Sikob sc->fc.itx_post = NULL; 741103285Sikob sc->fc.timeout = fwohci_timeout; 742103285Sikob sc->fc.poll = fwohci_poll; 743103285Sikob sc->fc.set_intr = fwohci_set_intr; 744106790Ssimokawa 745113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 746113584Ssimokawa 747108530Ssimokawa fw_init(&sc->fc); 748108530Ssimokawa fwohci_reset(sc, dev); 749103285Sikob 750108530Ssimokawa return 0; 751103285Sikob} 752106790Ssimokawa 753106790Ssimokawavoid 754106790Ssimokawafwohci_timeout(void *arg) 755103285Sikob{ 756103285Sikob struct fwohci_softc *sc; 757103285Sikob 758103285Sikob sc = (struct fwohci_softc *)arg; 759103285Sikob} 760106790Ssimokawa 761106790Ssimokawau_int32_t 762106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 763103285Sikob{ 764103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 765103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 766103285Sikob} 767103285Sikob 768108527Ssimokawaint 769108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 770108527Ssimokawa{ 771108527Ssimokawa int i; 772108527Ssimokawa 773113584Ssimokawa if (sc->sid_buf != NULL) 774113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 775113584Ssimokawa if (sc->fc.config_rom != NULL) 776113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 777108527Ssimokawa 778108527Ssimokawa fwohci_db_free(&sc->arrq); 779108527Ssimokawa fwohci_db_free(&sc->arrs); 780108527Ssimokawa 781108527Ssimokawa fwohci_db_free(&sc->atrq); 782108527Ssimokawa fwohci_db_free(&sc->atrs); 783108527Ssimokawa 784108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 785108527Ssimokawa fwohci_db_free(&sc->it[i]); 786108527Ssimokawa fwohci_db_free(&sc->ir[i]); 787108527Ssimokawa } 788108527Ssimokawa 789108527Ssimokawa return 0; 790108527Ssimokawa} 791108527Ssimokawa 792108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 793108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 794108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 795108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 796108655Ssimokawa} while (0) 797108655Ssimokawa 798106790Ssimokawastatic void 799113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 800113584Ssimokawa{ 801113584Ssimokawa struct fwohcidb_tr *db_tr; 802113584Ssimokawa volatile struct fwohcidb *db; 803113584Ssimokawa bus_dma_segment_t *s; 804113584Ssimokawa int i; 805113584Ssimokawa 806113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 807113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 808113584Ssimokawa if (error) { 809113584Ssimokawa if (firewire_debug || error != EFBIG) 810113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 811113584Ssimokawa return; 812113584Ssimokawa } 813113584Ssimokawa for (i = 0; i < nseg; i++) { 814113584Ssimokawa s = &segs[i]; 815113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 816113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 817113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 818113584Ssimokawa db++; 819113584Ssimokawa db_tr->dbcnt++; 820113584Ssimokawa } 821113584Ssimokawa} 822113584Ssimokawa 823113584Ssimokawastatic void 824113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 825113584Ssimokawa bus_size_t size, int error) 826113584Ssimokawa{ 827113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 828113584Ssimokawa} 829113584Ssimokawa 830113584Ssimokawastatic void 831106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 832103285Sikob{ 833103285Sikob int i, s; 834113584Ssimokawa int tcode, hdr_len, pl_off, pl_len; 835103285Sikob int fsegment = -1; 836103285Sikob u_int32_t off; 837103285Sikob struct fw_xfer *xfer; 838103285Sikob struct fw_pkt *fp; 839103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 840103285Sikob struct fwohcidb_tr *db_tr; 841103285Sikob volatile struct fwohcidb *db; 842119155Ssimokawa volatile u_int32_t *ld; 843103285Sikob struct tcode_info *info; 844108655Ssimokawa static int maxdesc=0; 845103285Sikob 846103285Sikob if(&sc->atrq == dbch){ 847103285Sikob off = OHCI_ATQOFF; 848103285Sikob }else if(&sc->atrs == dbch){ 849103285Sikob off = OHCI_ATSOFF; 850103285Sikob }else{ 851103285Sikob return; 852103285Sikob } 853103285Sikob 854103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 855103285Sikob return; 856103285Sikob 857103285Sikob s = splfw(); 858103285Sikob db_tr = dbch->top; 859103285Sikobtxloop: 860103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 861103285Sikob if(xfer == NULL){ 862103285Sikob goto kick; 863103285Sikob } 864103285Sikob if(dbch->xferq.queued == 0 ){ 865103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 866103285Sikob } 867103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 868103285Sikob db_tr->xfer = xfer; 869103285Sikob xfer->state = FWXF_START; 870103285Sikob 871113584Ssimokawa fp = (struct fw_pkt *)xfer->send.buf; 872103285Sikob tcode = fp->mode.common.tcode; 873103285Sikob 874103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 875103285Sikob info = &tinfo[tcode]; 876113584Ssimokawa hdr_len = pl_off = info->hdr_len; 877119155Ssimokawa 878119155Ssimokawa ld = &ohcifp->mode.ld[0]; 879119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 880119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 881119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 882119155Ssimokawa 883119155Ssimokawa ohcifp->mode.common.spd = xfer->spd & 0x7; 884103285Sikob if (tcode == FWTCODE_STREAM ){ 885103285Sikob hdr_len = 8; 886113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 887103285Sikob } else if (tcode == FWTCODE_PHY) { 888103285Sikob hdr_len = 12; 889119155Ssimokawa ld[1] = fp->mode.ld[1]; 890119155Ssimokawa ld[2] = fp->mode.ld[2]; 891103285Sikob ohcifp->mode.common.spd = 0; 892103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 893103285Sikob } else { 894113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 895103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 896103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 897103285Sikob } 898103285Sikob db = &db_tr->db[0]; 899113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 900113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 901119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 902113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 903103285Sikob/* Specify bound timer of asy. responce */ 904103285Sikob if(&sc->atrs == dbch){ 905113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 906113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 907103285Sikob } 908113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 909113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 910113584Ssimokawa hdr_len = 12; 911113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 912119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 913113584Ssimokawa#endif 914103285Sikob 915111942Ssimokawaagain: 916103285Sikob db_tr->dbcnt = 2; 917103285Sikob db = &db_tr->db[db_tr->dbcnt]; 918113584Ssimokawa pl_len = xfer->send.len - pl_off; 919113584Ssimokawa if (pl_len > 0) { 920113584Ssimokawa int err; 921113584Ssimokawa /* handle payload */ 922103285Sikob if (xfer->mbuf == NULL) { 923113584Ssimokawa caddr_t pl_addr; 924103285Sikob 925113584Ssimokawa pl_addr = xfer->send.buf + pl_off; 926113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 927113584Ssimokawa pl_addr, pl_len, 928113584Ssimokawa fwohci_execute_db, db_tr, 929113584Ssimokawa /*flags*/0); 930103285Sikob } else { 931111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 932113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 933113584Ssimokawa xfer->mbuf, 934113584Ssimokawa fwohci_execute_db2, db_tr, 935113584Ssimokawa /* flags */0); 936113584Ssimokawa if (err == EFBIG) { 937113584Ssimokawa struct mbuf *m0; 938113584Ssimokawa 939113584Ssimokawa if (firewire_debug) 940113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 941113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 942113584Ssimokawa if (m0 != NULL) { 943111942Ssimokawa m_copydata(xfer->mbuf, 0, 944111942Ssimokawa xfer->mbuf->m_pkthdr.len, 945113584Ssimokawa mtod(m0, caddr_t)); 946113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 947111942Ssimokawa xfer->mbuf->m_pkthdr.len; 948111942Ssimokawa m_freem(xfer->mbuf); 949113584Ssimokawa xfer->mbuf = m0; 950111942Ssimokawa goto again; 951111942Ssimokawa } 952111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 953111942Ssimokawa } 954103285Sikob } 955113584Ssimokawa if (err) 956113584Ssimokawa printf("dmamap_load: err=%d\n", err); 957113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 958113584Ssimokawa BUS_DMASYNC_PREWRITE); 959113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 960113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 961113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 962113584Ssimokawa OHCI_OUTPUT_MORE); 963113584Ssimokawa#endif 964103285Sikob } 965108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 966108655Ssimokawa maxdesc = db_tr->dbcnt; 967108655Ssimokawa if (bootverbose) 968108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 969108655Ssimokawa } 970103285Sikob /* last db */ 971103285Sikob LAST_DB(db_tr, db); 972113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 973113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 974113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 975113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 976103285Sikob 977103285Sikob if(fsegment == -1 ) 978103285Sikob fsegment = db_tr->dbcnt; 979103285Sikob if (dbch->pdb_tr != NULL) { 980103285Sikob LAST_DB(dbch->pdb_tr, db); 981113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 982103285Sikob } 983103285Sikob dbch->pdb_tr = db_tr; 984103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 985103285Sikob if(db_tr != dbch->bottom){ 986103285Sikob goto txloop; 987103285Sikob } else { 988107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 989103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 990103285Sikob } 991103285Sikobkick: 992103285Sikob /* kick asy q */ 993113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 994113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 995103285Sikob 996103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 997103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 998103285Sikob } else { 999107653Ssimokawa if (bootverbose) 1000107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1001103285Sikob OREAD(sc, OHCI_DMACTL(off))); 1002113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1003103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1004103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1005103285Sikob } 1006106790Ssimokawa 1007103285Sikob dbch->top = db_tr; 1008103285Sikob splx(s); 1009103285Sikob return; 1010103285Sikob} 1011106790Ssimokawa 1012106790Ssimokawastatic void 1013106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1014103285Sikob{ 1015103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1016103285Sikob fwohci_start( sc, &(sc->atrq)); 1017103285Sikob return; 1018103285Sikob} 1019106790Ssimokawa 1020106790Ssimokawastatic void 1021106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1022103285Sikob{ 1023103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1024103285Sikob fwohci_start( sc, &(sc->atrs)); 1025103285Sikob return; 1026103285Sikob} 1027106790Ssimokawa 1028106790Ssimokawavoid 1029106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1030103285Sikob{ 1031113584Ssimokawa int s, ch, err = 0; 1032103285Sikob struct fwohcidb_tr *tr; 1033103285Sikob volatile struct fwohcidb *db; 1034103285Sikob struct fw_xfer *xfer; 1035103285Sikob u_int32_t off; 1036113584Ssimokawa u_int stat, status; 1037103285Sikob int packets; 1038103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1039113584Ssimokawa 1040103285Sikob if(&sc->atrq == dbch){ 1041103285Sikob off = OHCI_ATQOFF; 1042113584Ssimokawa ch = ATRQ_CH; 1043103285Sikob }else if(&sc->atrs == dbch){ 1044103285Sikob off = OHCI_ATSOFF; 1045113584Ssimokawa ch = ATRS_CH; 1046103285Sikob }else{ 1047103285Sikob return; 1048103285Sikob } 1049103285Sikob s = splfw(); 1050103285Sikob tr = dbch->bottom; 1051103285Sikob packets = 0; 1052113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1053113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1054103285Sikob while(dbch->xferq.queued > 0){ 1055103285Sikob LAST_DB(tr, db); 1056113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1057113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1058103285Sikob if (fc->status != FWBUSRESET) 1059103285Sikob /* maybe out of order?? */ 1060103285Sikob goto out; 1061103285Sikob } 1062113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1063113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1064113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1065119155Ssimokawa#if 1 1066119155Ssimokawa if (firewire_debug) 1067119155Ssimokawa dump_db(sc, ch); 1068103285Sikob#endif 1069113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1070113584Ssimokawa /* Stop DMA */ 1071103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1072103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1073103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1074103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1075103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1076103285Sikob } 1077113584Ssimokawa stat = status & FWOHCIEV_MASK; 1078103285Sikob switch(stat){ 1079110577Ssimokawa case FWOHCIEV_ACKPEND: 1080103285Sikob case FWOHCIEV_ACKCOMPL: 1081103285Sikob err = 0; 1082103285Sikob break; 1083103285Sikob case FWOHCIEV_ACKBSA: 1084103285Sikob case FWOHCIEV_ACKBSB: 1085110577Ssimokawa case FWOHCIEV_ACKBSX: 1086103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1087103285Sikob err = EBUSY; 1088103285Sikob break; 1089103285Sikob case FWOHCIEV_FLUSHED: 1090103285Sikob case FWOHCIEV_ACKTARD: 1091103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1092103285Sikob err = EAGAIN; 1093103285Sikob break; 1094103285Sikob case FWOHCIEV_MISSACK: 1095103285Sikob case FWOHCIEV_UNDRRUN: 1096103285Sikob case FWOHCIEV_OVRRUN: 1097103285Sikob case FWOHCIEV_DESCERR: 1098103285Sikob case FWOHCIEV_DTRDERR: 1099103285Sikob case FWOHCIEV_TIMEOUT: 1100103285Sikob case FWOHCIEV_TCODERR: 1101103285Sikob case FWOHCIEV_UNKNOWN: 1102103285Sikob case FWOHCIEV_ACKDERR: 1103103285Sikob case FWOHCIEV_ACKTERR: 1104103285Sikob default: 1105103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1106103285Sikob stat, fwohcicode[stat]); 1107103285Sikob err = EINVAL; 1108103285Sikob break; 1109103285Sikob } 1110110577Ssimokawa if (tr->xfer != NULL) { 1111103285Sikob xfer = tr->xfer; 1112113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1113119289Ssimokawa#if 0 1114113584Ssimokawa if (firewire_debug) 1115113584Ssimokawa printf("already rcvd\n"); 1116119289Ssimokawa#endif 1117113584Ssimokawa fw_xfer_done(xfer); 1118113584Ssimokawa } else { 1119114218Ssimokawa xfer->state = FWXF_SENT; 1120114218Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1121114218Ssimokawa xfer->state = FWXF_BUSY; 1122114218Ssimokawa xfer->resp = err; 1123114218Ssimokawa if (xfer->retry_req != NULL) 1124114218Ssimokawa xfer->retry_req(xfer); 1125114224Ssimokawa else { 1126114224Ssimokawa xfer->recv.len = 0; 1127114218Ssimokawa fw_xfer_done(xfer); 1128114224Ssimokawa } 1129114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1130114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1131114218Ssimokawa xfer->state = FWXF_SENTERR; 1132114218Ssimokawa xfer->resp = err; 1133114224Ssimokawa xfer->recv.len = 0; 1134113584Ssimokawa fw_xfer_done(xfer); 1135114218Ssimokawa } 1136103285Sikob } 1137110577Ssimokawa /* 1138110577Ssimokawa * The watchdog timer takes care of split 1139110577Ssimokawa * transcation timeout for ACKPEND case. 1140110577Ssimokawa */ 1141113584Ssimokawa } else { 1142113584Ssimokawa printf("this shouldn't happen\n"); 1143103285Sikob } 1144110269Ssimokawa dbch->xferq.queued --; 1145103285Sikob tr->xfer = NULL; 1146103285Sikob 1147103285Sikob packets ++; 1148103285Sikob tr = STAILQ_NEXT(tr, link); 1149103285Sikob dbch->bottom = tr; 1150111956Ssimokawa if (dbch->bottom == dbch->top) { 1151111956Ssimokawa /* we reaches the end of context program */ 1152111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1153111956Ssimokawa printf("queued > 0\n"); 1154111956Ssimokawa break; 1155111956Ssimokawa } 1156103285Sikob } 1157103285Sikobout: 1158103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1159103285Sikob printf("make free slot\n"); 1160103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1161103285Sikob fwohci_start(sc, dbch); 1162103285Sikob } 1163103285Sikob splx(s); 1164103285Sikob} 1165106790Ssimokawa 1166106790Ssimokawastatic void 1167106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1168103285Sikob{ 1169103285Sikob struct fwohcidb_tr *db_tr; 1170113584Ssimokawa int idb; 1171103285Sikob 1172108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1173108527Ssimokawa return; 1174108527Ssimokawa 1175113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1176103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1177113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1178113584Ssimokawa db_tr->buf != NULL) { 1179113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1180113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1181113584Ssimokawa db_tr->buf = NULL; 1182113584Ssimokawa } else if (db_tr->dma_map != NULL) 1183113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1184103285Sikob } 1185103285Sikob dbch->ndb = 0; 1186103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1187113584Ssimokawa fwdma_free_multiseg(dbch->am); 1188110195Ssimokawa free(db_tr, M_FW); 1189103285Sikob STAILQ_INIT(&dbch->db_trq); 1190108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1191103285Sikob} 1192106790Ssimokawa 1193106790Ssimokawastatic void 1194113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1195103285Sikob{ 1196103285Sikob int idb; 1197103285Sikob struct fwohcidb_tr *db_tr; 1198108642Ssimokawa 1199108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1200108642Ssimokawa goto out; 1201108642Ssimokawa 1202113584Ssimokawa /* create dma_tag for buffers */ 1203113584Ssimokawa#define MAX_REQCOUNT 0xffff 1204113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1205113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1206113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1207113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1208113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1209113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1210113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1211113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1212117126Sscottl /*flags*/ 0, 1213117228Ssimokawa#if __FreeBSD_version >= 501102 1214117126Sscottl /*lockfunc*/busdma_lock_mutex, 1215117228Ssimokawa /*lockarg*/&Giant, 1216117228Ssimokawa#endif 1217117228Ssimokawa &dbch->dmat)) 1218113584Ssimokawa return; 1219113584Ssimokawa 1220103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1221103285Sikob /* DB entry must start at 16 bytes bounary. */ 1222103285Sikob STAILQ_INIT(&dbch->db_trq); 1223103285Sikob db_tr = (struct fwohcidb_tr *) 1224103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1225113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1226103285Sikob if(db_tr == NULL){ 1227109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1228103285Sikob return; 1229103285Sikob } 1230109379Ssimokawa 1231113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1232113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1233113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1234113584Ssimokawa if (dbch->am == NULL) { 1235113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1236103285Sikob return; 1237103285Sikob } 1238103285Sikob /* Attach DB to DMA ch. */ 1239103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1240103285Sikob db_tr->dbcnt = 0; 1241113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1242113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1243113584Ssimokawa /* create dmamap for buffers */ 1244113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1245113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1246113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1247113584Ssimokawa printf("bus_dmamap_create failed\n"); 1248113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1249113584Ssimokawa fwohci_db_free(dbch); 1250113584Ssimokawa return; 1251113584Ssimokawa } 1252103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1253113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1254108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1255108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1256108530Ssimokawa ].start = (caddr_t)db_tr; 1257108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1258108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1259108530Ssimokawa ].end = (caddr_t)db_tr; 1260103285Sikob } 1261103285Sikob db_tr++; 1262103285Sikob } 1263103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1264103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1265108642Ssimokawaout: 1266108642Ssimokawa dbch->xferq.queued = 0; 1267108642Ssimokawa dbch->pdb_tr = NULL; 1268103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1269103285Sikob dbch->bottom = dbch->top; 1270108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1271103285Sikob} 1272106790Ssimokawa 1273106790Ssimokawastatic int 1274106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1275103285Sikob{ 1276103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1277113584Ssimokawa int sleepch; 1278109890Ssimokawa 1279113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1280113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1281103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1282103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1283109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1284113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1285103285Sikob fwohci_db_free(&sc->it[dmach]); 1286103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1287103285Sikob return 0; 1288103285Sikob} 1289106790Ssimokawa 1290106790Ssimokawastatic int 1291106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1292103285Sikob{ 1293103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1294113584Ssimokawa int sleepch; 1295103285Sikob 1296103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1297103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1298103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1299109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1300113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1301103285Sikob fwohci_db_free(&sc->ir[dmach]); 1302103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1303103285Sikob return 0; 1304103285Sikob} 1305106790Ssimokawa 1306113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1307106790Ssimokawastatic void 1308106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1309103285Sikob{ 1310113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1311103285Sikob return; 1312103285Sikob} 1313103285Sikob#endif 1314103285Sikob 1315106790Ssimokawastatic int 1316106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1317103285Sikob{ 1318103285Sikob int err = 0; 1319113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1320103285Sikob u_int32_t off = NULL; 1321103285Sikob struct fwohcidb_tr *db_tr; 1322109892Ssimokawa volatile struct fwohcidb *db; 1323103285Sikob 1324103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1325103285Sikob err = EINVAL; 1326103285Sikob return err; 1327103285Sikob } 1328103285Sikob z = dbch->ndesc; 1329103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1330103285Sikob if( &sc->it[dmach] == dbch){ 1331103285Sikob off = OHCI_ITOFF(dmach); 1332103285Sikob break; 1333103285Sikob } 1334103285Sikob } 1335103285Sikob if(off == NULL){ 1336103285Sikob err = EINVAL; 1337103285Sikob return err; 1338103285Sikob } 1339103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1340103285Sikob return err; 1341103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1342103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1343103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1344103285Sikob } 1345103285Sikob db_tr = dbch->top; 1346113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1347113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1348103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1349103285Sikob break; 1350103285Sikob } 1351109892Ssimokawa db = db_tr->db; 1352113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1353113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1354113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1355113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1356103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1357103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1358113584Ssimokawa FWOHCI_DMA_SET( 1359113584Ssimokawa db[ldesc].db.desc.cmd, 1360113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1361109280Ssimokawa /* OHCI 1.1 and above */ 1362113584Ssimokawa FWOHCI_DMA_SET( 1363113584Ssimokawa db[0].db.desc.cmd, 1364113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1365103285Sikob } 1366103285Sikob } 1367103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1368103285Sikob } 1369113584Ssimokawa FWOHCI_DMA_CLEAR( 1370113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1371103285Sikob return err; 1372103285Sikob} 1373106790Ssimokawa 1374106790Ssimokawastatic int 1375106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1376103285Sikob{ 1377103285Sikob int err = 0; 1378109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1379103285Sikob u_int32_t off = NULL; 1380103285Sikob struct fwohcidb_tr *db_tr; 1381109892Ssimokawa volatile struct fwohcidb *db; 1382103285Sikob 1383103285Sikob z = dbch->ndesc; 1384103285Sikob if(&sc->arrq == dbch){ 1385103285Sikob off = OHCI_ARQOFF; 1386103285Sikob }else if(&sc->arrs == dbch){ 1387103285Sikob off = OHCI_ARSOFF; 1388103285Sikob }else{ 1389103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1390103285Sikob if( &sc->ir[dmach] == dbch){ 1391103285Sikob off = OHCI_IROFF(dmach); 1392103285Sikob break; 1393103285Sikob } 1394103285Sikob } 1395103285Sikob } 1396103285Sikob if(off == NULL){ 1397103285Sikob err = EINVAL; 1398103285Sikob return err; 1399103285Sikob } 1400103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1401103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1402103285Sikob return err; 1403103285Sikob }else{ 1404103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1405103285Sikob err = EBUSY; 1406103285Sikob return err; 1407103285Sikob } 1408103285Sikob } 1409103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1410108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1411103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1412103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1413103285Sikob } 1414103285Sikob db_tr = dbch->top; 1415113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1416113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1417113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1418103285Sikob break; 1419109892Ssimokawa db = db_tr->db; 1420109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1421113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1422113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1423103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1424103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1425113584Ssimokawa FWOHCI_DMA_SET( 1426113584Ssimokawa db[ldesc].db.desc.cmd, 1427113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1428113584Ssimokawa FWOHCI_DMA_CLEAR( 1429113584Ssimokawa db[ldesc].db.desc.depend, 1430113584Ssimokawa 0xf); 1431103285Sikob } 1432103285Sikob } 1433103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1434103285Sikob } 1435113584Ssimokawa FWOHCI_DMA_CLEAR( 1436113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1437103285Sikob dbch->buf_offset = 0; 1438113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1439113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1440103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1441103285Sikob return err; 1442103285Sikob }else{ 1443113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1444103285Sikob } 1445103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1446103285Sikob return err; 1447103285Sikob} 1448106790Ssimokawa 1449106790Ssimokawastatic int 1450113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1451109890Ssimokawa{ 1452109890Ssimokawa int sec, cycle, cycle_match; 1453109890Ssimokawa 1454109890Ssimokawa cycle = cycle_now & 0x1fff; 1455109890Ssimokawa sec = cycle_now >> 13; 1456109890Ssimokawa#define CYCLE_MOD 0x10 1457113584Ssimokawa#if 1 1458109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1459113584Ssimokawa#else 1460113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1461113584Ssimokawa#endif 1462109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1463109890Ssimokawa if (cycle >= 8000) { 1464109890Ssimokawa sec ++; 1465109890Ssimokawa cycle -= 8000; 1466109890Ssimokawa } 1467113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1468109890Ssimokawa if (cycle >= 8000) { 1469109890Ssimokawa sec ++; 1470109890Ssimokawa if (cycle == 8000) 1471109890Ssimokawa cycle = 0; 1472109890Ssimokawa else 1473109890Ssimokawa cycle = CYCLE_MOD; 1474109890Ssimokawa } 1475109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1476109890Ssimokawa 1477109890Ssimokawa return(cycle_match); 1478109890Ssimokawa} 1479109890Ssimokawa 1480109890Ssimokawastatic int 1481106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1482103285Sikob{ 1483103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1484103285Sikob int err = 0; 1485103285Sikob unsigned short tag, ich; 1486103285Sikob struct fwohci_dbch *dbch; 1487109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1488109356Ssimokawa u_int32_t stat; 1489109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1490109890Ssimokawa struct fw_xferq *it; 1491103285Sikob 1492103285Sikob dbch = &sc->it[dmach]; 1493109890Ssimokawa it = &dbch->xferq; 1494109890Ssimokawa 1495109890Ssimokawa tag = (it->flag >> 6) & 3; 1496109890Ssimokawa ich = it->flag & 0x3f; 1497109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1498109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1499103285Sikob dbch->ndesc = 3; 1500113584Ssimokawa fwohci_db_init(sc, dbch); 1501109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1502109179Ssimokawa return ENOMEM; 1503103285Sikob err = fwohci_tx_enable(sc, dbch); 1504103285Sikob } 1505103285Sikob if(err) 1506103285Sikob return err; 1507109890Ssimokawa 1508109892Ssimokawa ldesc = dbch->ndesc - 1; 1509109890Ssimokawa s = splfw(); 1510109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1511109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1512109890Ssimokawa volatile struct fwohcidb *db; 1513109890Ssimokawa 1514113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1515113584Ssimokawa BUS_DMASYNC_PREWRITE); 1516109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1517109890Ssimokawa if (prev != NULL) { 1518109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1519113584Ssimokawa#if 0 /* XXX necessary? */ 1520113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1521113584Ssimokawa OHCI_BRANCH_ALWAYS); 1522113584Ssimokawa#endif 1523109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1524109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1525113584Ssimokawa ((struct fwohcidb_tr *) 1526113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1527109892Ssimokawa#else 1528113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1529113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1530109892Ssimokawa#endif 1531103285Sikob } 1532109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1533109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1534109890Ssimokawa prev = chunk; 1535109403Ssimokawa } 1536113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1537113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1538109890Ssimokawa splx(s); 1539109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1540113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1541113584Ssimokawa printf("stat 0x%x\n", stat); 1542113584Ssimokawa 1543109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1544109890Ssimokawa return 0; 1545109890Ssimokawa 1546113584Ssimokawa#if 0 1547109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1548113584Ssimokawa#endif 1549109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1550109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1551109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1552113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1553109890Ssimokawa 1554109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1555113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1556113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1557113584Ssimokawa if (firewire_debug) { 1558109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1559113584Ssimokawa#if 1 1560113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1561113584Ssimokawa#endif 1562113584Ssimokawa } 1563109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1564109890Ssimokawa#if 1 1565109890Ssimokawa /* Don't start until all chunks are buffered */ 1566109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1567109890Ssimokawa goto out; 1568109890Ssimokawa#endif 1569113584Ssimokawa#if 1 1570109890Ssimokawa /* Clear cycle match counter bits */ 1571109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1572109890Ssimokawa 1573109356Ssimokawa /* 2bit second + 13bit cycle */ 1574109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1575113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1576109890Ssimokawa 1577109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1578109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1579109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1580113584Ssimokawa#else 1581113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1582113584Ssimokawa#endif 1583113584Ssimokawa if (firewire_debug) { 1584109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1585109403Ssimokawa cycle_now, cycle_match); 1586113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1587113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1588113584Ssimokawa } 1589109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1590109890Ssimokawa device_printf(sc->fc.dev, 1591109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1592113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1593103285Sikob } 1594109890Ssimokawaout: 1595103285Sikob return err; 1596103285Sikob} 1597106790Ssimokawa 1598106790Ssimokawastatic int 1599113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1600103285Sikob{ 1601103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1602109890Ssimokawa int err = 0, s, ldesc; 1603103285Sikob unsigned short tag, ich; 1604109736Ssimokawa u_int32_t stat; 1605109890Ssimokawa struct fwohci_dbch *dbch; 1606113584Ssimokawa struct fwohcidb_tr *db_tr; 1607109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1608109890Ssimokawa struct fw_xferq *ir; 1609103285Sikob 1610109890Ssimokawa dbch = &sc->ir[dmach]; 1611109890Ssimokawa ir = &dbch->xferq; 1612109890Ssimokawa 1613109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1614109890Ssimokawa tag = (ir->flag >> 6) & 3; 1615109890Ssimokawa ich = ir->flag & 0x3f; 1616108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1617108995Ssimokawa 1618109890Ssimokawa ir->queued = 0; 1619109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1620109890Ssimokawa dbch->ndesc = 2; 1621113584Ssimokawa fwohci_db_init(sc, dbch); 1622109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1623109179Ssimokawa return ENOMEM; 1624109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1625103285Sikob } 1626103285Sikob if(err) 1627103285Sikob return err; 1628103285Sikob 1629109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1630109890Ssimokawa if (first == NULL) { 1631109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1632109890Ssimokawa return 0; 1633109890Ssimokawa } 1634109890Ssimokawa 1635111892Ssimokawa ldesc = dbch->ndesc - 1; 1636111892Ssimokawa s = splfw(); 1637109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1638109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1639109890Ssimokawa volatile struct fwohcidb *db; 1640109890Ssimokawa 1641111942Ssimokawa#if 1 /* XXX for if_fwe */ 1642113584Ssimokawa if (chunk->mbuf != NULL) { 1643113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1644113584Ssimokawa db_tr->dbcnt = 1; 1645113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1646113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1647113584Ssimokawa /* flags */0); 1648113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1649113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1650113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1651113584Ssimokawa } 1652111942Ssimokawa#endif 1653109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1654113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1655113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1656109890Ssimokawa if (prev != NULL) { 1657109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1658113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1659103285Sikob } 1660109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1661109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1662109890Ssimokawa prev = chunk; 1663103285Sikob } 1664113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1665113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1666109890Ssimokawa splx(s); 1667109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1668109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1669109890Ssimokawa return 0; 1670109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1671109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1672109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1673109890Ssimokawa } 1674109890Ssimokawa 1675113584Ssimokawa if (firewire_debug) 1676113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1677109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1678109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1679109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1680109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1681109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1682109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1683113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1684109890Ssimokawa | dbch->ndesc); 1685109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1686109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1687113584Ssimokawa#if 0 1688113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1689113584Ssimokawa#endif 1690103285Sikob return err; 1691103285Sikob} 1692106790Ssimokawa 1693106790Ssimokawaint 1694110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1695103285Sikob{ 1696103285Sikob u_int i; 1697103285Sikob 1698103285Sikob/* Now stopping all DMA channel */ 1699103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1700103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1701103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1702103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1703103285Sikob 1704103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1705103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1706103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1707103285Sikob } 1708103285Sikob 1709103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1710103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1711103285Sikob 1712103285Sikob/* Stop interrupt */ 1713103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1714103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1715103285Sikob | OHCI_INT_PHY_INT 1716103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1717103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1718103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1719103285Sikob | OHCI_INT_PHY_BUS_R); 1720116978Ssimokawa 1721118416Ssimokawa if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1722118416Ssimokawa fw_drain_txq(&sc->fc); 1723116978Ssimokawa 1724108642Ssimokawa/* XXX Link down? Bus reset? */ 1725103285Sikob return 0; 1726103285Sikob} 1727103285Sikob 1728108642Ssimokawaint 1729108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1730108642Ssimokawa{ 1731108642Ssimokawa int i; 1732116978Ssimokawa struct fw_xferq *ir; 1733116978Ssimokawa struct fw_bulkxfer *chunk; 1734108642Ssimokawa 1735108642Ssimokawa fwohci_reset(sc, dev); 1736108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1737108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1738116978Ssimokawa ir = &sc->ir[i].xferq; 1739116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1740108642Ssimokawa device_printf(sc->fc.dev, 1741108642Ssimokawa "resume iso receive ch: %d\n", i); 1742116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1743116978Ssimokawa /* requeue stdma to stfree */ 1744116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1745116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1746116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1747116978Ssimokawa } 1748108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1749108642Ssimokawa } 1750108642Ssimokawa } 1751108642Ssimokawa 1752108642Ssimokawa bus_generic_resume(dev); 1753108642Ssimokawa sc->fc.ibr(&sc->fc); 1754108642Ssimokawa return 0; 1755108642Ssimokawa} 1756108642Ssimokawa 1757103285Sikob#define ACK_ALL 1758103285Sikobstatic void 1759106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1760103285Sikob{ 1761103285Sikob u_int32_t irstat, itstat; 1762103285Sikob u_int i; 1763103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1764103285Sikob 1765103285Sikob#ifdef OHCI_DEBUG 1766103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1767103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1768103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1769103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1770103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1771103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1772103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1773103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1774103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1775103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1776103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1777103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1778103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1779103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1780103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1781103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1782103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1783103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1784103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1785103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1786103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1787103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1788103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1789103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1790103285Sikob ); 1791103285Sikob#endif 1792103285Sikob/* Bus reset */ 1793103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1794111074Ssimokawa if (fc->status == FWBUSRESET) 1795111074Ssimokawa goto busresetout; 1796111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1797111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1798111074Ssimokawa 1799103285Sikob device_printf(fc->dev, "BUS reset\n"); 1800103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1801103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1802103285Sikob 1803103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1804103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1805103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1806103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1807103285Sikob 1808103285Sikob#ifndef ACK_ALL 1809103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1810103285Sikob#endif 1811110798Ssimokawa fw_busreset(fc); 1812116376Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1813116376Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1814103285Sikob } 1815111074Ssimokawabusresetout: 1816103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1817103285Sikob#ifndef ACK_ALL 1818103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1819103285Sikob#endif 1820113584Ssimokawa#if __FreeBSD_version >= 500000 1821113584Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1822113584Ssimokawa#else 1823113584Ssimokawa irstat = sc->irstat; 1824113584Ssimokawa sc->irstat = 0; 1825113584Ssimokawa#endif 1826103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1827109644Ssimokawa struct fwohci_dbch *dbch; 1828109644Ssimokawa 1829103285Sikob if((irstat & (1 << i)) != 0){ 1830109644Ssimokawa dbch = &sc->ir[i]; 1831109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1832109644Ssimokawa device_printf(sc->fc.dev, 1833109644Ssimokawa "dma(%d) not active\n", i); 1834109644Ssimokawa continue; 1835109644Ssimokawa } 1836113584Ssimokawa fwohci_rbuf_update(sc, i); 1837103285Sikob } 1838103285Sikob } 1839103285Sikob } 1840103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1841103285Sikob#ifndef ACK_ALL 1842103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1843103285Sikob#endif 1844113584Ssimokawa#if __FreeBSD_version >= 500000 1845113584Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1846113584Ssimokawa#else 1847113584Ssimokawa itstat = sc->itstat; 1848113584Ssimokawa sc->itstat = 0; 1849113584Ssimokawa#endif 1850103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1851103285Sikob if((itstat & (1 << i)) != 0){ 1852103285Sikob fwohci_tbuf_update(sc, i); 1853103285Sikob } 1854103285Sikob } 1855103285Sikob } 1856103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1857103285Sikob#ifndef ACK_ALL 1858103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1859103285Sikob#endif 1860103285Sikob#if 0 1861103285Sikob dump_dma(sc, ARRS_CH); 1862103285Sikob dump_db(sc, ARRS_CH); 1863103285Sikob#endif 1864106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1865103285Sikob } 1866103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1867103285Sikob#ifndef ACK_ALL 1868103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1869103285Sikob#endif 1870103285Sikob#if 0 1871103285Sikob dump_dma(sc, ARRQ_CH); 1872103285Sikob dump_db(sc, ARRQ_CH); 1873103285Sikob#endif 1874106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1875103285Sikob } 1876103285Sikob if(stat & OHCI_INT_PHY_SID){ 1877113584Ssimokawa u_int32_t *buf, node_id; 1878103285Sikob int plen; 1879103285Sikob 1880103285Sikob#ifndef ACK_ALL 1881103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1882103285Sikob#endif 1883111074Ssimokawa /* Enable bus reset interrupt */ 1884111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1885111787Ssimokawa /* Allow async. request to us */ 1886111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1887111787Ssimokawa /* XXX insecure ?? */ 1888111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1889111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1890111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1891112523Ssimokawa /* Set ATRetries register */ 1892112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1893103285Sikob/* 1894103285Sikob** Checking whether the node is root or not. If root, turn on 1895103285Sikob** cycle master. 1896103285Sikob*/ 1897113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1898113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1899113584Ssimokawa 1900113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1901113584Ssimokawa node_id, (plen >> 16) & 0xff); 1902113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1903103285Sikob printf("Bus reset failure\n"); 1904103285Sikob goto sidout; 1905103285Sikob } 1906113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1907103285Sikob printf("CYCLEMASTER mode\n"); 1908103285Sikob OWRITE(sc, OHCI_LNKCTL, 1909103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1910113584Ssimokawa } else { 1911103285Sikob printf("non CYCLEMASTER mode\n"); 1912103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1913103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1914103285Sikob } 1915113584Ssimokawa fc->nodeid = node_id & 0x3f; 1916103285Sikob 1917113584Ssimokawa if (plen & OHCI_SID_ERR) { 1918113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1919113584Ssimokawa goto sidout; 1920113584Ssimokawa } 1921113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1922109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1923109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1924109736Ssimokawa goto sidout; 1925109736Ssimokawa } 1926103285Sikob plen -= 4; /* chop control info */ 1927113584Ssimokawa buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1928113584Ssimokawa if (buf == NULL) { 1929113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1930113584Ssimokawa goto sidout; 1931113584Ssimokawa } 1932113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1933113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1934110269Ssimokawa#if 1 1935110269Ssimokawa /* pending all pre-bus_reset packets */ 1936110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1937110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1938110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1939110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1940110798Ssimokawa fw_drain_txq(fc); 1941110269Ssimokawa#endif 1942113584Ssimokawa fw_sidrcv(fc, buf, plen); 1943113584Ssimokawa free(buf, M_FW); 1944103285Sikob } 1945103285Sikobsidout: 1946103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1947103285Sikob#ifndef ACK_ALL 1948103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1949103285Sikob#endif 1950103285Sikob fwohci_txd(sc, &(sc->atrq)); 1951103285Sikob } 1952103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1953103285Sikob#ifndef ACK_ALL 1954103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1955103285Sikob#endif 1956103285Sikob fwohci_txd(sc, &(sc->atrs)); 1957103285Sikob } 1958103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1959103285Sikob#ifndef ACK_ALL 1960103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1961103285Sikob#endif 1962103285Sikob device_printf(fc->dev, "posted write error\n"); 1963103285Sikob } 1964103285Sikob if((stat & OHCI_INT_ERR )){ 1965103285Sikob#ifndef ACK_ALL 1966103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1967103285Sikob#endif 1968103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1969103285Sikob } 1970103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1971103285Sikob#ifndef ACK_ALL 1972103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1973103285Sikob#endif 1974103285Sikob device_printf(fc->dev, "phy int\n"); 1975103285Sikob } 1976103285Sikob 1977103285Sikob return; 1978103285Sikob} 1979103285Sikob 1980113584Ssimokawa#if FWOHCI_TASKQUEUE 1981113584Ssimokawastatic void 1982113584Ssimokawafwohci_complete(void *arg, int pending) 1983113584Ssimokawa{ 1984113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1985113584Ssimokawa u_int32_t stat; 1986113584Ssimokawa 1987113584Ssimokawaagain: 1988113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 1989113584Ssimokawa if (stat) 1990113584Ssimokawa fwohci_intr_body(sc, stat, -1); 1991113584Ssimokawa else 1992113584Ssimokawa return; 1993113584Ssimokawa goto again; 1994113584Ssimokawa} 1995113584Ssimokawa#endif 1996113584Ssimokawa 1997113584Ssimokawastatic u_int32_t 1998113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 1999113584Ssimokawa{ 2000113584Ssimokawa u_int32_t stat, irstat, itstat; 2001113584Ssimokawa 2002113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 2003113584Ssimokawa if (stat == 0xffffffff) { 2004113584Ssimokawa device_printf(sc->fc.dev, 2005113584Ssimokawa "device physically ejected?\n"); 2006113584Ssimokawa return(stat); 2007113584Ssimokawa } 2008113584Ssimokawa#ifdef ACK_ALL 2009113584Ssimokawa if (stat) 2010113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2011113584Ssimokawa#endif 2012113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2013113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2014113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2015113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2016113584Ssimokawa } 2017113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2018113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2019113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2020113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2021113584Ssimokawa } 2022113584Ssimokawa return(stat); 2023113584Ssimokawa} 2024113584Ssimokawa 2025103285Sikobvoid 2026103285Sikobfwohci_intr(void *arg) 2027103285Sikob{ 2028103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2029113584Ssimokawa u_int32_t stat; 2030113584Ssimokawa#if !FWOHCI_TASKQUEUE 2031113584Ssimokawa u_int32_t bus_reset = 0; 2032113584Ssimokawa#endif 2033103285Sikob 2034103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 2035103285Sikob /* polling mode */ 2036103285Sikob return; 2037103285Sikob } 2038103285Sikob 2039113584Ssimokawa#if !FWOHCI_TASKQUEUE 2040113584Ssimokawaagain: 2041103285Sikob#endif 2042113584Ssimokawa stat = fwochi_check_stat(sc); 2043113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2044113584Ssimokawa return; 2045113584Ssimokawa#if FWOHCI_TASKQUEUE 2046113584Ssimokawa atomic_set_int(&sc->intstat, stat); 2047113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 2048113584Ssimokawa if (stat) 2049113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2050113584Ssimokawa#else 2051113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 2052113584Ssimokawa if ((stat & ~bus_reset) == 0) 2053113584Ssimokawa return; 2054113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2055113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2056113584Ssimokawa goto again; 2057113584Ssimokawa#endif 2058103285Sikob} 2059103285Sikob 2060116897Ssimokawavoid 2061103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2062103285Sikob{ 2063103285Sikob int s; 2064103285Sikob u_int32_t stat; 2065103285Sikob struct fwohci_softc *sc; 2066103285Sikob 2067103285Sikob 2068103285Sikob sc = (struct fwohci_softc *)fc; 2069103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2070103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2071103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2072103285Sikob#if 0 2073103285Sikob if (!quick) { 2074103285Sikob#else 2075103285Sikob if (1) { 2076103285Sikob#endif 2077113584Ssimokawa stat = fwochi_check_stat(sc); 2078113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2079103285Sikob return; 2080103285Sikob } 2081103285Sikob s = splfw(); 2082106789Ssimokawa fwohci_intr_body(sc, stat, count); 2083103285Sikob splx(s); 2084103285Sikob} 2085103285Sikob 2086103285Sikobstatic void 2087103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2088103285Sikob{ 2089103285Sikob struct fwohci_softc *sc; 2090103285Sikob 2091103285Sikob sc = (struct fwohci_softc *)fc; 2092107653Ssimokawa if (bootverbose) 2093108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2094103285Sikob if (enable) { 2095103285Sikob sc->intmask |= OHCI_INT_EN; 2096103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2097103285Sikob } else { 2098103285Sikob sc->intmask &= ~OHCI_INT_EN; 2099103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2100103285Sikob } 2101103285Sikob} 2102103285Sikob 2103106790Ssimokawastatic void 2104106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2105103285Sikob{ 2106103285Sikob struct firewire_comm *fc = &sc->fc; 2107109890Ssimokawa volatile struct fwohcidb *db; 2108109890Ssimokawa struct fw_bulkxfer *chunk; 2109109890Ssimokawa struct fw_xferq *it; 2110109890Ssimokawa u_int32_t stat, count; 2111113584Ssimokawa int s, w=0, ldesc; 2112103285Sikob 2113109890Ssimokawa it = fc->it[dmach]; 2114113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2115109890Ssimokawa s = splfw(); /* unnecessary ? */ 2116113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2117119155Ssimokawa if (firewire_debug) 2118119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2119109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2120109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2121113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2122113584Ssimokawa >> OHCI_STATUS_SHIFT; 2123109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2124119155Ssimokawa /* timestamp */ 2125113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2126113584Ssimokawa & OHCI_COUNT_MASK; 2127109890Ssimokawa if (stat == 0) 2128109890Ssimokawa break; 2129109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2130109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2131109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2132109890Ssimokawa#if 0 2133109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2134109179Ssimokawa#endif 2135109890Ssimokawa break; 2136109890Ssimokawa default: 2137109423Ssimokawa device_printf(fc->dev, 2138113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2139113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2140109890Ssimokawa } 2141109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2142109890Ssimokawa w++; 2143109403Ssimokawa } 2144109890Ssimokawa splx(s); 2145109890Ssimokawa if (w) 2146109890Ssimokawa wakeup(it); 2147103285Sikob} 2148106790Ssimokawa 2149106790Ssimokawastatic void 2150106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2151103285Sikob{ 2152109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2153113584Ssimokawa volatile struct fwohcidb_tr *db_tr; 2154109890Ssimokawa struct fw_bulkxfer *chunk; 2155109890Ssimokawa struct fw_xferq *ir; 2156109890Ssimokawa u_int32_t stat; 2157113584Ssimokawa int s, w=0, ldesc; 2158109179Ssimokawa 2159109890Ssimokawa ir = fc->ir[dmach]; 2160113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2161113584Ssimokawa#if 0 2162113584Ssimokawa dump_db(sc, dmach); 2163113584Ssimokawa#endif 2164109890Ssimokawa s = splfw(); 2165113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2166109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2167113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2168113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2169113584Ssimokawa >> OHCI_STATUS_SHIFT; 2170109890Ssimokawa if (stat == 0) 2171109890Ssimokawa break; 2172113584Ssimokawa 2173113584Ssimokawa if (chunk->mbuf != NULL) { 2174113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2175113584Ssimokawa BUS_DMASYNC_POSTREAD); 2176113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2177113584Ssimokawa } else if (ir->buf != NULL) { 2178113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2179113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2180113584Ssimokawa } else { 2181113584Ssimokawa /* XXX */ 2182113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2183113584Ssimokawa } 2184113584Ssimokawa 2185109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2186109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2187109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2188109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2189111942Ssimokawa chunk->resp = 0; 2190109890Ssimokawa break; 2191109890Ssimokawa default: 2192111942Ssimokawa chunk->resp = EINVAL; 2193109890Ssimokawa device_printf(fc->dev, 2194113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2195113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2196109890Ssimokawa } 2197109890Ssimokawa w++; 2198103285Sikob } 2199109890Ssimokawa splx(s); 2200111942Ssimokawa if (w) { 2201111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2202111942Ssimokawa ir->hand(ir); 2203111942Ssimokawa else 2204111942Ssimokawa wakeup(ir); 2205111942Ssimokawa } 2206103285Sikob} 2207106790Ssimokawa 2208106790Ssimokawavoid 2209106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2210106790Ssimokawa{ 2211103285Sikob u_int32_t off, cntl, stat, cmd, match; 2212103285Sikob 2213103285Sikob if(ch == 0){ 2214103285Sikob off = OHCI_ATQOFF; 2215103285Sikob }else if(ch == 1){ 2216103285Sikob off = OHCI_ATSOFF; 2217103285Sikob }else if(ch == 2){ 2218103285Sikob off = OHCI_ARQOFF; 2219103285Sikob }else if(ch == 3){ 2220103285Sikob off = OHCI_ARSOFF; 2221103285Sikob }else if(ch < IRX_CH){ 2222103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2223103285Sikob }else{ 2224103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2225103285Sikob } 2226103285Sikob cntl = stat = OREAD(sc, off); 2227103285Sikob cmd = OREAD(sc, off + 0xc); 2228103285Sikob match = OREAD(sc, off + 0x10); 2229103285Sikob 2230113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2231103285Sikob ch, 2232103285Sikob cntl, 2233103285Sikob cmd, 2234103285Sikob match); 2235103285Sikob stat &= 0xffff ; 2236113584Ssimokawa if (stat) { 2237103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2238103285Sikob ch, 2239103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2240103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2241103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2242103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2243103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2244103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2245103285Sikob fwohcicode[stat & 0x1f], 2246103285Sikob stat & 0x1f 2247103285Sikob ); 2248103285Sikob }else{ 2249103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2250103285Sikob } 2251103285Sikob} 2252106790Ssimokawa 2253106790Ssimokawavoid 2254106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2255106790Ssimokawa{ 2256103285Sikob struct fwohci_dbch *dbch; 2257113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2258103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2259103285Sikob int idb, jdb; 2260103285Sikob u_int32_t cmd, off; 2261103285Sikob if(ch == 0){ 2262103285Sikob off = OHCI_ATQOFF; 2263103285Sikob dbch = &sc->atrq; 2264103285Sikob }else if(ch == 1){ 2265103285Sikob off = OHCI_ATSOFF; 2266103285Sikob dbch = &sc->atrs; 2267103285Sikob }else if(ch == 2){ 2268103285Sikob off = OHCI_ARQOFF; 2269103285Sikob dbch = &sc->arrq; 2270103285Sikob }else if(ch == 3){ 2271103285Sikob off = OHCI_ARSOFF; 2272103285Sikob dbch = &sc->arrs; 2273103285Sikob }else if(ch < IRX_CH){ 2274103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2275103285Sikob dbch = &sc->it[ch - ITX_CH]; 2276103285Sikob }else { 2277103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2278103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2279103285Sikob } 2280103285Sikob cmd = OREAD(sc, off + 0xc); 2281103285Sikob 2282103285Sikob if( dbch->ndb == 0 ){ 2283103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2284103285Sikob return; 2285103285Sikob } 2286103285Sikob pp = dbch->top; 2287103285Sikob prev = pp->db; 2288103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2289103285Sikob if(pp == NULL){ 2290103285Sikob curr = NULL; 2291103285Sikob goto outdb; 2292103285Sikob } 2293103285Sikob cp = STAILQ_NEXT(pp, link); 2294103285Sikob if(cp == NULL){ 2295103285Sikob curr = NULL; 2296103285Sikob goto outdb; 2297103285Sikob } 2298103285Sikob np = STAILQ_NEXT(cp, link); 2299103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2300113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2301103285Sikob curr = cp->db; 2302103285Sikob if(np != NULL){ 2303103285Sikob next = np->db; 2304103285Sikob }else{ 2305103285Sikob next = NULL; 2306103285Sikob } 2307103285Sikob goto outdb; 2308103285Sikob } 2309103285Sikob } 2310103285Sikob pp = STAILQ_NEXT(pp, link); 2311103285Sikob prev = pp->db; 2312103285Sikob } 2313103285Sikoboutdb: 2314103285Sikob if( curr != NULL){ 2315113584Ssimokawa#if 0 2316103285Sikob printf("Prev DB %d\n", ch); 2317113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2318113584Ssimokawa#endif 2319103285Sikob printf("Current DB %d\n", ch); 2320113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2321113584Ssimokawa#if 0 2322103285Sikob printf("Next DB %d\n", ch); 2323113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2324113584Ssimokawa#endif 2325103285Sikob }else{ 2326103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2327103285Sikob } 2328103285Sikob return; 2329103285Sikob} 2330106790Ssimokawa 2331106790Ssimokawavoid 2332113584Ssimokawaprint_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2333113584Ssimokawa u_int32_t ch, u_int32_t max) 2334106790Ssimokawa{ 2335103285Sikob fwohcireg_t stat; 2336103285Sikob int i, key; 2337113584Ssimokawa u_int32_t cmd, res; 2338103285Sikob 2339103285Sikob if(db == NULL){ 2340103285Sikob printf("No Descriptor is found\n"); 2341103285Sikob return; 2342103285Sikob } 2343103285Sikob 2344103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2345103285Sikob ch, 2346103285Sikob "Current", 2347103285Sikob "OP ", 2348103285Sikob "KEY", 2349103285Sikob "INT", 2350103285Sikob "BR ", 2351103285Sikob "len", 2352103285Sikob "Addr", 2353103285Sikob "Depend", 2354103285Sikob "Stat", 2355103285Sikob "Cnt"); 2356103285Sikob for( i = 0 ; i <= max ; i ++){ 2357113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2358113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2359113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2360113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2361108712Ssimokawa#if __FreeBSD_version >= 500000 2362113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2363114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2364108712Ssimokawa#else 2365108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2366114142Ssimokawa db_tr->bus_addr, 2367108712Ssimokawa#endif 2368113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2369113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2370113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2371113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2372113584Ssimokawa cmd & OHCI_COUNT_MASK, 2373113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2374113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2375113584Ssimokawa stat, 2376113584Ssimokawa res & OHCI_COUNT_MASK); 2377103285Sikob if(stat & 0xff00){ 2378103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2379103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2380103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2381103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2382103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2383103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2384103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2385103285Sikob fwohcicode[stat & 0x1f], 2386103285Sikob stat & 0x1f 2387103285Sikob ); 2388103285Sikob }else{ 2389103285Sikob printf(" Nostat\n"); 2390103285Sikob } 2391103285Sikob if(key == OHCI_KEY_ST2 ){ 2392103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2393113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2394113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2395113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2396113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2397103285Sikob } 2398103285Sikob if(key == OHCI_KEY_DEVICE){ 2399103285Sikob return; 2400103285Sikob } 2401113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2402103285Sikob == OHCI_BRANCH_ALWAYS){ 2403103285Sikob return; 2404103285Sikob } 2405113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2406103285Sikob == OHCI_OUTPUT_LAST){ 2407103285Sikob return; 2408103285Sikob } 2409113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2410103285Sikob == OHCI_INPUT_LAST){ 2411103285Sikob return; 2412103285Sikob } 2413103285Sikob if(key == OHCI_KEY_ST2 ){ 2414103285Sikob i++; 2415103285Sikob } 2416103285Sikob } 2417103285Sikob return; 2418103285Sikob} 2419106790Ssimokawa 2420106790Ssimokawavoid 2421106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2422103285Sikob{ 2423103285Sikob struct fwohci_softc *sc; 2424103285Sikob u_int32_t fun; 2425103285Sikob 2426110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2427103285Sikob sc = (struct fwohci_softc *)fc; 2428108276Ssimokawa 2429108276Ssimokawa /* 2430108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2431108276Ssimokawa * shouldn't became the root node. 2432108276Ssimokawa */ 2433103285Sikob#if 1 2434103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2435109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2436103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2437109280Ssimokawa#else /* Short bus reset */ 2438103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2439109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2440103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2441103285Sikob#endif 2442103285Sikob} 2443106790Ssimokawa 2444106790Ssimokawavoid 2445106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2446103285Sikob{ 2447103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2448103285Sikob struct fwohci_dbch *dbch; 2449109892Ssimokawa volatile struct fwohcidb *db; 2450103285Sikob struct fw_pkt *fp; 2451103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2452103285Sikob unsigned short chtag; 2453103285Sikob int idb; 2454103285Sikob 2455103285Sikob dbch = &sc->it[dmach]; 2456103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2457103285Sikob 2458103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2459103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2460103285Sikob/* 2461113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2462103285Sikob*/ 2463113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2464109892Ssimokawa db = db_tr->db; 2465103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2466109892Ssimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2467113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2468119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2469113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2470103285Sikob ohcifp->mode.stream.chtag = chtag; 2471103285Sikob ohcifp->mode.stream.tcode = 0xa; 2472113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2473113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2474113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2475113584Ssimokawa#endif 2476103285Sikob 2477113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2478113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2479113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2480109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2481113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2482103285Sikob | OHCI_UPDATE 2483109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2484109892Ssimokawa db[0].db.desc.depend = 2485109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2486113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2487109892Ssimokawa#else 2488113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2489113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2490109892Ssimokawa#endif 2491103285Sikob bulkxfer->end = (caddr_t)db_tr; 2492103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2493103285Sikob } 2494109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2495113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2496113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2497109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2498109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2499109280Ssimokawa /* OHCI 1.1 and above */ 2500109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2501109892Ssimokawa#endif 2502109892Ssimokawa/* 2503103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2504103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2505113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2506103285Sikob*/ 2507103285Sikob return; 2508103285Sikob} 2509106790Ssimokawa 2510106790Ssimokawastatic int 2511113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2512113584Ssimokawa int poffset) 2513103285Sikob{ 2514103285Sikob volatile struct fwohcidb *db = db_tr->db; 2515113584Ssimokawa struct fw_xferq *it; 2516103285Sikob int err = 0; 2517113584Ssimokawa 2518113584Ssimokawa it = &dbch->xferq; 2519113584Ssimokawa if(it->buf == 0){ 2520103285Sikob err = EINVAL; 2521103285Sikob return err; 2522103285Sikob } 2523113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2524103285Sikob db_tr->dbcnt = 3; 2525103285Sikob 2526113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2527113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2528119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2529119155Ssimokawa bzero((void *)(uintptr_t)(volatile void *) 2530119155Ssimokawa &db[1].db.immed[0], sizeof(db[1].db.immed)); 2531113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2532113584Ssimokawa fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2533113584Ssimokawa 2534113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2535113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2536109892Ssimokawa#if 1 2537113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2538113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2539109892Ssimokawa#endif 2540113584Ssimokawa return 0; 2541103285Sikob} 2542106790Ssimokawa 2543106790Ssimokawaint 2544113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2545113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2546103285Sikob{ 2547103285Sikob volatile struct fwohcidb *db = db_tr->db; 2548113584Ssimokawa struct fw_xferq *ir; 2549113584Ssimokawa int i, ldesc; 2550113584Ssimokawa bus_addr_t dbuf[2]; 2551103285Sikob int dsiz[2]; 2552103285Sikob 2553113584Ssimokawa ir = &dbch->xferq; 2554113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2555113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2556113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2557113584Ssimokawa if (db_tr->buf == NULL) 2558113584Ssimokawa return(ENOMEM); 2559103285Sikob db_tr->dbcnt = 1; 2560113584Ssimokawa dsiz[0] = ir->psize; 2561113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2562113584Ssimokawa BUS_DMASYNC_PREREAD); 2563113584Ssimokawa } else { 2564113584Ssimokawa db_tr->dbcnt = 0; 2565113584Ssimokawa if (dummy_dma != NULL) { 2566113584Ssimokawa dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2567113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2568113584Ssimokawa } 2569113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2570113584Ssimokawa if (ir->buf != NULL) { 2571113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2572113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2573113584Ssimokawa } 2574113584Ssimokawa db_tr->dbcnt++; 2575103285Sikob } 2576103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2577113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2578113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2579113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2580113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2581103285Sikob } 2582113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2583103285Sikob } 2584113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2585113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2586113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2587103285Sikob } 2588113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2589113584Ssimokawa return 0; 2590103285Sikob} 2591106790Ssimokawa 2592113584Ssimokawa 2593113584Ssimokawastatic int 2594113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2595103285Sikob{ 2596113584Ssimokawa struct fw_pkt *fp0; 2597113584Ssimokawa u_int32_t ld0; 2598113584Ssimokawa int slen; 2599113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2600113584Ssimokawa int i; 2601113584Ssimokawa#endif 2602103285Sikob 2603113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2604113584Ssimokawa#if 0 2605113584Ssimokawa printf("ld0: x%08x\n", ld0); 2606113584Ssimokawa#endif 2607113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2608113584Ssimokawa switch (fp0->mode.common.tcode) { 2609113584Ssimokawa case FWTCODE_RREQQ: 2610113584Ssimokawa case FWTCODE_WRES: 2611113584Ssimokawa case FWTCODE_WREQQ: 2612113584Ssimokawa case FWTCODE_RRESQ: 2613113584Ssimokawa case FWOHCITCODE_PHY: 2614113584Ssimokawa slen = 12; 2615113584Ssimokawa break; 2616113584Ssimokawa case FWTCODE_RREQB: 2617113584Ssimokawa case FWTCODE_WREQB: 2618113584Ssimokawa case FWTCODE_LREQ: 2619113584Ssimokawa case FWTCODE_RRESB: 2620113584Ssimokawa case FWTCODE_LRES: 2621113584Ssimokawa slen = 16; 2622113584Ssimokawa break; 2623113584Ssimokawa default: 2624113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2625113584Ssimokawa return(0); 2626103285Sikob } 2627113584Ssimokawa if (slen > len) { 2628113584Ssimokawa if (firewire_debug) 2629113584Ssimokawa printf("splitted header\n"); 2630113584Ssimokawa return(-slen); 2631103285Sikob } 2632113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2633113584Ssimokawa for(i = 0; i < slen/4; i ++) 2634113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2635113584Ssimokawa#endif 2636113584Ssimokawa return(slen); 2637103285Sikob} 2638103285Sikob 2639113584Ssimokawa#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2640103285Sikobstatic int 2641113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2642103285Sikob{ 2643113584Ssimokawa int r; 2644103285Sikob 2645103285Sikob switch(fp->mode.common.tcode){ 2646103285Sikob case FWTCODE_RREQQ: 2647110798Ssimokawa r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2648110798Ssimokawa break; 2649103285Sikob case FWTCODE_WRES: 2650110798Ssimokawa r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2651110798Ssimokawa break; 2652103285Sikob case FWTCODE_WREQQ: 2653110798Ssimokawa r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2654110798Ssimokawa break; 2655103285Sikob case FWTCODE_RREQB: 2656110798Ssimokawa r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2657110798Ssimokawa break; 2658103285Sikob case FWTCODE_RRESQ: 2659110798Ssimokawa r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2660110798Ssimokawa break; 2661103285Sikob case FWTCODE_WREQB: 2662110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2663103285Sikob + sizeof(u_int32_t); 2664110798Ssimokawa break; 2665103285Sikob case FWTCODE_LREQ: 2666110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2667103285Sikob + sizeof(u_int32_t); 2668110798Ssimokawa break; 2669103285Sikob case FWTCODE_RRESB: 2670110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2671103285Sikob + sizeof(u_int32_t); 2672110798Ssimokawa break; 2673103285Sikob case FWTCODE_LRES: 2674110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2675103285Sikob + sizeof(u_int32_t); 2676110798Ssimokawa break; 2677103285Sikob case FWOHCITCODE_PHY: 2678110798Ssimokawa r = 16; 2679110798Ssimokawa break; 2680110798Ssimokawa default: 2681110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2682110798Ssimokawa fp->mode.common.tcode); 2683110798Ssimokawa r = 0; 2684103285Sikob } 2685110798Ssimokawa if (r > dbch->xferq.psize) { 2686110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2687110798Ssimokawa /* panic ? */ 2688110798Ssimokawa } 2689110798Ssimokawa return r; 2690103285Sikob} 2691103285Sikob 2692106790Ssimokawastatic void 2693113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2694113584Ssimokawa{ 2695113584Ssimokawa volatile struct fwohcidb *db = &db_tr->db[0]; 2696113584Ssimokawa 2697113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2698113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2699113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2700113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2701113584Ssimokawa dbch->bottom = db_tr; 2702113584Ssimokawa} 2703113584Ssimokawa 2704113584Ssimokawastatic void 2705106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2706103285Sikob{ 2707103285Sikob struct fwohcidb_tr *db_tr; 2708113584Ssimokawa struct iovec vec[2]; 2709113584Ssimokawa struct fw_pkt pktbuf; 2710113584Ssimokawa int nvec; 2711103285Sikob struct fw_pkt *fp; 2712103285Sikob u_int8_t *ld; 2713113584Ssimokawa u_int32_t stat, off, status; 2714103285Sikob u_int spd; 2715113584Ssimokawa int len, plen, hlen, pcnt, offset; 2716103285Sikob int s; 2717103285Sikob caddr_t buf; 2718103285Sikob int resCount; 2719103285Sikob 2720103285Sikob if(&sc->arrq == dbch){ 2721103285Sikob off = OHCI_ARQOFF; 2722103285Sikob }else if(&sc->arrs == dbch){ 2723103285Sikob off = OHCI_ARSOFF; 2724103285Sikob }else{ 2725103285Sikob return; 2726103285Sikob } 2727103285Sikob 2728103285Sikob s = splfw(); 2729103285Sikob db_tr = dbch->top; 2730103285Sikob pcnt = 0; 2731103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2732113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2733113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2734113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2735113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2736113584Ssimokawa#if 0 2737113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2738113584Ssimokawa#endif 2739113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2740113584Ssimokawa len = dbch->xferq.psize - resCount; 2741113584Ssimokawa ld = (u_int8_t *)db_tr->buf; 2742113584Ssimokawa if (dbch->pdb_tr == NULL) { 2743113584Ssimokawa len -= dbch->buf_offset; 2744113584Ssimokawa ld += dbch->buf_offset; 2745113584Ssimokawa } 2746113584Ssimokawa if (len > 0) 2747113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2748113584Ssimokawa BUS_DMASYNC_POSTREAD); 2749103285Sikob while (len > 0 ) { 2750106789Ssimokawa if (count >= 0 && count-- == 0) 2751106789Ssimokawa goto out; 2752113584Ssimokawa if(dbch->pdb_tr != NULL){ 2753113584Ssimokawa /* we have a fragment in previous buffer */ 2754113584Ssimokawa int rlen; 2755103285Sikob 2756113584Ssimokawa offset = dbch->buf_offset; 2757113584Ssimokawa if (offset < 0) 2758113584Ssimokawa offset = - offset; 2759113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2760113584Ssimokawa rlen = dbch->xferq.psize - offset; 2761113584Ssimokawa if (firewire_debug) 2762113584Ssimokawa printf("rlen=%d, offset=%d\n", 2763113584Ssimokawa rlen, dbch->buf_offset); 2764113584Ssimokawa if (dbch->buf_offset < 0) { 2765113584Ssimokawa /* splitted in header, pull up */ 2766113584Ssimokawa char *p; 2767113584Ssimokawa 2768113584Ssimokawa p = (char *)&pktbuf; 2769113584Ssimokawa bcopy(buf, p, rlen); 2770113584Ssimokawa p += rlen; 2771113584Ssimokawa /* this must be too long but harmless */ 2772113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2773113584Ssimokawa if (rlen < 0) 2774113584Ssimokawa printf("why rlen < 0\n"); 2775113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2776103285Sikob ld += rlen; 2777103285Sikob len -= rlen; 2778113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2779113584Ssimokawa if (hlen < 0) { 2780113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2781113584Ssimokawa } 2782113584Ssimokawa offset = sizeof(pktbuf); 2783113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2784113584Ssimokawa vec[0].iov_len = offset; 2785113584Ssimokawa } else { 2786113584Ssimokawa /* splitted in payload */ 2787113584Ssimokawa offset = rlen; 2788113584Ssimokawa vec[0].iov_base = buf; 2789113584Ssimokawa vec[0].iov_len = rlen; 2790103285Sikob } 2791113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2792113584Ssimokawa nvec = 1; 2793113584Ssimokawa } else { 2794113584Ssimokawa /* no fragment in previous buffer */ 2795103285Sikob fp=(struct fw_pkt *)ld; 2796113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2797113584Ssimokawa if (hlen == 0) 2798113584Ssimokawa /* XXX need reset */ 2799103285Sikob goto out; 2800113584Ssimokawa if (hlen < 0) { 2801113584Ssimokawa dbch->pdb_tr = db_tr; 2802113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2803113584Ssimokawa /* sanity check */ 2804113584Ssimokawa if (resCount != 0) 2805113584Ssimokawa printf("resCount != 0 !?\n"); 2806113584Ssimokawa goto out; 2807103285Sikob } 2808113584Ssimokawa offset = 0; 2809113584Ssimokawa nvec = 0; 2810113584Ssimokawa } 2811113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2812113584Ssimokawa if (plen < 0) { 2813113584Ssimokawa /* minimum header size + trailer 2814113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2815113584Ssimokawa printf("plen is negative! offset=%d\n", offset); 2816113584Ssimokawa goto out; 2817113584Ssimokawa } 2818113584Ssimokawa if (plen > 0) { 2819113584Ssimokawa len -= plen; 2820113584Ssimokawa if (len < 0) { 2821113584Ssimokawa dbch->pdb_tr = db_tr; 2822113584Ssimokawa if (firewire_debug) 2823113584Ssimokawa printf("splitted payload\n"); 2824113584Ssimokawa /* sanity check */ 2825113584Ssimokawa if (resCount != 0) 2826113584Ssimokawa printf("resCount != 0 !?\n"); 2827113584Ssimokawa goto out; 2828103285Sikob } 2829113584Ssimokawa vec[nvec].iov_base = ld; 2830113584Ssimokawa vec[nvec].iov_len = plen; 2831113584Ssimokawa nvec ++; 2832103285Sikob ld += plen; 2833103285Sikob } 2834113584Ssimokawa dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2835113584Ssimokawa if (nvec == 0) 2836113584Ssimokawa printf("nvec == 0\n"); 2837113584Ssimokawa 2838103285Sikob/* DMA result-code will be written at the tail of packet */ 2839113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2840113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2841113584Ssimokawa#else 2842113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2843113584Ssimokawa#endif 2844110577Ssimokawa#if 0 2845113584Ssimokawa printf("plen: %d, stat %x\n", plen ,stat); 2846103285Sikob#endif 2847113584Ssimokawa spd = (stat >> 5) & 0x3; 2848113584Ssimokawa stat &= 0x1f; 2849113584Ssimokawa switch(stat){ 2850113584Ssimokawa case FWOHCIEV_ACKPEND: 2851113584Ssimokawa#if 0 2852113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2853113584Ssimokawa#endif 2854113584Ssimokawa /* fall through */ 2855113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2856113584Ssimokawa if ((vec[nvec-1].iov_len -= 2857113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2858113584Ssimokawa nvec--; 2859113584Ssimokawa fw_rcv(&sc->fc, vec, nvec, 0, spd); 2860103285Sikob break; 2861113584Ssimokawa case FWOHCIEV_BUSRST: 2862113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2863113584Ssimokawa printf("got BUSRST packet!?\n"); 2864113584Ssimokawa break; 2865113584Ssimokawa default: 2866113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2867103285Sikob#if 0 /* XXX */ 2868113584Ssimokawa goto out; 2869103285Sikob#endif 2870113584Ssimokawa break; 2871103285Sikob } 2872103285Sikob pcnt ++; 2873113584Ssimokawa if (dbch->pdb_tr != NULL) { 2874113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2875113584Ssimokawa dbch->pdb_tr = NULL; 2876113584Ssimokawa } 2877113584Ssimokawa 2878113584Ssimokawa } 2879103285Sikobout: 2880103285Sikob if (resCount == 0) { 2881103285Sikob /* done on this buffer */ 2882113584Ssimokawa if (dbch->pdb_tr == NULL) { 2883113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2884113584Ssimokawa dbch->buf_offset = 0; 2885113584Ssimokawa } else 2886113584Ssimokawa if (dbch->pdb_tr != db_tr) 2887113584Ssimokawa printf("pdb_tr != db_tr\n"); 2888103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2889113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2890113584Ssimokawa >> OHCI_STATUS_SHIFT; 2891113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2892113584Ssimokawa & OHCI_COUNT_MASK; 2893113584Ssimokawa /* XXX check buffer overrun */ 2894103285Sikob dbch->top = db_tr; 2895103285Sikob } else { 2896103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2897103285Sikob break; 2898103285Sikob } 2899103285Sikob /* XXX make sure DMA is not dead */ 2900103285Sikob } 2901103285Sikob#if 0 2902103285Sikob if (pcnt < 1) 2903103285Sikob printf("fwohci_arcv: no packets\n"); 2904103285Sikob#endif 2905103285Sikob splx(s); 2906103285Sikob} 2907