fwohci.c revision 118820
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 118820 2003-08-12 13:01:27Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#include <dev/firewire/firewire.h> 62#include <dev/firewire/firewirereg.h> 63#include <dev/firewire/fwdma.h> 64#include <dev/firewire/fwohcireg.h> 65#include <dev/firewire/fwohcivar.h> 66#include <dev/firewire/firewire_phy.h> 67 68#undef OHCI_DEBUG 69 70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71 "STOR","LOAD","NOP ","STOP",}; 72 73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74 "UNDEF","REG","SYS","DEV"}; 75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76char fwohcicode[32][0x20]={ 77 "No stat","Undef","long","miss Ack err", 78 "underrun","overrun","desc err", "data read err", 79 "data write err","bus reset","timeout","tcode err", 80 "Undef","Undef","unknown event","flushed", 81 "Undef","ack complete","ack pend","Undef", 82 "ack busy_X","ack busy_A","ack busy_B","Undef", 83 "Undef","Undef","Undef","ack tardy", 84 "Undef","ack data_err","ack type_err",""}; 85 86#define MAX_SPEED 3 87extern char linkspeed[][0x10]; 88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89 90static struct tcode_info tinfo[] = { 91/* hdr_len block flag*/ 92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94/* 2 WRES */ {12, FWTI_RES}, 95/* 3 XXX */ { 0, 0}, 96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98/* 6 RRESQ */ {16, FWTI_RES}, 99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100/* 8 CYCS */ { 0, 0}, 101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104/* c XXX */ { 0, 0}, 105/* d XXX */ { 0, 0}, 106/* e PHY */ {12, FWTI_REQ}, 107/* f XXX */ { 0, 0} 108}; 109 110#define OHCI_WRITE_SIGMASK 0xffff0000 111#define OHCI_READ_SIGMASK 0xffff0000 112 113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115 116static void fwohci_ibr __P((struct firewire_comm *)); 117static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118static void fwohci_db_free __P((struct fwohci_dbch *)); 119static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121static void fwohci_start_atq __P((struct firewire_comm *)); 122static void fwohci_start_ats __P((struct firewire_comm *)); 123static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128static int fwohci_irx_enable __P((struct firewire_comm *, int)); 129static int fwohci_irx_disable __P((struct firewire_comm *, int)); 130#if BYTE_ORDER == BIG_ENDIAN 131static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132#endif 133static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134static int fwohci_itx_disable __P((struct firewire_comm *, int)); 135static void fwohci_timeout __P((void *)); 136static void fwohci_set_intr __P((struct firewire_comm *, int)); 137 138static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140static void dump_db __P((struct fwohci_softc *, u_int32_t)); 141static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147#if FWOHCI_TASKQUEUE 148static void fwohci_complete(void *, int); 149#endif 150 151/* 152 * memory allocated for DMA programs 153 */ 154#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155 156/* #define NDB 1024 */ 157#define NDB FWMAXQUEUE 158#define NDVDB (DVBUF * NDB) 159 160#define OHCI_VERSION 0x00 161#define OHCI_ATRETRY 0x08 162#define OHCI_CROMHDR 0x18 163#define OHCI_BUS_OPT 0x20 164#define OHCI_BUSIRMC (1 << 31) 165#define OHCI_BUSCMC (1 << 30) 166#define OHCI_BUSISC (1 << 29) 167#define OHCI_BUSBMC (1 << 28) 168#define OHCI_BUSPMC (1 << 27) 169#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 170 OHCI_BUSBMC | OHCI_BUSPMC 171 172#define OHCI_EUID_HI 0x24 173#define OHCI_EUID_LO 0x28 174 175#define OHCI_CROMPTR 0x34 176#define OHCI_HCCCTL 0x50 177#define OHCI_HCCCTLCLR 0x54 178#define OHCI_AREQHI 0x100 179#define OHCI_AREQHICLR 0x104 180#define OHCI_AREQLO 0x108 181#define OHCI_AREQLOCLR 0x10c 182#define OHCI_PREQHI 0x110 183#define OHCI_PREQHICLR 0x114 184#define OHCI_PREQLO 0x118 185#define OHCI_PREQLOCLR 0x11c 186#define OHCI_PREQUPPER 0x120 187 188#define OHCI_SID_BUF 0x64 189#define OHCI_SID_CNT 0x68 190#define OHCI_SID_ERR (1 << 31) 191#define OHCI_SID_CNT_MASK 0xffc 192 193#define OHCI_IT_STAT 0x90 194#define OHCI_IT_STATCLR 0x94 195#define OHCI_IT_MASK 0x98 196#define OHCI_IT_MASKCLR 0x9c 197 198#define OHCI_IR_STAT 0xa0 199#define OHCI_IR_STATCLR 0xa4 200#define OHCI_IR_MASK 0xa8 201#define OHCI_IR_MASKCLR 0xac 202 203#define OHCI_LNKCTL 0xe0 204#define OHCI_LNKCTLCLR 0xe4 205 206#define OHCI_PHYACCESS 0xec 207#define OHCI_CYCLETIMER 0xf0 208 209#define OHCI_DMACTL(off) (off) 210#define OHCI_DMACTLCLR(off) (off + 4) 211#define OHCI_DMACMD(off) (off + 0xc) 212#define OHCI_DMAMATCH(off) (off + 0x10) 213 214#define OHCI_ATQOFF 0x180 215#define OHCI_ATQCTL OHCI_ATQOFF 216#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 217#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 218#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 219 220#define OHCI_ATSOFF 0x1a0 221#define OHCI_ATSCTL OHCI_ATSOFF 222#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 223#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 224#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 225 226#define OHCI_ARQOFF 0x1c0 227#define OHCI_ARQCTL OHCI_ARQOFF 228#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 229#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 230#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 231 232#define OHCI_ARSOFF 0x1e0 233#define OHCI_ARSCTL OHCI_ARSOFF 234#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 235#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 236#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 237 238#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 239#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 240#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 241#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 242 243#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 244#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 245#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 246#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 247#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 248 249d_ioctl_t fwohci_ioctl; 250 251/* 252 * Communication with PHY device 253 */ 254static u_int32_t 255fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 256{ 257 u_int32_t fun; 258 259 addr &= 0xf; 260 data &= 0xff; 261 262 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 263 OWRITE(sc, OHCI_PHYACCESS, fun); 264 DELAY(100); 265 266 return(fwphy_rddata( sc, addr)); 267} 268 269static u_int32_t 270fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 271{ 272 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 273 int i; 274 u_int32_t bm; 275 276#define OHCI_CSR_DATA 0x0c 277#define OHCI_CSR_COMP 0x10 278#define OHCI_CSR_CONT 0x14 279#define OHCI_BUS_MANAGER_ID 0 280 281 OWRITE(sc, OHCI_CSR_DATA, node); 282 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 283 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 284 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 285 DELAY(10); 286 bm = OREAD(sc, OHCI_CSR_DATA); 287 if((bm & 0x3f) == 0x3f) 288 bm = node; 289 if (bootverbose) 290 device_printf(sc->fc.dev, 291 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 292 293 return(bm); 294} 295 296static u_int32_t 297fwphy_rddata(struct fwohci_softc *sc, u_int addr) 298{ 299 u_int32_t fun, stat; 300 u_int i, retry = 0; 301 302 addr &= 0xf; 303#define MAX_RETRY 100 304again: 305 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 306 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 307 OWRITE(sc, OHCI_PHYACCESS, fun); 308 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 309 fun = OREAD(sc, OHCI_PHYACCESS); 310 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 311 break; 312 DELAY(100); 313 } 314 if(i >= MAX_RETRY) { 315 if (bootverbose) 316 device_printf(sc->fc.dev, "phy read failed(1).\n"); 317 if (++retry < MAX_RETRY) { 318 DELAY(100); 319 goto again; 320 } 321 } 322 /* Make sure that SCLK is started */ 323 stat = OREAD(sc, FWOHCI_INTSTAT); 324 if ((stat & OHCI_INT_REG_FAIL) != 0 || 325 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 326 if (bootverbose) 327 device_printf(sc->fc.dev, "phy read failed(2).\n"); 328 if (++retry < MAX_RETRY) { 329 DELAY(100); 330 goto again; 331 } 332 } 333 if (bootverbose || retry >= MAX_RETRY) 334 device_printf(sc->fc.dev, 335 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 336#undef MAX_RETRY 337 return((fun >> PHYDEV_RDDATA )& 0xff); 338} 339/* Device specific ioctl. */ 340int 341fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 342{ 343 struct firewire_softc *sc; 344 struct fwohci_softc *fc; 345 int unit = DEV2UNIT(dev); 346 int err = 0; 347 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 348 u_int32_t *dmach = (u_int32_t *) data; 349 350 sc = devclass_get_softc(firewire_devclass, unit); 351 if(sc == NULL){ 352 return(EINVAL); 353 } 354 fc = (struct fwohci_softc *)sc->fc; 355 356 if (!data) 357 return(EINVAL); 358 359 switch (cmd) { 360 case FWOHCI_WRREG: 361#define OHCI_MAX_REG 0x800 362 if(reg->addr <= OHCI_MAX_REG){ 363 OWRITE(fc, reg->addr, reg->data); 364 reg->data = OREAD(fc, reg->addr); 365 }else{ 366 err = EINVAL; 367 } 368 break; 369 case FWOHCI_RDREG: 370 if(reg->addr <= OHCI_MAX_REG){ 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376/* Read DMA descriptors for debug */ 377 case DUMPDMA: 378 if(*dmach <= OHCI_MAX_DMA_CH ){ 379 dump_dma(fc, *dmach); 380 dump_db(fc, *dmach); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385 default: 386 break; 387 } 388 return err; 389} 390 391static int 392fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 393{ 394 u_int32_t reg, reg2; 395 int e1394a = 1; 396/* 397 * probe PHY parameters 398 * 0. to prove PHY version, whether compliance of 1394a. 399 * 1. to probe maximum speed supported by the PHY and 400 * number of port supported by core-logic. 401 * It is not actually available port on your PC . 402 */ 403 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 404 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 405 406 if((reg >> 5) != 7 ){ 407 sc->fc.mode &= ~FWPHYASYST; 408 sc->fc.nport = reg & FW_PHY_NP; 409 sc->fc.speed = reg & FW_PHY_SPD >> 6; 410 if (sc->fc.speed > MAX_SPEED) { 411 device_printf(dev, "invalid speed %d (fixed to %d).\n", 412 sc->fc.speed, MAX_SPEED); 413 sc->fc.speed = MAX_SPEED; 414 } 415 device_printf(dev, 416 "Phy 1394 only %s, %d ports.\n", 417 linkspeed[sc->fc.speed], sc->fc.nport); 418 }else{ 419 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 420 sc->fc.mode |= FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394a available %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 432 /* check programPhyEnable */ 433 reg2 = fwphy_rddata(sc, 5); 434#if 0 435 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 436#else /* XXX force to enable 1394a */ 437 if (e1394a) { 438#endif 439 if (bootverbose) 440 device_printf(dev, 441 "Enable 1394a Enhancements\n"); 442 /* enable EAA EMC */ 443 reg2 |= 0x03; 444 /* set aPhyEnhanceEnable */ 445 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 446 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 447 } else { 448 /* for safe */ 449 reg2 &= ~0x83; 450 } 451 reg2 = fwphy_wrdata(sc, 5, reg2); 452 } 453 454 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 455 if((reg >> 5) == 7 ){ 456 reg = fwphy_rddata(sc, 4); 457 reg |= 1 << 6; 458 fwphy_wrdata(sc, 4, reg); 459 reg = fwphy_rddata(sc, 4); 460 } 461 return 0; 462} 463 464 465void 466fwohci_reset(struct fwohci_softc *sc, device_t dev) 467{ 468 int i, max_rec, speed; 469 u_int32_t reg, reg2; 470 struct fwohcidb_tr *db_tr; 471 472 /* Disable interrupt */ 473 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 474 475 /* Now stopping all DMA channel */ 476 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 477 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 478 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 479 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 480 481 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 482 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 483 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 484 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 485 } 486 487 /* FLUSH FIFO and reset Transmitter/Reciever */ 488 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 489 if (bootverbose) 490 device_printf(dev, "resetting OHCI..."); 491 i = 0; 492 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 493 if (i++ > 100) break; 494 DELAY(1000); 495 } 496 if (bootverbose) 497 printf("done (loop=%d)\n", i); 498 499 /* Probe phy */ 500 fwohci_probe_phy(sc, dev); 501 502 /* Probe link */ 503 reg = OREAD(sc, OHCI_BUS_OPT); 504 reg2 = reg | OHCI_BUSFNC; 505 max_rec = (reg & 0x0000f000) >> 12; 506 speed = (reg & 0x00000007); 507 device_printf(dev, "Link %s, max_rec %d bytes.\n", 508 linkspeed[speed], MAXREC(max_rec)); 509 /* XXX fix max_rec */ 510 sc->fc.maxrec = sc->fc.speed + 8; 511 if (max_rec != sc->fc.maxrec) { 512 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 513 device_printf(dev, "max_rec %d -> %d\n", 514 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 515 } 516 if (bootverbose) 517 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 518 OWRITE(sc, OHCI_BUS_OPT, reg2); 519 520 /* Initialize registers */ 521 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 522 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 523 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 524 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 525 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 526 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 527 fw_busreset(&sc->fc); 528 529 /* Enable link */ 530 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 531 532 /* Force to start async RX DMA */ 533 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 534 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 535 fwohci_rx_enable(sc, &sc->arrq); 536 fwohci_rx_enable(sc, &sc->arrs); 537 538 /* Initialize async TX */ 539 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 540 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 541 542 /* AT Retries */ 543 OWRITE(sc, FWOHCI_RETRY, 544 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 545 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 546 547 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 548 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 549 sc->atrq.bottom = sc->atrq.top; 550 sc->atrs.bottom = sc->atrs.top; 551 552 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 553 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 554 db_tr->xfer = NULL; 555 } 556 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 558 db_tr->xfer = NULL; 559 } 560 561 562 /* Enable interrupt */ 563 OWRITE(sc, FWOHCI_INTMASK, 564 OHCI_INT_ERR | OHCI_INT_PHY_SID 565 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 566 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 567 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 568 fwohci_set_intr(&sc->fc, 1); 569 570} 571 572int 573fwohci_init(struct fwohci_softc *sc, device_t dev) 574{ 575 int i; 576 u_int32_t reg; 577 u_int8_t ui[8]; 578 579#if FWOHCI_TASKQUEUE 580 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 581#endif 582 583 reg = OREAD(sc, OHCI_VERSION); 584 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586 587 if (((reg>>16) & 0xff) < 1) { 588 device_printf(dev, "invalid OHCI version\n"); 589 return (ENXIO); 590 } 591 592/* Available Isochrounous DMA channel probe */ 593 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 595 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 596 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 597 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 598 for (i = 0; i < 0x20; i++) 599 if ((reg & (1 << i)) == 0) 600 break; 601 sc->fc.nisodma = i; 602 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 603 if (i == 0) 604 return (ENXIO); 605 606 sc->fc.arq = &sc->arrq.xferq; 607 sc->fc.ars = &sc->arrs.xferq; 608 sc->fc.atq = &sc->atrq.xferq; 609 sc->fc.ats = &sc->atrs.xferq; 610 611 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 612 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 613 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 614 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 615 616 sc->arrq.xferq.start = NULL; 617 sc->arrs.xferq.start = NULL; 618 sc->atrq.xferq.start = fwohci_start_atq; 619 sc->atrs.xferq.start = fwohci_start_ats; 620 621 sc->arrq.xferq.buf = NULL; 622 sc->arrs.xferq.buf = NULL; 623 sc->atrq.xferq.buf = NULL; 624 sc->atrs.xferq.buf = NULL; 625 626 sc->arrq.xferq.dmach = -1; 627 sc->arrs.xferq.dmach = -1; 628 sc->atrq.xferq.dmach = -1; 629 sc->atrs.xferq.dmach = -1; 630 631 sc->arrq.ndesc = 1; 632 sc->arrs.ndesc = 1; 633 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 634 sc->atrs.ndesc = 2; 635 636 sc->arrq.ndb = NDB; 637 sc->arrs.ndb = NDB / 2; 638 sc->atrq.ndb = NDB; 639 sc->atrs.ndb = NDB / 2; 640 641 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 642 sc->fc.it[i] = &sc->it[i].xferq; 643 sc->fc.ir[i] = &sc->ir[i].xferq; 644 sc->it[i].xferq.dmach = i; 645 sc->ir[i].xferq.dmach = i; 646 sc->it[i].ndb = 0; 647 sc->ir[i].ndb = 0; 648 } 649 650 sc->fc.tcode = tinfo; 651 sc->fc.dev = dev; 652 653 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 654 &sc->crom_dma, BUS_DMA_WAITOK); 655 if(sc->fc.config_rom == NULL){ 656 device_printf(dev, "config_rom alloc failed."); 657 return ENOMEM; 658 } 659 660#if 0 661 bzero(&sc->fc.config_rom[0], CROMSIZE); 662 sc->fc.config_rom[1] = 0x31333934; 663 sc->fc.config_rom[2] = 0xf000a002; 664 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 665 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 666 sc->fc.config_rom[5] = 0; 667 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 668 669 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 670#endif 671 672 673/* SID recieve buffer must allign 2^11 */ 674#define OHCI_SIDSIZE (1 << 11) 675 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 676 &sc->sid_dma, BUS_DMA_WAITOK); 677 if (sc->sid_buf == NULL) { 678 device_printf(dev, "sid_buf alloc failed."); 679 return ENOMEM; 680 } 681 682 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 683 &sc->dummy_dma, BUS_DMA_WAITOK); 684 685 if (sc->dummy_dma.v_addr == NULL) { 686 device_printf(dev, "dummy_dma alloc failed."); 687 return ENOMEM; 688 } 689 690 fwohci_db_init(sc, &sc->arrq); 691 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 692 return ENOMEM; 693 694 fwohci_db_init(sc, &sc->arrs); 695 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 696 return ENOMEM; 697 698 fwohci_db_init(sc, &sc->atrq); 699 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 700 return ENOMEM; 701 702 fwohci_db_init(sc, &sc->atrs); 703 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 704 return ENOMEM; 705 706 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 707 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 708 for( i = 0 ; i < 8 ; i ++) 709 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 710 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 711 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 712 713 sc->fc.ioctl = fwohci_ioctl; 714 sc->fc.cyctimer = fwohci_cyctimer; 715 sc->fc.set_bmr = fwohci_set_bus_manager; 716 sc->fc.ibr = fwohci_ibr; 717 sc->fc.irx_enable = fwohci_irx_enable; 718 sc->fc.irx_disable = fwohci_irx_disable; 719 720 sc->fc.itx_enable = fwohci_itxbuf_enable; 721 sc->fc.itx_disable = fwohci_itx_disable; 722#if BYTE_ORDER == BIG_ENDIAN 723 sc->fc.irx_post = fwohci_irx_post; 724#else 725 sc->fc.irx_post = NULL; 726#endif 727 sc->fc.itx_post = NULL; 728 sc->fc.timeout = fwohci_timeout; 729 sc->fc.poll = fwohci_poll; 730 sc->fc.set_intr = fwohci_set_intr; 731 732 sc->intmask = sc->irstat = sc->itstat = 0; 733 734 fw_init(&sc->fc); 735 fwohci_reset(sc, dev); 736 737 return 0; 738} 739 740void 741fwohci_timeout(void *arg) 742{ 743 struct fwohci_softc *sc; 744 745 sc = (struct fwohci_softc *)arg; 746} 747 748u_int32_t 749fwohci_cyctimer(struct firewire_comm *fc) 750{ 751 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 752 return(OREAD(sc, OHCI_CYCLETIMER)); 753} 754 755int 756fwohci_detach(struct fwohci_softc *sc, device_t dev) 757{ 758 int i; 759 760 if (sc->sid_buf != NULL) 761 fwdma_free(&sc->fc, &sc->sid_dma); 762 if (sc->fc.config_rom != NULL) 763 fwdma_free(&sc->fc, &sc->crom_dma); 764 765 fwohci_db_free(&sc->arrq); 766 fwohci_db_free(&sc->arrs); 767 768 fwohci_db_free(&sc->atrq); 769 fwohci_db_free(&sc->atrs); 770 771 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 772 fwohci_db_free(&sc->it[i]); 773 fwohci_db_free(&sc->ir[i]); 774 } 775 776 return 0; 777} 778 779#define LAST_DB(dbtr, db) do { \ 780 struct fwohcidb_tr *_dbtr = (dbtr); \ 781 int _cnt = _dbtr->dbcnt; \ 782 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 783} while (0) 784 785static void 786fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 787{ 788 struct fwohcidb_tr *db_tr; 789 volatile struct fwohcidb *db; 790 bus_dma_segment_t *s; 791 int i; 792 793 db_tr = (struct fwohcidb_tr *)arg; 794 db = &db_tr->db[db_tr->dbcnt]; 795 if (error) { 796 if (firewire_debug || error != EFBIG) 797 printf("fwohci_execute_db: error=%d\n", error); 798 return; 799 } 800 for (i = 0; i < nseg; i++) { 801 s = &segs[i]; 802 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 803 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 804 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 805 db++; 806 db_tr->dbcnt++; 807 } 808} 809 810static void 811fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 812 bus_size_t size, int error) 813{ 814 fwohci_execute_db(arg, segs, nseg, error); 815} 816 817static void 818fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 819{ 820 int i, s; 821 int tcode, hdr_len, pl_off, pl_len; 822 int fsegment = -1; 823 u_int32_t off; 824 struct fw_xfer *xfer; 825 struct fw_pkt *fp; 826 volatile struct fwohci_txpkthdr *ohcifp; 827 struct fwohcidb_tr *db_tr; 828 volatile struct fwohcidb *db; 829 struct tcode_info *info; 830 static int maxdesc=0; 831 832 if(&sc->atrq == dbch){ 833 off = OHCI_ATQOFF; 834 }else if(&sc->atrs == dbch){ 835 off = OHCI_ATSOFF; 836 }else{ 837 return; 838 } 839 840 if (dbch->flags & FWOHCI_DBCH_FULL) 841 return; 842 843 s = splfw(); 844 db_tr = dbch->top; 845txloop: 846 xfer = STAILQ_FIRST(&dbch->xferq.q); 847 if(xfer == NULL){ 848 goto kick; 849 } 850 if(dbch->xferq.queued == 0 ){ 851 device_printf(sc->fc.dev, "TX queue empty\n"); 852 } 853 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 854 db_tr->xfer = xfer; 855 xfer->state = FWXF_START; 856 857 fp = (struct fw_pkt *)xfer->send.buf; 858 tcode = fp->mode.common.tcode; 859 860 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 861 info = &tinfo[tcode]; 862 hdr_len = pl_off = info->hdr_len; 863 for( i = 0 ; i < pl_off ; i+= 4){ 864 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 865 } 866 ohcifp->mode.common.spd = xfer->spd; 867 if (tcode == FWTCODE_STREAM ){ 868 hdr_len = 8; 869 ohcifp->mode.stream.len = fp->mode.stream.len; 870 } else if (tcode == FWTCODE_PHY) { 871 hdr_len = 12; 872 ohcifp->mode.ld[1] = fp->mode.ld[1]; 873 ohcifp->mode.ld[2] = fp->mode.ld[2]; 874 ohcifp->mode.common.spd = 0; 875 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 876 } else { 877 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 878 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 879 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 880 } 881 db = &db_tr->db[0]; 882 FWOHCI_DMA_WRITE(db->db.desc.cmd, 883 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 884 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 885/* Specify bound timer of asy. responce */ 886 if(&sc->atrs == dbch){ 887 FWOHCI_DMA_WRITE(db->db.desc.res, 888 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 889 } 890#if BYTE_ORDER == BIG_ENDIAN 891 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 892 hdr_len = 12; 893 for (i = 0; i < hdr_len/4; i ++) 894 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 895#endif 896 897again: 898 db_tr->dbcnt = 2; 899 db = &db_tr->db[db_tr->dbcnt]; 900 pl_len = xfer->send.len - pl_off; 901 if (pl_len > 0) { 902 int err; 903 /* handle payload */ 904 if (xfer->mbuf == NULL) { 905 caddr_t pl_addr; 906 907 pl_addr = xfer->send.buf + pl_off; 908 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 909 pl_addr, pl_len, 910 fwohci_execute_db, db_tr, 911 /*flags*/0); 912 } else { 913 /* XXX we can handle only 6 (=8-2) mbuf chains */ 914 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 915 xfer->mbuf, 916 fwohci_execute_db2, db_tr, 917 /* flags */0); 918 if (err == EFBIG) { 919 struct mbuf *m0; 920 921 if (firewire_debug) 922 device_printf(sc->fc.dev, "EFBIG.\n"); 923 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 924 if (m0 != NULL) { 925 m_copydata(xfer->mbuf, 0, 926 xfer->mbuf->m_pkthdr.len, 927 mtod(m0, caddr_t)); 928 m0->m_len = m0->m_pkthdr.len = 929 xfer->mbuf->m_pkthdr.len; 930 m_freem(xfer->mbuf); 931 xfer->mbuf = m0; 932 goto again; 933 } 934 device_printf(sc->fc.dev, "m_getcl failed.\n"); 935 } 936 } 937 if (err) 938 printf("dmamap_load: err=%d\n", err); 939 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 940 BUS_DMASYNC_PREWRITE); 941#if 0 /* OHCI_OUTPUT_MODE == 0 */ 942 for (i = 2; i < db_tr->dbcnt; i++) 943 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 944 OHCI_OUTPUT_MORE); 945#endif 946 } 947 if (maxdesc < db_tr->dbcnt) { 948 maxdesc = db_tr->dbcnt; 949 if (bootverbose) 950 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 951 } 952 /* last db */ 953 LAST_DB(db_tr, db); 954 FWOHCI_DMA_SET(db->db.desc.cmd, 955 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 956 FWOHCI_DMA_WRITE(db->db.desc.depend, 957 STAILQ_NEXT(db_tr, link)->bus_addr); 958 959 if(fsegment == -1 ) 960 fsegment = db_tr->dbcnt; 961 if (dbch->pdb_tr != NULL) { 962 LAST_DB(dbch->pdb_tr, db); 963 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 964 } 965 dbch->pdb_tr = db_tr; 966 db_tr = STAILQ_NEXT(db_tr, link); 967 if(db_tr != dbch->bottom){ 968 goto txloop; 969 } else { 970 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 971 dbch->flags |= FWOHCI_DBCH_FULL; 972 } 973kick: 974 /* kick asy q */ 975 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 976 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 977 978 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 979 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 980 } else { 981 if (bootverbose) 982 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 983 OREAD(sc, OHCI_DMACTL(off))); 984 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 985 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 986 dbch->xferq.flag |= FWXFERQ_RUNNING; 987 } 988 989 dbch->top = db_tr; 990 splx(s); 991 return; 992} 993 994static void 995fwohci_start_atq(struct firewire_comm *fc) 996{ 997 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 998 fwohci_start( sc, &(sc->atrq)); 999 return; 1000} 1001 1002static void 1003fwohci_start_ats(struct firewire_comm *fc) 1004{ 1005 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1006 fwohci_start( sc, &(sc->atrs)); 1007 return; 1008} 1009 1010void 1011fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1012{ 1013 int s, ch, err = 0; 1014 struct fwohcidb_tr *tr; 1015 volatile struct fwohcidb *db; 1016 struct fw_xfer *xfer; 1017 u_int32_t off; 1018 u_int stat, status; 1019 int packets; 1020 struct firewire_comm *fc = (struct firewire_comm *)sc; 1021 1022 if(&sc->atrq == dbch){ 1023 off = OHCI_ATQOFF; 1024 ch = ATRQ_CH; 1025 }else if(&sc->atrs == dbch){ 1026 off = OHCI_ATSOFF; 1027 ch = ATRS_CH; 1028 }else{ 1029 return; 1030 } 1031 s = splfw(); 1032 tr = dbch->bottom; 1033 packets = 0; 1034 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1035 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1036 while(dbch->xferq.queued > 0){ 1037 LAST_DB(tr, db); 1038 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1039 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1040 if (fc->status != FWBUSRESET) 1041 /* maybe out of order?? */ 1042 goto out; 1043 } 1044 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1045 BUS_DMASYNC_POSTWRITE); 1046 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1047#if 0 1048 dump_db(sc, ch); 1049#endif 1050 if(status & OHCI_CNTL_DMA_DEAD) { 1051 /* Stop DMA */ 1052 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1053 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1054 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1055 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1056 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1057 } 1058 stat = status & FWOHCIEV_MASK; 1059 switch(stat){ 1060 case FWOHCIEV_ACKPEND: 1061 case FWOHCIEV_ACKCOMPL: 1062 err = 0; 1063 break; 1064 case FWOHCIEV_ACKBSA: 1065 case FWOHCIEV_ACKBSB: 1066 case FWOHCIEV_ACKBSX: 1067 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1068 err = EBUSY; 1069 break; 1070 case FWOHCIEV_FLUSHED: 1071 case FWOHCIEV_ACKTARD: 1072 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1073 err = EAGAIN; 1074 break; 1075 case FWOHCIEV_MISSACK: 1076 case FWOHCIEV_UNDRRUN: 1077 case FWOHCIEV_OVRRUN: 1078 case FWOHCIEV_DESCERR: 1079 case FWOHCIEV_DTRDERR: 1080 case FWOHCIEV_TIMEOUT: 1081 case FWOHCIEV_TCODERR: 1082 case FWOHCIEV_UNKNOWN: 1083 case FWOHCIEV_ACKDERR: 1084 case FWOHCIEV_ACKTERR: 1085 default: 1086 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1087 stat, fwohcicode[stat]); 1088 err = EINVAL; 1089 break; 1090 } 1091 if (tr->xfer != NULL) { 1092 xfer = tr->xfer; 1093 if (xfer->state == FWXF_RCVD) { 1094 if (firewire_debug) 1095 printf("already rcvd\n"); 1096 fw_xfer_done(xfer); 1097 } else { 1098 xfer->state = FWXF_SENT; 1099 if (err == EBUSY && fc->status != FWBUSRESET) { 1100 xfer->state = FWXF_BUSY; 1101 xfer->resp = err; 1102 if (xfer->retry_req != NULL) 1103 xfer->retry_req(xfer); 1104 else { 1105 xfer->recv.len = 0; 1106 fw_xfer_done(xfer); 1107 } 1108 } else if (stat != FWOHCIEV_ACKPEND) { 1109 if (stat != FWOHCIEV_ACKCOMPL) 1110 xfer->state = FWXF_SENTERR; 1111 xfer->resp = err; 1112 xfer->recv.len = 0; 1113 fw_xfer_done(xfer); 1114 } 1115 } 1116 /* 1117 * The watchdog timer takes care of split 1118 * transcation timeout for ACKPEND case. 1119 */ 1120 } else { 1121 printf("this shouldn't happen\n"); 1122 } 1123 dbch->xferq.queued --; 1124 tr->xfer = NULL; 1125 1126 packets ++; 1127 tr = STAILQ_NEXT(tr, link); 1128 dbch->bottom = tr; 1129 if (dbch->bottom == dbch->top) { 1130 /* we reaches the end of context program */ 1131 if (firewire_debug && dbch->xferq.queued > 0) 1132 printf("queued > 0\n"); 1133 break; 1134 } 1135 } 1136out: 1137 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1138 printf("make free slot\n"); 1139 dbch->flags &= ~FWOHCI_DBCH_FULL; 1140 fwohci_start(sc, dbch); 1141 } 1142 splx(s); 1143} 1144 1145static void 1146fwohci_db_free(struct fwohci_dbch *dbch) 1147{ 1148 struct fwohcidb_tr *db_tr; 1149 int idb; 1150 1151 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1152 return; 1153 1154 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1155 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1156 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1157 db_tr->buf != NULL) { 1158 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1159 db_tr->buf, dbch->xferq.psize); 1160 db_tr->buf = NULL; 1161 } else if (db_tr->dma_map != NULL) 1162 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1163 } 1164 dbch->ndb = 0; 1165 db_tr = STAILQ_FIRST(&dbch->db_trq); 1166 fwdma_free_multiseg(dbch->am); 1167 free(db_tr, M_FW); 1168 STAILQ_INIT(&dbch->db_trq); 1169 dbch->flags &= ~FWOHCI_DBCH_INIT; 1170} 1171 1172static void 1173fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1174{ 1175 int idb; 1176 struct fwohcidb_tr *db_tr; 1177 1178 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1179 goto out; 1180 1181 /* create dma_tag for buffers */ 1182#define MAX_REQCOUNT 0xffff 1183 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1184 /*alignment*/ 1, /*boundary*/ 0, 1185 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1186 /*highaddr*/ BUS_SPACE_MAXADDR, 1187 /*filter*/NULL, /*filterarg*/NULL, 1188 /*maxsize*/ dbch->xferq.psize, 1189 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1190 /*maxsegsz*/ MAX_REQCOUNT, 1191 /*flags*/ 0, 1192#if __FreeBSD_version >= 501102 1193 /*lockfunc*/busdma_lock_mutex, 1194 /*lockarg*/&Giant, 1195#endif 1196 &dbch->dmat)) 1197 return; 1198 1199 /* allocate DB entries and attach one to each DMA channels */ 1200 /* DB entry must start at 16 bytes bounary. */ 1201 STAILQ_INIT(&dbch->db_trq); 1202 db_tr = (struct fwohcidb_tr *) 1203 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1204 M_FW, M_WAITOK | M_ZERO); 1205 if(db_tr == NULL){ 1206 printf("fwohci_db_init: malloc(1) failed\n"); 1207 return; 1208 } 1209 1210#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1211 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1212 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1213 if (dbch->am == NULL) { 1214 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1215 return; 1216 } 1217 /* Attach DB to DMA ch. */ 1218 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1219 db_tr->dbcnt = 0; 1220 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1221 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1222 /* create dmamap for buffers */ 1223 /* XXX do we need 4bytes alignment tag? */ 1224 /* XXX don't alloc dma_map for AR */ 1225 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1226 printf("bus_dmamap_create failed\n"); 1227 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1228 fwohci_db_free(dbch); 1229 return; 1230 } 1231 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1232 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1233 if (idb % dbch->xferq.bnpacket == 0) 1234 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1235 ].start = (caddr_t)db_tr; 1236 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1237 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1238 ].end = (caddr_t)db_tr; 1239 } 1240 db_tr++; 1241 } 1242 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1243 = STAILQ_FIRST(&dbch->db_trq); 1244out: 1245 dbch->xferq.queued = 0; 1246 dbch->pdb_tr = NULL; 1247 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1248 dbch->bottom = dbch->top; 1249 dbch->flags = FWOHCI_DBCH_INIT; 1250} 1251 1252static int 1253fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1254{ 1255 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1256 int sleepch; 1257 1258 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1259 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1260 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1261 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1262 /* XXX we cannot free buffers until the DMA really stops */ 1263 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1264 fwohci_db_free(&sc->it[dmach]); 1265 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1266 return 0; 1267} 1268 1269static int 1270fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1271{ 1272 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1273 int sleepch; 1274 1275 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1276 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1277 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1278 /* XXX we cannot free buffers until the DMA really stops */ 1279 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1280 fwohci_db_free(&sc->ir[dmach]); 1281 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1282 return 0; 1283} 1284 1285#if BYTE_ORDER == BIG_ENDIAN 1286static void 1287fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1288{ 1289 qld[0] = FWOHCI_DMA_READ(qld[0]); 1290 return; 1291} 1292#endif 1293 1294static int 1295fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1296{ 1297 int err = 0; 1298 int idb, z, i, dmach = 0, ldesc; 1299 u_int32_t off = NULL; 1300 struct fwohcidb_tr *db_tr; 1301 volatile struct fwohcidb *db; 1302 1303 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1304 err = EINVAL; 1305 return err; 1306 } 1307 z = dbch->ndesc; 1308 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1309 if( &sc->it[dmach] == dbch){ 1310 off = OHCI_ITOFF(dmach); 1311 break; 1312 } 1313 } 1314 if(off == NULL){ 1315 err = EINVAL; 1316 return err; 1317 } 1318 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1319 return err; 1320 dbch->xferq.flag |= FWXFERQ_RUNNING; 1321 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1322 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1323 } 1324 db_tr = dbch->top; 1325 for (idb = 0; idb < dbch->ndb; idb ++) { 1326 fwohci_add_tx_buf(dbch, db_tr, idb); 1327 if(STAILQ_NEXT(db_tr, link) == NULL){ 1328 break; 1329 } 1330 db = db_tr->db; 1331 ldesc = db_tr->dbcnt - 1; 1332 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1333 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1334 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1335 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1336 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1337 FWOHCI_DMA_SET( 1338 db[ldesc].db.desc.cmd, 1339 OHCI_INTERRUPT_ALWAYS); 1340 /* OHCI 1.1 and above */ 1341 FWOHCI_DMA_SET( 1342 db[0].db.desc.cmd, 1343 OHCI_INTERRUPT_ALWAYS); 1344 } 1345 } 1346 db_tr = STAILQ_NEXT(db_tr, link); 1347 } 1348 FWOHCI_DMA_CLEAR( 1349 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1350 return err; 1351} 1352 1353static int 1354fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1355{ 1356 int err = 0; 1357 int idb, z, i, dmach = 0, ldesc; 1358 u_int32_t off = NULL; 1359 struct fwohcidb_tr *db_tr; 1360 volatile struct fwohcidb *db; 1361 1362 z = dbch->ndesc; 1363 if(&sc->arrq == dbch){ 1364 off = OHCI_ARQOFF; 1365 }else if(&sc->arrs == dbch){ 1366 off = OHCI_ARSOFF; 1367 }else{ 1368 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1369 if( &sc->ir[dmach] == dbch){ 1370 off = OHCI_IROFF(dmach); 1371 break; 1372 } 1373 } 1374 } 1375 if(off == NULL){ 1376 err = EINVAL; 1377 return err; 1378 } 1379 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1380 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1381 return err; 1382 }else{ 1383 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1384 err = EBUSY; 1385 return err; 1386 } 1387 } 1388 dbch->xferq.flag |= FWXFERQ_RUNNING; 1389 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1390 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1391 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1392 } 1393 db_tr = dbch->top; 1394 for (idb = 0; idb < dbch->ndb; idb ++) { 1395 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1396 if (STAILQ_NEXT(db_tr, link) == NULL) 1397 break; 1398 db = db_tr->db; 1399 ldesc = db_tr->dbcnt - 1; 1400 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1401 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1402 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1403 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1404 FWOHCI_DMA_SET( 1405 db[ldesc].db.desc.cmd, 1406 OHCI_INTERRUPT_ALWAYS); 1407 FWOHCI_DMA_CLEAR( 1408 db[ldesc].db.desc.depend, 1409 0xf); 1410 } 1411 } 1412 db_tr = STAILQ_NEXT(db_tr, link); 1413 } 1414 FWOHCI_DMA_CLEAR( 1415 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1416 dbch->buf_offset = 0; 1417 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1418 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1419 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1420 return err; 1421 }else{ 1422 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1423 } 1424 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1425 return err; 1426} 1427 1428static int 1429fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1430{ 1431 int sec, cycle, cycle_match; 1432 1433 cycle = cycle_now & 0x1fff; 1434 sec = cycle_now >> 13; 1435#define CYCLE_MOD 0x10 1436#if 1 1437#define CYCLE_DELAY 8 /* min delay to start DMA */ 1438#else 1439#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1440#endif 1441 cycle = cycle + CYCLE_DELAY; 1442 if (cycle >= 8000) { 1443 sec ++; 1444 cycle -= 8000; 1445 } 1446 cycle = roundup2(cycle, CYCLE_MOD); 1447 if (cycle >= 8000) { 1448 sec ++; 1449 if (cycle == 8000) 1450 cycle = 0; 1451 else 1452 cycle = CYCLE_MOD; 1453 } 1454 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1455 1456 return(cycle_match); 1457} 1458 1459static int 1460fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1461{ 1462 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1463 int err = 0; 1464 unsigned short tag, ich; 1465 struct fwohci_dbch *dbch; 1466 int cycle_match, cycle_now, s, ldesc; 1467 u_int32_t stat; 1468 struct fw_bulkxfer *first, *chunk, *prev; 1469 struct fw_xferq *it; 1470 1471 dbch = &sc->it[dmach]; 1472 it = &dbch->xferq; 1473 1474 tag = (it->flag >> 6) & 3; 1475 ich = it->flag & 0x3f; 1476 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1477 dbch->ndb = it->bnpacket * it->bnchunk; 1478 dbch->ndesc = 3; 1479 fwohci_db_init(sc, dbch); 1480 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1481 return ENOMEM; 1482 err = fwohci_tx_enable(sc, dbch); 1483 } 1484 if(err) 1485 return err; 1486 1487 ldesc = dbch->ndesc - 1; 1488 s = splfw(); 1489 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1490 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1491 volatile struct fwohcidb *db; 1492 1493 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1494 BUS_DMASYNC_PREWRITE); 1495 fwohci_txbufdb(sc, dmach, chunk); 1496 if (prev != NULL) { 1497 db = ((struct fwohcidb_tr *)(prev->end))->db; 1498#if 0 /* XXX necessary? */ 1499 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1500 OHCI_BRANCH_ALWAYS); 1501#endif 1502#if 0 /* if bulkxfer->npacket changes */ 1503 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1504 ((struct fwohcidb_tr *) 1505 (chunk->start))->bus_addr | dbch->ndesc; 1506#else 1507 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1508 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1509#endif 1510 } 1511 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1512 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1513 prev = chunk; 1514 } 1515 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1516 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1517 splx(s); 1518 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1519 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1520 printf("stat 0x%x\n", stat); 1521 1522 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1523 return 0; 1524 1525#if 0 1526 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1527#endif 1528 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1529 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1530 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1531 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1532 1533 first = STAILQ_FIRST(&it->stdma); 1534 OWRITE(sc, OHCI_ITCMD(dmach), 1535 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1536 if (firewire_debug) { 1537 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1538#if 1 1539 dump_dma(sc, ITX_CH + dmach); 1540#endif 1541 } 1542 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1543#if 1 1544 /* Don't start until all chunks are buffered */ 1545 if (STAILQ_FIRST(&it->stfree) != NULL) 1546 goto out; 1547#endif 1548#if 1 1549 /* Clear cycle match counter bits */ 1550 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1551 1552 /* 2bit second + 13bit cycle */ 1553 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1554 cycle_match = fwohci_next_cycle(fc, cycle_now); 1555 1556 OWRITE(sc, OHCI_ITCTL(dmach), 1557 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1558 | OHCI_CNTL_DMA_RUN); 1559#else 1560 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1561#endif 1562 if (firewire_debug) { 1563 printf("cycle_match: 0x%04x->0x%04x\n", 1564 cycle_now, cycle_match); 1565 dump_dma(sc, ITX_CH + dmach); 1566 dump_db(sc, ITX_CH + dmach); 1567 } 1568 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1569 device_printf(sc->fc.dev, 1570 "IT DMA underrun (0x%08x)\n", stat); 1571 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1572 } 1573out: 1574 return err; 1575} 1576 1577static int 1578fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1579{ 1580 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1581 int err = 0, s, ldesc; 1582 unsigned short tag, ich; 1583 u_int32_t stat; 1584 struct fwohci_dbch *dbch; 1585 struct fwohcidb_tr *db_tr; 1586 struct fw_bulkxfer *first, *prev, *chunk; 1587 struct fw_xferq *ir; 1588 1589 dbch = &sc->ir[dmach]; 1590 ir = &dbch->xferq; 1591 1592 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1593 tag = (ir->flag >> 6) & 3; 1594 ich = ir->flag & 0x3f; 1595 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1596 1597 ir->queued = 0; 1598 dbch->ndb = ir->bnpacket * ir->bnchunk; 1599 dbch->ndesc = 2; 1600 fwohci_db_init(sc, dbch); 1601 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1602 return ENOMEM; 1603 err = fwohci_rx_enable(sc, dbch); 1604 } 1605 if(err) 1606 return err; 1607 1608 first = STAILQ_FIRST(&ir->stfree); 1609 if (first == NULL) { 1610 device_printf(fc->dev, "IR DMA no free chunk\n"); 1611 return 0; 1612 } 1613 1614 ldesc = dbch->ndesc - 1; 1615 s = splfw(); 1616 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1617 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1618 volatile struct fwohcidb *db; 1619 1620#if 1 /* XXX for if_fwe */ 1621 if (chunk->mbuf != NULL) { 1622 db_tr = (struct fwohcidb_tr *)(chunk->start); 1623 db_tr->dbcnt = 1; 1624 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1625 chunk->mbuf, fwohci_execute_db2, db_tr, 1626 /* flags */0); 1627 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1628 OHCI_UPDATE | OHCI_INPUT_LAST | 1629 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1630 } 1631#endif 1632 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1633 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1634 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1635 if (prev != NULL) { 1636 db = ((struct fwohcidb_tr *)(prev->end))->db; 1637 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1638 } 1639 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1640 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1641 prev = chunk; 1642 } 1643 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1644 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1645 splx(s); 1646 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1647 if (stat & OHCI_CNTL_DMA_ACTIVE) 1648 return 0; 1649 if (stat & OHCI_CNTL_DMA_RUN) { 1650 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1651 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1652 } 1653 1654 if (firewire_debug) 1655 printf("start IR DMA 0x%x\n", stat); 1656 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1657 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1658 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1659 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1660 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1661 OWRITE(sc, OHCI_IRCMD(dmach), 1662 ((struct fwohcidb_tr *)(first->start))->bus_addr 1663 | dbch->ndesc); 1664 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1665 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1666#if 0 1667 dump_db(sc, IRX_CH + dmach); 1668#endif 1669 return err; 1670} 1671 1672int 1673fwohci_stop(struct fwohci_softc *sc, device_t dev) 1674{ 1675 u_int i; 1676 1677/* Now stopping all DMA channel */ 1678 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1679 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1680 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1681 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1682 1683 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1684 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1685 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1686 } 1687 1688/* FLUSH FIFO and reset Transmitter/Reciever */ 1689 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1690 1691/* Stop interrupt */ 1692 OWRITE(sc, FWOHCI_INTMASKCLR, 1693 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1694 | OHCI_INT_PHY_INT 1695 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1696 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1697 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1698 | OHCI_INT_PHY_BUS_R); 1699 1700 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1701 fw_drain_txq(&sc->fc); 1702 1703/* XXX Link down? Bus reset? */ 1704 return 0; 1705} 1706 1707int 1708fwohci_resume(struct fwohci_softc *sc, device_t dev) 1709{ 1710 int i; 1711 struct fw_xferq *ir; 1712 struct fw_bulkxfer *chunk; 1713 1714 fwohci_reset(sc, dev); 1715 /* XXX resume isochronus receive automatically. (how about TX?) */ 1716 for(i = 0; i < sc->fc.nisodma; i ++) { 1717 ir = &sc->ir[i].xferq; 1718 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1719 device_printf(sc->fc.dev, 1720 "resume iso receive ch: %d\n", i); 1721 ir->flag &= ~FWXFERQ_RUNNING; 1722 /* requeue stdma to stfree */ 1723 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1724 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1725 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1726 } 1727 sc->fc.irx_enable(&sc->fc, i); 1728 } 1729 } 1730 1731 bus_generic_resume(dev); 1732 sc->fc.ibr(&sc->fc); 1733 return 0; 1734} 1735 1736#define ACK_ALL 1737static void 1738fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1739{ 1740 u_int32_t irstat, itstat; 1741 u_int i; 1742 struct firewire_comm *fc = (struct firewire_comm *)sc; 1743 1744#ifdef OHCI_DEBUG 1745 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1746 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1747 stat & OHCI_INT_EN ? "DMA_EN ":"", 1748 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1749 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1750 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1751 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1752 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1753 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1754 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1755 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1756 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1757 stat & OHCI_INT_PHY_SID ? "SID ":"", 1758 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1759 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1760 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1761 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1762 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1763 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1764 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1765 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1766 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1767 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1768 stat, OREAD(sc, FWOHCI_INTMASK) 1769 ); 1770#endif 1771/* Bus reset */ 1772 if(stat & OHCI_INT_PHY_BUS_R ){ 1773 if (fc->status == FWBUSRESET) 1774 goto busresetout; 1775 /* Disable bus reset interrupt until sid recv. */ 1776 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1777 1778 device_printf(fc->dev, "BUS reset\n"); 1779 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1780 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1781 1782 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1783 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1784 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1785 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1786 1787#ifndef ACK_ALL 1788 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1789#endif 1790 fw_busreset(fc); 1791 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1792 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1793 } 1794busresetout: 1795 if((stat & OHCI_INT_DMA_IR )){ 1796#ifndef ACK_ALL 1797 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1798#endif 1799#if __FreeBSD_version >= 500000 1800 irstat = atomic_readandclear_int(&sc->irstat); 1801#else 1802 irstat = sc->irstat; 1803 sc->irstat = 0; 1804#endif 1805 for(i = 0; i < fc->nisodma ; i++){ 1806 struct fwohci_dbch *dbch; 1807 1808 if((irstat & (1 << i)) != 0){ 1809 dbch = &sc->ir[i]; 1810 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1811 device_printf(sc->fc.dev, 1812 "dma(%d) not active\n", i); 1813 continue; 1814 } 1815 fwohci_rbuf_update(sc, i); 1816 } 1817 } 1818 } 1819 if((stat & OHCI_INT_DMA_IT )){ 1820#ifndef ACK_ALL 1821 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1822#endif 1823#if __FreeBSD_version >= 500000 1824 itstat = atomic_readandclear_int(&sc->itstat); 1825#else 1826 itstat = sc->itstat; 1827 sc->itstat = 0; 1828#endif 1829 for(i = 0; i < fc->nisodma ; i++){ 1830 if((itstat & (1 << i)) != 0){ 1831 fwohci_tbuf_update(sc, i); 1832 } 1833 } 1834 } 1835 if((stat & OHCI_INT_DMA_PRRS )){ 1836#ifndef ACK_ALL 1837 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1838#endif 1839#if 0 1840 dump_dma(sc, ARRS_CH); 1841 dump_db(sc, ARRS_CH); 1842#endif 1843 fwohci_arcv(sc, &sc->arrs, count); 1844 } 1845 if((stat & OHCI_INT_DMA_PRRQ )){ 1846#ifndef ACK_ALL 1847 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1848#endif 1849#if 0 1850 dump_dma(sc, ARRQ_CH); 1851 dump_db(sc, ARRQ_CH); 1852#endif 1853 fwohci_arcv(sc, &sc->arrq, count); 1854 } 1855 if(stat & OHCI_INT_PHY_SID){ 1856 u_int32_t *buf, node_id; 1857 int plen; 1858 1859#ifndef ACK_ALL 1860 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1861#endif 1862 /* Enable bus reset interrupt */ 1863 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1864 /* Allow async. request to us */ 1865 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1866 /* XXX insecure ?? */ 1867 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1868 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1869 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1870 /* Set ATRetries register */ 1871 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1872/* 1873** Checking whether the node is root or not. If root, turn on 1874** cycle master. 1875*/ 1876 node_id = OREAD(sc, FWOHCI_NODEID); 1877 plen = OREAD(sc, OHCI_SID_CNT); 1878 1879 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1880 node_id, (plen >> 16) & 0xff); 1881 if (!(node_id & OHCI_NODE_VALID)) { 1882 printf("Bus reset failure\n"); 1883 goto sidout; 1884 } 1885 if (node_id & OHCI_NODE_ROOT) { 1886 printf("CYCLEMASTER mode\n"); 1887 OWRITE(sc, OHCI_LNKCTL, 1888 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1889 } else { 1890 printf("non CYCLEMASTER mode\n"); 1891 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1892 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1893 } 1894 fc->nodeid = node_id & 0x3f; 1895 1896 if (plen & OHCI_SID_ERR) { 1897 device_printf(fc->dev, "SID Error\n"); 1898 goto sidout; 1899 } 1900 plen &= OHCI_SID_CNT_MASK; 1901 if (plen < 4 || plen > OHCI_SIDSIZE) { 1902 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1903 goto sidout; 1904 } 1905 plen -= 4; /* chop control info */ 1906 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1907 if (buf == NULL) { 1908 device_printf(fc->dev, "malloc failed\n"); 1909 goto sidout; 1910 } 1911 for (i = 0; i < plen / 4; i ++) 1912 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1913#if 1 1914 /* pending all pre-bus_reset packets */ 1915 fwohci_txd(sc, &sc->atrq); 1916 fwohci_txd(sc, &sc->atrs); 1917 fwohci_arcv(sc, &sc->arrs, -1); 1918 fwohci_arcv(sc, &sc->arrq, -1); 1919 fw_drain_txq(fc); 1920#endif 1921 fw_sidrcv(fc, buf, plen); 1922 free(buf, M_FW); 1923 } 1924sidout: 1925 if((stat & OHCI_INT_DMA_ATRQ )){ 1926#ifndef ACK_ALL 1927 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1928#endif 1929 fwohci_txd(sc, &(sc->atrq)); 1930 } 1931 if((stat & OHCI_INT_DMA_ATRS )){ 1932#ifndef ACK_ALL 1933 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1934#endif 1935 fwohci_txd(sc, &(sc->atrs)); 1936 } 1937 if((stat & OHCI_INT_PW_ERR )){ 1938#ifndef ACK_ALL 1939 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1940#endif 1941 device_printf(fc->dev, "posted write error\n"); 1942 } 1943 if((stat & OHCI_INT_ERR )){ 1944#ifndef ACK_ALL 1945 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1946#endif 1947 device_printf(fc->dev, "unrecoverable error\n"); 1948 } 1949 if((stat & OHCI_INT_PHY_INT)) { 1950#ifndef ACK_ALL 1951 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1952#endif 1953 device_printf(fc->dev, "phy int\n"); 1954 } 1955 1956 return; 1957} 1958 1959#if FWOHCI_TASKQUEUE 1960static void 1961fwohci_complete(void *arg, int pending) 1962{ 1963 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1964 u_int32_t stat; 1965 1966again: 1967 stat = atomic_readandclear_int(&sc->intstat); 1968 if (stat) 1969 fwohci_intr_body(sc, stat, -1); 1970 else 1971 return; 1972 goto again; 1973} 1974#endif 1975 1976static u_int32_t 1977fwochi_check_stat(struct fwohci_softc *sc) 1978{ 1979 u_int32_t stat, irstat, itstat; 1980 1981 stat = OREAD(sc, FWOHCI_INTSTAT); 1982 if (stat == 0xffffffff) { 1983 device_printf(sc->fc.dev, 1984 "device physically ejected?\n"); 1985 return(stat); 1986 } 1987#ifdef ACK_ALL 1988 if (stat) 1989 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1990#endif 1991 if (stat & OHCI_INT_DMA_IR) { 1992 irstat = OREAD(sc, OHCI_IR_STAT); 1993 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1994 atomic_set_int(&sc->irstat, irstat); 1995 } 1996 if (stat & OHCI_INT_DMA_IT) { 1997 itstat = OREAD(sc, OHCI_IT_STAT); 1998 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1999 atomic_set_int(&sc->itstat, itstat); 2000 } 2001 return(stat); 2002} 2003 2004void 2005fwohci_intr(void *arg) 2006{ 2007 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2008 u_int32_t stat; 2009#if !FWOHCI_TASKQUEUE 2010 u_int32_t bus_reset = 0; 2011#endif 2012 2013 if (!(sc->intmask & OHCI_INT_EN)) { 2014 /* polling mode */ 2015 return; 2016 } 2017 2018#if !FWOHCI_TASKQUEUE 2019again: 2020#endif 2021 stat = fwochi_check_stat(sc); 2022 if (stat == 0 || stat == 0xffffffff) 2023 return; 2024#if FWOHCI_TASKQUEUE 2025 atomic_set_int(&sc->intstat, stat); 2026 /* XXX mask bus reset intr. during bus reset phase */ 2027 if (stat) 2028 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2029#else 2030 /* We cannot clear bus reset event during bus reset phase */ 2031 if ((stat & ~bus_reset) == 0) 2032 return; 2033 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2034 fwohci_intr_body(sc, stat, -1); 2035 goto again; 2036#endif 2037} 2038 2039void 2040fwohci_poll(struct firewire_comm *fc, int quick, int count) 2041{ 2042 int s; 2043 u_int32_t stat; 2044 struct fwohci_softc *sc; 2045 2046 2047 sc = (struct fwohci_softc *)fc; 2048 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2049 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2050 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2051#if 0 2052 if (!quick) { 2053#else 2054 if (1) { 2055#endif 2056 stat = fwochi_check_stat(sc); 2057 if (stat == 0 || stat == 0xffffffff) 2058 return; 2059 } 2060 s = splfw(); 2061 fwohci_intr_body(sc, stat, count); 2062 splx(s); 2063} 2064 2065static void 2066fwohci_set_intr(struct firewire_comm *fc, int enable) 2067{ 2068 struct fwohci_softc *sc; 2069 2070 sc = (struct fwohci_softc *)fc; 2071 if (bootverbose) 2072 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2073 if (enable) { 2074 sc->intmask |= OHCI_INT_EN; 2075 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2076 } else { 2077 sc->intmask &= ~OHCI_INT_EN; 2078 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2079 } 2080} 2081 2082static void 2083fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2084{ 2085 struct firewire_comm *fc = &sc->fc; 2086 volatile struct fwohcidb *db; 2087 struct fw_bulkxfer *chunk; 2088 struct fw_xferq *it; 2089 u_int32_t stat, count; 2090 int s, w=0, ldesc; 2091 2092 it = fc->it[dmach]; 2093 ldesc = sc->it[dmach].ndesc - 1; 2094 s = splfw(); /* unnecessary ? */ 2095 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2096 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2097 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2098 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2099 >> OHCI_STATUS_SHIFT; 2100 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2101 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2102 & OHCI_COUNT_MASK; 2103 if (stat == 0) 2104 break; 2105 STAILQ_REMOVE_HEAD(&it->stdma, link); 2106 switch (stat & FWOHCIEV_MASK){ 2107 case FWOHCIEV_ACKCOMPL: 2108#if 0 2109 device_printf(fc->dev, "0x%08x\n", count); 2110#endif 2111 break; 2112 default: 2113 device_printf(fc->dev, 2114 "Isochronous transmit err %02x(%s)\n", 2115 stat, fwohcicode[stat & 0x1f]); 2116 } 2117 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2118 w++; 2119 } 2120 splx(s); 2121 if (w) 2122 wakeup(it); 2123} 2124 2125static void 2126fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2127{ 2128 struct firewire_comm *fc = &sc->fc; 2129 volatile struct fwohcidb_tr *db_tr; 2130 struct fw_bulkxfer *chunk; 2131 struct fw_xferq *ir; 2132 u_int32_t stat; 2133 int s, w=0, ldesc; 2134 2135 ir = fc->ir[dmach]; 2136 ldesc = sc->ir[dmach].ndesc - 1; 2137#if 0 2138 dump_db(sc, dmach); 2139#endif 2140 s = splfw(); 2141 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2142 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2143 db_tr = (struct fwohcidb_tr *)chunk->end; 2144 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2145 >> OHCI_STATUS_SHIFT; 2146 if (stat == 0) 2147 break; 2148 2149 if (chunk->mbuf != NULL) { 2150 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2151 BUS_DMASYNC_POSTREAD); 2152 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2153 } else if (ir->buf != NULL) { 2154 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2155 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2156 } else { 2157 /* XXX */ 2158 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2159 } 2160 2161 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2162 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2163 switch (stat & FWOHCIEV_MASK) { 2164 case FWOHCIEV_ACKCOMPL: 2165 chunk->resp = 0; 2166 break; 2167 default: 2168 chunk->resp = EINVAL; 2169 device_printf(fc->dev, 2170 "Isochronous receive err %02x(%s)\n", 2171 stat, fwohcicode[stat & 0x1f]); 2172 } 2173 w++; 2174 } 2175 splx(s); 2176 if (w) { 2177 if (ir->flag & FWXFERQ_HANDLER) 2178 ir->hand(ir); 2179 else 2180 wakeup(ir); 2181 } 2182} 2183 2184void 2185dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2186{ 2187 u_int32_t off, cntl, stat, cmd, match; 2188 2189 if(ch == 0){ 2190 off = OHCI_ATQOFF; 2191 }else if(ch == 1){ 2192 off = OHCI_ATSOFF; 2193 }else if(ch == 2){ 2194 off = OHCI_ARQOFF; 2195 }else if(ch == 3){ 2196 off = OHCI_ARSOFF; 2197 }else if(ch < IRX_CH){ 2198 off = OHCI_ITCTL(ch - ITX_CH); 2199 }else{ 2200 off = OHCI_IRCTL(ch - IRX_CH); 2201 } 2202 cntl = stat = OREAD(sc, off); 2203 cmd = OREAD(sc, off + 0xc); 2204 match = OREAD(sc, off + 0x10); 2205 2206 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2207 ch, 2208 cntl, 2209 cmd, 2210 match); 2211 stat &= 0xffff ; 2212 if (stat) { 2213 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2214 ch, 2215 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2216 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2217 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2218 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2219 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2220 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2221 fwohcicode[stat & 0x1f], 2222 stat & 0x1f 2223 ); 2224 }else{ 2225 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2226 } 2227} 2228 2229void 2230dump_db(struct fwohci_softc *sc, u_int32_t ch) 2231{ 2232 struct fwohci_dbch *dbch; 2233 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2234 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2235 int idb, jdb; 2236 u_int32_t cmd, off; 2237 if(ch == 0){ 2238 off = OHCI_ATQOFF; 2239 dbch = &sc->atrq; 2240 }else if(ch == 1){ 2241 off = OHCI_ATSOFF; 2242 dbch = &sc->atrs; 2243 }else if(ch == 2){ 2244 off = OHCI_ARQOFF; 2245 dbch = &sc->arrq; 2246 }else if(ch == 3){ 2247 off = OHCI_ARSOFF; 2248 dbch = &sc->arrs; 2249 }else if(ch < IRX_CH){ 2250 off = OHCI_ITCTL(ch - ITX_CH); 2251 dbch = &sc->it[ch - ITX_CH]; 2252 }else { 2253 off = OHCI_IRCTL(ch - IRX_CH); 2254 dbch = &sc->ir[ch - IRX_CH]; 2255 } 2256 cmd = OREAD(sc, off + 0xc); 2257 2258 if( dbch->ndb == 0 ){ 2259 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2260 return; 2261 } 2262 pp = dbch->top; 2263 prev = pp->db; 2264 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2265 if(pp == NULL){ 2266 curr = NULL; 2267 goto outdb; 2268 } 2269 cp = STAILQ_NEXT(pp, link); 2270 if(cp == NULL){ 2271 curr = NULL; 2272 goto outdb; 2273 } 2274 np = STAILQ_NEXT(cp, link); 2275 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2276 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2277 curr = cp->db; 2278 if(np != NULL){ 2279 next = np->db; 2280 }else{ 2281 next = NULL; 2282 } 2283 goto outdb; 2284 } 2285 } 2286 pp = STAILQ_NEXT(pp, link); 2287 prev = pp->db; 2288 } 2289outdb: 2290 if( curr != NULL){ 2291#if 0 2292 printf("Prev DB %d\n", ch); 2293 print_db(pp, prev, ch, dbch->ndesc); 2294#endif 2295 printf("Current DB %d\n", ch); 2296 print_db(cp, curr, ch, dbch->ndesc); 2297#if 0 2298 printf("Next DB %d\n", ch); 2299 print_db(np, next, ch, dbch->ndesc); 2300#endif 2301 }else{ 2302 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2303 } 2304 return; 2305} 2306 2307void 2308print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2309 u_int32_t ch, u_int32_t max) 2310{ 2311 fwohcireg_t stat; 2312 int i, key; 2313 u_int32_t cmd, res; 2314 2315 if(db == NULL){ 2316 printf("No Descriptor is found\n"); 2317 return; 2318 } 2319 2320 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2321 ch, 2322 "Current", 2323 "OP ", 2324 "KEY", 2325 "INT", 2326 "BR ", 2327 "len", 2328 "Addr", 2329 "Depend", 2330 "Stat", 2331 "Cnt"); 2332 for( i = 0 ; i <= max ; i ++){ 2333 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2334 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2335 key = cmd & OHCI_KEY_MASK; 2336 stat = res >> OHCI_STATUS_SHIFT; 2337#if __FreeBSD_version >= 500000 2338 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2339 (uintmax_t)db_tr->bus_addr, 2340#else 2341 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2342 db_tr->bus_addr, 2343#endif 2344 dbcode[(cmd >> 28) & 0xf], 2345 dbkey[(cmd >> 24) & 0x7], 2346 dbcond[(cmd >> 20) & 0x3], 2347 dbcond[(cmd >> 18) & 0x3], 2348 cmd & OHCI_COUNT_MASK, 2349 FWOHCI_DMA_READ(db[i].db.desc.addr), 2350 FWOHCI_DMA_READ(db[i].db.desc.depend), 2351 stat, 2352 res & OHCI_COUNT_MASK); 2353 if(stat & 0xff00){ 2354 printf(" %s%s%s%s%s%s %s(%x)\n", 2355 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2356 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2357 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2358 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2359 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2360 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2361 fwohcicode[stat & 0x1f], 2362 stat & 0x1f 2363 ); 2364 }else{ 2365 printf(" Nostat\n"); 2366 } 2367 if(key == OHCI_KEY_ST2 ){ 2368 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2369 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2370 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2371 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2372 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2373 } 2374 if(key == OHCI_KEY_DEVICE){ 2375 return; 2376 } 2377 if((cmd & OHCI_BRANCH_MASK) 2378 == OHCI_BRANCH_ALWAYS){ 2379 return; 2380 } 2381 if((cmd & OHCI_CMD_MASK) 2382 == OHCI_OUTPUT_LAST){ 2383 return; 2384 } 2385 if((cmd & OHCI_CMD_MASK) 2386 == OHCI_INPUT_LAST){ 2387 return; 2388 } 2389 if(key == OHCI_KEY_ST2 ){ 2390 i++; 2391 } 2392 } 2393 return; 2394} 2395 2396void 2397fwohci_ibr(struct firewire_comm *fc) 2398{ 2399 struct fwohci_softc *sc; 2400 u_int32_t fun; 2401 2402 device_printf(fc->dev, "Initiate bus reset\n"); 2403 sc = (struct fwohci_softc *)fc; 2404 2405 /* 2406 * Set root hold-off bit so that non cyclemaster capable node 2407 * shouldn't became the root node. 2408 */ 2409#if 1 2410 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2411 fun |= FW_PHY_IBR | FW_PHY_RHB; 2412 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2413#else /* Short bus reset */ 2414 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2415 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2416 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2417#endif 2418} 2419 2420void 2421fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2422{ 2423 struct fwohcidb_tr *db_tr, *fdb_tr; 2424 struct fwohci_dbch *dbch; 2425 volatile struct fwohcidb *db; 2426 struct fw_pkt *fp; 2427 volatile struct fwohci_txpkthdr *ohcifp; 2428 unsigned short chtag; 2429 int idb; 2430 2431 dbch = &sc->it[dmach]; 2432 chtag = sc->it[dmach].xferq.flag & 0xff; 2433 2434 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2435 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2436/* 2437device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2438*/ 2439 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2440 db = db_tr->db; 2441 fp = (struct fw_pkt *)db_tr->buf; 2442 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2443 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2444 ohcifp->mode.stream.len = fp->mode.stream.len; 2445 ohcifp->mode.stream.chtag = chtag; 2446 ohcifp->mode.stream.tcode = 0xa; 2447 ohcifp->mode.stream.spd = 0; 2448#if BYTE_ORDER == BIG_ENDIAN 2449 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2450 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2451#endif 2452 2453 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2454 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2455 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2456#if 0 /* if bulkxfer->npackets changes */ 2457 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2458 | OHCI_UPDATE 2459 | OHCI_BRANCH_ALWAYS; 2460 db[0].db.desc.depend = 2461 = db[dbch->ndesc - 1].db.desc.depend 2462 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2463#else 2464 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2465 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2466#endif 2467 bulkxfer->end = (caddr_t)db_tr; 2468 db_tr = STAILQ_NEXT(db_tr, link); 2469 } 2470 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2471 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2472 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2473#if 0 /* if bulkxfer->npackets changes */ 2474 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2475 /* OHCI 1.1 and above */ 2476 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2477#endif 2478/* 2479 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2480 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2481device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2482*/ 2483 return; 2484} 2485 2486static int 2487fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2488 int poffset) 2489{ 2490 volatile struct fwohcidb *db = db_tr->db; 2491 struct fw_xferq *it; 2492 int err = 0; 2493 2494 it = &dbch->xferq; 2495 if(it->buf == 0){ 2496 err = EINVAL; 2497 return err; 2498 } 2499 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2500 db_tr->dbcnt = 3; 2501 2502 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2503 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2504 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2505 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2506 2507 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2508 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2509#if 1 2510 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2511 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2512#endif 2513 return 0; 2514} 2515 2516int 2517fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2518 int poffset, struct fwdma_alloc *dummy_dma) 2519{ 2520 volatile struct fwohcidb *db = db_tr->db; 2521 struct fw_xferq *ir; 2522 int i, ldesc; 2523 bus_addr_t dbuf[2]; 2524 int dsiz[2]; 2525 2526 ir = &dbch->xferq; 2527 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2528 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2529 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2530 if (db_tr->buf == NULL) 2531 return(ENOMEM); 2532 db_tr->dbcnt = 1; 2533 dsiz[0] = ir->psize; 2534 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2535 BUS_DMASYNC_PREREAD); 2536 } else { 2537 db_tr->dbcnt = 0; 2538 if (dummy_dma != NULL) { 2539 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2540 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2541 } 2542 dsiz[db_tr->dbcnt] = ir->psize; 2543 if (ir->buf != NULL) { 2544 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2545 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2546 } 2547 db_tr->dbcnt++; 2548 } 2549 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2550 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2551 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2552 if (ir->flag & FWXFERQ_STREAM) { 2553 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2554 } 2555 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2556 } 2557 ldesc = db_tr->dbcnt - 1; 2558 if (ir->flag & FWXFERQ_STREAM) { 2559 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2560 } 2561 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2562 return 0; 2563} 2564 2565 2566static int 2567fwohci_arcv_swap(struct fw_pkt *fp, int len) 2568{ 2569 struct fw_pkt *fp0; 2570 u_int32_t ld0; 2571 int slen; 2572#if BYTE_ORDER == BIG_ENDIAN 2573 int i; 2574#endif 2575 2576 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2577#if 0 2578 printf("ld0: x%08x\n", ld0); 2579#endif 2580 fp0 = (struct fw_pkt *)&ld0; 2581 switch (fp0->mode.common.tcode) { 2582 case FWTCODE_RREQQ: 2583 case FWTCODE_WRES: 2584 case FWTCODE_WREQQ: 2585 case FWTCODE_RRESQ: 2586 case FWOHCITCODE_PHY: 2587 slen = 12; 2588 break; 2589 case FWTCODE_RREQB: 2590 case FWTCODE_WREQB: 2591 case FWTCODE_LREQ: 2592 case FWTCODE_RRESB: 2593 case FWTCODE_LRES: 2594 slen = 16; 2595 break; 2596 default: 2597 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2598 return(0); 2599 } 2600 if (slen > len) { 2601 if (firewire_debug) 2602 printf("splitted header\n"); 2603 return(-slen); 2604 } 2605#if BYTE_ORDER == BIG_ENDIAN 2606 for(i = 0; i < slen/4; i ++) 2607 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2608#endif 2609 return(slen); 2610} 2611 2612#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2613static int 2614fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2615{ 2616 int r; 2617 2618 switch(fp->mode.common.tcode){ 2619 case FWTCODE_RREQQ: 2620 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2621 break; 2622 case FWTCODE_WRES: 2623 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2624 break; 2625 case FWTCODE_WREQQ: 2626 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2627 break; 2628 case FWTCODE_RREQB: 2629 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2630 break; 2631 case FWTCODE_RRESQ: 2632 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2633 break; 2634 case FWTCODE_WREQB: 2635 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2636 + sizeof(u_int32_t); 2637 break; 2638 case FWTCODE_LREQ: 2639 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2640 + sizeof(u_int32_t); 2641 break; 2642 case FWTCODE_RRESB: 2643 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2644 + sizeof(u_int32_t); 2645 break; 2646 case FWTCODE_LRES: 2647 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2648 + sizeof(u_int32_t); 2649 break; 2650 case FWOHCITCODE_PHY: 2651 r = 16; 2652 break; 2653 default: 2654 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2655 fp->mode.common.tcode); 2656 r = 0; 2657 } 2658 if (r > dbch->xferq.psize) { 2659 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2660 /* panic ? */ 2661 } 2662 return r; 2663} 2664 2665static void 2666fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2667{ 2668 volatile struct fwohcidb *db = &db_tr->db[0]; 2669 2670 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2671 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2672 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2673 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2674 dbch->bottom = db_tr; 2675} 2676 2677static void 2678fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2679{ 2680 struct fwohcidb_tr *db_tr; 2681 struct iovec vec[2]; 2682 struct fw_pkt pktbuf; 2683 int nvec; 2684 struct fw_pkt *fp; 2685 u_int8_t *ld; 2686 u_int32_t stat, off, status; 2687 u_int spd; 2688 int len, plen, hlen, pcnt, offset; 2689 int s; 2690 caddr_t buf; 2691 int resCount; 2692 2693 if(&sc->arrq == dbch){ 2694 off = OHCI_ARQOFF; 2695 }else if(&sc->arrs == dbch){ 2696 off = OHCI_ARSOFF; 2697 }else{ 2698 return; 2699 } 2700 2701 s = splfw(); 2702 db_tr = dbch->top; 2703 pcnt = 0; 2704 /* XXX we cannot handle a packet which lies in more than two buf */ 2705 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2706 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2707 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2708 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2709#if 0 2710 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2711#endif 2712 while (status & OHCI_CNTL_DMA_ACTIVE) { 2713 len = dbch->xferq.psize - resCount; 2714 ld = (u_int8_t *)db_tr->buf; 2715 if (dbch->pdb_tr == NULL) { 2716 len -= dbch->buf_offset; 2717 ld += dbch->buf_offset; 2718 } 2719 if (len > 0) 2720 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2721 BUS_DMASYNC_POSTREAD); 2722 while (len > 0 ) { 2723 if (count >= 0 && count-- == 0) 2724 goto out; 2725 if(dbch->pdb_tr != NULL){ 2726 /* we have a fragment in previous buffer */ 2727 int rlen; 2728 2729 offset = dbch->buf_offset; 2730 if (offset < 0) 2731 offset = - offset; 2732 buf = dbch->pdb_tr->buf + offset; 2733 rlen = dbch->xferq.psize - offset; 2734 if (firewire_debug) 2735 printf("rlen=%d, offset=%d\n", 2736 rlen, dbch->buf_offset); 2737 if (dbch->buf_offset < 0) { 2738 /* splitted in header, pull up */ 2739 char *p; 2740 2741 p = (char *)&pktbuf; 2742 bcopy(buf, p, rlen); 2743 p += rlen; 2744 /* this must be too long but harmless */ 2745 rlen = sizeof(pktbuf) - rlen; 2746 if (rlen < 0) 2747 printf("why rlen < 0\n"); 2748 bcopy(db_tr->buf, p, rlen); 2749 ld += rlen; 2750 len -= rlen; 2751 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2752 if (hlen < 0) { 2753 printf("hlen < 0 shouldn't happen"); 2754 } 2755 offset = sizeof(pktbuf); 2756 vec[0].iov_base = (char *)&pktbuf; 2757 vec[0].iov_len = offset; 2758 } else { 2759 /* splitted in payload */ 2760 offset = rlen; 2761 vec[0].iov_base = buf; 2762 vec[0].iov_len = rlen; 2763 } 2764 fp=(struct fw_pkt *)vec[0].iov_base; 2765 nvec = 1; 2766 } else { 2767 /* no fragment in previous buffer */ 2768 fp=(struct fw_pkt *)ld; 2769 hlen = fwohci_arcv_swap(fp, len); 2770 if (hlen == 0) 2771 /* XXX need reset */ 2772 goto out; 2773 if (hlen < 0) { 2774 dbch->pdb_tr = db_tr; 2775 dbch->buf_offset = - dbch->buf_offset; 2776 /* sanity check */ 2777 if (resCount != 0) 2778 printf("resCount != 0 !?\n"); 2779 goto out; 2780 } 2781 offset = 0; 2782 nvec = 0; 2783 } 2784 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2785 if (plen < 0) { 2786 /* minimum header size + trailer 2787 = sizeof(fw_pkt) so this shouldn't happens */ 2788 printf("plen is negative! offset=%d\n", offset); 2789 goto out; 2790 } 2791 if (plen > 0) { 2792 len -= plen; 2793 if (len < 0) { 2794 dbch->pdb_tr = db_tr; 2795 if (firewire_debug) 2796 printf("splitted payload\n"); 2797 /* sanity check */ 2798 if (resCount != 0) 2799 printf("resCount != 0 !?\n"); 2800 goto out; 2801 } 2802 vec[nvec].iov_base = ld; 2803 vec[nvec].iov_len = plen; 2804 nvec ++; 2805 ld += plen; 2806 } 2807 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2808 if (nvec == 0) 2809 printf("nvec == 0\n"); 2810 2811/* DMA result-code will be written at the tail of packet */ 2812#if BYTE_ORDER == BIG_ENDIAN 2813 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2814#else 2815 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2816#endif 2817#if 0 2818 printf("plen: %d, stat %x\n", plen ,stat); 2819#endif 2820 spd = (stat >> 5) & 0x3; 2821 stat &= 0x1f; 2822 switch(stat){ 2823 case FWOHCIEV_ACKPEND: 2824#if 0 2825 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2826#endif 2827 /* fall through */ 2828 case FWOHCIEV_ACKCOMPL: 2829 if ((vec[nvec-1].iov_len -= 2830 sizeof(struct fwohci_trailer)) == 0) 2831 nvec--; 2832 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2833 break; 2834 case FWOHCIEV_BUSRST: 2835 if (sc->fc.status != FWBUSRESET) 2836 printf("got BUSRST packet!?\n"); 2837 break; 2838 default: 2839 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2840#if 0 /* XXX */ 2841 goto out; 2842#endif 2843 break; 2844 } 2845 pcnt ++; 2846 if (dbch->pdb_tr != NULL) { 2847 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2848 dbch->pdb_tr = NULL; 2849 } 2850 2851 } 2852out: 2853 if (resCount == 0) { 2854 /* done on this buffer */ 2855 if (dbch->pdb_tr == NULL) { 2856 fwohci_arcv_free_buf(dbch, db_tr); 2857 dbch->buf_offset = 0; 2858 } else 2859 if (dbch->pdb_tr != db_tr) 2860 printf("pdb_tr != db_tr\n"); 2861 db_tr = STAILQ_NEXT(db_tr, link); 2862 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2863 >> OHCI_STATUS_SHIFT; 2864 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2865 & OHCI_COUNT_MASK; 2866 /* XXX check buffer overrun */ 2867 dbch->top = db_tr; 2868 } else { 2869 dbch->buf_offset = dbch->xferq.psize - resCount; 2870 break; 2871 } 2872 /* XXX make sure DMA is not dead */ 2873 } 2874#if 0 2875 if (pcnt < 1) 2876 printf("fwohci_arcv: no packets\n"); 2877#endif 2878 splx(s); 2879} 2880