fwohci.c revision 118293
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 118293 2003-08-01 04:51:21Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#include <dev/firewire/firewire.h> 62#include <dev/firewire/firewirereg.h> 63#include <dev/firewire/fwdma.h> 64#include <dev/firewire/fwohcireg.h> 65#include <dev/firewire/fwohcivar.h> 66#include <dev/firewire/firewire_phy.h> 67 68#undef OHCI_DEBUG 69 70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71 "STOR","LOAD","NOP ","STOP",}; 72 73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74 "UNDEF","REG","SYS","DEV"}; 75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76char fwohcicode[32][0x20]={ 77 "No stat","Undef","long","miss Ack err", 78 "underrun","overrun","desc err", "data read err", 79 "data write err","bus reset","timeout","tcode err", 80 "Undef","Undef","unknown event","flushed", 81 "Undef","ack complete","ack pend","Undef", 82 "ack busy_X","ack busy_A","ack busy_B","Undef", 83 "Undef","Undef","Undef","ack tardy", 84 "Undef","ack data_err","ack type_err",""}; 85 86#define MAX_SPEED 3 87extern char linkspeed[][0x10]; 88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89 90static struct tcode_info tinfo[] = { 91/* hdr_len block flag*/ 92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94/* 2 WRES */ {12, FWTI_RES}, 95/* 3 XXX */ { 0, 0}, 96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98/* 6 RRESQ */ {16, FWTI_RES}, 99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100/* 8 CYCS */ { 0, 0}, 101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104/* c XXX */ { 0, 0}, 105/* d XXX */ { 0, 0}, 106/* e PHY */ {12, FWTI_REQ}, 107/* f XXX */ { 0, 0} 108}; 109 110#define OHCI_WRITE_SIGMASK 0xffff0000 111#define OHCI_READ_SIGMASK 0xffff0000 112 113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115 116static void fwohci_ibr __P((struct firewire_comm *)); 117static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118static void fwohci_db_free __P((struct fwohci_dbch *)); 119static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121static void fwohci_start_atq __P((struct firewire_comm *)); 122static void fwohci_start_ats __P((struct firewire_comm *)); 123static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128static int fwohci_irx_enable __P((struct firewire_comm *, int)); 129static int fwohci_irx_disable __P((struct firewire_comm *, int)); 130#if BYTE_ORDER == BIG_ENDIAN 131static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132#endif 133static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134static int fwohci_itx_disable __P((struct firewire_comm *, int)); 135static void fwohci_timeout __P((void *)); 136static void fwohci_set_intr __P((struct firewire_comm *, int)); 137 138static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140static void dump_db __P((struct fwohci_softc *, u_int32_t)); 141static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147#if FWOHCI_TASKQUEUE 148static void fwohci_complete(void *, int); 149#endif 150 151/* 152 * memory allocated for DMA programs 153 */ 154#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155 156/* #define NDB 1024 */ 157#define NDB FWMAXQUEUE 158#define NDVDB (DVBUF * NDB) 159 160#define OHCI_VERSION 0x00 161#define OHCI_ATRETRY 0x08 162#define OHCI_CROMHDR 0x18 163#define OHCI_BUS_OPT 0x20 164#define OHCI_BUSIRMC (1 << 31) 165#define OHCI_BUSCMC (1 << 30) 166#define OHCI_BUSISC (1 << 29) 167#define OHCI_BUSBMC (1 << 28) 168#define OHCI_BUSPMC (1 << 27) 169#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 170 OHCI_BUSBMC | OHCI_BUSPMC 171 172#define OHCI_EUID_HI 0x24 173#define OHCI_EUID_LO 0x28 174 175#define OHCI_CROMPTR 0x34 176#define OHCI_HCCCTL 0x50 177#define OHCI_HCCCTLCLR 0x54 178#define OHCI_AREQHI 0x100 179#define OHCI_AREQHICLR 0x104 180#define OHCI_AREQLO 0x108 181#define OHCI_AREQLOCLR 0x10c 182#define OHCI_PREQHI 0x110 183#define OHCI_PREQHICLR 0x114 184#define OHCI_PREQLO 0x118 185#define OHCI_PREQLOCLR 0x11c 186#define OHCI_PREQUPPER 0x120 187 188#define OHCI_SID_BUF 0x64 189#define OHCI_SID_CNT 0x68 190#define OHCI_SID_ERR (1 << 31) 191#define OHCI_SID_CNT_MASK 0xffc 192 193#define OHCI_IT_STAT 0x90 194#define OHCI_IT_STATCLR 0x94 195#define OHCI_IT_MASK 0x98 196#define OHCI_IT_MASKCLR 0x9c 197 198#define OHCI_IR_STAT 0xa0 199#define OHCI_IR_STATCLR 0xa4 200#define OHCI_IR_MASK 0xa8 201#define OHCI_IR_MASKCLR 0xac 202 203#define OHCI_LNKCTL 0xe0 204#define OHCI_LNKCTLCLR 0xe4 205 206#define OHCI_PHYACCESS 0xec 207#define OHCI_CYCLETIMER 0xf0 208 209#define OHCI_DMACTL(off) (off) 210#define OHCI_DMACTLCLR(off) (off + 4) 211#define OHCI_DMACMD(off) (off + 0xc) 212#define OHCI_DMAMATCH(off) (off + 0x10) 213 214#define OHCI_ATQOFF 0x180 215#define OHCI_ATQCTL OHCI_ATQOFF 216#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 217#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 218#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 219 220#define OHCI_ATSOFF 0x1a0 221#define OHCI_ATSCTL OHCI_ATSOFF 222#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 223#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 224#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 225 226#define OHCI_ARQOFF 0x1c0 227#define OHCI_ARQCTL OHCI_ARQOFF 228#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 229#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 230#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 231 232#define OHCI_ARSOFF 0x1e0 233#define OHCI_ARSCTL OHCI_ARSOFF 234#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 235#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 236#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 237 238#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 239#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 240#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 241#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 242 243#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 244#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 245#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 246#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 247#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 248 249d_ioctl_t fwohci_ioctl; 250 251/* 252 * Communication with PHY device 253 */ 254static u_int32_t 255fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 256{ 257 u_int32_t fun; 258 259 addr &= 0xf; 260 data &= 0xff; 261 262 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 263 OWRITE(sc, OHCI_PHYACCESS, fun); 264 DELAY(100); 265 266 return(fwphy_rddata( sc, addr)); 267} 268 269static u_int32_t 270fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 271{ 272 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 273 int i; 274 u_int32_t bm; 275 276#define OHCI_CSR_DATA 0x0c 277#define OHCI_CSR_COMP 0x10 278#define OHCI_CSR_CONT 0x14 279#define OHCI_BUS_MANAGER_ID 0 280 281 OWRITE(sc, OHCI_CSR_DATA, node); 282 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 283 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 284 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 285 DELAY(10); 286 bm = OREAD(sc, OHCI_CSR_DATA); 287 if((bm & 0x3f) == 0x3f) 288 bm = node; 289 if (bootverbose) 290 device_printf(sc->fc.dev, 291 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 292 293 return(bm); 294} 295 296static u_int32_t 297fwphy_rddata(struct fwohci_softc *sc, u_int addr) 298{ 299 u_int32_t fun, stat; 300 u_int i, retry = 0; 301 302 addr &= 0xf; 303#define MAX_RETRY 100 304again: 305 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 306 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 307 OWRITE(sc, OHCI_PHYACCESS, fun); 308 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 309 fun = OREAD(sc, OHCI_PHYACCESS); 310 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 311 break; 312 DELAY(100); 313 } 314 if(i >= MAX_RETRY) { 315 if (bootverbose) 316 device_printf(sc->fc.dev, "phy read failed(1).\n"); 317 if (++retry < MAX_RETRY) { 318 DELAY(100); 319 goto again; 320 } 321 } 322 /* Make sure that SCLK is started */ 323 stat = OREAD(sc, FWOHCI_INTSTAT); 324 if ((stat & OHCI_INT_REG_FAIL) != 0 || 325 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 326 if (bootverbose) 327 device_printf(sc->fc.dev, "phy read failed(2).\n"); 328 if (++retry < MAX_RETRY) { 329 DELAY(100); 330 goto again; 331 } 332 } 333 if (bootverbose || retry >= MAX_RETRY) 334 device_printf(sc->fc.dev, 335 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 336#undef MAX_RETRY 337 return((fun >> PHYDEV_RDDATA )& 0xff); 338} 339/* Device specific ioctl. */ 340int 341fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 342{ 343 struct firewire_softc *sc; 344 struct fwohci_softc *fc; 345 int unit = DEV2UNIT(dev); 346 int err = 0; 347 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 348 u_int32_t *dmach = (u_int32_t *) data; 349 350 sc = devclass_get_softc(firewire_devclass, unit); 351 if(sc == NULL){ 352 return(EINVAL); 353 } 354 fc = (struct fwohci_softc *)sc->fc; 355 356 if (!data) 357 return(EINVAL); 358 359 switch (cmd) { 360 case FWOHCI_WRREG: 361#define OHCI_MAX_REG 0x800 362 if(reg->addr <= OHCI_MAX_REG){ 363 OWRITE(fc, reg->addr, reg->data); 364 reg->data = OREAD(fc, reg->addr); 365 }else{ 366 err = EINVAL; 367 } 368 break; 369 case FWOHCI_RDREG: 370 if(reg->addr <= OHCI_MAX_REG){ 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376/* Read DMA descriptors for debug */ 377 case DUMPDMA: 378 if(*dmach <= OHCI_MAX_DMA_CH ){ 379 dump_dma(fc, *dmach); 380 dump_db(fc, *dmach); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385 default: 386 break; 387 } 388 return err; 389} 390 391static int 392fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 393{ 394 u_int32_t reg, reg2; 395 int e1394a = 1; 396/* 397 * probe PHY parameters 398 * 0. to prove PHY version, whether compliance of 1394a. 399 * 1. to probe maximum speed supported by the PHY and 400 * number of port supported by core-logic. 401 * It is not actually available port on your PC . 402 */ 403 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 404 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 405 406 if((reg >> 5) != 7 ){ 407 sc->fc.mode &= ~FWPHYASYST; 408 sc->fc.nport = reg & FW_PHY_NP; 409 sc->fc.speed = reg & FW_PHY_SPD >> 6; 410 if (sc->fc.speed > MAX_SPEED) { 411 device_printf(dev, "invalid speed %d (fixed to %d).\n", 412 sc->fc.speed, MAX_SPEED); 413 sc->fc.speed = MAX_SPEED; 414 } 415 device_printf(dev, 416 "Phy 1394 only %s, %d ports.\n", 417 linkspeed[sc->fc.speed], sc->fc.nport); 418 }else{ 419 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 420 sc->fc.mode |= FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394a available %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 432 /* check programPhyEnable */ 433 reg2 = fwphy_rddata(sc, 5); 434#if 0 435 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 436#else /* XXX force to enable 1394a */ 437 if (e1394a) { 438#endif 439 if (bootverbose) 440 device_printf(dev, 441 "Enable 1394a Enhancements\n"); 442 /* enable EAA EMC */ 443 reg2 |= 0x03; 444 /* set aPhyEnhanceEnable */ 445 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 446 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 447 } else { 448 /* for safe */ 449 reg2 &= ~0x83; 450 } 451 reg2 = fwphy_wrdata(sc, 5, reg2); 452 } 453 454 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 455 if((reg >> 5) == 7 ){ 456 reg = fwphy_rddata(sc, 4); 457 reg |= 1 << 6; 458 fwphy_wrdata(sc, 4, reg); 459 reg = fwphy_rddata(sc, 4); 460 } 461 return 0; 462} 463 464 465void 466fwohci_reset(struct fwohci_softc *sc, device_t dev) 467{ 468 int i, max_rec, speed; 469 u_int32_t reg, reg2; 470 struct fwohcidb_tr *db_tr; 471 472 /* Disable interrupt */ 473 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 474 475 /* Now stopping all DMA channel */ 476 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 477 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 478 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 479 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 480 481 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 482 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 483 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 484 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 485 } 486 487 /* FLUSH FIFO and reset Transmitter/Reciever */ 488 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 489 if (bootverbose) 490 device_printf(dev, "resetting OHCI..."); 491 i = 0; 492 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 493 if (i++ > 100) break; 494 DELAY(1000); 495 } 496 if (bootverbose) 497 printf("done (loop=%d)\n", i); 498 499 /* Probe phy */ 500 fwohci_probe_phy(sc, dev); 501 502 /* Probe link */ 503 reg = OREAD(sc, OHCI_BUS_OPT); 504 reg2 = reg | OHCI_BUSFNC; 505 max_rec = (reg & 0x0000f000) >> 12; 506 speed = (reg & 0x00000007); 507 device_printf(dev, "Link %s, max_rec %d bytes.\n", 508 linkspeed[speed], MAXREC(max_rec)); 509 /* XXX fix max_rec */ 510 sc->fc.maxrec = sc->fc.speed + 8; 511 if (max_rec != sc->fc.maxrec) { 512 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 513 device_printf(dev, "max_rec %d -> %d\n", 514 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 515 } 516 if (bootverbose) 517 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 518 OWRITE(sc, OHCI_BUS_OPT, reg2); 519 520 /* Initialize registers */ 521 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 522 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 523 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 524 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 525 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 526 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 527 fw_busreset(&sc->fc); 528 529 /* Enable link */ 530 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 531 532 /* Force to start async RX DMA */ 533 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 534 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 535 fwohci_rx_enable(sc, &sc->arrq); 536 fwohci_rx_enable(sc, &sc->arrs); 537 538 /* Initialize async TX */ 539 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 540 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 541 542 /* AT Retries */ 543 OWRITE(sc, FWOHCI_RETRY, 544 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 545 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 546 547 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 548 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 549 sc->atrq.bottom = sc->atrq.top; 550 sc->atrs.bottom = sc->atrs.top; 551 552 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 553 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 554 db_tr->xfer = NULL; 555 } 556 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 558 db_tr->xfer = NULL; 559 } 560 561 562 /* Enable interrupt */ 563 OWRITE(sc, FWOHCI_INTMASK, 564 OHCI_INT_ERR | OHCI_INT_PHY_SID 565 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 566 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 567 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 568 fwohci_set_intr(&sc->fc, 1); 569 570} 571 572int 573fwohci_init(struct fwohci_softc *sc, device_t dev) 574{ 575 int i; 576 u_int32_t reg; 577 u_int8_t ui[8]; 578 579#if FWOHCI_TASKQUEUE 580 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 581#endif 582 583 reg = OREAD(sc, OHCI_VERSION); 584 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586 587/* Available Isochrounous DMA channel probe */ 588 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 589 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 590 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 591 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 592 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 593 for (i = 0; i < 0x20; i++) 594 if ((reg & (1 << i)) == 0) 595 break; 596 sc->fc.nisodma = i; 597 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 598 599 sc->fc.arq = &sc->arrq.xferq; 600 sc->fc.ars = &sc->arrs.xferq; 601 sc->fc.atq = &sc->atrq.xferq; 602 sc->fc.ats = &sc->atrs.xferq; 603 604 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 605 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 606 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 607 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 608 609 sc->arrq.xferq.start = NULL; 610 sc->arrs.xferq.start = NULL; 611 sc->atrq.xferq.start = fwohci_start_atq; 612 sc->atrs.xferq.start = fwohci_start_ats; 613 614 sc->arrq.xferq.buf = NULL; 615 sc->arrs.xferq.buf = NULL; 616 sc->atrq.xferq.buf = NULL; 617 sc->atrs.xferq.buf = NULL; 618 619 sc->arrq.xferq.dmach = -1; 620 sc->arrs.xferq.dmach = -1; 621 sc->atrq.xferq.dmach = -1; 622 sc->atrs.xferq.dmach = -1; 623 624 sc->arrq.ndesc = 1; 625 sc->arrs.ndesc = 1; 626 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 627 sc->atrs.ndesc = 2; 628 629 sc->arrq.ndb = NDB; 630 sc->arrs.ndb = NDB / 2; 631 sc->atrq.ndb = NDB; 632 sc->atrs.ndb = NDB / 2; 633 634 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 635 sc->fc.it[i] = &sc->it[i].xferq; 636 sc->fc.ir[i] = &sc->ir[i].xferq; 637 sc->it[i].xferq.dmach = i; 638 sc->ir[i].xferq.dmach = i; 639 sc->it[i].ndb = 0; 640 sc->ir[i].ndb = 0; 641 } 642 643 sc->fc.tcode = tinfo; 644 sc->fc.dev = dev; 645 646 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 647 &sc->crom_dma, BUS_DMA_WAITOK); 648 if(sc->fc.config_rom == NULL){ 649 device_printf(dev, "config_rom alloc failed."); 650 return ENOMEM; 651 } 652 653#if 0 654 bzero(&sc->fc.config_rom[0], CROMSIZE); 655 sc->fc.config_rom[1] = 0x31333934; 656 sc->fc.config_rom[2] = 0xf000a002; 657 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 658 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 659 sc->fc.config_rom[5] = 0; 660 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 661 662 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 663#endif 664 665 666/* SID recieve buffer must allign 2^11 */ 667#define OHCI_SIDSIZE (1 << 11) 668 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 669 &sc->sid_dma, BUS_DMA_WAITOK); 670 if (sc->sid_buf == NULL) { 671 device_printf(dev, "sid_buf alloc failed."); 672 return ENOMEM; 673 } 674 675 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 676 &sc->dummy_dma, BUS_DMA_WAITOK); 677 678 if (sc->dummy_dma.v_addr == NULL) { 679 device_printf(dev, "dummy_dma alloc failed."); 680 return ENOMEM; 681 } 682 683 fwohci_db_init(sc, &sc->arrq); 684 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 685 return ENOMEM; 686 687 fwohci_db_init(sc, &sc->arrs); 688 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 689 return ENOMEM; 690 691 fwohci_db_init(sc, &sc->atrq); 692 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 693 return ENOMEM; 694 695 fwohci_db_init(sc, &sc->atrs); 696 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 697 return ENOMEM; 698 699 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 700 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 701 for( i = 0 ; i < 8 ; i ++) 702 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 703 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 704 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 705 706 sc->fc.ioctl = fwohci_ioctl; 707 sc->fc.cyctimer = fwohci_cyctimer; 708 sc->fc.set_bmr = fwohci_set_bus_manager; 709 sc->fc.ibr = fwohci_ibr; 710 sc->fc.irx_enable = fwohci_irx_enable; 711 sc->fc.irx_disable = fwohci_irx_disable; 712 713 sc->fc.itx_enable = fwohci_itxbuf_enable; 714 sc->fc.itx_disable = fwohci_itx_disable; 715#if BYTE_ORDER == BIG_ENDIAN 716 sc->fc.irx_post = fwohci_irx_post; 717#else 718 sc->fc.irx_post = NULL; 719#endif 720 sc->fc.itx_post = NULL; 721 sc->fc.timeout = fwohci_timeout; 722 sc->fc.poll = fwohci_poll; 723 sc->fc.set_intr = fwohci_set_intr; 724 725 sc->intmask = sc->irstat = sc->itstat = 0; 726 727 fw_init(&sc->fc); 728 fwohci_reset(sc, dev); 729 730 return 0; 731} 732 733void 734fwohci_timeout(void *arg) 735{ 736 struct fwohci_softc *sc; 737 738 sc = (struct fwohci_softc *)arg; 739} 740 741u_int32_t 742fwohci_cyctimer(struct firewire_comm *fc) 743{ 744 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 745 return(OREAD(sc, OHCI_CYCLETIMER)); 746} 747 748int 749fwohci_detach(struct fwohci_softc *sc, device_t dev) 750{ 751 int i; 752 753 if (sc->sid_buf != NULL) 754 fwdma_free(&sc->fc, &sc->sid_dma); 755 if (sc->fc.config_rom != NULL) 756 fwdma_free(&sc->fc, &sc->crom_dma); 757 758 fwohci_db_free(&sc->arrq); 759 fwohci_db_free(&sc->arrs); 760 761 fwohci_db_free(&sc->atrq); 762 fwohci_db_free(&sc->atrs); 763 764 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 765 fwohci_db_free(&sc->it[i]); 766 fwohci_db_free(&sc->ir[i]); 767 } 768 769 return 0; 770} 771 772#define LAST_DB(dbtr, db) do { \ 773 struct fwohcidb_tr *_dbtr = (dbtr); \ 774 int _cnt = _dbtr->dbcnt; \ 775 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 776} while (0) 777 778static void 779fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 780{ 781 struct fwohcidb_tr *db_tr; 782 volatile struct fwohcidb *db; 783 bus_dma_segment_t *s; 784 int i; 785 786 db_tr = (struct fwohcidb_tr *)arg; 787 db = &db_tr->db[db_tr->dbcnt]; 788 if (error) { 789 if (firewire_debug || error != EFBIG) 790 printf("fwohci_execute_db: error=%d\n", error); 791 return; 792 } 793 for (i = 0; i < nseg; i++) { 794 s = &segs[i]; 795 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 796 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 797 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 798 db++; 799 db_tr->dbcnt++; 800 } 801} 802 803static void 804fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 805 bus_size_t size, int error) 806{ 807 fwohci_execute_db(arg, segs, nseg, error); 808} 809 810static void 811fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 812{ 813 int i, s; 814 int tcode, hdr_len, pl_off, pl_len; 815 int fsegment = -1; 816 u_int32_t off; 817 struct fw_xfer *xfer; 818 struct fw_pkt *fp; 819 volatile struct fwohci_txpkthdr *ohcifp; 820 struct fwohcidb_tr *db_tr; 821 volatile struct fwohcidb *db; 822 struct tcode_info *info; 823 static int maxdesc=0; 824 825 if(&sc->atrq == dbch){ 826 off = OHCI_ATQOFF; 827 }else if(&sc->atrs == dbch){ 828 off = OHCI_ATSOFF; 829 }else{ 830 return; 831 } 832 833 if (dbch->flags & FWOHCI_DBCH_FULL) 834 return; 835 836 s = splfw(); 837 db_tr = dbch->top; 838txloop: 839 xfer = STAILQ_FIRST(&dbch->xferq.q); 840 if(xfer == NULL){ 841 goto kick; 842 } 843 if(dbch->xferq.queued == 0 ){ 844 device_printf(sc->fc.dev, "TX queue empty\n"); 845 } 846 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 847 db_tr->xfer = xfer; 848 xfer->state = FWXF_START; 849 850 fp = (struct fw_pkt *)xfer->send.buf; 851 tcode = fp->mode.common.tcode; 852 853 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 854 info = &tinfo[tcode]; 855 hdr_len = pl_off = info->hdr_len; 856 for( i = 0 ; i < pl_off ; i+= 4){ 857 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 858 } 859 ohcifp->mode.common.spd = xfer->spd; 860 if (tcode == FWTCODE_STREAM ){ 861 hdr_len = 8; 862 ohcifp->mode.stream.len = fp->mode.stream.len; 863 } else if (tcode == FWTCODE_PHY) { 864 hdr_len = 12; 865 ohcifp->mode.ld[1] = fp->mode.ld[1]; 866 ohcifp->mode.ld[2] = fp->mode.ld[2]; 867 ohcifp->mode.common.spd = 0; 868 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 869 } else { 870 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 871 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 872 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 873 } 874 db = &db_tr->db[0]; 875 FWOHCI_DMA_WRITE(db->db.desc.cmd, 876 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 877 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 878/* Specify bound timer of asy. responce */ 879 if(&sc->atrs == dbch){ 880 FWOHCI_DMA_WRITE(db->db.desc.res, 881 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 882 } 883#if BYTE_ORDER == BIG_ENDIAN 884 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 885 hdr_len = 12; 886 for (i = 0; i < hdr_len/4; i ++) 887 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 888#endif 889 890again: 891 db_tr->dbcnt = 2; 892 db = &db_tr->db[db_tr->dbcnt]; 893 pl_len = xfer->send.len - pl_off; 894 if (pl_len > 0) { 895 int err; 896 /* handle payload */ 897 if (xfer->mbuf == NULL) { 898 caddr_t pl_addr; 899 900 pl_addr = xfer->send.buf + pl_off; 901 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 902 pl_addr, pl_len, 903 fwohci_execute_db, db_tr, 904 /*flags*/0); 905 } else { 906 /* XXX we can handle only 6 (=8-2) mbuf chains */ 907 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 908 xfer->mbuf, 909 fwohci_execute_db2, db_tr, 910 /* flags */0); 911 if (err == EFBIG) { 912 struct mbuf *m0; 913 914 if (firewire_debug) 915 device_printf(sc->fc.dev, "EFBIG.\n"); 916 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 917 if (m0 != NULL) { 918 m_copydata(xfer->mbuf, 0, 919 xfer->mbuf->m_pkthdr.len, 920 mtod(m0, caddr_t)); 921 m0->m_len = m0->m_pkthdr.len = 922 xfer->mbuf->m_pkthdr.len; 923 m_freem(xfer->mbuf); 924 xfer->mbuf = m0; 925 goto again; 926 } 927 device_printf(sc->fc.dev, "m_getcl failed.\n"); 928 } 929 } 930 if (err) 931 printf("dmamap_load: err=%d\n", err); 932 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 933 BUS_DMASYNC_PREWRITE); 934#if 0 /* OHCI_OUTPUT_MODE == 0 */ 935 for (i = 2; i < db_tr->dbcnt; i++) 936 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 937 OHCI_OUTPUT_MORE); 938#endif 939 } 940 if (maxdesc < db_tr->dbcnt) { 941 maxdesc = db_tr->dbcnt; 942 if (bootverbose) 943 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 944 } 945 /* last db */ 946 LAST_DB(db_tr, db); 947 FWOHCI_DMA_SET(db->db.desc.cmd, 948 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 949 FWOHCI_DMA_WRITE(db->db.desc.depend, 950 STAILQ_NEXT(db_tr, link)->bus_addr); 951 952 if(fsegment == -1 ) 953 fsegment = db_tr->dbcnt; 954 if (dbch->pdb_tr != NULL) { 955 LAST_DB(dbch->pdb_tr, db); 956 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 957 } 958 dbch->pdb_tr = db_tr; 959 db_tr = STAILQ_NEXT(db_tr, link); 960 if(db_tr != dbch->bottom){ 961 goto txloop; 962 } else { 963 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 964 dbch->flags |= FWOHCI_DBCH_FULL; 965 } 966kick: 967 /* kick asy q */ 968 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 969 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 970 971 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 972 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 973 } else { 974 if (bootverbose) 975 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 976 OREAD(sc, OHCI_DMACTL(off))); 977 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 978 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 979 dbch->xferq.flag |= FWXFERQ_RUNNING; 980 } 981 982 dbch->top = db_tr; 983 splx(s); 984 return; 985} 986 987static void 988fwohci_start_atq(struct firewire_comm *fc) 989{ 990 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 991 fwohci_start( sc, &(sc->atrq)); 992 return; 993} 994 995static void 996fwohci_start_ats(struct firewire_comm *fc) 997{ 998 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 999 fwohci_start( sc, &(sc->atrs)); 1000 return; 1001} 1002 1003void 1004fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1005{ 1006 int s, ch, err = 0; 1007 struct fwohcidb_tr *tr; 1008 volatile struct fwohcidb *db; 1009 struct fw_xfer *xfer; 1010 u_int32_t off; 1011 u_int stat, status; 1012 int packets; 1013 struct firewire_comm *fc = (struct firewire_comm *)sc; 1014 1015 if(&sc->atrq == dbch){ 1016 off = OHCI_ATQOFF; 1017 ch = ATRQ_CH; 1018 }else if(&sc->atrs == dbch){ 1019 off = OHCI_ATSOFF; 1020 ch = ATRS_CH; 1021 }else{ 1022 return; 1023 } 1024 s = splfw(); 1025 tr = dbch->bottom; 1026 packets = 0; 1027 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1028 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1029 while(dbch->xferq.queued > 0){ 1030 LAST_DB(tr, db); 1031 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1032 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1033 if (fc->status != FWBUSRESET) 1034 /* maybe out of order?? */ 1035 goto out; 1036 } 1037 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1038 BUS_DMASYNC_POSTWRITE); 1039 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1040#if 0 1041 dump_db(sc, ch); 1042#endif 1043 if(status & OHCI_CNTL_DMA_DEAD) { 1044 /* Stop DMA */ 1045 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1046 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1047 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1048 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1049 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1050 } 1051 stat = status & FWOHCIEV_MASK; 1052 switch(stat){ 1053 case FWOHCIEV_ACKPEND: 1054 case FWOHCIEV_ACKCOMPL: 1055 err = 0; 1056 break; 1057 case FWOHCIEV_ACKBSA: 1058 case FWOHCIEV_ACKBSB: 1059 case FWOHCIEV_ACKBSX: 1060 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1061 err = EBUSY; 1062 break; 1063 case FWOHCIEV_FLUSHED: 1064 case FWOHCIEV_ACKTARD: 1065 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1066 err = EAGAIN; 1067 break; 1068 case FWOHCIEV_MISSACK: 1069 case FWOHCIEV_UNDRRUN: 1070 case FWOHCIEV_OVRRUN: 1071 case FWOHCIEV_DESCERR: 1072 case FWOHCIEV_DTRDERR: 1073 case FWOHCIEV_TIMEOUT: 1074 case FWOHCIEV_TCODERR: 1075 case FWOHCIEV_UNKNOWN: 1076 case FWOHCIEV_ACKDERR: 1077 case FWOHCIEV_ACKTERR: 1078 default: 1079 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1080 stat, fwohcicode[stat]); 1081 err = EINVAL; 1082 break; 1083 } 1084 if (tr->xfer != NULL) { 1085 xfer = tr->xfer; 1086 if (xfer->state == FWXF_RCVD) { 1087 if (firewire_debug) 1088 printf("already rcvd\n"); 1089 fw_xfer_done(xfer); 1090 } else { 1091 xfer->state = FWXF_SENT; 1092 if (err == EBUSY && fc->status != FWBUSRESET) { 1093 xfer->state = FWXF_BUSY; 1094 xfer->resp = err; 1095 if (xfer->retry_req != NULL) 1096 xfer->retry_req(xfer); 1097 else { 1098 xfer->recv.len = 0; 1099 fw_xfer_done(xfer); 1100 } 1101 } else if (stat != FWOHCIEV_ACKPEND) { 1102 if (stat != FWOHCIEV_ACKCOMPL) 1103 xfer->state = FWXF_SENTERR; 1104 xfer->resp = err; 1105 xfer->recv.len = 0; 1106 fw_xfer_done(xfer); 1107 } 1108 } 1109 /* 1110 * The watchdog timer takes care of split 1111 * transcation timeout for ACKPEND case. 1112 */ 1113 } else { 1114 printf("this shouldn't happen\n"); 1115 } 1116 dbch->xferq.queued --; 1117 tr->xfer = NULL; 1118 1119 packets ++; 1120 tr = STAILQ_NEXT(tr, link); 1121 dbch->bottom = tr; 1122 if (dbch->bottom == dbch->top) { 1123 /* we reaches the end of context program */ 1124 if (firewire_debug && dbch->xferq.queued > 0) 1125 printf("queued > 0\n"); 1126 break; 1127 } 1128 } 1129out: 1130 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1131 printf("make free slot\n"); 1132 dbch->flags &= ~FWOHCI_DBCH_FULL; 1133 fwohci_start(sc, dbch); 1134 } 1135 splx(s); 1136} 1137 1138static void 1139fwohci_db_free(struct fwohci_dbch *dbch) 1140{ 1141 struct fwohcidb_tr *db_tr; 1142 int idb; 1143 1144 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1145 return; 1146 1147 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1148 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1149 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1150 db_tr->buf != NULL) { 1151 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1152 db_tr->buf, dbch->xferq.psize); 1153 db_tr->buf = NULL; 1154 } else if (db_tr->dma_map != NULL) 1155 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1156 } 1157 dbch->ndb = 0; 1158 db_tr = STAILQ_FIRST(&dbch->db_trq); 1159 fwdma_free_multiseg(dbch->am); 1160 free(db_tr, M_FW); 1161 STAILQ_INIT(&dbch->db_trq); 1162 dbch->flags &= ~FWOHCI_DBCH_INIT; 1163} 1164 1165static void 1166fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1167{ 1168 int idb; 1169 struct fwohcidb_tr *db_tr; 1170 1171 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1172 goto out; 1173 1174 /* create dma_tag for buffers */ 1175#define MAX_REQCOUNT 0xffff 1176 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1177 /*alignment*/ 1, /*boundary*/ 0, 1178 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1179 /*highaddr*/ BUS_SPACE_MAXADDR, 1180 /*filter*/NULL, /*filterarg*/NULL, 1181 /*maxsize*/ dbch->xferq.psize, 1182 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1183 /*maxsegsz*/ MAX_REQCOUNT, 1184 /*flags*/ 0, 1185#if __FreeBSD_version >= 501102 1186 /*lockfunc*/busdma_lock_mutex, 1187 /*lockarg*/&Giant, 1188#endif 1189 &dbch->dmat)) 1190 return; 1191 1192 /* allocate DB entries and attach one to each DMA channels */ 1193 /* DB entry must start at 16 bytes bounary. */ 1194 STAILQ_INIT(&dbch->db_trq); 1195 db_tr = (struct fwohcidb_tr *) 1196 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1197 M_FW, M_WAITOK | M_ZERO); 1198 if(db_tr == NULL){ 1199 printf("fwohci_db_init: malloc(1) failed\n"); 1200 return; 1201 } 1202 1203#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1204 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1205 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1206 if (dbch->am == NULL) { 1207 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1208 return; 1209 } 1210 /* Attach DB to DMA ch. */ 1211 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1212 db_tr->dbcnt = 0; 1213 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1214 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1215 /* create dmamap for buffers */ 1216 /* XXX do we need 4bytes alignment tag? */ 1217 /* XXX don't alloc dma_map for AR */ 1218 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1219 printf("bus_dmamap_create failed\n"); 1220 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1221 fwohci_db_free(dbch); 1222 return; 1223 } 1224 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1225 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1226 if (idb % dbch->xferq.bnpacket == 0) 1227 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1228 ].start = (caddr_t)db_tr; 1229 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1230 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1231 ].end = (caddr_t)db_tr; 1232 } 1233 db_tr++; 1234 } 1235 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1236 = STAILQ_FIRST(&dbch->db_trq); 1237out: 1238 dbch->xferq.queued = 0; 1239 dbch->pdb_tr = NULL; 1240 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1241 dbch->bottom = dbch->top; 1242 dbch->flags = FWOHCI_DBCH_INIT; 1243} 1244 1245static int 1246fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1247{ 1248 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1249 int sleepch; 1250 1251 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1252 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1253 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1254 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1255 /* XXX we cannot free buffers until the DMA really stops */ 1256 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1257 fwohci_db_free(&sc->it[dmach]); 1258 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1259 return 0; 1260} 1261 1262static int 1263fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1264{ 1265 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1266 int sleepch; 1267 1268 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1269 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1270 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1271 /* XXX we cannot free buffers until the DMA really stops */ 1272 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1273 fwohci_db_free(&sc->ir[dmach]); 1274 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1275 return 0; 1276} 1277 1278#if BYTE_ORDER == BIG_ENDIAN 1279static void 1280fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1281{ 1282 qld[0] = FWOHCI_DMA_READ(qld[0]); 1283 return; 1284} 1285#endif 1286 1287static int 1288fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1289{ 1290 int err = 0; 1291 int idb, z, i, dmach = 0, ldesc; 1292 u_int32_t off = NULL; 1293 struct fwohcidb_tr *db_tr; 1294 volatile struct fwohcidb *db; 1295 1296 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1297 err = EINVAL; 1298 return err; 1299 } 1300 z = dbch->ndesc; 1301 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1302 if( &sc->it[dmach] == dbch){ 1303 off = OHCI_ITOFF(dmach); 1304 break; 1305 } 1306 } 1307 if(off == NULL){ 1308 err = EINVAL; 1309 return err; 1310 } 1311 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1312 return err; 1313 dbch->xferq.flag |= FWXFERQ_RUNNING; 1314 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1315 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1316 } 1317 db_tr = dbch->top; 1318 for (idb = 0; idb < dbch->ndb; idb ++) { 1319 fwohci_add_tx_buf(dbch, db_tr, idb); 1320 if(STAILQ_NEXT(db_tr, link) == NULL){ 1321 break; 1322 } 1323 db = db_tr->db; 1324 ldesc = db_tr->dbcnt - 1; 1325 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1326 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1327 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1328 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1329 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1330 FWOHCI_DMA_SET( 1331 db[ldesc].db.desc.cmd, 1332 OHCI_INTERRUPT_ALWAYS); 1333 /* OHCI 1.1 and above */ 1334 FWOHCI_DMA_SET( 1335 db[0].db.desc.cmd, 1336 OHCI_INTERRUPT_ALWAYS); 1337 } 1338 } 1339 db_tr = STAILQ_NEXT(db_tr, link); 1340 } 1341 FWOHCI_DMA_CLEAR( 1342 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1343 return err; 1344} 1345 1346static int 1347fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1348{ 1349 int err = 0; 1350 int idb, z, i, dmach = 0, ldesc; 1351 u_int32_t off = NULL; 1352 struct fwohcidb_tr *db_tr; 1353 volatile struct fwohcidb *db; 1354 1355 z = dbch->ndesc; 1356 if(&sc->arrq == dbch){ 1357 off = OHCI_ARQOFF; 1358 }else if(&sc->arrs == dbch){ 1359 off = OHCI_ARSOFF; 1360 }else{ 1361 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1362 if( &sc->ir[dmach] == dbch){ 1363 off = OHCI_IROFF(dmach); 1364 break; 1365 } 1366 } 1367 } 1368 if(off == NULL){ 1369 err = EINVAL; 1370 return err; 1371 } 1372 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1373 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1374 return err; 1375 }else{ 1376 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1377 err = EBUSY; 1378 return err; 1379 } 1380 } 1381 dbch->xferq.flag |= FWXFERQ_RUNNING; 1382 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1383 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1384 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1385 } 1386 db_tr = dbch->top; 1387 for (idb = 0; idb < dbch->ndb; idb ++) { 1388 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1389 if (STAILQ_NEXT(db_tr, link) == NULL) 1390 break; 1391 db = db_tr->db; 1392 ldesc = db_tr->dbcnt - 1; 1393 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1394 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1395 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1396 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1397 FWOHCI_DMA_SET( 1398 db[ldesc].db.desc.cmd, 1399 OHCI_INTERRUPT_ALWAYS); 1400 FWOHCI_DMA_CLEAR( 1401 db[ldesc].db.desc.depend, 1402 0xf); 1403 } 1404 } 1405 db_tr = STAILQ_NEXT(db_tr, link); 1406 } 1407 FWOHCI_DMA_CLEAR( 1408 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1409 dbch->buf_offset = 0; 1410 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1411 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1412 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1413 return err; 1414 }else{ 1415 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1416 } 1417 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1418 return err; 1419} 1420 1421static int 1422fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1423{ 1424 int sec, cycle, cycle_match; 1425 1426 cycle = cycle_now & 0x1fff; 1427 sec = cycle_now >> 13; 1428#define CYCLE_MOD 0x10 1429#if 1 1430#define CYCLE_DELAY 8 /* min delay to start DMA */ 1431#else 1432#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1433#endif 1434 cycle = cycle + CYCLE_DELAY; 1435 if (cycle >= 8000) { 1436 sec ++; 1437 cycle -= 8000; 1438 } 1439 cycle = roundup2(cycle, CYCLE_MOD); 1440 if (cycle >= 8000) { 1441 sec ++; 1442 if (cycle == 8000) 1443 cycle = 0; 1444 else 1445 cycle = CYCLE_MOD; 1446 } 1447 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1448 1449 return(cycle_match); 1450} 1451 1452static int 1453fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1454{ 1455 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1456 int err = 0; 1457 unsigned short tag, ich; 1458 struct fwohci_dbch *dbch; 1459 int cycle_match, cycle_now, s, ldesc; 1460 u_int32_t stat; 1461 struct fw_bulkxfer *first, *chunk, *prev; 1462 struct fw_xferq *it; 1463 1464 dbch = &sc->it[dmach]; 1465 it = &dbch->xferq; 1466 1467 tag = (it->flag >> 6) & 3; 1468 ich = it->flag & 0x3f; 1469 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1470 dbch->ndb = it->bnpacket * it->bnchunk; 1471 dbch->ndesc = 3; 1472 fwohci_db_init(sc, dbch); 1473 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1474 return ENOMEM; 1475 err = fwohci_tx_enable(sc, dbch); 1476 } 1477 if(err) 1478 return err; 1479 1480 ldesc = dbch->ndesc - 1; 1481 s = splfw(); 1482 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1483 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1484 volatile struct fwohcidb *db; 1485 1486 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1487 BUS_DMASYNC_PREWRITE); 1488 fwohci_txbufdb(sc, dmach, chunk); 1489 if (prev != NULL) { 1490 db = ((struct fwohcidb_tr *)(prev->end))->db; 1491#if 0 /* XXX necessary? */ 1492 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1493 OHCI_BRANCH_ALWAYS); 1494#endif 1495#if 0 /* if bulkxfer->npacket changes */ 1496 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1497 ((struct fwohcidb_tr *) 1498 (chunk->start))->bus_addr | dbch->ndesc; 1499#else 1500 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1501 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1502#endif 1503 } 1504 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1505 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1506 prev = chunk; 1507 } 1508 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1509 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1510 splx(s); 1511 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1512 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1513 printf("stat 0x%x\n", stat); 1514 1515 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1516 return 0; 1517 1518#if 0 1519 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1520#endif 1521 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1522 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1523 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1524 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1525 1526 first = STAILQ_FIRST(&it->stdma); 1527 OWRITE(sc, OHCI_ITCMD(dmach), 1528 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1529 if (firewire_debug) { 1530 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1531#if 1 1532 dump_dma(sc, ITX_CH + dmach); 1533#endif 1534 } 1535 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1536#if 1 1537 /* Don't start until all chunks are buffered */ 1538 if (STAILQ_FIRST(&it->stfree) != NULL) 1539 goto out; 1540#endif 1541#if 1 1542 /* Clear cycle match counter bits */ 1543 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1544 1545 /* 2bit second + 13bit cycle */ 1546 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1547 cycle_match = fwohci_next_cycle(fc, cycle_now); 1548 1549 OWRITE(sc, OHCI_ITCTL(dmach), 1550 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1551 | OHCI_CNTL_DMA_RUN); 1552#else 1553 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1554#endif 1555 if (firewire_debug) { 1556 printf("cycle_match: 0x%04x->0x%04x\n", 1557 cycle_now, cycle_match); 1558 dump_dma(sc, ITX_CH + dmach); 1559 dump_db(sc, ITX_CH + dmach); 1560 } 1561 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1562 device_printf(sc->fc.dev, 1563 "IT DMA underrun (0x%08x)\n", stat); 1564 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1565 } 1566out: 1567 return err; 1568} 1569 1570static int 1571fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1572{ 1573 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1574 int err = 0, s, ldesc; 1575 unsigned short tag, ich; 1576 u_int32_t stat; 1577 struct fwohci_dbch *dbch; 1578 struct fwohcidb_tr *db_tr; 1579 struct fw_bulkxfer *first, *prev, *chunk; 1580 struct fw_xferq *ir; 1581 1582 dbch = &sc->ir[dmach]; 1583 ir = &dbch->xferq; 1584 1585 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1586 tag = (ir->flag >> 6) & 3; 1587 ich = ir->flag & 0x3f; 1588 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1589 1590 ir->queued = 0; 1591 dbch->ndb = ir->bnpacket * ir->bnchunk; 1592 dbch->ndesc = 2; 1593 fwohci_db_init(sc, dbch); 1594 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1595 return ENOMEM; 1596 err = fwohci_rx_enable(sc, dbch); 1597 } 1598 if(err) 1599 return err; 1600 1601 first = STAILQ_FIRST(&ir->stfree); 1602 if (first == NULL) { 1603 device_printf(fc->dev, "IR DMA no free chunk\n"); 1604 return 0; 1605 } 1606 1607 ldesc = dbch->ndesc - 1; 1608 s = splfw(); 1609 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1610 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1611 volatile struct fwohcidb *db; 1612 1613#if 1 /* XXX for if_fwe */ 1614 if (chunk->mbuf != NULL) { 1615 db_tr = (struct fwohcidb_tr *)(chunk->start); 1616 db_tr->dbcnt = 1; 1617 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1618 chunk->mbuf, fwohci_execute_db2, db_tr, 1619 /* flags */0); 1620 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1621 OHCI_UPDATE | OHCI_INPUT_LAST | 1622 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1623 } 1624#endif 1625 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1626 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1627 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1628 if (prev != NULL) { 1629 db = ((struct fwohcidb_tr *)(prev->end))->db; 1630 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1631 } 1632 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1633 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1634 prev = chunk; 1635 } 1636 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1637 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1638 splx(s); 1639 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1640 if (stat & OHCI_CNTL_DMA_ACTIVE) 1641 return 0; 1642 if (stat & OHCI_CNTL_DMA_RUN) { 1643 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1644 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1645 } 1646 1647 if (firewire_debug) 1648 printf("start IR DMA 0x%x\n", stat); 1649 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1650 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1651 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1652 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1653 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1654 OWRITE(sc, OHCI_IRCMD(dmach), 1655 ((struct fwohcidb_tr *)(first->start))->bus_addr 1656 | dbch->ndesc); 1657 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1658 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1659#if 0 1660 dump_db(sc, IRX_CH + dmach); 1661#endif 1662 return err; 1663} 1664 1665int 1666fwohci_stop(struct fwohci_softc *sc, device_t dev) 1667{ 1668 u_int i; 1669 1670/* Now stopping all DMA channel */ 1671 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1672 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1673 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1674 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1675 1676 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1677 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1678 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1679 } 1680 1681/* FLUSH FIFO and reset Transmitter/Reciever */ 1682 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1683 1684/* Stop interrupt */ 1685 OWRITE(sc, FWOHCI_INTMASKCLR, 1686 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1687 | OHCI_INT_PHY_INT 1688 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1689 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1690 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1691 | OHCI_INT_PHY_BUS_R); 1692 1693 fw_drain_txq(&sc->fc); 1694 1695/* XXX Link down? Bus reset? */ 1696 return 0; 1697} 1698 1699int 1700fwohci_resume(struct fwohci_softc *sc, device_t dev) 1701{ 1702 int i; 1703 struct fw_xferq *ir; 1704 struct fw_bulkxfer *chunk; 1705 1706 fwohci_reset(sc, dev); 1707 /* XXX resume isochronus receive automatically. (how about TX?) */ 1708 for(i = 0; i < sc->fc.nisodma; i ++) { 1709 ir = &sc->ir[i].xferq; 1710 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1711 device_printf(sc->fc.dev, 1712 "resume iso receive ch: %d\n", i); 1713 ir->flag &= ~FWXFERQ_RUNNING; 1714 /* requeue stdma to stfree */ 1715 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1716 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1717 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1718 } 1719 sc->fc.irx_enable(&sc->fc, i); 1720 } 1721 } 1722 1723 bus_generic_resume(dev); 1724 sc->fc.ibr(&sc->fc); 1725 return 0; 1726} 1727 1728#define ACK_ALL 1729static void 1730fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1731{ 1732 u_int32_t irstat, itstat; 1733 u_int i; 1734 struct firewire_comm *fc = (struct firewire_comm *)sc; 1735 1736#ifdef OHCI_DEBUG 1737 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1738 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1739 stat & OHCI_INT_EN ? "DMA_EN ":"", 1740 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1741 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1742 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1743 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1744 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1745 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1746 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1747 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1748 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1749 stat & OHCI_INT_PHY_SID ? "SID ":"", 1750 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1751 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1752 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1753 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1754 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1755 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1756 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1757 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1758 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1759 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1760 stat, OREAD(sc, FWOHCI_INTMASK) 1761 ); 1762#endif 1763/* Bus reset */ 1764 if(stat & OHCI_INT_PHY_BUS_R ){ 1765 if (fc->status == FWBUSRESET) 1766 goto busresetout; 1767 /* Disable bus reset interrupt until sid recv. */ 1768 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1769 1770 device_printf(fc->dev, "BUS reset\n"); 1771 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1772 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1773 1774 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1775 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1776 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1777 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1778 1779#ifndef ACK_ALL 1780 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1781#endif 1782 fw_busreset(fc); 1783 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1784 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1785 } 1786busresetout: 1787 if((stat & OHCI_INT_DMA_IR )){ 1788#ifndef ACK_ALL 1789 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1790#endif 1791#if __FreeBSD_version >= 500000 1792 irstat = atomic_readandclear_int(&sc->irstat); 1793#else 1794 irstat = sc->irstat; 1795 sc->irstat = 0; 1796#endif 1797 for(i = 0; i < fc->nisodma ; i++){ 1798 struct fwohci_dbch *dbch; 1799 1800 if((irstat & (1 << i)) != 0){ 1801 dbch = &sc->ir[i]; 1802 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1803 device_printf(sc->fc.dev, 1804 "dma(%d) not active\n", i); 1805 continue; 1806 } 1807 fwohci_rbuf_update(sc, i); 1808 } 1809 } 1810 } 1811 if((stat & OHCI_INT_DMA_IT )){ 1812#ifndef ACK_ALL 1813 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1814#endif 1815#if __FreeBSD_version >= 500000 1816 itstat = atomic_readandclear_int(&sc->itstat); 1817#else 1818 itstat = sc->itstat; 1819 sc->itstat = 0; 1820#endif 1821 for(i = 0; i < fc->nisodma ; i++){ 1822 if((itstat & (1 << i)) != 0){ 1823 fwohci_tbuf_update(sc, i); 1824 } 1825 } 1826 } 1827 if((stat & OHCI_INT_DMA_PRRS )){ 1828#ifndef ACK_ALL 1829 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1830#endif 1831#if 0 1832 dump_dma(sc, ARRS_CH); 1833 dump_db(sc, ARRS_CH); 1834#endif 1835 fwohci_arcv(sc, &sc->arrs, count); 1836 } 1837 if((stat & OHCI_INT_DMA_PRRQ )){ 1838#ifndef ACK_ALL 1839 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1840#endif 1841#if 0 1842 dump_dma(sc, ARRQ_CH); 1843 dump_db(sc, ARRQ_CH); 1844#endif 1845 fwohci_arcv(sc, &sc->arrq, count); 1846 } 1847 if(stat & OHCI_INT_PHY_SID){ 1848 u_int32_t *buf, node_id; 1849 int plen; 1850 1851#ifndef ACK_ALL 1852 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1853#endif 1854 /* Enable bus reset interrupt */ 1855 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1856 /* Allow async. request to us */ 1857 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1858 /* XXX insecure ?? */ 1859 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1860 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1861 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1862 /* Set ATRetries register */ 1863 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1864/* 1865** Checking whether the node is root or not. If root, turn on 1866** cycle master. 1867*/ 1868 node_id = OREAD(sc, FWOHCI_NODEID); 1869 plen = OREAD(sc, OHCI_SID_CNT); 1870 1871 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1872 node_id, (plen >> 16) & 0xff); 1873 if (!(node_id & OHCI_NODE_VALID)) { 1874 printf("Bus reset failure\n"); 1875 goto sidout; 1876 } 1877 if (node_id & OHCI_NODE_ROOT) { 1878 printf("CYCLEMASTER mode\n"); 1879 OWRITE(sc, OHCI_LNKCTL, 1880 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1881 } else { 1882 printf("non CYCLEMASTER mode\n"); 1883 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1884 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1885 } 1886 fc->nodeid = node_id & 0x3f; 1887 1888 if (plen & OHCI_SID_ERR) { 1889 device_printf(fc->dev, "SID Error\n"); 1890 goto sidout; 1891 } 1892 plen &= OHCI_SID_CNT_MASK; 1893 if (plen < 4 || plen > OHCI_SIDSIZE) { 1894 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1895 goto sidout; 1896 } 1897 plen -= 4; /* chop control info */ 1898 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1899 if (buf == NULL) { 1900 device_printf(fc->dev, "malloc failed\n"); 1901 goto sidout; 1902 } 1903 for (i = 0; i < plen / 4; i ++) 1904 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1905#if 1 1906 /* pending all pre-bus_reset packets */ 1907 fwohci_txd(sc, &sc->atrq); 1908 fwohci_txd(sc, &sc->atrs); 1909 fwohci_arcv(sc, &sc->arrs, -1); 1910 fwohci_arcv(sc, &sc->arrq, -1); 1911 fw_drain_txq(fc); 1912#endif 1913 fw_sidrcv(fc, buf, plen); 1914 free(buf, M_FW); 1915 } 1916sidout: 1917 if((stat & OHCI_INT_DMA_ATRQ )){ 1918#ifndef ACK_ALL 1919 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1920#endif 1921 fwohci_txd(sc, &(sc->atrq)); 1922 } 1923 if((stat & OHCI_INT_DMA_ATRS )){ 1924#ifndef ACK_ALL 1925 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1926#endif 1927 fwohci_txd(sc, &(sc->atrs)); 1928 } 1929 if((stat & OHCI_INT_PW_ERR )){ 1930#ifndef ACK_ALL 1931 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1932#endif 1933 device_printf(fc->dev, "posted write error\n"); 1934 } 1935 if((stat & OHCI_INT_ERR )){ 1936#ifndef ACK_ALL 1937 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1938#endif 1939 device_printf(fc->dev, "unrecoverable error\n"); 1940 } 1941 if((stat & OHCI_INT_PHY_INT)) { 1942#ifndef ACK_ALL 1943 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1944#endif 1945 device_printf(fc->dev, "phy int\n"); 1946 } 1947 1948 return; 1949} 1950 1951#if FWOHCI_TASKQUEUE 1952static void 1953fwohci_complete(void *arg, int pending) 1954{ 1955 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1956 u_int32_t stat; 1957 1958again: 1959 stat = atomic_readandclear_int(&sc->intstat); 1960 if (stat) 1961 fwohci_intr_body(sc, stat, -1); 1962 else 1963 return; 1964 goto again; 1965} 1966#endif 1967 1968static u_int32_t 1969fwochi_check_stat(struct fwohci_softc *sc) 1970{ 1971 u_int32_t stat, irstat, itstat; 1972 1973 stat = OREAD(sc, FWOHCI_INTSTAT); 1974 if (stat == 0xffffffff) { 1975 device_printf(sc->fc.dev, 1976 "device physically ejected?\n"); 1977 return(stat); 1978 } 1979#ifdef ACK_ALL 1980 if (stat) 1981 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1982#endif 1983 if (stat & OHCI_INT_DMA_IR) { 1984 irstat = OREAD(sc, OHCI_IR_STAT); 1985 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1986 atomic_set_int(&sc->irstat, irstat); 1987 } 1988 if (stat & OHCI_INT_DMA_IT) { 1989 itstat = OREAD(sc, OHCI_IT_STAT); 1990 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1991 atomic_set_int(&sc->itstat, itstat); 1992 } 1993 return(stat); 1994} 1995 1996void 1997fwohci_intr(void *arg) 1998{ 1999 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2000 u_int32_t stat; 2001#if !FWOHCI_TASKQUEUE 2002 u_int32_t bus_reset = 0; 2003#endif 2004 2005 if (!(sc->intmask & OHCI_INT_EN)) { 2006 /* polling mode */ 2007 return; 2008 } 2009 2010#if !FWOHCI_TASKQUEUE 2011again: 2012#endif 2013 stat = fwochi_check_stat(sc); 2014 if (stat == 0 || stat == 0xffffffff) 2015 return; 2016#if FWOHCI_TASKQUEUE 2017 atomic_set_int(&sc->intstat, stat); 2018 /* XXX mask bus reset intr. during bus reset phase */ 2019 if (stat) 2020 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2021#else 2022 /* We cannot clear bus reset event during bus reset phase */ 2023 if ((stat & ~bus_reset) == 0) 2024 return; 2025 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2026 fwohci_intr_body(sc, stat, -1); 2027 goto again; 2028#endif 2029} 2030 2031void 2032fwohci_poll(struct firewire_comm *fc, int quick, int count) 2033{ 2034 int s; 2035 u_int32_t stat; 2036 struct fwohci_softc *sc; 2037 2038 2039 sc = (struct fwohci_softc *)fc; 2040 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2041 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2042 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2043#if 0 2044 if (!quick) { 2045#else 2046 if (1) { 2047#endif 2048 stat = fwochi_check_stat(sc); 2049 if (stat == 0 || stat == 0xffffffff) 2050 return; 2051 } 2052 s = splfw(); 2053 fwohci_intr_body(sc, stat, count); 2054 splx(s); 2055} 2056 2057static void 2058fwohci_set_intr(struct firewire_comm *fc, int enable) 2059{ 2060 struct fwohci_softc *sc; 2061 2062 sc = (struct fwohci_softc *)fc; 2063 if (bootverbose) 2064 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2065 if (enable) { 2066 sc->intmask |= OHCI_INT_EN; 2067 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2068 } else { 2069 sc->intmask &= ~OHCI_INT_EN; 2070 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2071 } 2072} 2073 2074static void 2075fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2076{ 2077 struct firewire_comm *fc = &sc->fc; 2078 volatile struct fwohcidb *db; 2079 struct fw_bulkxfer *chunk; 2080 struct fw_xferq *it; 2081 u_int32_t stat, count; 2082 int s, w=0, ldesc; 2083 2084 it = fc->it[dmach]; 2085 ldesc = sc->it[dmach].ndesc - 1; 2086 s = splfw(); /* unnecessary ? */ 2087 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2088 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2089 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2090 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2091 >> OHCI_STATUS_SHIFT; 2092 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2093 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2094 & OHCI_COUNT_MASK; 2095 if (stat == 0) 2096 break; 2097 STAILQ_REMOVE_HEAD(&it->stdma, link); 2098 switch (stat & FWOHCIEV_MASK){ 2099 case FWOHCIEV_ACKCOMPL: 2100#if 0 2101 device_printf(fc->dev, "0x%08x\n", count); 2102#endif 2103 break; 2104 default: 2105 device_printf(fc->dev, 2106 "Isochronous transmit err %02x(%s)\n", 2107 stat, fwohcicode[stat & 0x1f]); 2108 } 2109 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2110 w++; 2111 } 2112 splx(s); 2113 if (w) 2114 wakeup(it); 2115} 2116 2117static void 2118fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2119{ 2120 struct firewire_comm *fc = &sc->fc; 2121 volatile struct fwohcidb_tr *db_tr; 2122 struct fw_bulkxfer *chunk; 2123 struct fw_xferq *ir; 2124 u_int32_t stat; 2125 int s, w=0, ldesc; 2126 2127 ir = fc->ir[dmach]; 2128 ldesc = sc->ir[dmach].ndesc - 1; 2129#if 0 2130 dump_db(sc, dmach); 2131#endif 2132 s = splfw(); 2133 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2134 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2135 db_tr = (struct fwohcidb_tr *)chunk->end; 2136 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2137 >> OHCI_STATUS_SHIFT; 2138 if (stat == 0) 2139 break; 2140 2141 if (chunk->mbuf != NULL) { 2142 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2143 BUS_DMASYNC_POSTREAD); 2144 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2145 } else if (ir->buf != NULL) { 2146 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2147 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2148 } else { 2149 /* XXX */ 2150 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2151 } 2152 2153 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2154 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2155 switch (stat & FWOHCIEV_MASK) { 2156 case FWOHCIEV_ACKCOMPL: 2157 chunk->resp = 0; 2158 break; 2159 default: 2160 chunk->resp = EINVAL; 2161 device_printf(fc->dev, 2162 "Isochronous receive err %02x(%s)\n", 2163 stat, fwohcicode[stat & 0x1f]); 2164 } 2165 w++; 2166 } 2167 splx(s); 2168 if (w) { 2169 if (ir->flag & FWXFERQ_HANDLER) 2170 ir->hand(ir); 2171 else 2172 wakeup(ir); 2173 } 2174} 2175 2176void 2177dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2178{ 2179 u_int32_t off, cntl, stat, cmd, match; 2180 2181 if(ch == 0){ 2182 off = OHCI_ATQOFF; 2183 }else if(ch == 1){ 2184 off = OHCI_ATSOFF; 2185 }else if(ch == 2){ 2186 off = OHCI_ARQOFF; 2187 }else if(ch == 3){ 2188 off = OHCI_ARSOFF; 2189 }else if(ch < IRX_CH){ 2190 off = OHCI_ITCTL(ch - ITX_CH); 2191 }else{ 2192 off = OHCI_IRCTL(ch - IRX_CH); 2193 } 2194 cntl = stat = OREAD(sc, off); 2195 cmd = OREAD(sc, off + 0xc); 2196 match = OREAD(sc, off + 0x10); 2197 2198 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2199 ch, 2200 cntl, 2201 cmd, 2202 match); 2203 stat &= 0xffff ; 2204 if (stat) { 2205 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2206 ch, 2207 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2208 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2209 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2210 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2211 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2212 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2213 fwohcicode[stat & 0x1f], 2214 stat & 0x1f 2215 ); 2216 }else{ 2217 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2218 } 2219} 2220 2221void 2222dump_db(struct fwohci_softc *sc, u_int32_t ch) 2223{ 2224 struct fwohci_dbch *dbch; 2225 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2226 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2227 int idb, jdb; 2228 u_int32_t cmd, off; 2229 if(ch == 0){ 2230 off = OHCI_ATQOFF; 2231 dbch = &sc->atrq; 2232 }else if(ch == 1){ 2233 off = OHCI_ATSOFF; 2234 dbch = &sc->atrs; 2235 }else if(ch == 2){ 2236 off = OHCI_ARQOFF; 2237 dbch = &sc->arrq; 2238 }else if(ch == 3){ 2239 off = OHCI_ARSOFF; 2240 dbch = &sc->arrs; 2241 }else if(ch < IRX_CH){ 2242 off = OHCI_ITCTL(ch - ITX_CH); 2243 dbch = &sc->it[ch - ITX_CH]; 2244 }else { 2245 off = OHCI_IRCTL(ch - IRX_CH); 2246 dbch = &sc->ir[ch - IRX_CH]; 2247 } 2248 cmd = OREAD(sc, off + 0xc); 2249 2250 if( dbch->ndb == 0 ){ 2251 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2252 return; 2253 } 2254 pp = dbch->top; 2255 prev = pp->db; 2256 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2257 if(pp == NULL){ 2258 curr = NULL; 2259 goto outdb; 2260 } 2261 cp = STAILQ_NEXT(pp, link); 2262 if(cp == NULL){ 2263 curr = NULL; 2264 goto outdb; 2265 } 2266 np = STAILQ_NEXT(cp, link); 2267 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2268 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2269 curr = cp->db; 2270 if(np != NULL){ 2271 next = np->db; 2272 }else{ 2273 next = NULL; 2274 } 2275 goto outdb; 2276 } 2277 } 2278 pp = STAILQ_NEXT(pp, link); 2279 prev = pp->db; 2280 } 2281outdb: 2282 if( curr != NULL){ 2283#if 0 2284 printf("Prev DB %d\n", ch); 2285 print_db(pp, prev, ch, dbch->ndesc); 2286#endif 2287 printf("Current DB %d\n", ch); 2288 print_db(cp, curr, ch, dbch->ndesc); 2289#if 0 2290 printf("Next DB %d\n", ch); 2291 print_db(np, next, ch, dbch->ndesc); 2292#endif 2293 }else{ 2294 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2295 } 2296 return; 2297} 2298 2299void 2300print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2301 u_int32_t ch, u_int32_t max) 2302{ 2303 fwohcireg_t stat; 2304 int i, key; 2305 u_int32_t cmd, res; 2306 2307 if(db == NULL){ 2308 printf("No Descriptor is found\n"); 2309 return; 2310 } 2311 2312 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2313 ch, 2314 "Current", 2315 "OP ", 2316 "KEY", 2317 "INT", 2318 "BR ", 2319 "len", 2320 "Addr", 2321 "Depend", 2322 "Stat", 2323 "Cnt"); 2324 for( i = 0 ; i <= max ; i ++){ 2325 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2326 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2327 key = cmd & OHCI_KEY_MASK; 2328 stat = res >> OHCI_STATUS_SHIFT; 2329#if __FreeBSD_version >= 500000 2330 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2331 (uintmax_t)db_tr->bus_addr, 2332#else 2333 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2334 db_tr->bus_addr, 2335#endif 2336 dbcode[(cmd >> 28) & 0xf], 2337 dbkey[(cmd >> 24) & 0x7], 2338 dbcond[(cmd >> 20) & 0x3], 2339 dbcond[(cmd >> 18) & 0x3], 2340 cmd & OHCI_COUNT_MASK, 2341 FWOHCI_DMA_READ(db[i].db.desc.addr), 2342 FWOHCI_DMA_READ(db[i].db.desc.depend), 2343 stat, 2344 res & OHCI_COUNT_MASK); 2345 if(stat & 0xff00){ 2346 printf(" %s%s%s%s%s%s %s(%x)\n", 2347 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2348 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2349 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2350 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2351 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2352 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2353 fwohcicode[stat & 0x1f], 2354 stat & 0x1f 2355 ); 2356 }else{ 2357 printf(" Nostat\n"); 2358 } 2359 if(key == OHCI_KEY_ST2 ){ 2360 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2361 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2362 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2363 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2364 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2365 } 2366 if(key == OHCI_KEY_DEVICE){ 2367 return; 2368 } 2369 if((cmd & OHCI_BRANCH_MASK) 2370 == OHCI_BRANCH_ALWAYS){ 2371 return; 2372 } 2373 if((cmd & OHCI_CMD_MASK) 2374 == OHCI_OUTPUT_LAST){ 2375 return; 2376 } 2377 if((cmd & OHCI_CMD_MASK) 2378 == OHCI_INPUT_LAST){ 2379 return; 2380 } 2381 if(key == OHCI_KEY_ST2 ){ 2382 i++; 2383 } 2384 } 2385 return; 2386} 2387 2388void 2389fwohci_ibr(struct firewire_comm *fc) 2390{ 2391 struct fwohci_softc *sc; 2392 u_int32_t fun; 2393 2394 device_printf(fc->dev, "Initiate bus reset\n"); 2395 sc = (struct fwohci_softc *)fc; 2396 2397 /* 2398 * Set root hold-off bit so that non cyclemaster capable node 2399 * shouldn't became the root node. 2400 */ 2401#if 1 2402 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2403 fun |= FW_PHY_IBR | FW_PHY_RHB; 2404 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2405#else /* Short bus reset */ 2406 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2407 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2408 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2409#endif 2410} 2411 2412void 2413fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2414{ 2415 struct fwohcidb_tr *db_tr, *fdb_tr; 2416 struct fwohci_dbch *dbch; 2417 volatile struct fwohcidb *db; 2418 struct fw_pkt *fp; 2419 volatile struct fwohci_txpkthdr *ohcifp; 2420 unsigned short chtag; 2421 int idb; 2422 2423 dbch = &sc->it[dmach]; 2424 chtag = sc->it[dmach].xferq.flag & 0xff; 2425 2426 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2427 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2428/* 2429device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2430*/ 2431 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2432 db = db_tr->db; 2433 fp = (struct fw_pkt *)db_tr->buf; 2434 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2435 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2436 ohcifp->mode.stream.len = fp->mode.stream.len; 2437 ohcifp->mode.stream.chtag = chtag; 2438 ohcifp->mode.stream.tcode = 0xa; 2439 ohcifp->mode.stream.spd = 0; 2440#if BYTE_ORDER == BIG_ENDIAN 2441 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2442 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2443#endif 2444 2445 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2446 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2447 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2448#if 0 /* if bulkxfer->npackets changes */ 2449 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2450 | OHCI_UPDATE 2451 | OHCI_BRANCH_ALWAYS; 2452 db[0].db.desc.depend = 2453 = db[dbch->ndesc - 1].db.desc.depend 2454 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2455#else 2456 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2457 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2458#endif 2459 bulkxfer->end = (caddr_t)db_tr; 2460 db_tr = STAILQ_NEXT(db_tr, link); 2461 } 2462 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2463 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2464 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2465#if 0 /* if bulkxfer->npackets changes */ 2466 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2467 /* OHCI 1.1 and above */ 2468 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2469#endif 2470/* 2471 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2472 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2473device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2474*/ 2475 return; 2476} 2477 2478static int 2479fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2480 int poffset) 2481{ 2482 volatile struct fwohcidb *db = db_tr->db; 2483 struct fw_xferq *it; 2484 int err = 0; 2485 2486 it = &dbch->xferq; 2487 if(it->buf == 0){ 2488 err = EINVAL; 2489 return err; 2490 } 2491 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2492 db_tr->dbcnt = 3; 2493 2494 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2495 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2496 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2497 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2498 2499 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2500 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2501#if 1 2502 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2503 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2504#endif 2505 return 0; 2506} 2507 2508int 2509fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2510 int poffset, struct fwdma_alloc *dummy_dma) 2511{ 2512 volatile struct fwohcidb *db = db_tr->db; 2513 struct fw_xferq *ir; 2514 int i, ldesc; 2515 bus_addr_t dbuf[2]; 2516 int dsiz[2]; 2517 2518 ir = &dbch->xferq; 2519 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2520 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2521 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2522 if (db_tr->buf == NULL) 2523 return(ENOMEM); 2524 db_tr->dbcnt = 1; 2525 dsiz[0] = ir->psize; 2526 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2527 BUS_DMASYNC_PREREAD); 2528 } else { 2529 db_tr->dbcnt = 0; 2530 if (dummy_dma != NULL) { 2531 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2532 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2533 } 2534 dsiz[db_tr->dbcnt] = ir->psize; 2535 if (ir->buf != NULL) { 2536 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2537 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2538 } 2539 db_tr->dbcnt++; 2540 } 2541 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2542 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2543 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2544 if (ir->flag & FWXFERQ_STREAM) { 2545 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2546 } 2547 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2548 } 2549 ldesc = db_tr->dbcnt - 1; 2550 if (ir->flag & FWXFERQ_STREAM) { 2551 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2552 } 2553 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2554 return 0; 2555} 2556 2557 2558static int 2559fwohci_arcv_swap(struct fw_pkt *fp, int len) 2560{ 2561 struct fw_pkt *fp0; 2562 u_int32_t ld0; 2563 int slen; 2564#if BYTE_ORDER == BIG_ENDIAN 2565 int i; 2566#endif 2567 2568 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2569#if 0 2570 printf("ld0: x%08x\n", ld0); 2571#endif 2572 fp0 = (struct fw_pkt *)&ld0; 2573 switch (fp0->mode.common.tcode) { 2574 case FWTCODE_RREQQ: 2575 case FWTCODE_WRES: 2576 case FWTCODE_WREQQ: 2577 case FWTCODE_RRESQ: 2578 case FWOHCITCODE_PHY: 2579 slen = 12; 2580 break; 2581 case FWTCODE_RREQB: 2582 case FWTCODE_WREQB: 2583 case FWTCODE_LREQ: 2584 case FWTCODE_RRESB: 2585 case FWTCODE_LRES: 2586 slen = 16; 2587 break; 2588 default: 2589 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2590 return(0); 2591 } 2592 if (slen > len) { 2593 if (firewire_debug) 2594 printf("splitted header\n"); 2595 return(-slen); 2596 } 2597#if BYTE_ORDER == BIG_ENDIAN 2598 for(i = 0; i < slen/4; i ++) 2599 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2600#endif 2601 return(slen); 2602} 2603 2604#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2605static int 2606fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2607{ 2608 int r; 2609 2610 switch(fp->mode.common.tcode){ 2611 case FWTCODE_RREQQ: 2612 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2613 break; 2614 case FWTCODE_WRES: 2615 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2616 break; 2617 case FWTCODE_WREQQ: 2618 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2619 break; 2620 case FWTCODE_RREQB: 2621 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2622 break; 2623 case FWTCODE_RRESQ: 2624 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2625 break; 2626 case FWTCODE_WREQB: 2627 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2628 + sizeof(u_int32_t); 2629 break; 2630 case FWTCODE_LREQ: 2631 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2632 + sizeof(u_int32_t); 2633 break; 2634 case FWTCODE_RRESB: 2635 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2636 + sizeof(u_int32_t); 2637 break; 2638 case FWTCODE_LRES: 2639 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2640 + sizeof(u_int32_t); 2641 break; 2642 case FWOHCITCODE_PHY: 2643 r = 16; 2644 break; 2645 default: 2646 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2647 fp->mode.common.tcode); 2648 r = 0; 2649 } 2650 if (r > dbch->xferq.psize) { 2651 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2652 /* panic ? */ 2653 } 2654 return r; 2655} 2656 2657static void 2658fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2659{ 2660 volatile struct fwohcidb *db = &db_tr->db[0]; 2661 2662 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2663 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2664 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2665 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2666 dbch->bottom = db_tr; 2667} 2668 2669static void 2670fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2671{ 2672 struct fwohcidb_tr *db_tr; 2673 struct iovec vec[2]; 2674 struct fw_pkt pktbuf; 2675 int nvec; 2676 struct fw_pkt *fp; 2677 u_int8_t *ld; 2678 u_int32_t stat, off, status; 2679 u_int spd; 2680 int len, plen, hlen, pcnt, offset; 2681 int s; 2682 caddr_t buf; 2683 int resCount; 2684 2685 if(&sc->arrq == dbch){ 2686 off = OHCI_ARQOFF; 2687 }else if(&sc->arrs == dbch){ 2688 off = OHCI_ARSOFF; 2689 }else{ 2690 return; 2691 } 2692 2693 s = splfw(); 2694 db_tr = dbch->top; 2695 pcnt = 0; 2696 /* XXX we cannot handle a packet which lies in more than two buf */ 2697 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2698 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2699 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2700 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2701#if 0 2702 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2703#endif 2704 while (status & OHCI_CNTL_DMA_ACTIVE) { 2705 len = dbch->xferq.psize - resCount; 2706 ld = (u_int8_t *)db_tr->buf; 2707 if (dbch->pdb_tr == NULL) { 2708 len -= dbch->buf_offset; 2709 ld += dbch->buf_offset; 2710 } 2711 if (len > 0) 2712 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2713 BUS_DMASYNC_POSTREAD); 2714 while (len > 0 ) { 2715 if (count >= 0 && count-- == 0) 2716 goto out; 2717 if(dbch->pdb_tr != NULL){ 2718 /* we have a fragment in previous buffer */ 2719 int rlen; 2720 2721 offset = dbch->buf_offset; 2722 if (offset < 0) 2723 offset = - offset; 2724 buf = dbch->pdb_tr->buf + offset; 2725 rlen = dbch->xferq.psize - offset; 2726 if (firewire_debug) 2727 printf("rlen=%d, offset=%d\n", 2728 rlen, dbch->buf_offset); 2729 if (dbch->buf_offset < 0) { 2730 /* splitted in header, pull up */ 2731 char *p; 2732 2733 p = (char *)&pktbuf; 2734 bcopy(buf, p, rlen); 2735 p += rlen; 2736 /* this must be too long but harmless */ 2737 rlen = sizeof(pktbuf) - rlen; 2738 if (rlen < 0) 2739 printf("why rlen < 0\n"); 2740 bcopy(db_tr->buf, p, rlen); 2741 ld += rlen; 2742 len -= rlen; 2743 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2744 if (hlen < 0) { 2745 printf("hlen < 0 shouldn't happen"); 2746 } 2747 offset = sizeof(pktbuf); 2748 vec[0].iov_base = (char *)&pktbuf; 2749 vec[0].iov_len = offset; 2750 } else { 2751 /* splitted in payload */ 2752 offset = rlen; 2753 vec[0].iov_base = buf; 2754 vec[0].iov_len = rlen; 2755 } 2756 fp=(struct fw_pkt *)vec[0].iov_base; 2757 nvec = 1; 2758 } else { 2759 /* no fragment in previous buffer */ 2760 fp=(struct fw_pkt *)ld; 2761 hlen = fwohci_arcv_swap(fp, len); 2762 if (hlen == 0) 2763 /* XXX need reset */ 2764 goto out; 2765 if (hlen < 0) { 2766 dbch->pdb_tr = db_tr; 2767 dbch->buf_offset = - dbch->buf_offset; 2768 /* sanity check */ 2769 if (resCount != 0) 2770 printf("resCount != 0 !?\n"); 2771 goto out; 2772 } 2773 offset = 0; 2774 nvec = 0; 2775 } 2776 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2777 if (plen < 0) { 2778 /* minimum header size + trailer 2779 = sizeof(fw_pkt) so this shouldn't happens */ 2780 printf("plen is negative! offset=%d\n", offset); 2781 goto out; 2782 } 2783 if (plen > 0) { 2784 len -= plen; 2785 if (len < 0) { 2786 dbch->pdb_tr = db_tr; 2787 if (firewire_debug) 2788 printf("splitted payload\n"); 2789 /* sanity check */ 2790 if (resCount != 0) 2791 printf("resCount != 0 !?\n"); 2792 goto out; 2793 } 2794 vec[nvec].iov_base = ld; 2795 vec[nvec].iov_len = plen; 2796 nvec ++; 2797 ld += plen; 2798 } 2799 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2800 if (nvec == 0) 2801 printf("nvec == 0\n"); 2802 2803/* DMA result-code will be written at the tail of packet */ 2804#if BYTE_ORDER == BIG_ENDIAN 2805 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2806#else 2807 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2808#endif 2809#if 0 2810 printf("plen: %d, stat %x\n", plen ,stat); 2811#endif 2812 spd = (stat >> 5) & 0x3; 2813 stat &= 0x1f; 2814 switch(stat){ 2815 case FWOHCIEV_ACKPEND: 2816#if 0 2817 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2818#endif 2819 /* fall through */ 2820 case FWOHCIEV_ACKCOMPL: 2821 if ((vec[nvec-1].iov_len -= 2822 sizeof(struct fwohci_trailer)) == 0) 2823 nvec--; 2824 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2825 break; 2826 case FWOHCIEV_BUSRST: 2827 if (sc->fc.status != FWBUSRESET) 2828 printf("got BUSRST packet!?\n"); 2829 break; 2830 default: 2831 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2832#if 0 /* XXX */ 2833 goto out; 2834#endif 2835 break; 2836 } 2837 pcnt ++; 2838 if (dbch->pdb_tr != NULL) { 2839 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2840 dbch->pdb_tr = NULL; 2841 } 2842 2843 } 2844out: 2845 if (resCount == 0) { 2846 /* done on this buffer */ 2847 if (dbch->pdb_tr == NULL) { 2848 fwohci_arcv_free_buf(dbch, db_tr); 2849 dbch->buf_offset = 0; 2850 } else 2851 if (dbch->pdb_tr != db_tr) 2852 printf("pdb_tr != db_tr\n"); 2853 db_tr = STAILQ_NEXT(db_tr, link); 2854 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2855 >> OHCI_STATUS_SHIFT; 2856 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2857 & OHCI_COUNT_MASK; 2858 /* XXX check buffer overrun */ 2859 dbch->top = db_tr; 2860 } else { 2861 dbch->buf_offset = dbch->xferq.psize - resCount; 2862 break; 2863 } 2864 /* XXX make sure DMA is not dead */ 2865 } 2866#if 0 2867 if (pcnt < 1) 2868 printf("fwohci_arcv: no packets\n"); 2869#endif 2870 splx(s); 2871} 2872