fwohci.c revision 113584
1103285Sikob/* 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 113584 2003-04-17 03:38:03Z simokawa $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46109890Ssimokawa#include <sys/proc.h> 47103285Sikob#include <sys/systm.h> 48103285Sikob#include <sys/types.h> 49103285Sikob#include <sys/mbuf.h> 50103285Sikob#include <sys/mman.h> 51103285Sikob#include <sys/socket.h> 52103285Sikob#include <sys/socketvar.h> 53103285Sikob#include <sys/signalvar.h> 54103285Sikob#include <sys/malloc.h> 55103285Sikob#include <sys/sockio.h> 56103285Sikob#include <sys/bus.h> 57103285Sikob#include <sys/kernel.h> 58103285Sikob#include <sys/conf.h> 59113584Ssimokawa#include <sys/endian.h> 60103285Sikob 61103285Sikob#include <machine/bus.h> 62103285Sikob#include <machine/resource.h> 63103285Sikob#include <sys/rman.h> 64103285Sikob 65103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 66103285Sikob#include <machine/clock.h> 67103285Sikob#include <pci/pcivar.h> 68103285Sikob#include <pci/pcireg.h> 69103285Sikob 70103285Sikob#include <dev/firewire/firewire.h> 71103285Sikob#include <dev/firewire/firewirereg.h> 72113584Ssimokawa#include <dev/firewire/fwdma.h> 73103285Sikob#include <dev/firewire/fwohcireg.h> 74103285Sikob#include <dev/firewire/fwohcivar.h> 75103285Sikob#include <dev/firewire/firewire_phy.h> 76103285Sikob 77109179Ssimokawa#include <dev/firewire/iec68113.h> 78109179Ssimokawa 79103285Sikob#undef OHCI_DEBUG 80106802Ssimokawa 81103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82103285Sikob "STOR","LOAD","NOP ","STOP",}; 83113584Ssimokawa 84103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85103285Sikob "UNDEF","REG","SYS","DEV"}; 86113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 87103285Sikobchar fwohcicode[32][0x20]={ 88103285Sikob "No stat","Undef","long","miss Ack err", 89103285Sikob "underrun","overrun","desc err", "data read err", 90103285Sikob "data write err","bus reset","timeout","tcode err", 91103285Sikob "Undef","Undef","unknown event","flushed", 92103285Sikob "Undef","ack complete","ack pend","Undef", 93103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 94103285Sikob "Undef","Undef","Undef","ack tardy", 95103285Sikob "Undef","ack data_err","ack type_err",""}; 96113584Ssimokawa 97103285Sikob#define MAX_SPEED 2 98103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 99103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 100103285Sikob 101103285Sikobstatic struct tcode_info tinfo[] = { 102103285Sikob/* hdr_len block flag*/ 103103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 104103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 105103285Sikob/* 2 WRES */ {12, FWTI_RES}, 106103285Sikob/* 3 XXX */ { 0, 0}, 107103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 108103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 109103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 110103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 111103285Sikob/* 8 CYCS */ { 0, 0}, 112103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 113103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 114103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 115103285Sikob/* c XXX */ { 0, 0}, 116103285Sikob/* d XXX */ { 0, 0}, 117103285Sikob/* e PHY */ {12, FWTI_REQ}, 118103285Sikob/* f XXX */ { 0, 0} 119103285Sikob}; 120103285Sikob 121103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 122103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 123103285Sikob 124103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 125103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 126103285Sikob 127103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 128113584Ssimokawastatic void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 129103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 130106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 134103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 136103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 137103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 138103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 139103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 140103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 141113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 142103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 143113584Ssimokawa#endif 144103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 145103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 146103285Sikobstatic void fwohci_timeout __P((void *)); 147103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 148103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 149113584Ssimokawa 150113584Ssimokawastatic int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 151113584Ssimokawastatic int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 152103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 153113584Ssimokawastatic void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 154103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 155103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 156103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 157103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 159113584Ssimokawa#if FWOHCI_TASKQUEUE 160113584Ssimokawastatic void fwohci_complete(void *, int); 161113584Ssimokawa#endif 162103285Sikob 163103285Sikob/* 164103285Sikob * memory allocated for DMA programs 165103285Sikob */ 166103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 167103285Sikob 168103285Sikob/* #define NDB 1024 */ 169103285Sikob#define NDB FWMAXQUEUE 170103285Sikob#define NDVDB (DVBUF * NDB) 171103285Sikob 172103285Sikob#define OHCI_VERSION 0x00 173112523Ssimokawa#define OHCI_ATRETRY 0x08 174103285Sikob#define OHCI_CROMHDR 0x18 175103285Sikob#define OHCI_BUS_OPT 0x20 176103285Sikob#define OHCI_BUSIRMC (1 << 31) 177103285Sikob#define OHCI_BUSCMC (1 << 30) 178103285Sikob#define OHCI_BUSISC (1 << 29) 179103285Sikob#define OHCI_BUSBMC (1 << 28) 180103285Sikob#define OHCI_BUSPMC (1 << 27) 181103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 182103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 183103285Sikob 184103285Sikob#define OHCI_EUID_HI 0x24 185103285Sikob#define OHCI_EUID_LO 0x28 186103285Sikob 187103285Sikob#define OHCI_CROMPTR 0x34 188103285Sikob#define OHCI_HCCCTL 0x50 189103285Sikob#define OHCI_HCCCTLCLR 0x54 190103285Sikob#define OHCI_AREQHI 0x100 191103285Sikob#define OHCI_AREQHICLR 0x104 192103285Sikob#define OHCI_AREQLO 0x108 193103285Sikob#define OHCI_AREQLOCLR 0x10c 194103285Sikob#define OHCI_PREQHI 0x110 195103285Sikob#define OHCI_PREQHICLR 0x114 196103285Sikob#define OHCI_PREQLO 0x118 197103285Sikob#define OHCI_PREQLOCLR 0x11c 198103285Sikob#define OHCI_PREQUPPER 0x120 199103285Sikob 200103285Sikob#define OHCI_SID_BUF 0x64 201103285Sikob#define OHCI_SID_CNT 0x68 202113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 203103285Sikob#define OHCI_SID_CNT_MASK 0xffc 204103285Sikob 205103285Sikob#define OHCI_IT_STAT 0x90 206103285Sikob#define OHCI_IT_STATCLR 0x94 207103285Sikob#define OHCI_IT_MASK 0x98 208103285Sikob#define OHCI_IT_MASKCLR 0x9c 209103285Sikob 210103285Sikob#define OHCI_IR_STAT 0xa0 211103285Sikob#define OHCI_IR_STATCLR 0xa4 212103285Sikob#define OHCI_IR_MASK 0xa8 213103285Sikob#define OHCI_IR_MASKCLR 0xac 214103285Sikob 215103285Sikob#define OHCI_LNKCTL 0xe0 216103285Sikob#define OHCI_LNKCTLCLR 0xe4 217103285Sikob 218103285Sikob#define OHCI_PHYACCESS 0xec 219103285Sikob#define OHCI_CYCLETIMER 0xf0 220103285Sikob 221103285Sikob#define OHCI_DMACTL(off) (off) 222103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 223103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 224103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 225103285Sikob 226103285Sikob#define OHCI_ATQOFF 0x180 227103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 228103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 229103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 230103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 231103285Sikob 232103285Sikob#define OHCI_ATSOFF 0x1a0 233103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 234103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 235103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 236103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 237103285Sikob 238103285Sikob#define OHCI_ARQOFF 0x1c0 239103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 240103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 241103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 242103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 243103285Sikob 244103285Sikob#define OHCI_ARSOFF 0x1e0 245103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 246103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 247103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 248103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 249103285Sikob 250103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 251103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 252103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 253103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 254103285Sikob 255103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 256103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 257103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 258103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 259103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 260103285Sikob 261103285Sikobd_ioctl_t fwohci_ioctl; 262103285Sikob 263103285Sikob/* 264103285Sikob * Communication with PHY device 265103285Sikob */ 266106790Ssimokawastatic u_int32_t 267106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 268103285Sikob{ 269103285Sikob u_int32_t fun; 270103285Sikob 271103285Sikob addr &= 0xf; 272103285Sikob data &= 0xff; 273103285Sikob 274103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 275103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 276103285Sikob DELAY(100); 277103285Sikob 278103285Sikob return(fwphy_rddata( sc, addr)); 279103285Sikob} 280103285Sikob 281103285Sikobstatic u_int32_t 282103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 283103285Sikob{ 284103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 285103285Sikob int i; 286103285Sikob u_int32_t bm; 287103285Sikob 288103285Sikob#define OHCI_CSR_DATA 0x0c 289103285Sikob#define OHCI_CSR_COMP 0x10 290103285Sikob#define OHCI_CSR_CONT 0x14 291103285Sikob#define OHCI_BUS_MANAGER_ID 0 292103285Sikob 293103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 294103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 295103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 296103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 297109280Ssimokawa DELAY(10); 298103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 299107653Ssimokawa if((bm & 0x3f) == 0x3f) 300103285Sikob bm = node; 301107653Ssimokawa if (bootverbose) 302107653Ssimokawa device_printf(sc->fc.dev, 303107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 304103285Sikob 305103285Sikob return(bm); 306103285Sikob} 307103285Sikob 308106790Ssimokawastatic u_int32_t 309106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 310103285Sikob{ 311108500Ssimokawa u_int32_t fun, stat; 312108500Ssimokawa u_int i, retry = 0; 313103285Sikob 314103285Sikob addr &= 0xf; 315108500Ssimokawa#define MAX_RETRY 100 316108500Ssimokawaagain: 317108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 318103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 319103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 320108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 321103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 322103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 323103285Sikob break; 324109280Ssimokawa DELAY(100); 325103285Sikob } 326108500Ssimokawa if(i >= MAX_RETRY) { 327109280Ssimokawa if (bootverbose) 328109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 329108527Ssimokawa if (++retry < MAX_RETRY) { 330109280Ssimokawa DELAY(100); 331108527Ssimokawa goto again; 332108527Ssimokawa } 333108500Ssimokawa } 334108500Ssimokawa /* Make sure that SCLK is started */ 335108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 336108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 337108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 338109280Ssimokawa if (bootverbose) 339109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 340108500Ssimokawa if (++retry < MAX_RETRY) { 341109280Ssimokawa DELAY(100); 342108500Ssimokawa goto again; 343108500Ssimokawa } 344108500Ssimokawa } 345108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 346108500Ssimokawa device_printf(sc->fc.dev, 347108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 348108500Ssimokawa#undef MAX_RETRY 349103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 350103285Sikob} 351103285Sikob/* Device specific ioctl. */ 352103285Sikobint 353103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 354103285Sikob{ 355103285Sikob struct firewire_softc *sc; 356103285Sikob struct fwohci_softc *fc; 357103285Sikob int unit = DEV2UNIT(dev); 358103285Sikob int err = 0; 359103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 360103285Sikob u_int32_t *dmach = (u_int32_t *) data; 361103285Sikob 362103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 363103285Sikob if(sc == NULL){ 364103285Sikob return(EINVAL); 365103285Sikob } 366103285Sikob fc = (struct fwohci_softc *)sc->fc; 367103285Sikob 368103285Sikob if (!data) 369103285Sikob return(EINVAL); 370103285Sikob 371103285Sikob switch (cmd) { 372103285Sikob case FWOHCI_WRREG: 373103285Sikob#define OHCI_MAX_REG 0x800 374103285Sikob if(reg->addr <= OHCI_MAX_REG){ 375103285Sikob OWRITE(fc, reg->addr, reg->data); 376103285Sikob reg->data = OREAD(fc, reg->addr); 377103285Sikob }else{ 378103285Sikob err = EINVAL; 379103285Sikob } 380103285Sikob break; 381103285Sikob case FWOHCI_RDREG: 382103285Sikob if(reg->addr <= OHCI_MAX_REG){ 383103285Sikob reg->data = OREAD(fc, reg->addr); 384103285Sikob }else{ 385103285Sikob err = EINVAL; 386103285Sikob } 387103285Sikob break; 388103285Sikob/* Read DMA descriptors for debug */ 389103285Sikob case DUMPDMA: 390103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 391103285Sikob dump_dma(fc, *dmach); 392103285Sikob dump_db(fc, *dmach); 393103285Sikob }else{ 394103285Sikob err = EINVAL; 395103285Sikob } 396103285Sikob break; 397103285Sikob default: 398103285Sikob break; 399103285Sikob } 400103285Sikob return err; 401103285Sikob} 402106790Ssimokawa 403108530Ssimokawastatic int 404108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 405103285Sikob{ 406108530Ssimokawa u_int32_t reg, reg2; 407108530Ssimokawa int e1394a = 1; 408108530Ssimokawa/* 409108530Ssimokawa * probe PHY parameters 410108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 411108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 412108530Ssimokawa * number of port supported by core-logic. 413108530Ssimokawa * It is not actually available port on your PC . 414108530Ssimokawa */ 415108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 416108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417108530Ssimokawa 418108530Ssimokawa if((reg >> 5) != 7 ){ 419108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 420108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 421108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 422108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 423108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 424108530Ssimokawa sc->fc.speed, MAX_SPEED); 425108530Ssimokawa sc->fc.speed = MAX_SPEED; 426108530Ssimokawa } 427108530Ssimokawa device_printf(dev, 428108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 429108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 430108530Ssimokawa }else{ 431108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432108530Ssimokawa sc->fc.mode |= FWPHYASYST; 433108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 434108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 436108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 437108530Ssimokawa sc->fc.speed, MAX_SPEED); 438108530Ssimokawa sc->fc.speed = MAX_SPEED; 439108530Ssimokawa } 440108530Ssimokawa device_printf(dev, 441108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 442108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 443108530Ssimokawa 444108530Ssimokawa /* check programPhyEnable */ 445108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 446108530Ssimokawa#if 0 447108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448108530Ssimokawa#else /* XXX force to enable 1394a */ 449108530Ssimokawa if (e1394a) { 450108530Ssimokawa#endif 451108530Ssimokawa if (bootverbose) 452108530Ssimokawa device_printf(dev, 453108530Ssimokawa "Enable 1394a Enhancements\n"); 454108530Ssimokawa /* enable EAA EMC */ 455108530Ssimokawa reg2 |= 0x03; 456108530Ssimokawa /* set aPhyEnhanceEnable */ 457108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459108530Ssimokawa } else { 460108530Ssimokawa /* for safe */ 461108530Ssimokawa reg2 &= ~0x83; 462108530Ssimokawa } 463108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 464108530Ssimokawa } 465108530Ssimokawa 466108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467108530Ssimokawa if((reg >> 5) == 7 ){ 468108530Ssimokawa reg = fwphy_rddata(sc, 4); 469108530Ssimokawa reg |= 1 << 6; 470108530Ssimokawa fwphy_wrdata(sc, 4, reg); 471108530Ssimokawa reg = fwphy_rddata(sc, 4); 472108530Ssimokawa } 473108530Ssimokawa return 0; 474108530Ssimokawa} 475108530Ssimokawa 476108530Ssimokawa 477108530Ssimokawavoid 478108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 479108530Ssimokawa{ 480108701Ssimokawa int i, max_rec, speed; 481103285Sikob u_int32_t reg, reg2; 482103285Sikob struct fwohcidb_tr *db_tr; 483103285Sikob 484108701Ssimokawa /* Disable interrupt */ 485108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486108530Ssimokawa 487108701Ssimokawa /* Now stopping all DMA channel */ 488108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa 493108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa } 498108530Ssimokawa 499108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 500108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501108530Ssimokawa if (bootverbose) 502108530Ssimokawa device_printf(dev, "resetting OHCI..."); 503108530Ssimokawa i = 0; 504108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505108530Ssimokawa if (i++ > 100) break; 506108530Ssimokawa DELAY(1000); 507108530Ssimokawa } 508108530Ssimokawa if (bootverbose) 509108530Ssimokawa printf("done (loop=%d)\n", i); 510108530Ssimokawa 511108701Ssimokawa /* Probe phy */ 512108701Ssimokawa fwohci_probe_phy(sc, dev); 513108701Ssimokawa 514108701Ssimokawa /* Probe link */ 515108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 516108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 517108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 518108701Ssimokawa speed = (reg & 0x00000007); 519108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 520108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 521108701Ssimokawa /* XXX fix max_rec */ 522108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 523108701Ssimokawa if (max_rec != sc->fc.maxrec) { 524108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 526108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527108701Ssimokawa } 528108530Ssimokawa if (bootverbose) 529108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 531108530Ssimokawa 532108701Ssimokawa /* Initialize registers */ 533108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 535108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 538108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539108701Ssimokawa fw_busreset(&sc->fc); 540108530Ssimokawa 541108701Ssimokawa /* Enable link */ 542108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543108642Ssimokawa 544108701Ssimokawa /* Force to start async RX DMA */ 545108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 549108530Ssimokawa 550108701Ssimokawa /* Initialize async TX */ 551108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa /* AT Retries */ 554108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 555108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559108530Ssimokawa db_tr->xfer = NULL; 560108530Ssimokawa } 561108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563108530Ssimokawa db_tr->xfer = NULL; 564108530Ssimokawa } 565108530Ssimokawa 566108701Ssimokawa 567108701Ssimokawa /* Enable interrupt */ 568108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 569108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 570108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 574108530Ssimokawa 575108530Ssimokawa} 576108530Ssimokawa 577108530Ssimokawaint 578108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 579108530Ssimokawa{ 580108530Ssimokawa int i; 581108530Ssimokawa u_int32_t reg; 582109814Ssimokawa u_int8_t ui[8]; 583108530Ssimokawa 584113584Ssimokawa#if FWOHCI_TASKQUEUE 585113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 586113584Ssimokawa#endif 587113584Ssimokawa 588103285Sikob reg = OREAD(sc, OHCI_VERSION); 589103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 590103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 591103285Sikob 592110045Ssimokawa/* Available Isochrounous DMA channel probe */ 593110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 594110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 595110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 596110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 597110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 598110045Ssimokawa for (i = 0; i < 0x20; i++) 599110045Ssimokawa if ((reg & (1 << i)) == 0) 600110045Ssimokawa break; 601103285Sikob sc->fc.nisodma = i; 602103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 603103285Sikob 604103285Sikob sc->fc.arq = &sc->arrq.xferq; 605103285Sikob sc->fc.ars = &sc->arrs.xferq; 606103285Sikob sc->fc.atq = &sc->atrq.xferq; 607103285Sikob sc->fc.ats = &sc->atrs.xferq; 608103285Sikob 609113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 610113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 611113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 612113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 613113584Ssimokawa 614103285Sikob sc->arrq.xferq.start = NULL; 615103285Sikob sc->arrs.xferq.start = NULL; 616103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 617103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 618103285Sikob 619113584Ssimokawa sc->arrq.xferq.buf = NULL; 620113584Ssimokawa sc->arrs.xferq.buf = NULL; 621113584Ssimokawa sc->atrq.xferq.buf = NULL; 622113584Ssimokawa sc->atrs.xferq.buf = NULL; 623103285Sikob 624103285Sikob sc->arrq.ndesc = 1; 625103285Sikob sc->arrs.ndesc = 1; 626110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 627110593Ssimokawa sc->atrs.ndesc = 2; 628103285Sikob 629103285Sikob sc->arrq.ndb = NDB; 630103285Sikob sc->arrs.ndb = NDB / 2; 631103285Sikob sc->atrq.ndb = NDB; 632103285Sikob sc->atrs.ndb = NDB / 2; 633103285Sikob 634103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 635103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 636103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 637103285Sikob sc->it[i].ndb = 0; 638103285Sikob sc->ir[i].ndb = 0; 639103285Sikob } 640103285Sikob 641103285Sikob sc->fc.tcode = tinfo; 642113584Ssimokawa sc->fc.dev = dev; 643103285Sikob 644113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 645113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 646113584Ssimokawa if(sc->fc.config_rom == NULL){ 647113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 648103285Sikob return ENOMEM; 649103285Sikob } 650103285Sikob 651113584Ssimokawa#if 1 652103285Sikob sc->fc.config_rom[1] = 0x31333934; 653103285Sikob sc->fc.config_rom[2] = 0xf000a002; 654103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 655103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 656103285Sikob sc->fc.config_rom[5] = 0; 657103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 658103285Sikob 659103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 660113584Ssimokawa#endif 661103285Sikob 662103285Sikob 663103285Sikob/* SID recieve buffer must allign 2^11 */ 664103285Sikob#define OHCI_SIDSIZE (1 << 11) 665113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 666113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 667113584Ssimokawa if (sc->sid_buf == NULL) { 668113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 669108527Ssimokawa return ENOMEM; 670108527Ssimokawa } 671113584Ssimokawa 672113584Ssimokawa fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 673113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 674113584Ssimokawa 675113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 676113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 677109736Ssimokawa return ENOMEM; 678109736Ssimokawa } 679113584Ssimokawa 680113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 681108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 682108527Ssimokawa return ENOMEM; 683108527Ssimokawa 684113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 685108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 686108527Ssimokawa return ENOMEM; 687103285Sikob 688113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 689108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 690108527Ssimokawa return ENOMEM; 691108527Ssimokawa 692113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 693108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 694108527Ssimokawa return ENOMEM; 695103285Sikob 696109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 697109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 698109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 699109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 700103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 701109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 702109814Ssimokawa 703103285Sikob sc->fc.ioctl = fwohci_ioctl; 704103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 705103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 706103285Sikob sc->fc.ibr = fwohci_ibr; 707103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 708103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 709103285Sikob 710103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 711103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 712113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 713103285Sikob sc->fc.irx_post = fwohci_irx_post; 714113584Ssimokawa#else 715113584Ssimokawa sc->fc.irx_post = NULL; 716113584Ssimokawa#endif 717103285Sikob sc->fc.itx_post = NULL; 718103285Sikob sc->fc.timeout = fwohci_timeout; 719103285Sikob sc->fc.poll = fwohci_poll; 720103285Sikob sc->fc.set_intr = fwohci_set_intr; 721106790Ssimokawa 722113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 723113584Ssimokawa 724108530Ssimokawa fw_init(&sc->fc); 725108530Ssimokawa fwohci_reset(sc, dev); 726103285Sikob 727108530Ssimokawa return 0; 728103285Sikob} 729106790Ssimokawa 730106790Ssimokawavoid 731106790Ssimokawafwohci_timeout(void *arg) 732103285Sikob{ 733103285Sikob struct fwohci_softc *sc; 734103285Sikob 735103285Sikob sc = (struct fwohci_softc *)arg; 736103285Sikob} 737106790Ssimokawa 738106790Ssimokawau_int32_t 739106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 740103285Sikob{ 741103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 742103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 743103285Sikob} 744103285Sikob 745108527Ssimokawaint 746108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 747108527Ssimokawa{ 748108527Ssimokawa int i; 749108527Ssimokawa 750113584Ssimokawa if (sc->sid_buf != NULL) 751113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 752113584Ssimokawa if (sc->fc.config_rom != NULL) 753113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 754108527Ssimokawa 755108527Ssimokawa fwohci_db_free(&sc->arrq); 756108527Ssimokawa fwohci_db_free(&sc->arrs); 757108527Ssimokawa 758108527Ssimokawa fwohci_db_free(&sc->atrq); 759108527Ssimokawa fwohci_db_free(&sc->atrs); 760108527Ssimokawa 761108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 762108527Ssimokawa fwohci_db_free(&sc->it[i]); 763108527Ssimokawa fwohci_db_free(&sc->ir[i]); 764108527Ssimokawa } 765108527Ssimokawa 766108527Ssimokawa return 0; 767108527Ssimokawa} 768108527Ssimokawa 769108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 770108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 771108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 772108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 773108655Ssimokawa} while (0) 774108655Ssimokawa 775106790Ssimokawastatic void 776113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 777113584Ssimokawa{ 778113584Ssimokawa struct fwohcidb_tr *db_tr; 779113584Ssimokawa volatile struct fwohcidb *db; 780113584Ssimokawa bus_dma_segment_t *s; 781113584Ssimokawa int i; 782113584Ssimokawa 783113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 784113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 785113584Ssimokawa if (error) { 786113584Ssimokawa if (firewire_debug || error != EFBIG) 787113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 788113584Ssimokawa return; 789113584Ssimokawa } 790113584Ssimokawa for (i = 0; i < nseg; i++) { 791113584Ssimokawa s = &segs[i]; 792113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 793113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 794113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 795113584Ssimokawa db++; 796113584Ssimokawa db_tr->dbcnt++; 797113584Ssimokawa } 798113584Ssimokawa} 799113584Ssimokawa 800113584Ssimokawastatic void 801113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 802113584Ssimokawa bus_size_t size, int error) 803113584Ssimokawa{ 804113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 805113584Ssimokawa} 806113584Ssimokawa 807113584Ssimokawastatic void 808106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 809103285Sikob{ 810103285Sikob int i, s; 811113584Ssimokawa int tcode, hdr_len, pl_off, pl_len; 812103285Sikob int fsegment = -1; 813103285Sikob u_int32_t off; 814103285Sikob struct fw_xfer *xfer; 815103285Sikob struct fw_pkt *fp; 816103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 817103285Sikob struct fwohcidb_tr *db_tr; 818103285Sikob volatile struct fwohcidb *db; 819103285Sikob struct tcode_info *info; 820108655Ssimokawa static int maxdesc=0; 821103285Sikob 822103285Sikob if(&sc->atrq == dbch){ 823103285Sikob off = OHCI_ATQOFF; 824103285Sikob }else if(&sc->atrs == dbch){ 825103285Sikob off = OHCI_ATSOFF; 826103285Sikob }else{ 827103285Sikob return; 828103285Sikob } 829103285Sikob 830103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 831103285Sikob return; 832103285Sikob 833103285Sikob s = splfw(); 834103285Sikob db_tr = dbch->top; 835103285Sikobtxloop: 836103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 837103285Sikob if(xfer == NULL){ 838103285Sikob goto kick; 839103285Sikob } 840103285Sikob if(dbch->xferq.queued == 0 ){ 841103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 842103285Sikob } 843103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 844103285Sikob db_tr->xfer = xfer; 845103285Sikob xfer->state = FWXF_START; 846103285Sikob 847113584Ssimokawa fp = (struct fw_pkt *)xfer->send.buf; 848103285Sikob tcode = fp->mode.common.tcode; 849103285Sikob 850103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 851103285Sikob info = &tinfo[tcode]; 852113584Ssimokawa hdr_len = pl_off = info->hdr_len; 853113584Ssimokawa for( i = 0 ; i < pl_off ; i+= 4){ 854113584Ssimokawa ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 855103285Sikob } 856103285Sikob ohcifp->mode.common.spd = xfer->spd; 857103285Sikob if (tcode == FWTCODE_STREAM ){ 858103285Sikob hdr_len = 8; 859113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 860103285Sikob } else if (tcode == FWTCODE_PHY) { 861103285Sikob hdr_len = 12; 862113584Ssimokawa ohcifp->mode.ld[1] = fp->mode.ld[1]; 863113584Ssimokawa ohcifp->mode.ld[2] = fp->mode.ld[2]; 864103285Sikob ohcifp->mode.common.spd = 0; 865103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 866103285Sikob } else { 867113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 868103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 869103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 870103285Sikob } 871103285Sikob db = &db_tr->db[0]; 872113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 873113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 874113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 875103285Sikob/* Specify bound timer of asy. responce */ 876103285Sikob if(&sc->atrs == dbch){ 877113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 878113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 879103285Sikob } 880113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 881113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 882113584Ssimokawa hdr_len = 12; 883113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 884113584Ssimokawa FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 885113584Ssimokawa#endif 886103285Sikob 887111942Ssimokawaagain: 888103285Sikob db_tr->dbcnt = 2; 889103285Sikob db = &db_tr->db[db_tr->dbcnt]; 890113584Ssimokawa pl_len = xfer->send.len - pl_off; 891113584Ssimokawa if (pl_len > 0) { 892113584Ssimokawa int err; 893113584Ssimokawa /* handle payload */ 894103285Sikob if (xfer->mbuf == NULL) { 895113584Ssimokawa caddr_t pl_addr; 896103285Sikob 897113584Ssimokawa pl_addr = xfer->send.buf + pl_off; 898113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 899113584Ssimokawa pl_addr, pl_len, 900113584Ssimokawa fwohci_execute_db, db_tr, 901113584Ssimokawa /*flags*/0); 902103285Sikob } else { 903111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 904113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 905113584Ssimokawa xfer->mbuf, 906113584Ssimokawa fwohci_execute_db2, db_tr, 907113584Ssimokawa /* flags */0); 908113584Ssimokawa if (err == EFBIG) { 909113584Ssimokawa struct mbuf *m0; 910113584Ssimokawa 911113584Ssimokawa if (firewire_debug) 912113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 913113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 914113584Ssimokawa if (m0 != NULL) { 915111942Ssimokawa m_copydata(xfer->mbuf, 0, 916111942Ssimokawa xfer->mbuf->m_pkthdr.len, 917113584Ssimokawa mtod(m0, caddr_t)); 918113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 919111942Ssimokawa xfer->mbuf->m_pkthdr.len; 920111942Ssimokawa m_freem(xfer->mbuf); 921113584Ssimokawa xfer->mbuf = m0; 922111942Ssimokawa goto again; 923111942Ssimokawa } 924111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 925111942Ssimokawa } 926103285Sikob } 927113584Ssimokawa if (err) 928113584Ssimokawa printf("dmamap_load: err=%d\n", err); 929113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 930113584Ssimokawa BUS_DMASYNC_PREWRITE); 931113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 932113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 933113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 934113584Ssimokawa OHCI_OUTPUT_MORE); 935113584Ssimokawa#endif 936103285Sikob } 937108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 938108655Ssimokawa maxdesc = db_tr->dbcnt; 939108655Ssimokawa if (bootverbose) 940108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 941108655Ssimokawa } 942103285Sikob /* last db */ 943103285Sikob LAST_DB(db_tr, db); 944113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 945113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 946113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 947113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 948103285Sikob 949103285Sikob if(fsegment == -1 ) 950103285Sikob fsegment = db_tr->dbcnt; 951103285Sikob if (dbch->pdb_tr != NULL) { 952103285Sikob LAST_DB(dbch->pdb_tr, db); 953113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 954103285Sikob } 955103285Sikob dbch->pdb_tr = db_tr; 956103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 957103285Sikob if(db_tr != dbch->bottom){ 958103285Sikob goto txloop; 959103285Sikob } else { 960107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 961103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 962103285Sikob } 963103285Sikobkick: 964103285Sikob /* kick asy q */ 965113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 966113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 967103285Sikob 968103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 969103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 970103285Sikob } else { 971107653Ssimokawa if (bootverbose) 972107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 973103285Sikob OREAD(sc, OHCI_DMACTL(off))); 974113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 975103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 976103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 977103285Sikob } 978106790Ssimokawa 979103285Sikob dbch->top = db_tr; 980103285Sikob splx(s); 981103285Sikob return; 982103285Sikob} 983106790Ssimokawa 984106790Ssimokawastatic void 985106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 986103285Sikob{ 987103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 988103285Sikob fwohci_start( sc, &(sc->atrq)); 989103285Sikob return; 990103285Sikob} 991106790Ssimokawa 992106790Ssimokawastatic void 993106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 994103285Sikob{ 995103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 996103285Sikob fwohci_start( sc, &(sc->atrs)); 997103285Sikob return; 998103285Sikob} 999106790Ssimokawa 1000106790Ssimokawavoid 1001106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1002103285Sikob{ 1003113584Ssimokawa int s, ch, err = 0; 1004103285Sikob struct fwohcidb_tr *tr; 1005103285Sikob volatile struct fwohcidb *db; 1006103285Sikob struct fw_xfer *xfer; 1007103285Sikob u_int32_t off; 1008113584Ssimokawa u_int stat, status; 1009103285Sikob int packets; 1010103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1011113584Ssimokawa 1012103285Sikob if(&sc->atrq == dbch){ 1013103285Sikob off = OHCI_ATQOFF; 1014113584Ssimokawa ch = ATRQ_CH; 1015103285Sikob }else if(&sc->atrs == dbch){ 1016103285Sikob off = OHCI_ATSOFF; 1017113584Ssimokawa ch = ATRS_CH; 1018103285Sikob }else{ 1019103285Sikob return; 1020103285Sikob } 1021103285Sikob s = splfw(); 1022103285Sikob tr = dbch->bottom; 1023103285Sikob packets = 0; 1024113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1025113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1026103285Sikob while(dbch->xferq.queued > 0){ 1027103285Sikob LAST_DB(tr, db); 1028113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1029113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1030103285Sikob if (fc->status != FWBUSRESET) 1031103285Sikob /* maybe out of order?? */ 1032103285Sikob goto out; 1033103285Sikob } 1034113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1035113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1036113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1037113584Ssimokawa#if 0 1038113584Ssimokawa dump_db(sc, ch); 1039103285Sikob#endif 1040113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1041113584Ssimokawa /* Stop DMA */ 1042103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1043103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1044103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1045103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1046103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1047103285Sikob } 1048113584Ssimokawa stat = status & FWOHCIEV_MASK; 1049103285Sikob switch(stat){ 1050110577Ssimokawa case FWOHCIEV_ACKPEND: 1051103285Sikob case FWOHCIEV_ACKCOMPL: 1052103285Sikob err = 0; 1053103285Sikob break; 1054103285Sikob case FWOHCIEV_ACKBSA: 1055103285Sikob case FWOHCIEV_ACKBSB: 1056110577Ssimokawa case FWOHCIEV_ACKBSX: 1057103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1058103285Sikob err = EBUSY; 1059103285Sikob break; 1060103285Sikob case FWOHCIEV_FLUSHED: 1061103285Sikob case FWOHCIEV_ACKTARD: 1062103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1063103285Sikob err = EAGAIN; 1064103285Sikob break; 1065103285Sikob case FWOHCIEV_MISSACK: 1066103285Sikob case FWOHCIEV_UNDRRUN: 1067103285Sikob case FWOHCIEV_OVRRUN: 1068103285Sikob case FWOHCIEV_DESCERR: 1069103285Sikob case FWOHCIEV_DTRDERR: 1070103285Sikob case FWOHCIEV_TIMEOUT: 1071103285Sikob case FWOHCIEV_TCODERR: 1072103285Sikob case FWOHCIEV_UNKNOWN: 1073103285Sikob case FWOHCIEV_ACKDERR: 1074103285Sikob case FWOHCIEV_ACKTERR: 1075103285Sikob default: 1076103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1077103285Sikob stat, fwohcicode[stat]); 1078103285Sikob err = EINVAL; 1079103285Sikob break; 1080103285Sikob } 1081110577Ssimokawa if (tr->xfer != NULL) { 1082103285Sikob xfer = tr->xfer; 1083113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1084113584Ssimokawa if (firewire_debug) 1085113584Ssimokawa printf("already rcvd\n"); 1086113584Ssimokawa fw_xfer_done(xfer); 1087113584Ssimokawa } else { 1088103285Sikob xfer->state = FWXF_SENT; 1089110577Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1090103285Sikob xfer->state = FWXF_BUSY; 1091113584Ssimokawa xfer->resp = err; 1092113584Ssimokawa if (xfer->retry_req != NULL) 1093113584Ssimokawa xfer->retry_req(xfer); 1094113584Ssimokawa else 1095113584Ssimokawa fw_xfer_done(xfer); 1096110577Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1097103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1098103285Sikob xfer->state = FWXF_SENTERR; 1099103285Sikob xfer->resp = err; 1100113584Ssimokawa fw_xfer_done(xfer); 1101103285Sikob } 1102113584Ssimokawa } 1103110577Ssimokawa /* 1104110577Ssimokawa * The watchdog timer takes care of split 1105110577Ssimokawa * transcation timeout for ACKPEND case. 1106110577Ssimokawa */ 1107113584Ssimokawa } else { 1108113584Ssimokawa printf("this shouldn't happen\n"); 1109103285Sikob } 1110110269Ssimokawa dbch->xferq.queued --; 1111103285Sikob tr->xfer = NULL; 1112103285Sikob 1113103285Sikob packets ++; 1114103285Sikob tr = STAILQ_NEXT(tr, link); 1115103285Sikob dbch->bottom = tr; 1116111956Ssimokawa if (dbch->bottom == dbch->top) { 1117111956Ssimokawa /* we reaches the end of context program */ 1118111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1119111956Ssimokawa printf("queued > 0\n"); 1120111956Ssimokawa break; 1121111956Ssimokawa } 1122103285Sikob } 1123103285Sikobout: 1124103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1125103285Sikob printf("make free slot\n"); 1126103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1127103285Sikob fwohci_start(sc, dbch); 1128103285Sikob } 1129103285Sikob splx(s); 1130103285Sikob} 1131106790Ssimokawa 1132106790Ssimokawastatic void 1133106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1134103285Sikob{ 1135103285Sikob struct fwohcidb_tr *db_tr; 1136113584Ssimokawa int idb; 1137103285Sikob 1138108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1139108527Ssimokawa return; 1140108527Ssimokawa 1141113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1142103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1143113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1144113584Ssimokawa db_tr->buf != NULL) { 1145113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1146113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1147113584Ssimokawa db_tr->buf = NULL; 1148113584Ssimokawa } else if (db_tr->dma_map != NULL) 1149113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1150103285Sikob } 1151103285Sikob dbch->ndb = 0; 1152103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1153113584Ssimokawa fwdma_free_multiseg(dbch->am); 1154110195Ssimokawa free(db_tr, M_FW); 1155103285Sikob STAILQ_INIT(&dbch->db_trq); 1156108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1157103285Sikob} 1158106790Ssimokawa 1159106790Ssimokawastatic void 1160113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1161103285Sikob{ 1162103285Sikob int idb; 1163103285Sikob struct fwohcidb_tr *db_tr; 1164108642Ssimokawa 1165108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1166108642Ssimokawa goto out; 1167108642Ssimokawa 1168113584Ssimokawa /* create dma_tag for buffers */ 1169113584Ssimokawa#define MAX_REQCOUNT 0xffff 1170113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1171113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1172113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1173113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1174113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1175113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1176113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1177113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1178113584Ssimokawa /*flags*/ 0, &dbch->dmat)) 1179113584Ssimokawa return; 1180113584Ssimokawa 1181103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1182103285Sikob /* DB entry must start at 16 bytes bounary. */ 1183103285Sikob STAILQ_INIT(&dbch->db_trq); 1184103285Sikob db_tr = (struct fwohcidb_tr *) 1185103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1186113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1187103285Sikob if(db_tr == NULL){ 1188109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1189103285Sikob return; 1190103285Sikob } 1191109379Ssimokawa 1192113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1193113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1194113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1195113584Ssimokawa if (dbch->am == NULL) { 1196113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1197103285Sikob return; 1198103285Sikob } 1199103285Sikob /* Attach DB to DMA ch. */ 1200103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1201103285Sikob db_tr->dbcnt = 0; 1202113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1203113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1204113584Ssimokawa /* create dmamap for buffers */ 1205113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1206113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1207113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1208113584Ssimokawa printf("bus_dmamap_create failed\n"); 1209113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1210113584Ssimokawa fwohci_db_free(dbch); 1211113584Ssimokawa return; 1212113584Ssimokawa } 1213103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1214113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1215108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1216108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1217108530Ssimokawa ].start = (caddr_t)db_tr; 1218108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1219108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1220108530Ssimokawa ].end = (caddr_t)db_tr; 1221103285Sikob } 1222103285Sikob db_tr++; 1223103285Sikob } 1224103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1225103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1226108642Ssimokawaout: 1227108642Ssimokawa dbch->xferq.queued = 0; 1228108642Ssimokawa dbch->pdb_tr = NULL; 1229103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1230103285Sikob dbch->bottom = dbch->top; 1231108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1232103285Sikob} 1233106790Ssimokawa 1234106790Ssimokawastatic int 1235106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1236103285Sikob{ 1237103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1238113584Ssimokawa int sleepch; 1239109890Ssimokawa 1240113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1241113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1242103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1243103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1244109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1245113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1246103285Sikob fwohci_db_free(&sc->it[dmach]); 1247103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1248103285Sikob return 0; 1249103285Sikob} 1250106790Ssimokawa 1251106790Ssimokawastatic int 1252106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1253103285Sikob{ 1254103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1255113584Ssimokawa int sleepch; 1256103285Sikob 1257103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1258103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1259103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1260109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1261113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1262103285Sikob fwohci_db_free(&sc->ir[dmach]); 1263103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1264103285Sikob return 0; 1265103285Sikob} 1266106790Ssimokawa 1267113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1268106790Ssimokawastatic void 1269106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1270103285Sikob{ 1271113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1272103285Sikob return; 1273103285Sikob} 1274103285Sikob#endif 1275103285Sikob 1276106790Ssimokawastatic int 1277106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1278103285Sikob{ 1279103285Sikob int err = 0; 1280113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1281103285Sikob u_int32_t off = NULL; 1282103285Sikob struct fwohcidb_tr *db_tr; 1283109892Ssimokawa volatile struct fwohcidb *db; 1284103285Sikob 1285103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1286103285Sikob err = EINVAL; 1287103285Sikob return err; 1288103285Sikob } 1289103285Sikob z = dbch->ndesc; 1290103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1291103285Sikob if( &sc->it[dmach] == dbch){ 1292103285Sikob off = OHCI_ITOFF(dmach); 1293103285Sikob break; 1294103285Sikob } 1295103285Sikob } 1296103285Sikob if(off == NULL){ 1297103285Sikob err = EINVAL; 1298103285Sikob return err; 1299103285Sikob } 1300103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1301103285Sikob return err; 1302103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1303103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1304103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1305103285Sikob } 1306103285Sikob db_tr = dbch->top; 1307113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1308113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1309103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1310103285Sikob break; 1311103285Sikob } 1312109892Ssimokawa db = db_tr->db; 1313113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1314113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1315113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1316113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1317103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1318103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1319113584Ssimokawa FWOHCI_DMA_SET( 1320113584Ssimokawa db[ldesc].db.desc.cmd, 1321113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1322109280Ssimokawa /* OHCI 1.1 and above */ 1323113584Ssimokawa FWOHCI_DMA_SET( 1324113584Ssimokawa db[0].db.desc.cmd, 1325113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1326103285Sikob } 1327103285Sikob } 1328103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1329103285Sikob } 1330113584Ssimokawa FWOHCI_DMA_CLEAR( 1331113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1332103285Sikob return err; 1333103285Sikob} 1334106790Ssimokawa 1335106790Ssimokawastatic int 1336106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1337103285Sikob{ 1338103285Sikob int err = 0; 1339109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1340103285Sikob u_int32_t off = NULL; 1341103285Sikob struct fwohcidb_tr *db_tr; 1342109892Ssimokawa volatile struct fwohcidb *db; 1343103285Sikob 1344103285Sikob z = dbch->ndesc; 1345103285Sikob if(&sc->arrq == dbch){ 1346103285Sikob off = OHCI_ARQOFF; 1347103285Sikob }else if(&sc->arrs == dbch){ 1348103285Sikob off = OHCI_ARSOFF; 1349103285Sikob }else{ 1350103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1351103285Sikob if( &sc->ir[dmach] == dbch){ 1352103285Sikob off = OHCI_IROFF(dmach); 1353103285Sikob break; 1354103285Sikob } 1355103285Sikob } 1356103285Sikob } 1357103285Sikob if(off == NULL){ 1358103285Sikob err = EINVAL; 1359103285Sikob return err; 1360103285Sikob } 1361103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1362103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1363103285Sikob return err; 1364103285Sikob }else{ 1365103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1366103285Sikob err = EBUSY; 1367103285Sikob return err; 1368103285Sikob } 1369103285Sikob } 1370103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1371108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1372103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1373103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1374103285Sikob } 1375103285Sikob db_tr = dbch->top; 1376113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1377113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1378113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1379103285Sikob break; 1380109892Ssimokawa db = db_tr->db; 1381109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1382113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1383113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1384103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1385103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1386113584Ssimokawa FWOHCI_DMA_SET( 1387113584Ssimokawa db[ldesc].db.desc.cmd, 1388113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1389113584Ssimokawa FWOHCI_DMA_CLEAR( 1390113584Ssimokawa db[ldesc].db.desc.depend, 1391113584Ssimokawa 0xf); 1392103285Sikob } 1393103285Sikob } 1394103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1395103285Sikob } 1396113584Ssimokawa FWOHCI_DMA_CLEAR( 1397113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1398103285Sikob dbch->buf_offset = 0; 1399113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1400113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1401103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1402103285Sikob return err; 1403103285Sikob }else{ 1404113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1405103285Sikob } 1406103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1407103285Sikob return err; 1408103285Sikob} 1409106790Ssimokawa 1410106790Ssimokawastatic int 1411113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1412109890Ssimokawa{ 1413109890Ssimokawa int sec, cycle, cycle_match; 1414109890Ssimokawa 1415109890Ssimokawa cycle = cycle_now & 0x1fff; 1416109890Ssimokawa sec = cycle_now >> 13; 1417109890Ssimokawa#define CYCLE_MOD 0x10 1418113584Ssimokawa#if 1 1419109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1420113584Ssimokawa#else 1421113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1422113584Ssimokawa#endif 1423109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1424109890Ssimokawa if (cycle >= 8000) { 1425109890Ssimokawa sec ++; 1426109890Ssimokawa cycle -= 8000; 1427109890Ssimokawa } 1428113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1429109890Ssimokawa if (cycle >= 8000) { 1430109890Ssimokawa sec ++; 1431109890Ssimokawa if (cycle == 8000) 1432109890Ssimokawa cycle = 0; 1433109890Ssimokawa else 1434109890Ssimokawa cycle = CYCLE_MOD; 1435109890Ssimokawa } 1436109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1437109890Ssimokawa 1438109890Ssimokawa return(cycle_match); 1439109890Ssimokawa} 1440109890Ssimokawa 1441109890Ssimokawastatic int 1442106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1443103285Sikob{ 1444103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1445103285Sikob int err = 0; 1446103285Sikob unsigned short tag, ich; 1447103285Sikob struct fwohci_dbch *dbch; 1448109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1449109356Ssimokawa u_int32_t stat; 1450109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1451109890Ssimokawa struct fw_xferq *it; 1452103285Sikob 1453103285Sikob dbch = &sc->it[dmach]; 1454109890Ssimokawa it = &dbch->xferq; 1455109890Ssimokawa 1456109890Ssimokawa tag = (it->flag >> 6) & 3; 1457109890Ssimokawa ich = it->flag & 0x3f; 1458109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1459109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1460103285Sikob dbch->ndesc = 3; 1461113584Ssimokawa fwohci_db_init(sc, dbch); 1462109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1463109179Ssimokawa return ENOMEM; 1464103285Sikob err = fwohci_tx_enable(sc, dbch); 1465103285Sikob } 1466103285Sikob if(err) 1467103285Sikob return err; 1468109890Ssimokawa 1469109892Ssimokawa ldesc = dbch->ndesc - 1; 1470109890Ssimokawa s = splfw(); 1471109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1472109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1473109890Ssimokawa volatile struct fwohcidb *db; 1474109890Ssimokawa 1475113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1476113584Ssimokawa BUS_DMASYNC_PREWRITE); 1477109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1478109890Ssimokawa if (prev != NULL) { 1479109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1480113584Ssimokawa#if 0 /* XXX necessary? */ 1481113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1482113584Ssimokawa OHCI_BRANCH_ALWAYS); 1483113584Ssimokawa#endif 1484109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1485109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1486113584Ssimokawa ((struct fwohcidb_tr *) 1487113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1488109892Ssimokawa#else 1489113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1490113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1491109892Ssimokawa#endif 1492103285Sikob } 1493109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1494109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1495109890Ssimokawa prev = chunk; 1496109403Ssimokawa } 1497113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1498113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1499109890Ssimokawa splx(s); 1500109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1501113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1502113584Ssimokawa printf("stat 0x%x\n", stat); 1503113584Ssimokawa 1504109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1505109890Ssimokawa return 0; 1506109890Ssimokawa 1507113584Ssimokawa#if 0 1508109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1509113584Ssimokawa#endif 1510109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1511109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1512109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1513113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1514109890Ssimokawa 1515109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1516113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1517113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1518113584Ssimokawa if (firewire_debug) { 1519109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1520113584Ssimokawa#if 1 1521113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1522113584Ssimokawa#endif 1523113584Ssimokawa } 1524109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1525109890Ssimokawa#if 1 1526109890Ssimokawa /* Don't start until all chunks are buffered */ 1527109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1528109890Ssimokawa goto out; 1529109890Ssimokawa#endif 1530113584Ssimokawa#if 1 1531109890Ssimokawa /* Clear cycle match counter bits */ 1532109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1533109890Ssimokawa 1534109356Ssimokawa /* 2bit second + 13bit cycle */ 1535109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1536113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1537109890Ssimokawa 1538109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1539109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1540109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1541113584Ssimokawa#else 1542113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1543113584Ssimokawa#endif 1544113584Ssimokawa if (firewire_debug) { 1545109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1546109403Ssimokawa cycle_now, cycle_match); 1547113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1548113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1549113584Ssimokawa } 1550109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1551109890Ssimokawa device_printf(sc->fc.dev, 1552109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1553113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1554103285Sikob } 1555109890Ssimokawaout: 1556103285Sikob return err; 1557103285Sikob} 1558106790Ssimokawa 1559106790Ssimokawastatic int 1560113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1561103285Sikob{ 1562103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1563109890Ssimokawa int err = 0, s, ldesc; 1564103285Sikob unsigned short tag, ich; 1565109736Ssimokawa u_int32_t stat; 1566109890Ssimokawa struct fwohci_dbch *dbch; 1567113584Ssimokawa struct fwohcidb_tr *db_tr; 1568109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1569109890Ssimokawa struct fw_xferq *ir; 1570103285Sikob 1571109890Ssimokawa dbch = &sc->ir[dmach]; 1572109890Ssimokawa ir = &dbch->xferq; 1573109890Ssimokawa 1574109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1575109890Ssimokawa tag = (ir->flag >> 6) & 3; 1576109890Ssimokawa ich = ir->flag & 0x3f; 1577108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1578108995Ssimokawa 1579109890Ssimokawa ir->queued = 0; 1580109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1581109890Ssimokawa dbch->ndesc = 2; 1582113584Ssimokawa fwohci_db_init(sc, dbch); 1583109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1584109179Ssimokawa return ENOMEM; 1585109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1586103285Sikob } 1587103285Sikob if(err) 1588103285Sikob return err; 1589103285Sikob 1590109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1591109890Ssimokawa if (first == NULL) { 1592109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1593109890Ssimokawa return 0; 1594109890Ssimokawa } 1595109890Ssimokawa 1596111892Ssimokawa ldesc = dbch->ndesc - 1; 1597111892Ssimokawa s = splfw(); 1598109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1599109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1600109890Ssimokawa volatile struct fwohcidb *db; 1601109890Ssimokawa 1602111942Ssimokawa#if 1 /* XXX for if_fwe */ 1603113584Ssimokawa if (chunk->mbuf != NULL) { 1604113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1605113584Ssimokawa db_tr->dbcnt = 1; 1606113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1607113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1608113584Ssimokawa /* flags */0); 1609113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1610113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1611113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1612113584Ssimokawa } 1613111942Ssimokawa#endif 1614109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1615113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1616113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1617109890Ssimokawa if (prev != NULL) { 1618109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1619113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1620103285Sikob } 1621109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1622109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1623109890Ssimokawa prev = chunk; 1624103285Sikob } 1625113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1626113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1627109890Ssimokawa splx(s); 1628109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1629109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1630109890Ssimokawa return 0; 1631109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1632109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1633109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1634109890Ssimokawa } 1635109890Ssimokawa 1636113584Ssimokawa if (firewire_debug) 1637113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1638109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1639109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1640109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1641109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1642109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1643109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1644113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1645109890Ssimokawa | dbch->ndesc); 1646109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1647109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1648113584Ssimokawa#if 0 1649113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1650113584Ssimokawa#endif 1651103285Sikob return err; 1652103285Sikob} 1653106790Ssimokawa 1654106790Ssimokawaint 1655110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1656103285Sikob{ 1657103285Sikob u_int i; 1658103285Sikob 1659103285Sikob/* Now stopping all DMA channel */ 1660103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1661103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1662103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1663103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1664103285Sikob 1665103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1666103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1667103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1668103285Sikob } 1669103285Sikob 1670103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1671103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1672103285Sikob 1673103285Sikob/* Stop interrupt */ 1674103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1675103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1676103285Sikob | OHCI_INT_PHY_INT 1677103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1678103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1679103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1680103285Sikob | OHCI_INT_PHY_BUS_R); 1681108642Ssimokawa/* XXX Link down? Bus reset? */ 1682103285Sikob return 0; 1683103285Sikob} 1684103285Sikob 1685108642Ssimokawaint 1686108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1687108642Ssimokawa{ 1688108642Ssimokawa int i; 1689108642Ssimokawa 1690108642Ssimokawa fwohci_reset(sc, dev); 1691108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1692108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1693108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1694108642Ssimokawa device_printf(sc->fc.dev, 1695108642Ssimokawa "resume iso receive ch: %d\n", i); 1696108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1697108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1698108642Ssimokawa } 1699108642Ssimokawa } 1700108642Ssimokawa 1701108642Ssimokawa bus_generic_resume(dev); 1702108642Ssimokawa sc->fc.ibr(&sc->fc); 1703108642Ssimokawa return 0; 1704108642Ssimokawa} 1705108642Ssimokawa 1706103285Sikob#define ACK_ALL 1707103285Sikobstatic void 1708106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1709103285Sikob{ 1710103285Sikob u_int32_t irstat, itstat; 1711103285Sikob u_int i; 1712103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1713103285Sikob 1714103285Sikob#ifdef OHCI_DEBUG 1715103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1716103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1717103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1718103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1719103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1720103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1721103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1722103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1723103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1724103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1725103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1726103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1727103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1728103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1729103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1730103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1731103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1732103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1733103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1734103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1735103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1736103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1737103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1738103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1739103285Sikob ); 1740103285Sikob#endif 1741103285Sikob/* Bus reset */ 1742103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1743111074Ssimokawa if (fc->status == FWBUSRESET) 1744111074Ssimokawa goto busresetout; 1745111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1746111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1747111074Ssimokawa 1748103285Sikob device_printf(fc->dev, "BUS reset\n"); 1749103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1750103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1751103285Sikob 1752103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1753103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1754103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1755103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1756103285Sikob 1757103285Sikob#ifndef ACK_ALL 1758103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1759103285Sikob#endif 1760110798Ssimokawa fw_busreset(fc); 1761103285Sikob } 1762111074Ssimokawabusresetout: 1763103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1764103285Sikob#ifndef ACK_ALL 1765103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1766103285Sikob#endif 1767113584Ssimokawa#if __FreeBSD_version >= 500000 1768113584Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1769113584Ssimokawa#else 1770113584Ssimokawa irstat = sc->irstat; 1771113584Ssimokawa sc->irstat = 0; 1772113584Ssimokawa#endif 1773103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1774109644Ssimokawa struct fwohci_dbch *dbch; 1775109644Ssimokawa 1776103285Sikob if((irstat & (1 << i)) != 0){ 1777109644Ssimokawa dbch = &sc->ir[i]; 1778109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1779109644Ssimokawa device_printf(sc->fc.dev, 1780109644Ssimokawa "dma(%d) not active\n", i); 1781109644Ssimokawa continue; 1782109644Ssimokawa } 1783113584Ssimokawa fwohci_rbuf_update(sc, i); 1784103285Sikob } 1785103285Sikob } 1786103285Sikob } 1787103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1788103285Sikob#ifndef ACK_ALL 1789103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1790103285Sikob#endif 1791113584Ssimokawa#if __FreeBSD_version >= 500000 1792113584Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1793113584Ssimokawa#else 1794113584Ssimokawa itstat = sc->itstat; 1795113584Ssimokawa sc->itstat = 0; 1796113584Ssimokawa#endif 1797103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1798103285Sikob if((itstat & (1 << i)) != 0){ 1799103285Sikob fwohci_tbuf_update(sc, i); 1800103285Sikob } 1801103285Sikob } 1802103285Sikob } 1803103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1804103285Sikob#ifndef ACK_ALL 1805103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1806103285Sikob#endif 1807103285Sikob#if 0 1808103285Sikob dump_dma(sc, ARRS_CH); 1809103285Sikob dump_db(sc, ARRS_CH); 1810103285Sikob#endif 1811106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1812103285Sikob } 1813103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1814103285Sikob#ifndef ACK_ALL 1815103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1816103285Sikob#endif 1817103285Sikob#if 0 1818103285Sikob dump_dma(sc, ARRQ_CH); 1819103285Sikob dump_db(sc, ARRQ_CH); 1820103285Sikob#endif 1821106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1822103285Sikob } 1823103285Sikob if(stat & OHCI_INT_PHY_SID){ 1824113584Ssimokawa u_int32_t *buf, node_id; 1825103285Sikob int plen; 1826103285Sikob 1827103285Sikob#ifndef ACK_ALL 1828103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1829103285Sikob#endif 1830111074Ssimokawa /* Enable bus reset interrupt */ 1831111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1832111787Ssimokawa /* Allow async. request to us */ 1833111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1834111787Ssimokawa /* XXX insecure ?? */ 1835111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1836111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1837111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1838112523Ssimokawa /* Set ATRetries register */ 1839112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1840103285Sikob/* 1841103285Sikob** Checking whether the node is root or not. If root, turn on 1842103285Sikob** cycle master. 1843103285Sikob*/ 1844113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1845113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1846113584Ssimokawa 1847113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1848113584Ssimokawa node_id, (plen >> 16) & 0xff); 1849113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1850103285Sikob printf("Bus reset failure\n"); 1851103285Sikob goto sidout; 1852103285Sikob } 1853113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1854103285Sikob printf("CYCLEMASTER mode\n"); 1855103285Sikob OWRITE(sc, OHCI_LNKCTL, 1856103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1857113584Ssimokawa } else { 1858103285Sikob printf("non CYCLEMASTER mode\n"); 1859103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1860103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1861103285Sikob } 1862113584Ssimokawa fc->nodeid = node_id & 0x3f; 1863103285Sikob 1864113584Ssimokawa if (plen & OHCI_SID_ERR) { 1865113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1866113584Ssimokawa goto sidout; 1867113584Ssimokawa } 1868113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1869109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1870109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1871109736Ssimokawa goto sidout; 1872109736Ssimokawa } 1873103285Sikob plen -= 4; /* chop control info */ 1874113584Ssimokawa buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1875113584Ssimokawa if (buf == NULL) { 1876113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1877113584Ssimokawa goto sidout; 1878113584Ssimokawa } 1879113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1880113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1881110269Ssimokawa#if 1 1882110269Ssimokawa /* pending all pre-bus_reset packets */ 1883110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1884110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1885110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1886110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1887110798Ssimokawa fw_drain_txq(fc); 1888110269Ssimokawa#endif 1889113584Ssimokawa fw_sidrcv(fc, buf, plen); 1890113584Ssimokawa free(buf, M_FW); 1891103285Sikob } 1892103285Sikobsidout: 1893103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1894103285Sikob#ifndef ACK_ALL 1895103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1896103285Sikob#endif 1897103285Sikob fwohci_txd(sc, &(sc->atrq)); 1898103285Sikob } 1899103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1900103285Sikob#ifndef ACK_ALL 1901103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1902103285Sikob#endif 1903103285Sikob fwohci_txd(sc, &(sc->atrs)); 1904103285Sikob } 1905103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1906103285Sikob#ifndef ACK_ALL 1907103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1908103285Sikob#endif 1909103285Sikob device_printf(fc->dev, "posted write error\n"); 1910103285Sikob } 1911103285Sikob if((stat & OHCI_INT_ERR )){ 1912103285Sikob#ifndef ACK_ALL 1913103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1914103285Sikob#endif 1915103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1916103285Sikob } 1917103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1918103285Sikob#ifndef ACK_ALL 1919103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1920103285Sikob#endif 1921103285Sikob device_printf(fc->dev, "phy int\n"); 1922103285Sikob } 1923103285Sikob 1924103285Sikob return; 1925103285Sikob} 1926103285Sikob 1927113584Ssimokawa#if FWOHCI_TASKQUEUE 1928113584Ssimokawastatic void 1929113584Ssimokawafwohci_complete(void *arg, int pending) 1930113584Ssimokawa{ 1931113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1932113584Ssimokawa u_int32_t stat; 1933113584Ssimokawa 1934113584Ssimokawaagain: 1935113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 1936113584Ssimokawa if (stat) 1937113584Ssimokawa fwohci_intr_body(sc, stat, -1); 1938113584Ssimokawa else 1939113584Ssimokawa return; 1940113584Ssimokawa goto again; 1941113584Ssimokawa} 1942113584Ssimokawa#endif 1943113584Ssimokawa 1944113584Ssimokawastatic u_int32_t 1945113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 1946113584Ssimokawa{ 1947113584Ssimokawa u_int32_t stat, irstat, itstat; 1948113584Ssimokawa 1949113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 1950113584Ssimokawa if (stat == 0xffffffff) { 1951113584Ssimokawa device_printf(sc->fc.dev, 1952113584Ssimokawa "device physically ejected?\n"); 1953113584Ssimokawa return(stat); 1954113584Ssimokawa } 1955113584Ssimokawa#ifdef ACK_ALL 1956113584Ssimokawa if (stat) 1957113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1958113584Ssimokawa#endif 1959113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 1960113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 1961113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 1962113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 1963113584Ssimokawa } 1964113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 1965113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 1966113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 1967113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 1968113584Ssimokawa } 1969113584Ssimokawa return(stat); 1970113584Ssimokawa} 1971113584Ssimokawa 1972103285Sikobvoid 1973103285Sikobfwohci_intr(void *arg) 1974103285Sikob{ 1975103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1976113584Ssimokawa u_int32_t stat; 1977113584Ssimokawa#if !FWOHCI_TASKQUEUE 1978113584Ssimokawa u_int32_t bus_reset = 0; 1979113584Ssimokawa#endif 1980103285Sikob 1981103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1982103285Sikob /* polling mode */ 1983103285Sikob return; 1984103285Sikob } 1985103285Sikob 1986113584Ssimokawa#if !FWOHCI_TASKQUEUE 1987113584Ssimokawaagain: 1988103285Sikob#endif 1989113584Ssimokawa stat = fwochi_check_stat(sc); 1990113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 1991113584Ssimokawa return; 1992113584Ssimokawa#if FWOHCI_TASKQUEUE 1993113584Ssimokawa atomic_set_int(&sc->intstat, stat); 1994113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 1995113584Ssimokawa if (stat) 1996113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 1997113584Ssimokawa#else 1998113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 1999113584Ssimokawa if ((stat & ~bus_reset) == 0) 2000113584Ssimokawa return; 2001113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2002113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2003113584Ssimokawa goto again; 2004113584Ssimokawa#endif 2005103285Sikob} 2006103285Sikob 2007103285Sikobstatic void 2008103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2009103285Sikob{ 2010103285Sikob int s; 2011103285Sikob u_int32_t stat; 2012103285Sikob struct fwohci_softc *sc; 2013103285Sikob 2014103285Sikob 2015103285Sikob sc = (struct fwohci_softc *)fc; 2016103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2017103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2018103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2019103285Sikob#if 0 2020103285Sikob if (!quick) { 2021103285Sikob#else 2022103285Sikob if (1) { 2023103285Sikob#endif 2024113584Ssimokawa stat = fwochi_check_stat(sc); 2025113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2026103285Sikob return; 2027103285Sikob } 2028103285Sikob s = splfw(); 2029106789Ssimokawa fwohci_intr_body(sc, stat, count); 2030103285Sikob splx(s); 2031103285Sikob} 2032103285Sikob 2033103285Sikobstatic void 2034103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2035103285Sikob{ 2036103285Sikob struct fwohci_softc *sc; 2037103285Sikob 2038103285Sikob sc = (struct fwohci_softc *)fc; 2039107653Ssimokawa if (bootverbose) 2040108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2041103285Sikob if (enable) { 2042103285Sikob sc->intmask |= OHCI_INT_EN; 2043103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2044103285Sikob } else { 2045103285Sikob sc->intmask &= ~OHCI_INT_EN; 2046103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2047103285Sikob } 2048103285Sikob} 2049103285Sikob 2050106790Ssimokawastatic void 2051106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2052103285Sikob{ 2053103285Sikob struct firewire_comm *fc = &sc->fc; 2054109890Ssimokawa volatile struct fwohcidb *db; 2055109890Ssimokawa struct fw_bulkxfer *chunk; 2056109890Ssimokawa struct fw_xferq *it; 2057109890Ssimokawa u_int32_t stat, count; 2058113584Ssimokawa int s, w=0, ldesc; 2059103285Sikob 2060109890Ssimokawa it = fc->it[dmach]; 2061113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2062109890Ssimokawa s = splfw(); /* unnecessary ? */ 2063113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2064109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2065109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2066113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2067113584Ssimokawa >> OHCI_STATUS_SHIFT; 2068109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2069113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2070113584Ssimokawa & OHCI_COUNT_MASK; 2071109890Ssimokawa if (stat == 0) 2072109890Ssimokawa break; 2073109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2074109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2075109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2076109890Ssimokawa#if 0 2077109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2078109179Ssimokawa#endif 2079109890Ssimokawa break; 2080109890Ssimokawa default: 2081109423Ssimokawa device_printf(fc->dev, 2082113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2083113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2084109890Ssimokawa } 2085109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2086109890Ssimokawa w++; 2087109403Ssimokawa } 2088109890Ssimokawa splx(s); 2089109890Ssimokawa if (w) 2090109890Ssimokawa wakeup(it); 2091103285Sikob} 2092106790Ssimokawa 2093106790Ssimokawastatic void 2094106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2095103285Sikob{ 2096109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2097113584Ssimokawa volatile struct fwohcidb_tr *db_tr; 2098109890Ssimokawa struct fw_bulkxfer *chunk; 2099109890Ssimokawa struct fw_xferq *ir; 2100109890Ssimokawa u_int32_t stat; 2101113584Ssimokawa int s, w=0, ldesc; 2102109179Ssimokawa 2103109890Ssimokawa ir = fc->ir[dmach]; 2104113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2105113584Ssimokawa#if 0 2106113584Ssimokawa dump_db(sc, dmach); 2107113584Ssimokawa#endif 2108109890Ssimokawa s = splfw(); 2109113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2110109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2111113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2112113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2113113584Ssimokawa >> OHCI_STATUS_SHIFT; 2114109890Ssimokawa if (stat == 0) 2115109890Ssimokawa break; 2116113584Ssimokawa 2117113584Ssimokawa if (chunk->mbuf != NULL) { 2118113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2119113584Ssimokawa BUS_DMASYNC_POSTREAD); 2120113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2121113584Ssimokawa } else if (ir->buf != NULL) { 2122113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2123113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2124113584Ssimokawa } else { 2125113584Ssimokawa /* XXX */ 2126113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2127113584Ssimokawa } 2128113584Ssimokawa 2129109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2130109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2131109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2132109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2133111942Ssimokawa chunk->resp = 0; 2134109890Ssimokawa break; 2135109890Ssimokawa default: 2136111942Ssimokawa chunk->resp = EINVAL; 2137109890Ssimokawa device_printf(fc->dev, 2138113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2139113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2140109890Ssimokawa } 2141109890Ssimokawa w++; 2142103285Sikob } 2143109890Ssimokawa splx(s); 2144111942Ssimokawa if (w) { 2145111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2146111942Ssimokawa ir->hand(ir); 2147111942Ssimokawa else 2148111942Ssimokawa wakeup(ir); 2149111942Ssimokawa } 2150103285Sikob} 2151106790Ssimokawa 2152106790Ssimokawavoid 2153106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2154106790Ssimokawa{ 2155103285Sikob u_int32_t off, cntl, stat, cmd, match; 2156103285Sikob 2157103285Sikob if(ch == 0){ 2158103285Sikob off = OHCI_ATQOFF; 2159103285Sikob }else if(ch == 1){ 2160103285Sikob off = OHCI_ATSOFF; 2161103285Sikob }else if(ch == 2){ 2162103285Sikob off = OHCI_ARQOFF; 2163103285Sikob }else if(ch == 3){ 2164103285Sikob off = OHCI_ARSOFF; 2165103285Sikob }else if(ch < IRX_CH){ 2166103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2167103285Sikob }else{ 2168103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2169103285Sikob } 2170103285Sikob cntl = stat = OREAD(sc, off); 2171103285Sikob cmd = OREAD(sc, off + 0xc); 2172103285Sikob match = OREAD(sc, off + 0x10); 2173103285Sikob 2174113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2175103285Sikob ch, 2176103285Sikob cntl, 2177103285Sikob cmd, 2178103285Sikob match); 2179103285Sikob stat &= 0xffff ; 2180113584Ssimokawa if (stat) { 2181103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2182103285Sikob ch, 2183103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2184103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2185103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2186103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2187103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2188103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2189103285Sikob fwohcicode[stat & 0x1f], 2190103285Sikob stat & 0x1f 2191103285Sikob ); 2192103285Sikob }else{ 2193103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2194103285Sikob } 2195103285Sikob} 2196106790Ssimokawa 2197106790Ssimokawavoid 2198106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2199106790Ssimokawa{ 2200103285Sikob struct fwohci_dbch *dbch; 2201113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2202103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2203103285Sikob int idb, jdb; 2204103285Sikob u_int32_t cmd, off; 2205103285Sikob if(ch == 0){ 2206103285Sikob off = OHCI_ATQOFF; 2207103285Sikob dbch = &sc->atrq; 2208103285Sikob }else if(ch == 1){ 2209103285Sikob off = OHCI_ATSOFF; 2210103285Sikob dbch = &sc->atrs; 2211103285Sikob }else if(ch == 2){ 2212103285Sikob off = OHCI_ARQOFF; 2213103285Sikob dbch = &sc->arrq; 2214103285Sikob }else if(ch == 3){ 2215103285Sikob off = OHCI_ARSOFF; 2216103285Sikob dbch = &sc->arrs; 2217103285Sikob }else if(ch < IRX_CH){ 2218103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2219103285Sikob dbch = &sc->it[ch - ITX_CH]; 2220103285Sikob }else { 2221103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2222103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2223103285Sikob } 2224103285Sikob cmd = OREAD(sc, off + 0xc); 2225103285Sikob 2226103285Sikob if( dbch->ndb == 0 ){ 2227103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2228103285Sikob return; 2229103285Sikob } 2230103285Sikob pp = dbch->top; 2231103285Sikob prev = pp->db; 2232103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2233103285Sikob if(pp == NULL){ 2234103285Sikob curr = NULL; 2235103285Sikob goto outdb; 2236103285Sikob } 2237103285Sikob cp = STAILQ_NEXT(pp, link); 2238103285Sikob if(cp == NULL){ 2239103285Sikob curr = NULL; 2240103285Sikob goto outdb; 2241103285Sikob } 2242103285Sikob np = STAILQ_NEXT(cp, link); 2243103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2244113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2245103285Sikob curr = cp->db; 2246103285Sikob if(np != NULL){ 2247103285Sikob next = np->db; 2248103285Sikob }else{ 2249103285Sikob next = NULL; 2250103285Sikob } 2251103285Sikob goto outdb; 2252103285Sikob } 2253103285Sikob } 2254103285Sikob pp = STAILQ_NEXT(pp, link); 2255103285Sikob prev = pp->db; 2256103285Sikob } 2257103285Sikoboutdb: 2258103285Sikob if( curr != NULL){ 2259113584Ssimokawa#if 0 2260103285Sikob printf("Prev DB %d\n", ch); 2261113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2262113584Ssimokawa#endif 2263103285Sikob printf("Current DB %d\n", ch); 2264113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2265113584Ssimokawa#if 0 2266103285Sikob printf("Next DB %d\n", ch); 2267113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2268113584Ssimokawa#endif 2269103285Sikob }else{ 2270103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2271103285Sikob } 2272103285Sikob return; 2273103285Sikob} 2274106790Ssimokawa 2275106790Ssimokawavoid 2276113584Ssimokawaprint_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2277113584Ssimokawa u_int32_t ch, u_int32_t max) 2278106790Ssimokawa{ 2279103285Sikob fwohcireg_t stat; 2280103285Sikob int i, key; 2281113584Ssimokawa u_int32_t cmd, res; 2282103285Sikob 2283103285Sikob if(db == NULL){ 2284103285Sikob printf("No Descriptor is found\n"); 2285103285Sikob return; 2286103285Sikob } 2287103285Sikob 2288103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2289103285Sikob ch, 2290103285Sikob "Current", 2291103285Sikob "OP ", 2292103285Sikob "KEY", 2293103285Sikob "INT", 2294103285Sikob "BR ", 2295103285Sikob "len", 2296103285Sikob "Addr", 2297103285Sikob "Depend", 2298103285Sikob "Stat", 2299103285Sikob "Cnt"); 2300103285Sikob for( i = 0 ; i <= max ; i ++){ 2301113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2302113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2303113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2304113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2305108712Ssimokawa#if __FreeBSD_version >= 500000 2306106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2307108712Ssimokawa#else 2308108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2309108712Ssimokawa#endif 2310113584Ssimokawa db_tr->bus_addr, 2311113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2312113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2313113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2314113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2315113584Ssimokawa cmd & OHCI_COUNT_MASK, 2316113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2317113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2318113584Ssimokawa stat, 2319113584Ssimokawa res & OHCI_COUNT_MASK); 2320103285Sikob if(stat & 0xff00){ 2321103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2322103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2323103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2324103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2325103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2326103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2327103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2328103285Sikob fwohcicode[stat & 0x1f], 2329103285Sikob stat & 0x1f 2330103285Sikob ); 2331103285Sikob }else{ 2332103285Sikob printf(" Nostat\n"); 2333103285Sikob } 2334103285Sikob if(key == OHCI_KEY_ST2 ){ 2335103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2336113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2337113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2338113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2339113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2340103285Sikob } 2341103285Sikob if(key == OHCI_KEY_DEVICE){ 2342103285Sikob return; 2343103285Sikob } 2344113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2345103285Sikob == OHCI_BRANCH_ALWAYS){ 2346103285Sikob return; 2347103285Sikob } 2348113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2349103285Sikob == OHCI_OUTPUT_LAST){ 2350103285Sikob return; 2351103285Sikob } 2352113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2353103285Sikob == OHCI_INPUT_LAST){ 2354103285Sikob return; 2355103285Sikob } 2356103285Sikob if(key == OHCI_KEY_ST2 ){ 2357103285Sikob i++; 2358103285Sikob } 2359103285Sikob } 2360103285Sikob return; 2361103285Sikob} 2362106790Ssimokawa 2363106790Ssimokawavoid 2364106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2365103285Sikob{ 2366103285Sikob struct fwohci_softc *sc; 2367103285Sikob u_int32_t fun; 2368103285Sikob 2369110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2370103285Sikob sc = (struct fwohci_softc *)fc; 2371108276Ssimokawa 2372108276Ssimokawa /* 2373108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2374108276Ssimokawa * shouldn't became the root node. 2375108276Ssimokawa */ 2376103285Sikob#if 1 2377103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2378109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2379103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2380109280Ssimokawa#else /* Short bus reset */ 2381103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2382109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2383103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2384103285Sikob#endif 2385103285Sikob} 2386106790Ssimokawa 2387106790Ssimokawavoid 2388106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2389103285Sikob{ 2390103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2391103285Sikob struct fwohci_dbch *dbch; 2392109892Ssimokawa volatile struct fwohcidb *db; 2393103285Sikob struct fw_pkt *fp; 2394103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2395103285Sikob unsigned short chtag; 2396103285Sikob int idb; 2397103285Sikob 2398103285Sikob dbch = &sc->it[dmach]; 2399103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2400103285Sikob 2401103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2402103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2403103285Sikob/* 2404113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2405103285Sikob*/ 2406113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2407109892Ssimokawa db = db_tr->db; 2408103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2409109892Ssimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2410113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2411113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2412103285Sikob ohcifp->mode.stream.chtag = chtag; 2413103285Sikob ohcifp->mode.stream.tcode = 0xa; 2414109890Ssimokawa ohcifp->mode.stream.spd = 0; 2415113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2416113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2417113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2418113584Ssimokawa#endif 2419103285Sikob 2420113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2421113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2422113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2423109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2424113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2425103285Sikob | OHCI_UPDATE 2426109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2427109892Ssimokawa db[0].db.desc.depend = 2428109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2429113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2430109892Ssimokawa#else 2431113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2432113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2433109892Ssimokawa#endif 2434103285Sikob bulkxfer->end = (caddr_t)db_tr; 2435103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2436103285Sikob } 2437109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2438113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2439113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2440109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2441109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2442109280Ssimokawa /* OHCI 1.1 and above */ 2443109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2444109892Ssimokawa#endif 2445109892Ssimokawa/* 2446103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2447103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2448113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2449103285Sikob*/ 2450103285Sikob return; 2451103285Sikob} 2452106790Ssimokawa 2453106790Ssimokawastatic int 2454113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2455113584Ssimokawa int poffset) 2456103285Sikob{ 2457103285Sikob volatile struct fwohcidb *db = db_tr->db; 2458113584Ssimokawa struct fw_xferq *it; 2459103285Sikob int err = 0; 2460113584Ssimokawa 2461113584Ssimokawa it = &dbch->xferq; 2462113584Ssimokawa if(it->buf == 0){ 2463103285Sikob err = EINVAL; 2464103285Sikob return err; 2465103285Sikob } 2466113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2467103285Sikob db_tr->dbcnt = 3; 2468103285Sikob 2469113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2470113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2471113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2472113584Ssimokawa fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2473113584Ssimokawa 2474113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2475113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2476109892Ssimokawa#if 1 2477113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2478113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2479109892Ssimokawa#endif 2480113584Ssimokawa return 0; 2481103285Sikob} 2482106790Ssimokawa 2483106790Ssimokawaint 2484113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2485113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2486103285Sikob{ 2487103285Sikob volatile struct fwohcidb *db = db_tr->db; 2488113584Ssimokawa struct fw_xferq *ir; 2489113584Ssimokawa int i, ldesc; 2490113584Ssimokawa bus_addr_t dbuf[2]; 2491103285Sikob int dsiz[2]; 2492103285Sikob 2493113584Ssimokawa ir = &dbch->xferq; 2494113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2495113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2496113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2497113584Ssimokawa if (db_tr->buf == NULL) 2498113584Ssimokawa return(ENOMEM); 2499103285Sikob db_tr->dbcnt = 1; 2500113584Ssimokawa dsiz[0] = ir->psize; 2501113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2502113584Ssimokawa BUS_DMASYNC_PREREAD); 2503113584Ssimokawa } else { 2504113584Ssimokawa db_tr->dbcnt = 0; 2505113584Ssimokawa if (dummy_dma != NULL) { 2506113584Ssimokawa dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2507113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2508113584Ssimokawa } 2509113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2510113584Ssimokawa if (ir->buf != NULL) { 2511113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2512113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2513113584Ssimokawa } 2514113584Ssimokawa db_tr->dbcnt++; 2515103285Sikob } 2516103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2517113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2518113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2519113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2520113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2521103285Sikob } 2522113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2523103285Sikob } 2524113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2525113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2526113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2527103285Sikob } 2528113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2529113584Ssimokawa return 0; 2530103285Sikob} 2531106790Ssimokawa 2532113584Ssimokawa 2533113584Ssimokawastatic int 2534113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2535103285Sikob{ 2536113584Ssimokawa struct fw_pkt *fp0; 2537113584Ssimokawa u_int32_t ld0; 2538113584Ssimokawa int slen; 2539113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2540113584Ssimokawa int i; 2541113584Ssimokawa#endif 2542103285Sikob 2543113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2544113584Ssimokawa#if 0 2545113584Ssimokawa printf("ld0: x%08x\n", ld0); 2546113584Ssimokawa#endif 2547113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2548113584Ssimokawa switch (fp0->mode.common.tcode) { 2549113584Ssimokawa case FWTCODE_RREQQ: 2550113584Ssimokawa case FWTCODE_WRES: 2551113584Ssimokawa case FWTCODE_WREQQ: 2552113584Ssimokawa case FWTCODE_RRESQ: 2553113584Ssimokawa case FWOHCITCODE_PHY: 2554113584Ssimokawa slen = 12; 2555113584Ssimokawa break; 2556113584Ssimokawa case FWTCODE_RREQB: 2557113584Ssimokawa case FWTCODE_WREQB: 2558113584Ssimokawa case FWTCODE_LREQ: 2559113584Ssimokawa case FWTCODE_RRESB: 2560113584Ssimokawa case FWTCODE_LRES: 2561113584Ssimokawa slen = 16; 2562113584Ssimokawa break; 2563113584Ssimokawa default: 2564113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2565113584Ssimokawa return(0); 2566103285Sikob } 2567113584Ssimokawa if (slen > len) { 2568113584Ssimokawa if (firewire_debug) 2569113584Ssimokawa printf("splitted header\n"); 2570113584Ssimokawa return(-slen); 2571103285Sikob } 2572113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2573113584Ssimokawa for(i = 0; i < slen/4; i ++) 2574113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2575113584Ssimokawa#endif 2576113584Ssimokawa return(slen); 2577103285Sikob} 2578103285Sikob 2579113584Ssimokawa#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2580103285Sikobstatic int 2581113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2582103285Sikob{ 2583113584Ssimokawa int r; 2584103285Sikob 2585103285Sikob switch(fp->mode.common.tcode){ 2586103285Sikob case FWTCODE_RREQQ: 2587110798Ssimokawa r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2588110798Ssimokawa break; 2589103285Sikob case FWTCODE_WRES: 2590110798Ssimokawa r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2591110798Ssimokawa break; 2592103285Sikob case FWTCODE_WREQQ: 2593110798Ssimokawa r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2594110798Ssimokawa break; 2595103285Sikob case FWTCODE_RREQB: 2596110798Ssimokawa r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2597110798Ssimokawa break; 2598103285Sikob case FWTCODE_RRESQ: 2599110798Ssimokawa r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2600110798Ssimokawa break; 2601103285Sikob case FWTCODE_WREQB: 2602110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2603103285Sikob + sizeof(u_int32_t); 2604110798Ssimokawa break; 2605103285Sikob case FWTCODE_LREQ: 2606110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2607103285Sikob + sizeof(u_int32_t); 2608110798Ssimokawa break; 2609103285Sikob case FWTCODE_RRESB: 2610110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2611103285Sikob + sizeof(u_int32_t); 2612110798Ssimokawa break; 2613103285Sikob case FWTCODE_LRES: 2614110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2615103285Sikob + sizeof(u_int32_t); 2616110798Ssimokawa break; 2617103285Sikob case FWOHCITCODE_PHY: 2618110798Ssimokawa r = 16; 2619110798Ssimokawa break; 2620110798Ssimokawa default: 2621110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2622110798Ssimokawa fp->mode.common.tcode); 2623110798Ssimokawa r = 0; 2624103285Sikob } 2625110798Ssimokawa if (r > dbch->xferq.psize) { 2626110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2627110798Ssimokawa /* panic ? */ 2628110798Ssimokawa } 2629110798Ssimokawa return r; 2630103285Sikob} 2631103285Sikob 2632106790Ssimokawastatic void 2633113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2634113584Ssimokawa{ 2635113584Ssimokawa volatile struct fwohcidb *db = &db_tr->db[0]; 2636113584Ssimokawa 2637113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2638113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2639113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2640113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2641113584Ssimokawa dbch->bottom = db_tr; 2642113584Ssimokawa} 2643113584Ssimokawa 2644113584Ssimokawastatic void 2645106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2646103285Sikob{ 2647103285Sikob struct fwohcidb_tr *db_tr; 2648113584Ssimokawa struct iovec vec[2]; 2649113584Ssimokawa struct fw_pkt pktbuf; 2650113584Ssimokawa int nvec; 2651103285Sikob struct fw_pkt *fp; 2652103285Sikob u_int8_t *ld; 2653113584Ssimokawa u_int32_t stat, off, status; 2654103285Sikob u_int spd; 2655113584Ssimokawa int len, plen, hlen, pcnt, offset; 2656103285Sikob int s; 2657103285Sikob caddr_t buf; 2658103285Sikob int resCount; 2659103285Sikob 2660103285Sikob if(&sc->arrq == dbch){ 2661103285Sikob off = OHCI_ARQOFF; 2662103285Sikob }else if(&sc->arrs == dbch){ 2663103285Sikob off = OHCI_ARSOFF; 2664103285Sikob }else{ 2665103285Sikob return; 2666103285Sikob } 2667103285Sikob 2668103285Sikob s = splfw(); 2669103285Sikob db_tr = dbch->top; 2670103285Sikob pcnt = 0; 2671103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2672113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2673113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2674113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2675113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2676113584Ssimokawa#if 0 2677113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2678113584Ssimokawa#endif 2679113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2680113584Ssimokawa len = dbch->xferq.psize - resCount; 2681113584Ssimokawa ld = (u_int8_t *)db_tr->buf; 2682113584Ssimokawa if (dbch->pdb_tr == NULL) { 2683113584Ssimokawa len -= dbch->buf_offset; 2684113584Ssimokawa ld += dbch->buf_offset; 2685113584Ssimokawa } 2686113584Ssimokawa if (len > 0) 2687113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2688113584Ssimokawa BUS_DMASYNC_POSTREAD); 2689103285Sikob while (len > 0 ) { 2690106789Ssimokawa if (count >= 0 && count-- == 0) 2691106789Ssimokawa goto out; 2692113584Ssimokawa if(dbch->pdb_tr != NULL){ 2693113584Ssimokawa /* we have a fragment in previous buffer */ 2694113584Ssimokawa int rlen; 2695103285Sikob 2696113584Ssimokawa offset = dbch->buf_offset; 2697113584Ssimokawa if (offset < 0) 2698113584Ssimokawa offset = - offset; 2699113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2700113584Ssimokawa rlen = dbch->xferq.psize - offset; 2701113584Ssimokawa if (firewire_debug) 2702113584Ssimokawa printf("rlen=%d, offset=%d\n", 2703113584Ssimokawa rlen, dbch->buf_offset); 2704113584Ssimokawa if (dbch->buf_offset < 0) { 2705113584Ssimokawa /* splitted in header, pull up */ 2706113584Ssimokawa char *p; 2707113584Ssimokawa 2708113584Ssimokawa p = (char *)&pktbuf; 2709113584Ssimokawa bcopy(buf, p, rlen); 2710113584Ssimokawa p += rlen; 2711113584Ssimokawa /* this must be too long but harmless */ 2712113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2713113584Ssimokawa if (rlen < 0) 2714113584Ssimokawa printf("why rlen < 0\n"); 2715113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2716103285Sikob ld += rlen; 2717103285Sikob len -= rlen; 2718113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2719113584Ssimokawa if (hlen < 0) { 2720113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2721113584Ssimokawa } 2722113584Ssimokawa offset = sizeof(pktbuf); 2723113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2724113584Ssimokawa vec[0].iov_len = offset; 2725113584Ssimokawa } else { 2726113584Ssimokawa /* splitted in payload */ 2727113584Ssimokawa offset = rlen; 2728113584Ssimokawa vec[0].iov_base = buf; 2729113584Ssimokawa vec[0].iov_len = rlen; 2730103285Sikob } 2731113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2732113584Ssimokawa nvec = 1; 2733113584Ssimokawa } else { 2734113584Ssimokawa /* no fragment in previous buffer */ 2735103285Sikob fp=(struct fw_pkt *)ld; 2736113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2737113584Ssimokawa if (hlen == 0) 2738113584Ssimokawa /* XXX need reset */ 2739103285Sikob goto out; 2740113584Ssimokawa if (hlen < 0) { 2741113584Ssimokawa dbch->pdb_tr = db_tr; 2742113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2743113584Ssimokawa /* sanity check */ 2744113584Ssimokawa if (resCount != 0) 2745113584Ssimokawa printf("resCount != 0 !?\n"); 2746113584Ssimokawa goto out; 2747103285Sikob } 2748113584Ssimokawa offset = 0; 2749113584Ssimokawa nvec = 0; 2750113584Ssimokawa } 2751113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2752113584Ssimokawa if (plen < 0) { 2753113584Ssimokawa /* minimum header size + trailer 2754113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2755113584Ssimokawa printf("plen is negative! offset=%d\n", offset); 2756113584Ssimokawa goto out; 2757113584Ssimokawa } 2758113584Ssimokawa if (plen > 0) { 2759113584Ssimokawa len -= plen; 2760113584Ssimokawa if (len < 0) { 2761113584Ssimokawa dbch->pdb_tr = db_tr; 2762113584Ssimokawa if (firewire_debug) 2763113584Ssimokawa printf("splitted payload\n"); 2764113584Ssimokawa /* sanity check */ 2765113584Ssimokawa if (resCount != 0) 2766113584Ssimokawa printf("resCount != 0 !?\n"); 2767113584Ssimokawa goto out; 2768103285Sikob } 2769113584Ssimokawa vec[nvec].iov_base = ld; 2770113584Ssimokawa vec[nvec].iov_len = plen; 2771113584Ssimokawa nvec ++; 2772103285Sikob ld += plen; 2773103285Sikob } 2774113584Ssimokawa dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2775113584Ssimokawa if (nvec == 0) 2776113584Ssimokawa printf("nvec == 0\n"); 2777113584Ssimokawa 2778103285Sikob/* DMA result-code will be written at the tail of packet */ 2779113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2780113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2781113584Ssimokawa#else 2782113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2783113584Ssimokawa#endif 2784110577Ssimokawa#if 0 2785113584Ssimokawa printf("plen: %d, stat %x\n", plen ,stat); 2786103285Sikob#endif 2787113584Ssimokawa spd = (stat >> 5) & 0x3; 2788113584Ssimokawa stat &= 0x1f; 2789113584Ssimokawa switch(stat){ 2790113584Ssimokawa case FWOHCIEV_ACKPEND: 2791113584Ssimokawa#if 0 2792113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2793113584Ssimokawa#endif 2794113584Ssimokawa /* fall through */ 2795113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2796113584Ssimokawa if ((vec[nvec-1].iov_len -= 2797113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2798113584Ssimokawa nvec--; 2799113584Ssimokawa fw_rcv(&sc->fc, vec, nvec, 0, spd); 2800103285Sikob break; 2801113584Ssimokawa case FWOHCIEV_BUSRST: 2802113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2803113584Ssimokawa printf("got BUSRST packet!?\n"); 2804113584Ssimokawa break; 2805113584Ssimokawa default: 2806113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2807103285Sikob#if 0 /* XXX */ 2808113584Ssimokawa goto out; 2809103285Sikob#endif 2810113584Ssimokawa break; 2811103285Sikob } 2812103285Sikob pcnt ++; 2813113584Ssimokawa if (dbch->pdb_tr != NULL) { 2814113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2815113584Ssimokawa dbch->pdb_tr = NULL; 2816113584Ssimokawa } 2817113584Ssimokawa 2818113584Ssimokawa } 2819103285Sikobout: 2820103285Sikob if (resCount == 0) { 2821103285Sikob /* done on this buffer */ 2822113584Ssimokawa if (dbch->pdb_tr == NULL) { 2823113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2824113584Ssimokawa dbch->buf_offset = 0; 2825113584Ssimokawa } else 2826113584Ssimokawa if (dbch->pdb_tr != db_tr) 2827113584Ssimokawa printf("pdb_tr != db_tr\n"); 2828103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2829113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2830113584Ssimokawa >> OHCI_STATUS_SHIFT; 2831113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2832113584Ssimokawa & OHCI_COUNT_MASK; 2833113584Ssimokawa /* XXX check buffer overrun */ 2834103285Sikob dbch->top = db_tr; 2835103285Sikob } else { 2836103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2837103285Sikob break; 2838103285Sikob } 2839103285Sikob /* XXX make sure DMA is not dead */ 2840103285Sikob } 2841103285Sikob#if 0 2842103285Sikob if (pcnt < 1) 2843103285Sikob printf("fwohci_arcv: no packets\n"); 2844103285Sikob#endif 2845103285Sikob splx(s); 2846103285Sikob} 2847