fwohci.c revision 112523
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 112523 2003-03-24 04:06:21Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45109890Ssimokawa#include <sys/proc.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/types.h> 48103285Sikob#include <sys/mbuf.h> 49103285Sikob#include <sys/mman.h> 50103285Sikob#include <sys/socket.h> 51103285Sikob#include <sys/socketvar.h> 52103285Sikob#include <sys/signalvar.h> 53103285Sikob#include <sys/malloc.h> 54103285Sikob#include <sys/uio.h> 55103285Sikob#include <sys/sockio.h> 56103285Sikob#include <sys/bus.h> 57103285Sikob#include <sys/kernel.h> 58103285Sikob#include <sys/conf.h> 59103285Sikob 60103285Sikob#include <machine/bus.h> 61103285Sikob#include <machine/resource.h> 62103285Sikob#include <sys/rman.h> 63103285Sikob 64103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65103285Sikob#include <machine/clock.h> 66103285Sikob#include <pci/pcivar.h> 67103285Sikob#include <pci/pcireg.h> 68103285Sikob#include <vm/vm.h> 69103285Sikob#include <vm/vm_extern.h> 70103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 71103285Sikob 72103285Sikob#include <dev/firewire/firewire.h> 73103285Sikob#include <dev/firewire/firewirereg.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77103285Sikob 78109179Ssimokawa#include <dev/firewire/iec68113.h> 79109179Ssimokawa 80103285Sikob#undef OHCI_DEBUG 81106802Ssimokawa 82103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83103285Sikob "STOR","LOAD","NOP ","STOP",}; 84103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85103285Sikob "UNDEF","REG","SYS","DEV"}; 86103285Sikobchar fwohcicode[32][0x20]={ 87103285Sikob "No stat","Undef","long","miss Ack err", 88103285Sikob "underrun","overrun","desc err", "data read err", 89103285Sikob "data write err","bus reset","timeout","tcode err", 90103285Sikob "Undef","Undef","unknown event","flushed", 91103285Sikob "Undef","ack complete","ack pend","Undef", 92103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 93103285Sikob "Undef","Undef","Undef","ack tardy", 94103285Sikob "Undef","ack data_err","ack type_err",""}; 95103285Sikob#define MAX_SPEED 2 96103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 97103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99103285Sikob 100103285Sikobstatic struct tcode_info tinfo[] = { 101103285Sikob/* hdr_len block flag*/ 102103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104103285Sikob/* 2 WRES */ {12, FWTI_RES}, 105103285Sikob/* 3 XXX */ { 0, 0}, 106103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 109103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110103285Sikob/* 8 CYCS */ { 0, 0}, 111103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114103285Sikob/* c XXX */ { 0, 0}, 115103285Sikob/* d XXX */ { 0, 0}, 116103285Sikob/* e PHY */ {12, FWTI_REQ}, 117103285Sikob/* f XXX */ { 0, 0} 118103285Sikob}; 119103285Sikob 120103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 121103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 122103285Sikob 123103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125103285Sikob 126103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 127103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 128103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 129106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 134103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 146103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 149103285Sikobstatic void fwohci_timeout __P((void *)); 150103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 151103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 152103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 155103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161103285Sikob 162103285Sikob/* 163103285Sikob * memory allocated for DMA programs 164103285Sikob */ 165103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166103285Sikob 167103285Sikob/* #define NDB 1024 */ 168103285Sikob#define NDB FWMAXQUEUE 169103285Sikob#define NDVDB (DVBUF * NDB) 170103285Sikob 171103285Sikob#define OHCI_VERSION 0x00 172112523Ssimokawa#define OHCI_ATRETRY 0x08 173103285Sikob#define OHCI_CROMHDR 0x18 174103285Sikob#define OHCI_BUS_OPT 0x20 175103285Sikob#define OHCI_BUSIRMC (1 << 31) 176103285Sikob#define OHCI_BUSCMC (1 << 30) 177103285Sikob#define OHCI_BUSISC (1 << 29) 178103285Sikob#define OHCI_BUSBMC (1 << 28) 179103285Sikob#define OHCI_BUSPMC (1 << 27) 180103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 181103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 182103285Sikob 183103285Sikob#define OHCI_EUID_HI 0x24 184103285Sikob#define OHCI_EUID_LO 0x28 185103285Sikob 186103285Sikob#define OHCI_CROMPTR 0x34 187103285Sikob#define OHCI_HCCCTL 0x50 188103285Sikob#define OHCI_HCCCTLCLR 0x54 189103285Sikob#define OHCI_AREQHI 0x100 190103285Sikob#define OHCI_AREQHICLR 0x104 191103285Sikob#define OHCI_AREQLO 0x108 192103285Sikob#define OHCI_AREQLOCLR 0x10c 193103285Sikob#define OHCI_PREQHI 0x110 194103285Sikob#define OHCI_PREQHICLR 0x114 195103285Sikob#define OHCI_PREQLO 0x118 196103285Sikob#define OHCI_PREQLOCLR 0x11c 197103285Sikob#define OHCI_PREQUPPER 0x120 198103285Sikob 199103285Sikob#define OHCI_SID_BUF 0x64 200103285Sikob#define OHCI_SID_CNT 0x68 201103285Sikob#define OHCI_SID_CNT_MASK 0xffc 202103285Sikob 203103285Sikob#define OHCI_IT_STAT 0x90 204103285Sikob#define OHCI_IT_STATCLR 0x94 205103285Sikob#define OHCI_IT_MASK 0x98 206103285Sikob#define OHCI_IT_MASKCLR 0x9c 207103285Sikob 208103285Sikob#define OHCI_IR_STAT 0xa0 209103285Sikob#define OHCI_IR_STATCLR 0xa4 210103285Sikob#define OHCI_IR_MASK 0xa8 211103285Sikob#define OHCI_IR_MASKCLR 0xac 212103285Sikob 213103285Sikob#define OHCI_LNKCTL 0xe0 214103285Sikob#define OHCI_LNKCTLCLR 0xe4 215103285Sikob 216103285Sikob#define OHCI_PHYACCESS 0xec 217103285Sikob#define OHCI_CYCLETIMER 0xf0 218103285Sikob 219103285Sikob#define OHCI_DMACTL(off) (off) 220103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 221103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 222103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 223103285Sikob 224103285Sikob#define OHCI_ATQOFF 0x180 225103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 226103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 227103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 228103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 229103285Sikob 230103285Sikob#define OHCI_ATSOFF 0x1a0 231103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 232103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 233103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 234103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 235103285Sikob 236103285Sikob#define OHCI_ARQOFF 0x1c0 237103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 238103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 239103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 240103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 241103285Sikob 242103285Sikob#define OHCI_ARSOFF 0x1e0 243103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 244103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 245103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 246103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 247103285Sikob 248103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 249103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 250103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 251103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 252103285Sikob 253103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 254103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 255103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 256103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 257103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 258103285Sikob 259103285Sikobd_ioctl_t fwohci_ioctl; 260103285Sikob 261103285Sikob/* 262103285Sikob * Communication with PHY device 263103285Sikob */ 264106790Ssimokawastatic u_int32_t 265106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 266103285Sikob{ 267103285Sikob u_int32_t fun; 268103285Sikob 269103285Sikob addr &= 0xf; 270103285Sikob data &= 0xff; 271103285Sikob 272103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 273103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 274103285Sikob DELAY(100); 275103285Sikob 276103285Sikob return(fwphy_rddata( sc, addr)); 277103285Sikob} 278103285Sikob 279103285Sikobstatic u_int32_t 280103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 281103285Sikob{ 282103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 283103285Sikob int i; 284103285Sikob u_int32_t bm; 285103285Sikob 286103285Sikob#define OHCI_CSR_DATA 0x0c 287103285Sikob#define OHCI_CSR_COMP 0x10 288103285Sikob#define OHCI_CSR_CONT 0x14 289103285Sikob#define OHCI_BUS_MANAGER_ID 0 290103285Sikob 291103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 292103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 293103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 294103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 295109280Ssimokawa DELAY(10); 296103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 297107653Ssimokawa if((bm & 0x3f) == 0x3f) 298103285Sikob bm = node; 299107653Ssimokawa if (bootverbose) 300107653Ssimokawa device_printf(sc->fc.dev, 301107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 302103285Sikob 303103285Sikob return(bm); 304103285Sikob} 305103285Sikob 306106790Ssimokawastatic u_int32_t 307106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 308103285Sikob{ 309108500Ssimokawa u_int32_t fun, stat; 310108500Ssimokawa u_int i, retry = 0; 311103285Sikob 312103285Sikob addr &= 0xf; 313108500Ssimokawa#define MAX_RETRY 100 314108500Ssimokawaagain: 315108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 316103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 317103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 318108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 319103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 320103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 321103285Sikob break; 322109280Ssimokawa DELAY(100); 323103285Sikob } 324108500Ssimokawa if(i >= MAX_RETRY) { 325109280Ssimokawa if (bootverbose) 326109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 327108527Ssimokawa if (++retry < MAX_RETRY) { 328109280Ssimokawa DELAY(100); 329108527Ssimokawa goto again; 330108527Ssimokawa } 331108500Ssimokawa } 332108500Ssimokawa /* Make sure that SCLK is started */ 333108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 334108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 335108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 336109280Ssimokawa if (bootverbose) 337109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 338108500Ssimokawa if (++retry < MAX_RETRY) { 339109280Ssimokawa DELAY(100); 340108500Ssimokawa goto again; 341108500Ssimokawa } 342108500Ssimokawa } 343108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 344108500Ssimokawa device_printf(sc->fc.dev, 345108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 346108500Ssimokawa#undef MAX_RETRY 347103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 348103285Sikob} 349103285Sikob/* Device specific ioctl. */ 350103285Sikobint 351103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 352103285Sikob{ 353103285Sikob struct firewire_softc *sc; 354103285Sikob struct fwohci_softc *fc; 355103285Sikob int unit = DEV2UNIT(dev); 356103285Sikob int err = 0; 357103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 358103285Sikob u_int32_t *dmach = (u_int32_t *) data; 359103285Sikob 360103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 361103285Sikob if(sc == NULL){ 362103285Sikob return(EINVAL); 363103285Sikob } 364103285Sikob fc = (struct fwohci_softc *)sc->fc; 365103285Sikob 366103285Sikob if (!data) 367103285Sikob return(EINVAL); 368103285Sikob 369103285Sikob switch (cmd) { 370103285Sikob case FWOHCI_WRREG: 371103285Sikob#define OHCI_MAX_REG 0x800 372103285Sikob if(reg->addr <= OHCI_MAX_REG){ 373103285Sikob OWRITE(fc, reg->addr, reg->data); 374103285Sikob reg->data = OREAD(fc, reg->addr); 375103285Sikob }else{ 376103285Sikob err = EINVAL; 377103285Sikob } 378103285Sikob break; 379103285Sikob case FWOHCI_RDREG: 380103285Sikob if(reg->addr <= OHCI_MAX_REG){ 381103285Sikob reg->data = OREAD(fc, reg->addr); 382103285Sikob }else{ 383103285Sikob err = EINVAL; 384103285Sikob } 385103285Sikob break; 386103285Sikob/* Read DMA descriptors for debug */ 387103285Sikob case DUMPDMA: 388103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 389103285Sikob dump_dma(fc, *dmach); 390103285Sikob dump_db(fc, *dmach); 391103285Sikob }else{ 392103285Sikob err = EINVAL; 393103285Sikob } 394103285Sikob break; 395103285Sikob default: 396103285Sikob break; 397103285Sikob } 398103285Sikob return err; 399103285Sikob} 400106790Ssimokawa 401108530Ssimokawastatic int 402108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 403103285Sikob{ 404108530Ssimokawa u_int32_t reg, reg2; 405108530Ssimokawa int e1394a = 1; 406108530Ssimokawa/* 407108530Ssimokawa * probe PHY parameters 408108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 409108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 410108530Ssimokawa * number of port supported by core-logic. 411108530Ssimokawa * It is not actually available port on your PC . 412108530Ssimokawa */ 413108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 414108530Ssimokawa#if 0 415108530Ssimokawa /* XXX wait for SCLK. */ 416108530Ssimokawa DELAY(100000); 417108530Ssimokawa#endif 418108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 419108530Ssimokawa 420108530Ssimokawa if((reg >> 5) != 7 ){ 421108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 422108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 423108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 424108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 425108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 426108530Ssimokawa sc->fc.speed, MAX_SPEED); 427108530Ssimokawa sc->fc.speed = MAX_SPEED; 428108530Ssimokawa } 429108530Ssimokawa device_printf(dev, 430108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 431108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 432108530Ssimokawa }else{ 433108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 434108530Ssimokawa sc->fc.mode |= FWPHYASYST; 435108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 436108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 437108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 438108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 439108530Ssimokawa sc->fc.speed, MAX_SPEED); 440108530Ssimokawa sc->fc.speed = MAX_SPEED; 441108530Ssimokawa } 442108530Ssimokawa device_printf(dev, 443108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 444108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 445108530Ssimokawa 446108530Ssimokawa /* check programPhyEnable */ 447108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 448108530Ssimokawa#if 0 449108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 450108530Ssimokawa#else /* XXX force to enable 1394a */ 451108530Ssimokawa if (e1394a) { 452108530Ssimokawa#endif 453108530Ssimokawa if (bootverbose) 454108530Ssimokawa device_printf(dev, 455108530Ssimokawa "Enable 1394a Enhancements\n"); 456108530Ssimokawa /* enable EAA EMC */ 457108530Ssimokawa reg2 |= 0x03; 458108530Ssimokawa /* set aPhyEnhanceEnable */ 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 460108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 461108530Ssimokawa } else { 462108530Ssimokawa /* for safe */ 463108530Ssimokawa reg2 &= ~0x83; 464108530Ssimokawa } 465108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 466108530Ssimokawa } 467108530Ssimokawa 468108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 469108530Ssimokawa if((reg >> 5) == 7 ){ 470108530Ssimokawa reg = fwphy_rddata(sc, 4); 471108530Ssimokawa reg |= 1 << 6; 472108530Ssimokawa fwphy_wrdata(sc, 4, reg); 473108530Ssimokawa reg = fwphy_rddata(sc, 4); 474108530Ssimokawa } 475108530Ssimokawa return 0; 476108530Ssimokawa} 477108530Ssimokawa 478108530Ssimokawa 479108530Ssimokawavoid 480108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 481108530Ssimokawa{ 482108701Ssimokawa int i, max_rec, speed; 483103285Sikob u_int32_t reg, reg2; 484103285Sikob struct fwohcidb_tr *db_tr; 485103285Sikob 486108701Ssimokawa /* Disable interrupt */ 487108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 488108530Ssimokawa 489108701Ssimokawa /* Now stopping all DMA channel */ 490108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 494108530Ssimokawa 495108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 496108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 497108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 499108530Ssimokawa } 500108530Ssimokawa 501108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 502108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 503108530Ssimokawa if (bootverbose) 504108530Ssimokawa device_printf(dev, "resetting OHCI..."); 505108530Ssimokawa i = 0; 506108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 507108530Ssimokawa if (i++ > 100) break; 508108530Ssimokawa DELAY(1000); 509108530Ssimokawa } 510108530Ssimokawa if (bootverbose) 511108530Ssimokawa printf("done (loop=%d)\n", i); 512108530Ssimokawa 513108701Ssimokawa /* Probe phy */ 514108701Ssimokawa fwohci_probe_phy(sc, dev); 515108701Ssimokawa 516108701Ssimokawa /* Probe link */ 517108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 518108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 519108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 520108701Ssimokawa speed = (reg & 0x00000007); 521108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 522108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 523108701Ssimokawa /* XXX fix max_rec */ 524108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 525108701Ssimokawa if (max_rec != sc->fc.maxrec) { 526108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 527108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 528108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 529108701Ssimokawa } 530108530Ssimokawa if (bootverbose) 531108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 532108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 533108530Ssimokawa 534108701Ssimokawa /* Initialize registers */ 535108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 536108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 538108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 539108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 540108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 541108701Ssimokawa fw_busreset(&sc->fc); 542108530Ssimokawa 543108701Ssimokawa /* Enable link */ 544108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 545108642Ssimokawa 546108701Ssimokawa /* Force to start async RX DMA */ 547108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 548108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 550108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 551108530Ssimokawa 552108701Ssimokawa /* Initialize async TX */ 553108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 555108701Ssimokawa /* AT Retries */ 556108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 557108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 560108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 561108530Ssimokawa db_tr->xfer = NULL; 562108530Ssimokawa } 563108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 564108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 565108530Ssimokawa db_tr->xfer = NULL; 566108530Ssimokawa } 567108530Ssimokawa 568108701Ssimokawa 569108701Ssimokawa /* Enable interrupt */ 570108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 571108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 572108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 573108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 574108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 575108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 576108530Ssimokawa 577108530Ssimokawa} 578108530Ssimokawa 579108530Ssimokawaint 580108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 581108530Ssimokawa{ 582108530Ssimokawa int i; 583108530Ssimokawa u_int32_t reg; 584109814Ssimokawa u_int8_t ui[8]; 585108530Ssimokawa 586103285Sikob reg = OREAD(sc, OHCI_VERSION); 587103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 588103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 589103285Sikob 590110045Ssimokawa/* Available Isochrounous DMA channel probe */ 591110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 592110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 593110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 594110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 595110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 596110045Ssimokawa for (i = 0; i < 0x20; i++) 597110045Ssimokawa if ((reg & (1 << i)) == 0) 598110045Ssimokawa break; 599103285Sikob sc->fc.nisodma = i; 600103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 601103285Sikob 602103285Sikob sc->fc.arq = &sc->arrq.xferq; 603103285Sikob sc->fc.ars = &sc->arrs.xferq; 604103285Sikob sc->fc.atq = &sc->atrq.xferq; 605103285Sikob sc->fc.ats = &sc->atrs.xferq; 606103285Sikob 607103285Sikob sc->arrq.xferq.start = NULL; 608103285Sikob sc->arrs.xferq.start = NULL; 609103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 610103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 611103285Sikob 612103285Sikob sc->arrq.xferq.drain = NULL; 613103285Sikob sc->arrs.xferq.drain = NULL; 614103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 615103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 616103285Sikob 617103285Sikob sc->arrq.ndesc = 1; 618103285Sikob sc->arrs.ndesc = 1; 619110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 620110593Ssimokawa sc->atrs.ndesc = 2; 621103285Sikob 622103285Sikob sc->arrq.ndb = NDB; 623103285Sikob sc->arrs.ndb = NDB / 2; 624103285Sikob sc->atrq.ndb = NDB; 625103285Sikob sc->atrs.ndb = NDB / 2; 626103285Sikob 627103285Sikob sc->arrq.dummy = NULL; 628103285Sikob sc->arrs.dummy = NULL; 629103285Sikob sc->atrq.dummy = NULL; 630103285Sikob sc->atrs.dummy = NULL; 631103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 632103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 633103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 634103285Sikob sc->it[i].ndb = 0; 635103285Sikob sc->ir[i].ndb = 0; 636103285Sikob } 637103285Sikob 638103285Sikob sc->fc.tcode = tinfo; 639103285Sikob 640110195Ssimokawa sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 641103285Sikob 642103285Sikob if(sc->cromptr == NULL){ 643108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 644103285Sikob return ENOMEM; 645103285Sikob } 646103285Sikob sc->fc.dev = dev; 647103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 648103285Sikob 649103285Sikob sc->fc.config_rom[1] = 0x31333934; 650103285Sikob sc->fc.config_rom[2] = 0xf000a002; 651103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 652103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 653103285Sikob sc->fc.config_rom[5] = 0; 654103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 655103285Sikob 656103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 657103285Sikob 658103285Sikob 659103285Sikob/* SID recieve buffer must allign 2^11 */ 660103285Sikob#define OHCI_SIDSIZE (1 << 11) 661110195Ssimokawa sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 662108527Ssimokawa if (sc->fc.sid_buf == NULL) { 663108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 664108527Ssimokawa return ENOMEM; 665108527Ssimokawa } 666110016Ssimokawa if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 667109736Ssimokawa device_printf(dev, "sid_buf(%p) not aligned.\n", 668109736Ssimokawa sc->fc.sid_buf); 669109736Ssimokawa return ENOMEM; 670109736Ssimokawa } 671108530Ssimokawa 672103285Sikob fwohci_db_init(&sc->arrq); 673108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 674108527Ssimokawa return ENOMEM; 675108527Ssimokawa 676103285Sikob fwohci_db_init(&sc->arrs); 677108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 678108527Ssimokawa return ENOMEM; 679103285Sikob 680103285Sikob fwohci_db_init(&sc->atrq); 681108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 682108527Ssimokawa return ENOMEM; 683108527Ssimokawa 684103285Sikob fwohci_db_init(&sc->atrs); 685108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 686108527Ssimokawa return ENOMEM; 687103285Sikob 688109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 689109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 690109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 691109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 692103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 693109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 694109814Ssimokawa 695103285Sikob sc->fc.ioctl = fwohci_ioctl; 696103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 697103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 698103285Sikob sc->fc.ibr = fwohci_ibr; 699103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 700103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 701103285Sikob 702103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 703103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 704103285Sikob sc->fc.irx_post = fwohci_irx_post; 705103285Sikob sc->fc.itx_post = NULL; 706103285Sikob sc->fc.timeout = fwohci_timeout; 707103285Sikob sc->fc.poll = fwohci_poll; 708103285Sikob sc->fc.set_intr = fwohci_set_intr; 709106790Ssimokawa 710108530Ssimokawa fw_init(&sc->fc); 711108530Ssimokawa fwohci_reset(sc, dev); 712103285Sikob 713108530Ssimokawa return 0; 714103285Sikob} 715106790Ssimokawa 716106790Ssimokawavoid 717106790Ssimokawafwohci_timeout(void *arg) 718103285Sikob{ 719103285Sikob struct fwohci_softc *sc; 720103285Sikob 721103285Sikob sc = (struct fwohci_softc *)arg; 722103285Sikob} 723106790Ssimokawa 724106790Ssimokawau_int32_t 725106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 726103285Sikob{ 727103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 728103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 729103285Sikob} 730103285Sikob 731108527Ssimokawaint 732108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 733108527Ssimokawa{ 734108527Ssimokawa int i; 735108527Ssimokawa 736108527Ssimokawa if (sc->fc.sid_buf != NULL) 737110195Ssimokawa free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 738108527Ssimokawa if (sc->cromptr != NULL) 739110195Ssimokawa free((void *)sc->cromptr, M_FW); 740108527Ssimokawa 741108527Ssimokawa fwohci_db_free(&sc->arrq); 742108527Ssimokawa fwohci_db_free(&sc->arrs); 743108527Ssimokawa 744108527Ssimokawa fwohci_db_free(&sc->atrq); 745108527Ssimokawa fwohci_db_free(&sc->atrs); 746108527Ssimokawa 747108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 748108527Ssimokawa fwohci_db_free(&sc->it[i]); 749108527Ssimokawa fwohci_db_free(&sc->ir[i]); 750108527Ssimokawa } 751108527Ssimokawa 752108527Ssimokawa return 0; 753108527Ssimokawa} 754108527Ssimokawa 755108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 756108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 757108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 758108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 759108655Ssimokawa} while (0) 760108655Ssimokawa 761106790Ssimokawastatic void 762106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 763103285Sikob{ 764103285Sikob int i, s; 765103285Sikob int tcode, hdr_len, hdr_off, len; 766103285Sikob int fsegment = -1; 767103285Sikob u_int32_t off; 768103285Sikob struct fw_xfer *xfer; 769103285Sikob struct fw_pkt *fp; 770103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 771103285Sikob struct fwohcidb_tr *db_tr; 772103285Sikob volatile struct fwohcidb *db; 773103285Sikob struct mbuf *m; 774103285Sikob struct tcode_info *info; 775108655Ssimokawa static int maxdesc=0; 776103285Sikob 777103285Sikob if(&sc->atrq == dbch){ 778103285Sikob off = OHCI_ATQOFF; 779103285Sikob }else if(&sc->atrs == dbch){ 780103285Sikob off = OHCI_ATSOFF; 781103285Sikob }else{ 782103285Sikob return; 783103285Sikob } 784103285Sikob 785103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 786103285Sikob return; 787103285Sikob 788103285Sikob s = splfw(); 789103285Sikob db_tr = dbch->top; 790103285Sikobtxloop: 791103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 792103285Sikob if(xfer == NULL){ 793103285Sikob goto kick; 794103285Sikob } 795103285Sikob if(dbch->xferq.queued == 0 ){ 796103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 797103285Sikob } 798103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 799103285Sikob db_tr->xfer = xfer; 800103285Sikob xfer->state = FWXF_START; 801103285Sikob dbch->xferq.packets++; 802103285Sikob 803103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 804103285Sikob tcode = fp->mode.common.tcode; 805103285Sikob 806103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 807103285Sikob info = &tinfo[tcode]; 808103285Sikob hdr_len = hdr_off = info->hdr_len; 809103285Sikob /* fw_asyreq must pass valid send.len */ 810103285Sikob len = xfer->send.len; 811103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 812103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 813103285Sikob } 814112523Ssimokawa /* XXX payload must be network byte order */ 815112523Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) { 816112523Ssimokawa ohcifp->mode.ld[3] = htonl(ohcifp->mode.ld[3]); 817112523Ssimokawa } 818103285Sikob ohcifp->mode.common.spd = xfer->spd; 819103285Sikob if (tcode == FWTCODE_STREAM ){ 820103285Sikob hdr_len = 8; 821103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 822103285Sikob } else if (tcode == FWTCODE_PHY) { 823103285Sikob hdr_len = 12; 824103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 825103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 826103285Sikob ohcifp->mode.common.spd = 0; 827103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 828103285Sikob } else { 829103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 830103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 831103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 832103285Sikob } 833103285Sikob db = &db_tr->db[0]; 834109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 835109892Ssimokawa db->db.desc.reqcount = hdr_len; 836103285Sikob db->db.desc.status = 0; 837103285Sikob/* Specify bound timer of asy. responce */ 838103285Sikob if(&sc->atrs == dbch){ 839103285Sikob db->db.desc.count 840103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 841103285Sikob } 842103285Sikob 843111942Ssimokawaagain: 844103285Sikob db_tr->dbcnt = 2; 845103285Sikob db = &db_tr->db[db_tr->dbcnt]; 846103285Sikob if(len > hdr_off){ 847103285Sikob if (xfer->mbuf == NULL) { 848103285Sikob db->db.desc.addr 849103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 850109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE; 851109892Ssimokawa db->db.desc.reqcount = len - hdr_off; 852103285Sikob db->db.desc.status = 0; 853103285Sikob 854103285Sikob db_tr->dbcnt++; 855103285Sikob } else { 856109890Ssimokawa int mchain=0; 857111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 858108655Ssimokawa for (m = xfer->mbuf; m != NULL; m = m->m_next) { 859108655Ssimokawa if (m->m_len == 0) 860109890Ssimokawa /* unrecoverable error could occur. */ 861108655Ssimokawa continue; 862109890Ssimokawa mchain++; 863109890Ssimokawa if (db_tr->dbcnt >= dbch->ndesc) 864109890Ssimokawa continue; 865103285Sikob db->db.desc.addr 866103285Sikob = vtophys(mtod(m, caddr_t)); 867109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE; 868109892Ssimokawa db->db.desc.reqcount = m->m_len; 869103285Sikob db->db.desc.status = 0; 870103285Sikob db++; 871103285Sikob db_tr->dbcnt++; 872108655Ssimokawa } 873111942Ssimokawa if (mchain > dbch->ndesc - 2) { 874111942Ssimokawa struct mbuf *m_new; 875111942Ssimokawa if (bootverbose) 876111942Ssimokawa device_printf(sc->fc.dev, 877111942Ssimokawa "too long mbuf chain(%d)\n", 878111942Ssimokawa mchain); 879111942Ssimokawa m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 880111942Ssimokawa if (m_new != NULL) { 881111942Ssimokawa m_copydata(xfer->mbuf, 0, 882111942Ssimokawa xfer->mbuf->m_pkthdr.len, 883111942Ssimokawa mtod(m_new, caddr_t)); 884111942Ssimokawa m_new->m_pkthdr.len = m_new->m_len = 885111942Ssimokawa xfer->mbuf->m_pkthdr.len; 886111942Ssimokawa m_freem(xfer->mbuf); 887111942Ssimokawa xfer->mbuf = m_new; 888111942Ssimokawa goto again; 889111942Ssimokawa } 890111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 891111942Ssimokawa } 892103285Sikob } 893103285Sikob } 894108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 895108655Ssimokawa maxdesc = db_tr->dbcnt; 896108655Ssimokawa if (bootverbose) 897108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 898108655Ssimokawa } 899103285Sikob /* last db */ 900103285Sikob LAST_DB(db_tr, db); 901109892Ssimokawa db->db.desc.control |= OHCI_OUTPUT_LAST 902103285Sikob | OHCI_INTERRUPT_ALWAYS 903103285Sikob | OHCI_BRANCH_ALWAYS; 904103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 905103285Sikob 906103285Sikob if(fsegment == -1 ) 907103285Sikob fsegment = db_tr->dbcnt; 908103285Sikob if (dbch->pdb_tr != NULL) { 909103285Sikob LAST_DB(dbch->pdb_tr, db); 910103285Sikob db->db.desc.depend |= db_tr->dbcnt; 911103285Sikob } 912103285Sikob dbch->pdb_tr = db_tr; 913103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 914103285Sikob if(db_tr != dbch->bottom){ 915103285Sikob goto txloop; 916103285Sikob } else { 917107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 918103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 919103285Sikob } 920103285Sikobkick: 921103285Sikob /* kick asy q */ 922103285Sikob 923103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 924103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 925103285Sikob } else { 926107653Ssimokawa if (bootverbose) 927107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 928103285Sikob OREAD(sc, OHCI_DMACTL(off))); 929103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 930103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 931103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 932103285Sikob } 933106790Ssimokawa 934103285Sikob dbch->top = db_tr; 935103285Sikob splx(s); 936103285Sikob return; 937103285Sikob} 938106790Ssimokawa 939106790Ssimokawastatic void 940106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 941103285Sikob{ 942103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 943103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 944103285Sikob return; 945103285Sikob} 946106790Ssimokawa 947106790Ssimokawastatic void 948106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 949103285Sikob{ 950103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 951103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 952103285Sikob return; 953103285Sikob} 954106790Ssimokawa 955106790Ssimokawastatic void 956106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 957103285Sikob{ 958103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 959103285Sikob fwohci_start( sc, &(sc->atrq)); 960103285Sikob return; 961103285Sikob} 962106790Ssimokawa 963106790Ssimokawastatic void 964106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 965103285Sikob{ 966103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 967103285Sikob fwohci_start( sc, &(sc->atrs)); 968103285Sikob return; 969103285Sikob} 970106790Ssimokawa 971106790Ssimokawavoid 972106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 973103285Sikob{ 974103285Sikob int s, err = 0; 975103285Sikob struct fwohcidb_tr *tr; 976103285Sikob volatile struct fwohcidb *db; 977103285Sikob struct fw_xfer *xfer; 978103285Sikob u_int32_t off; 979103285Sikob u_int stat; 980103285Sikob int packets; 981103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 982103285Sikob if(&sc->atrq == dbch){ 983103285Sikob off = OHCI_ATQOFF; 984103285Sikob }else if(&sc->atrs == dbch){ 985103285Sikob off = OHCI_ATSOFF; 986103285Sikob }else{ 987103285Sikob return; 988103285Sikob } 989103285Sikob s = splfw(); 990103285Sikob tr = dbch->bottom; 991103285Sikob packets = 0; 992103285Sikob while(dbch->xferq.queued > 0){ 993103285Sikob LAST_DB(tr, db); 994103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 995103285Sikob if (fc->status != FWBUSRESET) 996103285Sikob /* maybe out of order?? */ 997103285Sikob goto out; 998103285Sikob } 999103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 1000103285Sikob#ifdef OHCI_DEBUG 1001103285Sikob dump_dma(sc, ch); 1002103285Sikob dump_db(sc, ch); 1003103285Sikob#endif 1004103285Sikob/* Stop DMA */ 1005103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1006103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1007103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1008103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1009103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1010103285Sikob } 1011103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 1012103285Sikob switch(stat){ 1013110577Ssimokawa case FWOHCIEV_ACKPEND: 1014103285Sikob case FWOHCIEV_ACKCOMPL: 1015103285Sikob err = 0; 1016103285Sikob break; 1017103285Sikob case FWOHCIEV_ACKBSA: 1018103285Sikob case FWOHCIEV_ACKBSB: 1019110577Ssimokawa case FWOHCIEV_ACKBSX: 1020103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1021103285Sikob err = EBUSY; 1022103285Sikob break; 1023103285Sikob case FWOHCIEV_FLUSHED: 1024103285Sikob case FWOHCIEV_ACKTARD: 1025103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1026103285Sikob err = EAGAIN; 1027103285Sikob break; 1028103285Sikob case FWOHCIEV_MISSACK: 1029103285Sikob case FWOHCIEV_UNDRRUN: 1030103285Sikob case FWOHCIEV_OVRRUN: 1031103285Sikob case FWOHCIEV_DESCERR: 1032103285Sikob case FWOHCIEV_DTRDERR: 1033103285Sikob case FWOHCIEV_TIMEOUT: 1034103285Sikob case FWOHCIEV_TCODERR: 1035103285Sikob case FWOHCIEV_UNKNOWN: 1036103285Sikob case FWOHCIEV_ACKDERR: 1037103285Sikob case FWOHCIEV_ACKTERR: 1038103285Sikob default: 1039103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1040103285Sikob stat, fwohcicode[stat]); 1041103285Sikob err = EINVAL; 1042103285Sikob break; 1043103285Sikob } 1044110577Ssimokawa if (tr->xfer != NULL) { 1045103285Sikob xfer = tr->xfer; 1046103285Sikob xfer->state = FWXF_SENT; 1047110577Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1048103285Sikob xfer->state = FWXF_BUSY; 1049110577Ssimokawa switch (xfer->act_type) { 1050103285Sikob case FWACT_XFER: 1051103285Sikob xfer->resp = err; 1052110577Ssimokawa if (xfer->retry_req != NULL) 1053103285Sikob xfer->retry_req(xfer); 1054110577Ssimokawa else 1055110577Ssimokawa fw_xfer_done(xfer); 1056103285Sikob break; 1057103285Sikob default: 1058103285Sikob break; 1059103285Sikob } 1060110577Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1061103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1062103285Sikob xfer->state = FWXF_SENTERR; 1063103285Sikob xfer->resp = err; 1064110577Ssimokawa switch (xfer->act_type) { 1065103285Sikob case FWACT_XFER: 1066103285Sikob fw_xfer_done(xfer); 1067103285Sikob break; 1068103285Sikob default: 1069103285Sikob break; 1070103285Sikob } 1071103285Sikob } 1072110577Ssimokawa /* 1073110577Ssimokawa * The watchdog timer takes care of split 1074110577Ssimokawa * transcation timeout for ACKPEND case. 1075110577Ssimokawa */ 1076103285Sikob } 1077110269Ssimokawa dbch->xferq.queued --; 1078103285Sikob tr->xfer = NULL; 1079103285Sikob 1080103285Sikob packets ++; 1081103285Sikob tr = STAILQ_NEXT(tr, link); 1082103285Sikob dbch->bottom = tr; 1083111956Ssimokawa if (dbch->bottom == dbch->top) { 1084111956Ssimokawa /* we reaches the end of context program */ 1085111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1086111956Ssimokawa printf("queued > 0\n"); 1087111956Ssimokawa break; 1088111956Ssimokawa } 1089103285Sikob } 1090103285Sikobout: 1091103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1092103285Sikob printf("make free slot\n"); 1093103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1094103285Sikob fwohci_start(sc, dbch); 1095103285Sikob } 1096103285Sikob splx(s); 1097103285Sikob} 1098106790Ssimokawa 1099106790Ssimokawastatic void 1100106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1101103285Sikob{ 1102110269Ssimokawa int i, s, found=0; 1103103285Sikob struct fwohcidb_tr *tr; 1104103285Sikob 1105103285Sikob if(xfer->state != FWXF_START) return; 1106103285Sikob 1107103285Sikob s = splfw(); 1108103285Sikob tr = dbch->bottom; 1109110269Ssimokawa for (i = 0; i < dbch->xferq.queued; i ++) { 1110103285Sikob if(tr->xfer == xfer){ 1111103285Sikob tr->xfer = NULL; 1112110269Ssimokawa#if 0 1113103285Sikob dbch->xferq.queued --; 1114103285Sikob /* XXX */ 1115103285Sikob if (tr == dbch->bottom) 1116103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1117103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1118103285Sikob printf("fwohci_drain: make slot\n"); 1119103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1120103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1121103285Sikob } 1122110269Ssimokawa#endif 1123110269Ssimokawa found ++; 1124103285Sikob break; 1125103285Sikob } 1126103285Sikob tr = STAILQ_NEXT(tr, link); 1127103285Sikob } 1128103285Sikob splx(s); 1129110269Ssimokawa if (!found) 1130110269Ssimokawa device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1131103285Sikob return; 1132103285Sikob} 1133103285Sikob 1134106790Ssimokawastatic void 1135106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1136103285Sikob{ 1137103285Sikob struct fwohcidb_tr *db_tr; 1138109379Ssimokawa int idb, i; 1139103285Sikob 1140108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1141108527Ssimokawa return; 1142108527Ssimokawa 1143103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1144103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1145103285Sikob idb < dbch->ndb; 1146103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1147108527Ssimokawa if (db_tr->buf != NULL) { 1148110195Ssimokawa free(db_tr->buf, M_FW); 1149108527Ssimokawa db_tr->buf = NULL; 1150108527Ssimokawa } 1151103285Sikob } 1152103285Sikob } 1153103285Sikob dbch->ndb = 0; 1154103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1155109379Ssimokawa for (i = 0; i < dbch->npages; i++) 1156110195Ssimokawa free(dbch->pages[i], M_FW); 1157110195Ssimokawa free(db_tr, M_FW); 1158103285Sikob STAILQ_INIT(&dbch->db_trq); 1159108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1160103285Sikob} 1161106790Ssimokawa 1162106790Ssimokawastatic void 1163106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1164103285Sikob{ 1165103285Sikob int idb; 1166103285Sikob struct fwohcidb_tr *db_tr; 1167109379Ssimokawa int ndbpp, i, j; 1168108642Ssimokawa 1169108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1170108642Ssimokawa goto out; 1171108642Ssimokawa 1172103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1173103285Sikob /* DB entry must start at 16 bytes bounary. */ 1174103285Sikob STAILQ_INIT(&dbch->db_trq); 1175103285Sikob db_tr = (struct fwohcidb_tr *) 1176103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1177110273Ssimokawa M_FW, M_ZERO); 1178103285Sikob if(db_tr == NULL){ 1179109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1180103285Sikob return; 1181103285Sikob } 1182109379Ssimokawa 1183109379Ssimokawa ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1184109379Ssimokawa dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1185109403Ssimokawa if (firewire_debug) 1186109403Ssimokawa printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1187109403Ssimokawa dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1188109379Ssimokawa if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1189109379Ssimokawa printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1190109379Ssimokawa dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1191103285Sikob return; 1192103285Sikob } 1193109379Ssimokawa for (i = 0; i < dbch->npages; i++) { 1194110273Ssimokawa dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1195109379Ssimokawa if (dbch->pages[i] == NULL) { 1196109379Ssimokawa printf("fwohci_db_init: malloc(2) failed\n"); 1197109379Ssimokawa for (j = 0; j < i; j ++) 1198110195Ssimokawa free(dbch->pages[j], M_FW); 1199110195Ssimokawa free(db_tr, M_FW); 1200109379Ssimokawa return; 1201109379Ssimokawa } 1202109379Ssimokawa } 1203103285Sikob /* Attach DB to DMA ch. */ 1204103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1205103285Sikob db_tr->dbcnt = 0; 1206109379Ssimokawa db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1207109379Ssimokawa + dbch->ndesc * (idb % ndbpp); 1208103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1209108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1210108530Ssimokawa dbch->xferq.bnpacket != 0) { 1211108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1212108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1213108530Ssimokawa ].start = (caddr_t)db_tr; 1214108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1215108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1216108530Ssimokawa ].end = (caddr_t)db_tr; 1217103285Sikob } 1218103285Sikob db_tr++; 1219103285Sikob } 1220103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1221103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1222108642Ssimokawaout: 1223108642Ssimokawa dbch->frag.buf = NULL; 1224108642Ssimokawa dbch->frag.len = 0; 1225108642Ssimokawa dbch->frag.plen = 0; 1226108642Ssimokawa dbch->xferq.queued = 0; 1227108642Ssimokawa dbch->pdb_tr = NULL; 1228103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1229103285Sikob dbch->bottom = dbch->top; 1230108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1231103285Sikob} 1232106790Ssimokawa 1233106790Ssimokawastatic int 1234106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1235103285Sikob{ 1236103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1237109890Ssimokawa int dummy; 1238109890Ssimokawa 1239103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1240103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1241103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1242109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1243109890Ssimokawa tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1244103285Sikob fwohci_db_free(&sc->it[dmach]); 1245103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1246103285Sikob return 0; 1247103285Sikob} 1248106790Ssimokawa 1249106790Ssimokawastatic int 1250106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1251103285Sikob{ 1252103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1253109890Ssimokawa int dummy; 1254103285Sikob 1255103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1256103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1257103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1258109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1259109890Ssimokawa tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1260103285Sikob if(sc->ir[dmach].dummy != NULL){ 1261110195Ssimokawa free(sc->ir[dmach].dummy, M_FW); 1262103285Sikob } 1263103285Sikob sc->ir[dmach].dummy = NULL; 1264103285Sikob fwohci_db_free(&sc->ir[dmach]); 1265103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1266103285Sikob return 0; 1267103285Sikob} 1268106790Ssimokawa 1269106790Ssimokawastatic void 1270106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1271103285Sikob{ 1272103285Sikob qld[0] = ntohl(qld[0]); 1273103285Sikob return; 1274103285Sikob} 1275106790Ssimokawa 1276106790Ssimokawastatic int 1277106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1278103285Sikob{ 1279103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1280103285Sikob int err = 0; 1281103285Sikob unsigned short tag, ich; 1282103285Sikob 1283103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1284103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1285103285Sikob 1286103285Sikob#if 0 1287103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1288103285Sikob wakeup(fc->ir[dmach]); 1289103285Sikob return err; 1290103285Sikob } 1291103285Sikob#endif 1292103285Sikob 1293103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1294103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1295103285Sikob sc->ir[dmach].xferq.queued = 0; 1296103285Sikob sc->ir[dmach].ndb = NDB; 1297109379Ssimokawa sc->ir[dmach].xferq.psize = PAGE_SIZE; 1298103285Sikob sc->ir[dmach].ndesc = 1; 1299103285Sikob fwohci_db_init(&sc->ir[dmach]); 1300109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1301109179Ssimokawa return ENOMEM; 1302103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1303103285Sikob } 1304103285Sikob if(err){ 1305103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1306103285Sikob return err; 1307103285Sikob } 1308103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1309103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1310103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1311103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1312103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1313103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1314103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1315103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1316103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1317103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1318103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1319103285Sikob } 1320103285Sikob return err; 1321103285Sikob} 1322106790Ssimokawa 1323106790Ssimokawastatic int 1324106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1325103285Sikob{ 1326103285Sikob int err = 0; 1327103285Sikob int idb, z, i, dmach = 0; 1328103285Sikob u_int32_t off = NULL; 1329103285Sikob struct fwohcidb_tr *db_tr; 1330109892Ssimokawa volatile struct fwohcidb *db; 1331103285Sikob 1332103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1333103285Sikob err = EINVAL; 1334103285Sikob return err; 1335103285Sikob } 1336103285Sikob z = dbch->ndesc; 1337103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1338103285Sikob if( &sc->it[dmach] == dbch){ 1339103285Sikob off = OHCI_ITOFF(dmach); 1340103285Sikob break; 1341103285Sikob } 1342103285Sikob } 1343103285Sikob if(off == NULL){ 1344103285Sikob err = EINVAL; 1345103285Sikob return err; 1346103285Sikob } 1347103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1348103285Sikob return err; 1349103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1350103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1351103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1352103285Sikob } 1353103285Sikob db_tr = dbch->top; 1354103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1355103285Sikob fwohci_add_tx_buf(db_tr, 1356103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1357103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1358103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1359103285Sikob break; 1360103285Sikob } 1361109892Ssimokawa db = db_tr->db; 1362109892Ssimokawa db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1363103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1364103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1365103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1366109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control 1367103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1368109280Ssimokawa /* OHCI 1.1 and above */ 1369109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1370109892Ssimokawa#if 0 1371109892Ssimokawa db[0].db.desc.depend &= ~0xf; 1372109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1373109892Ssimokawa#endif 1374103285Sikob } 1375103285Sikob } 1376103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1377103285Sikob } 1378103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1379103285Sikob return err; 1380103285Sikob} 1381106790Ssimokawa 1382106790Ssimokawastatic int 1383106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1384103285Sikob{ 1385103285Sikob int err = 0; 1386109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1387103285Sikob u_int32_t off = NULL; 1388103285Sikob struct fwohcidb_tr *db_tr; 1389109892Ssimokawa volatile struct fwohcidb *db; 1390103285Sikob 1391103285Sikob z = dbch->ndesc; 1392103285Sikob if(&sc->arrq == dbch){ 1393103285Sikob off = OHCI_ARQOFF; 1394103285Sikob }else if(&sc->arrs == dbch){ 1395103285Sikob off = OHCI_ARSOFF; 1396103285Sikob }else{ 1397103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1398103285Sikob if( &sc->ir[dmach] == dbch){ 1399103285Sikob off = OHCI_IROFF(dmach); 1400103285Sikob break; 1401103285Sikob } 1402103285Sikob } 1403103285Sikob } 1404103285Sikob if(off == NULL){ 1405103285Sikob err = EINVAL; 1406103285Sikob return err; 1407103285Sikob } 1408103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1409103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1410103285Sikob return err; 1411103285Sikob }else{ 1412103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1413103285Sikob err = EBUSY; 1414103285Sikob return err; 1415103285Sikob } 1416103285Sikob } 1417103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1418108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1419103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1420103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1421103285Sikob } 1422103285Sikob db_tr = dbch->top; 1423103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1424103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1425103285Sikob fwohci_add_rx_buf(db_tr, 1426103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1427103285Sikob }else{ 1428103285Sikob fwohci_add_rx_buf(db_tr, 1429103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1430111942Ssimokawa dbch->xferq.bulkxfer[idb 1431111942Ssimokawa / dbch->xferq.bnpacket].buf 1432111942Ssimokawa + dbch->xferq.psize * 1433111942Ssimokawa (idb % dbch->xferq.bnpacket), 1434103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1435103285Sikob } 1436103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1437103285Sikob break; 1438103285Sikob } 1439109892Ssimokawa db = db_tr->db; 1440109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1441109892Ssimokawa db[ldesc].db.desc.depend 1442103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1443103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1444103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1445109892Ssimokawa db[ldesc].db.desc.control 1446103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1447109892Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1448103285Sikob } 1449103285Sikob } 1450103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1451103285Sikob } 1452103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1453103285Sikob dbch->buf_offset = 0; 1454103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1455103285Sikob return err; 1456103285Sikob }else{ 1457103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1458103285Sikob } 1459103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1460103285Sikob return err; 1461103285Sikob} 1462106790Ssimokawa 1463106790Ssimokawastatic int 1464109890Ssimokawafwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1465109890Ssimokawa{ 1466109890Ssimokawa int sec, cycle, cycle_match; 1467109890Ssimokawa 1468109890Ssimokawa cycle = cycle_now & 0x1fff; 1469109890Ssimokawa sec = cycle_now >> 13; 1470109890Ssimokawa#define CYCLE_MOD 0x10 1471109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1472109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1473109890Ssimokawa if (cycle >= 8000) { 1474109890Ssimokawa sec ++; 1475109890Ssimokawa cycle -= 8000; 1476109890Ssimokawa } 1477109890Ssimokawa cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1478109890Ssimokawa if (cycle >= 8000) { 1479109890Ssimokawa sec ++; 1480109890Ssimokawa if (cycle == 8000) 1481109890Ssimokawa cycle = 0; 1482109890Ssimokawa else 1483109890Ssimokawa cycle = CYCLE_MOD; 1484109890Ssimokawa } 1485109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1486109890Ssimokawa 1487109890Ssimokawa return(cycle_match); 1488109890Ssimokawa} 1489109890Ssimokawa 1490109890Ssimokawastatic int 1491106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1492103285Sikob{ 1493103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1494103285Sikob int err = 0; 1495103285Sikob unsigned short tag, ich; 1496103285Sikob struct fwohci_dbch *dbch; 1497109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1498109356Ssimokawa u_int32_t stat; 1499109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1500109890Ssimokawa struct fw_xferq *it; 1501103285Sikob 1502103285Sikob dbch = &sc->it[dmach]; 1503109890Ssimokawa it = &dbch->xferq; 1504109890Ssimokawa 1505109890Ssimokawa tag = (it->flag >> 6) & 3; 1506109890Ssimokawa ich = it->flag & 0x3f; 1507109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1508109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1509103285Sikob dbch->ndesc = 3; 1510103285Sikob fwohci_db_init(dbch); 1511109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1512109179Ssimokawa return ENOMEM; 1513103285Sikob err = fwohci_tx_enable(sc, dbch); 1514103285Sikob } 1515103285Sikob if(err) 1516103285Sikob return err; 1517109890Ssimokawa 1518109892Ssimokawa ldesc = dbch->ndesc - 1; 1519109890Ssimokawa s = splfw(); 1520109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1521109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1522109890Ssimokawa volatile struct fwohcidb *db; 1523109890Ssimokawa 1524109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1525109892Ssimokawa#if 0 1526109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1527109890Ssimokawa db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1528109890Ssimokawa db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1529109890Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1530109890Ssimokawa db[0].db.desc.depend &= ~0xf; 1531109892Ssimokawa#endif 1532109890Ssimokawa if (prev != NULL) { 1533109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1534109892Ssimokawa db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1535109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1536109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1537109890Ssimokawa vtophys(((struct fwohcidb_tr *) 1538109890Ssimokawa (chunk->start))->db) | dbch->ndesc; 1539109892Ssimokawa#else 1540109892Ssimokawa db[0].db.desc.depend |= dbch->ndesc; 1541109892Ssimokawa db[ldesc].db.desc.depend |= dbch->ndesc; 1542109892Ssimokawa#endif 1543103285Sikob } 1544109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1545109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1546109890Ssimokawa prev = chunk; 1547109403Ssimokawa } 1548109890Ssimokawa splx(s); 1549109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1550109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1551109890Ssimokawa return 0; 1552109890Ssimokawa 1553109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1554109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1555109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1556109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1557109890Ssimokawa 1558109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1559109890Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1560109890Ssimokawa (first->start))->db) | dbch->ndesc); 1561109890Ssimokawa if (firewire_debug) 1562109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1563109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1564109890Ssimokawa#if 1 1565109890Ssimokawa /* Don't start until all chunks are buffered */ 1566109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1567109890Ssimokawa goto out; 1568109890Ssimokawa#endif 1569109802Ssimokawa#ifdef FWXFERQ_DV 1570109890Ssimokawa#define CYCLE_OFFSET 1 1571103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1572109802Ssimokawa struct fw_pkt *fp; 1573109802Ssimokawa struct fwohcidb_tr *db_tr; 1574109802Ssimokawa 1575103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1576103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1577109356Ssimokawa dbch->xferq.dvoffset = CYCLE_OFFSET; 1578109179Ssimokawa fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1579103285Sikob } 1580109802Ssimokawa#endif 1581109890Ssimokawa /* Clear cycle match counter bits */ 1582109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1583109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1584109890Ssimokawa 1585109356Ssimokawa /* 2bit second + 13bit cycle */ 1586109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1587109890Ssimokawa cycle_match = fwochi_next_cycle(fc, cycle_now); 1588109890Ssimokawa 1589109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1590109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1591109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1592109403Ssimokawa if (firewire_debug) 1593109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1594109403Ssimokawa cycle_now, cycle_match); 1595109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1596109890Ssimokawa device_printf(sc->fc.dev, 1597109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1598109403Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1599103285Sikob } 1600109890Ssimokawaout: 1601103285Sikob return err; 1602103285Sikob} 1603106790Ssimokawa 1604106790Ssimokawastatic int 1605106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1606103285Sikob{ 1607103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1608109890Ssimokawa int err = 0, s, ldesc; 1609103285Sikob unsigned short tag, ich; 1610109736Ssimokawa u_int32_t stat; 1611109890Ssimokawa struct fwohci_dbch *dbch; 1612109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1613109890Ssimokawa struct fw_xferq *ir; 1614103285Sikob 1615109890Ssimokawa dbch = &sc->ir[dmach]; 1616109890Ssimokawa ir = &dbch->xferq; 1617109890Ssimokawa 1618109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1619109890Ssimokawa tag = (ir->flag >> 6) & 3; 1620109890Ssimokawa ich = ir->flag & 0x3f; 1621108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1622108995Ssimokawa 1623109890Ssimokawa ir->queued = 0; 1624109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1625109890Ssimokawa dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1626110273Ssimokawa M_FW, 0); 1627109890Ssimokawa if (dbch->dummy == NULL) { 1628103285Sikob err = ENOMEM; 1629103285Sikob return err; 1630103285Sikob } 1631109890Ssimokawa dbch->ndesc = 2; 1632109890Ssimokawa fwohci_db_init(dbch); 1633109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1634109179Ssimokawa return ENOMEM; 1635109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1636103285Sikob } 1637103285Sikob if(err) 1638103285Sikob return err; 1639103285Sikob 1640109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1641109890Ssimokawa if (first == NULL) { 1642109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1643109890Ssimokawa return 0; 1644109890Ssimokawa } 1645109890Ssimokawa 1646111892Ssimokawa ldesc = dbch->ndesc - 1; 1647111892Ssimokawa s = splfw(); 1648109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1649109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1650109890Ssimokawa volatile struct fwohcidb *db; 1651109890Ssimokawa 1652111942Ssimokawa#if 1 /* XXX for if_fwe */ 1653111942Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 1654111942Ssimokawa db[ldesc].db.desc.addr = vtophys(chunk->buf); 1655111942Ssimokawa#endif 1656109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1657109890Ssimokawa db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1658109890Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1659109890Ssimokawa if (prev != NULL) { 1660109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1661109892Ssimokawa#if 0 1662109890Ssimokawa db[ldesc].db.desc.depend = 1663109890Ssimokawa vtophys(((struct fwohcidb_tr *) 1664109890Ssimokawa (chunk->start))->db) | dbch->ndesc; 1665109892Ssimokawa#else 1666109892Ssimokawa db[ldesc].db.desc.depend |= dbch->ndesc; 1667109892Ssimokawa#endif 1668103285Sikob } 1669109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1670109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1671109890Ssimokawa prev = chunk; 1672103285Sikob } 1673109890Ssimokawa splx(s); 1674109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1675109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1676109890Ssimokawa return 0; 1677109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1678109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1679109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1680109890Ssimokawa } 1681109890Ssimokawa 1682109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1683109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1684109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1685109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1686109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1687109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1688109890Ssimokawa vtophys(((struct fwohcidb_tr *)(first->start))->db) 1689109890Ssimokawa | dbch->ndesc); 1690109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1691109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1692103285Sikob return err; 1693103285Sikob} 1694106790Ssimokawa 1695106790Ssimokawastatic int 1696106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1697103285Sikob{ 1698103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1699103285Sikob int err = 0; 1700103285Sikob 1701103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1702103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1703103285Sikob return err; 1704103285Sikob }else{ 1705103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1706103285Sikob return err; 1707103285Sikob } 1708103285Sikob} 1709106790Ssimokawa 1710106790Ssimokawaint 1711110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1712103285Sikob{ 1713103285Sikob u_int i; 1714103285Sikob 1715103285Sikob/* Now stopping all DMA channel */ 1716103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1717103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1718103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1719103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1720103285Sikob 1721103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1722103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1723103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1724103285Sikob } 1725103285Sikob 1726103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1727103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1728103285Sikob 1729103285Sikob/* Stop interrupt */ 1730103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1731103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1732103285Sikob | OHCI_INT_PHY_INT 1733103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1734103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1735103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1736103285Sikob | OHCI_INT_PHY_BUS_R); 1737108642Ssimokawa/* XXX Link down? Bus reset? */ 1738103285Sikob return 0; 1739103285Sikob} 1740103285Sikob 1741108642Ssimokawaint 1742108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1743108642Ssimokawa{ 1744108642Ssimokawa int i; 1745108642Ssimokawa 1746108642Ssimokawa fwohci_reset(sc, dev); 1747108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1748108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1749108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1750108642Ssimokawa device_printf(sc->fc.dev, 1751108642Ssimokawa "resume iso receive ch: %d\n", i); 1752108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1753108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1754108642Ssimokawa } 1755108642Ssimokawa } 1756108642Ssimokawa 1757108642Ssimokawa bus_generic_resume(dev); 1758108642Ssimokawa sc->fc.ibr(&sc->fc); 1759108642Ssimokawa return 0; 1760108642Ssimokawa} 1761108642Ssimokawa 1762103285Sikob#define ACK_ALL 1763103285Sikobstatic void 1764106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1765103285Sikob{ 1766103285Sikob u_int32_t irstat, itstat; 1767103285Sikob u_int i; 1768103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1769103285Sikob 1770103285Sikob#ifdef OHCI_DEBUG 1771103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1772103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1773103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1774103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1775103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1776103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1777103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1778103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1779103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1780103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1781103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1782103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1783103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1784103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1785103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1786103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1787103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1788103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1789103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1790103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1791103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1792103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1793103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1794103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1795103285Sikob ); 1796103285Sikob#endif 1797103285Sikob/* Bus reset */ 1798103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1799111074Ssimokawa if (fc->status == FWBUSRESET) 1800111074Ssimokawa goto busresetout; 1801111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1802111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1803111074Ssimokawa 1804103285Sikob device_printf(fc->dev, "BUS reset\n"); 1805103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1806103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1807103285Sikob 1808103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1809103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1810103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1811103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1812103285Sikob 1813103285Sikob#ifndef ACK_ALL 1814103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1815103285Sikob#endif 1816110798Ssimokawa fw_busreset(fc); 1817103285Sikob } 1818111074Ssimokawabusresetout: 1819103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1820103285Sikob#ifndef ACK_ALL 1821103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1822103285Sikob#endif 1823103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1824109280Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 1825103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1826109644Ssimokawa struct fwohci_dbch *dbch; 1827109644Ssimokawa 1828103285Sikob if((irstat & (1 << i)) != 0){ 1829109644Ssimokawa dbch = &sc->ir[i]; 1830109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1831109644Ssimokawa device_printf(sc->fc.dev, 1832109644Ssimokawa "dma(%d) not active\n", i); 1833109644Ssimokawa continue; 1834109644Ssimokawa } 1835109644Ssimokawa if (dbch->xferq.flag & FWXFERQ_PACKET) { 1836109644Ssimokawa fwohci_ircv(sc, dbch, count); 1837109644Ssimokawa } else { 1838103285Sikob fwohci_rbuf_update(sc, i); 1839103285Sikob } 1840103285Sikob } 1841103285Sikob } 1842103285Sikob } 1843103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1844103285Sikob#ifndef ACK_ALL 1845103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1846103285Sikob#endif 1847103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1848109280Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 1849103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1850103285Sikob if((itstat & (1 << i)) != 0){ 1851103285Sikob fwohci_tbuf_update(sc, i); 1852103285Sikob } 1853103285Sikob } 1854103285Sikob } 1855103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1856103285Sikob#ifndef ACK_ALL 1857103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1858103285Sikob#endif 1859103285Sikob#if 0 1860103285Sikob dump_dma(sc, ARRS_CH); 1861103285Sikob dump_db(sc, ARRS_CH); 1862103285Sikob#endif 1863106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1864103285Sikob } 1865103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1866103285Sikob#ifndef ACK_ALL 1867103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1868103285Sikob#endif 1869103285Sikob#if 0 1870103285Sikob dump_dma(sc, ARRQ_CH); 1871103285Sikob dump_db(sc, ARRQ_CH); 1872103285Sikob#endif 1873106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1874103285Sikob } 1875103285Sikob if(stat & OHCI_INT_PHY_SID){ 1876103285Sikob caddr_t buf; 1877103285Sikob int plen; 1878103285Sikob 1879103285Sikob#ifndef ACK_ALL 1880103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1881103285Sikob#endif 1882111074Ssimokawa /* Enable bus reset interrupt */ 1883111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1884111787Ssimokawa /* Allow async. request to us */ 1885111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1886111787Ssimokawa /* XXX insecure ?? */ 1887111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1888111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1889111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1890112523Ssimokawa /* Set ATRetries register */ 1891112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1892103285Sikob/* 1893103285Sikob** Checking whether the node is root or not. If root, turn on 1894103285Sikob** cycle master. 1895103285Sikob*/ 1896103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1897103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1898103285Sikob printf("Bus reset failure\n"); 1899103285Sikob goto sidout; 1900103285Sikob } 1901103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1902103285Sikob printf("CYCLEMASTER mode\n"); 1903103285Sikob OWRITE(sc, OHCI_LNKCTL, 1904103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1905103285Sikob }else{ 1906103285Sikob printf("non CYCLEMASTER mode\n"); 1907103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1908103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1909103285Sikob } 1910103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1911103285Sikob 1912103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1913109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1914109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1915109736Ssimokawa goto sidout; 1916109736Ssimokawa } 1917103285Sikob plen -= 4; /* chop control info */ 1918110195Ssimokawa buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1919103285Sikob if(buf == NULL) goto sidout; 1920108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1921103285Sikob buf, plen); 1922110269Ssimokawa#if 1 1923110269Ssimokawa /* pending all pre-bus_reset packets */ 1924110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1925110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1926110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1927110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1928110798Ssimokawa fw_drain_txq(fc); 1929110269Ssimokawa#endif 1930103285Sikob fw_sidrcv(fc, buf, plen, 0); 1931103285Sikob } 1932103285Sikobsidout: 1933103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1934103285Sikob#ifndef ACK_ALL 1935103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1936103285Sikob#endif 1937103285Sikob fwohci_txd(sc, &(sc->atrq)); 1938103285Sikob } 1939103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1940103285Sikob#ifndef ACK_ALL 1941103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1942103285Sikob#endif 1943103285Sikob fwohci_txd(sc, &(sc->atrs)); 1944103285Sikob } 1945103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1946103285Sikob#ifndef ACK_ALL 1947103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1948103285Sikob#endif 1949103285Sikob device_printf(fc->dev, "posted write error\n"); 1950103285Sikob } 1951103285Sikob if((stat & OHCI_INT_ERR )){ 1952103285Sikob#ifndef ACK_ALL 1953103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1954103285Sikob#endif 1955103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1956103285Sikob } 1957103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1958103285Sikob#ifndef ACK_ALL 1959103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1960103285Sikob#endif 1961103285Sikob device_printf(fc->dev, "phy int\n"); 1962103285Sikob } 1963103285Sikob 1964103285Sikob return; 1965103285Sikob} 1966103285Sikob 1967103285Sikobvoid 1968103285Sikobfwohci_intr(void *arg) 1969103285Sikob{ 1970103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1971111074Ssimokawa u_int32_t stat, bus_reset = 0; 1972103285Sikob 1973103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1974103285Sikob /* polling mode */ 1975103285Sikob return; 1976103285Sikob } 1977103285Sikob 1978103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1979103285Sikob if (stat == 0xffffffff) { 1980103285Sikob device_printf(sc->fc.dev, 1981103285Sikob "device physically ejected?\n"); 1982103285Sikob return; 1983103285Sikob } 1984103285Sikob#ifdef ACK_ALL 1985103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1986103285Sikob#endif 1987111074Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 1988111074Ssimokawa if ((stat & ~bus_reset) == 0) 1989111074Ssimokawa return; 1990111074Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 1991106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1992103285Sikob } 1993103285Sikob} 1994103285Sikob 1995103285Sikobstatic void 1996103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1997103285Sikob{ 1998103285Sikob int s; 1999103285Sikob u_int32_t stat; 2000103285Sikob struct fwohci_softc *sc; 2001103285Sikob 2002103285Sikob 2003103285Sikob sc = (struct fwohci_softc *)fc; 2004103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2005103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2006103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2007103285Sikob#if 0 2008103285Sikob if (!quick) { 2009103285Sikob#else 2010103285Sikob if (1) { 2011103285Sikob#endif 2012103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 2013103285Sikob if (stat == 0) 2014103285Sikob return; 2015103285Sikob if (stat == 0xffffffff) { 2016103285Sikob device_printf(sc->fc.dev, 2017103285Sikob "device physically ejected?\n"); 2018103285Sikob return; 2019103285Sikob } 2020103285Sikob#ifdef ACK_ALL 2021103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2022103285Sikob#endif 2023103285Sikob } 2024103285Sikob s = splfw(); 2025106789Ssimokawa fwohci_intr_body(sc, stat, count); 2026103285Sikob splx(s); 2027103285Sikob} 2028103285Sikob 2029103285Sikobstatic void 2030103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2031103285Sikob{ 2032103285Sikob struct fwohci_softc *sc; 2033103285Sikob 2034103285Sikob sc = (struct fwohci_softc *)fc; 2035107653Ssimokawa if (bootverbose) 2036108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2037103285Sikob if (enable) { 2038103285Sikob sc->intmask |= OHCI_INT_EN; 2039103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2040103285Sikob } else { 2041103285Sikob sc->intmask &= ~OHCI_INT_EN; 2042103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2043103285Sikob } 2044103285Sikob} 2045103285Sikob 2046106790Ssimokawastatic void 2047106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2048103285Sikob{ 2049103285Sikob struct firewire_comm *fc = &sc->fc; 2050109890Ssimokawa volatile struct fwohcidb *db; 2051109890Ssimokawa struct fw_bulkxfer *chunk; 2052109890Ssimokawa struct fw_xferq *it; 2053109890Ssimokawa u_int32_t stat, count; 2054109890Ssimokawa int s, w=0; 2055103285Sikob 2056109890Ssimokawa it = fc->it[dmach]; 2057109890Ssimokawa s = splfw(); /* unnecessary ? */ 2058109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2059109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2060109890Ssimokawa stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2061109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2062109890Ssimokawa count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2063109890Ssimokawa if (stat == 0) 2064109890Ssimokawa break; 2065109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2066109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2067109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2068109890Ssimokawa#if 0 2069109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2070109179Ssimokawa#endif 2071109890Ssimokawa break; 2072109890Ssimokawa default: 2073109423Ssimokawa device_printf(fc->dev, 2074109890Ssimokawa "Isochronous transmit err %02x\n", stat); 2075109890Ssimokawa } 2076109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2077109890Ssimokawa w++; 2078109403Ssimokawa } 2079109890Ssimokawa splx(s); 2080109890Ssimokawa if (w) 2081109890Ssimokawa wakeup(it); 2082103285Sikob} 2083106790Ssimokawa 2084106790Ssimokawastatic void 2085106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2086103285Sikob{ 2087109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2088109890Ssimokawa volatile struct fwohcidb *db; 2089109890Ssimokawa struct fw_bulkxfer *chunk; 2090109890Ssimokawa struct fw_xferq *ir; 2091109890Ssimokawa u_int32_t stat; 2092109890Ssimokawa int s, w=0; 2093109179Ssimokawa 2094109890Ssimokawa ir = fc->ir[dmach]; 2095109890Ssimokawa s = splfw(); 2096109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2097109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2098109890Ssimokawa stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2099109890Ssimokawa if (stat == 0) 2100109890Ssimokawa break; 2101109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2102109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2103109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2104109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2105111942Ssimokawa chunk->resp = 0; 2106109890Ssimokawa break; 2107109890Ssimokawa default: 2108111942Ssimokawa chunk->resp = EINVAL; 2109109890Ssimokawa device_printf(fc->dev, 2110109890Ssimokawa "Isochronous receive err %02x\n", stat); 2111109890Ssimokawa } 2112109890Ssimokawa w++; 2113103285Sikob } 2114109890Ssimokawa splx(s); 2115111942Ssimokawa if (w) { 2116111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2117111942Ssimokawa ir->hand(ir); 2118111942Ssimokawa else 2119111942Ssimokawa wakeup(ir); 2120111942Ssimokawa } 2121103285Sikob} 2122106790Ssimokawa 2123106790Ssimokawavoid 2124106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2125106790Ssimokawa{ 2126103285Sikob u_int32_t off, cntl, stat, cmd, match; 2127103285Sikob 2128103285Sikob if(ch == 0){ 2129103285Sikob off = OHCI_ATQOFF; 2130103285Sikob }else if(ch == 1){ 2131103285Sikob off = OHCI_ATSOFF; 2132103285Sikob }else if(ch == 2){ 2133103285Sikob off = OHCI_ARQOFF; 2134103285Sikob }else if(ch == 3){ 2135103285Sikob off = OHCI_ARSOFF; 2136103285Sikob }else if(ch < IRX_CH){ 2137103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2138103285Sikob }else{ 2139103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2140103285Sikob } 2141103285Sikob cntl = stat = OREAD(sc, off); 2142103285Sikob cmd = OREAD(sc, off + 0xc); 2143103285Sikob match = OREAD(sc, off + 0x10); 2144103285Sikob 2145103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2146103285Sikob ch, 2147103285Sikob cntl, 2148103285Sikob stat, 2149103285Sikob cmd, 2150103285Sikob match); 2151103285Sikob stat &= 0xffff ; 2152103285Sikob if(stat & 0xff00){ 2153103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2154103285Sikob ch, 2155103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2156103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2157103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2158103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2159103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2160103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2161103285Sikob fwohcicode[stat & 0x1f], 2162103285Sikob stat & 0x1f 2163103285Sikob ); 2164103285Sikob }else{ 2165103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2166103285Sikob } 2167103285Sikob} 2168106790Ssimokawa 2169106790Ssimokawavoid 2170106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2171106790Ssimokawa{ 2172103285Sikob struct fwohci_dbch *dbch; 2173103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 2174103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2175103285Sikob int idb, jdb; 2176103285Sikob u_int32_t cmd, off; 2177103285Sikob if(ch == 0){ 2178103285Sikob off = OHCI_ATQOFF; 2179103285Sikob dbch = &sc->atrq; 2180103285Sikob }else if(ch == 1){ 2181103285Sikob off = OHCI_ATSOFF; 2182103285Sikob dbch = &sc->atrs; 2183103285Sikob }else if(ch == 2){ 2184103285Sikob off = OHCI_ARQOFF; 2185103285Sikob dbch = &sc->arrq; 2186103285Sikob }else if(ch == 3){ 2187103285Sikob off = OHCI_ARSOFF; 2188103285Sikob dbch = &sc->arrs; 2189103285Sikob }else if(ch < IRX_CH){ 2190103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2191103285Sikob dbch = &sc->it[ch - ITX_CH]; 2192103285Sikob }else { 2193103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2194103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2195103285Sikob } 2196103285Sikob cmd = OREAD(sc, off + 0xc); 2197103285Sikob 2198103285Sikob if( dbch->ndb == 0 ){ 2199103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2200103285Sikob return; 2201103285Sikob } 2202103285Sikob pp = dbch->top; 2203103285Sikob prev = pp->db; 2204103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2205103285Sikob if(pp == NULL){ 2206103285Sikob curr = NULL; 2207103285Sikob goto outdb; 2208103285Sikob } 2209103285Sikob cp = STAILQ_NEXT(pp, link); 2210103285Sikob if(cp == NULL){ 2211103285Sikob curr = NULL; 2212103285Sikob goto outdb; 2213103285Sikob } 2214103285Sikob np = STAILQ_NEXT(cp, link); 2215103285Sikob if(cp == NULL) break; 2216103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2217103285Sikob if((cmd & 0xfffffff0) 2218103285Sikob == vtophys(&(cp->db[jdb]))){ 2219103285Sikob curr = cp->db; 2220103285Sikob if(np != NULL){ 2221103285Sikob next = np->db; 2222103285Sikob }else{ 2223103285Sikob next = NULL; 2224103285Sikob } 2225103285Sikob goto outdb; 2226103285Sikob } 2227103285Sikob } 2228103285Sikob pp = STAILQ_NEXT(pp, link); 2229103285Sikob prev = pp->db; 2230103285Sikob } 2231103285Sikoboutdb: 2232103285Sikob if( curr != NULL){ 2233103285Sikob printf("Prev DB %d\n", ch); 2234103285Sikob print_db(prev, ch, dbch->ndesc); 2235103285Sikob printf("Current DB %d\n", ch); 2236103285Sikob print_db(curr, ch, dbch->ndesc); 2237103285Sikob printf("Next DB %d\n", ch); 2238103285Sikob print_db(next, ch, dbch->ndesc); 2239103285Sikob }else{ 2240103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2241103285Sikob } 2242103285Sikob return; 2243103285Sikob} 2244106790Ssimokawa 2245106790Ssimokawavoid 2246106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2247106790Ssimokawa{ 2248103285Sikob fwohcireg_t stat; 2249103285Sikob int i, key; 2250103285Sikob 2251103285Sikob if(db == NULL){ 2252103285Sikob printf("No Descriptor is found\n"); 2253103285Sikob return; 2254103285Sikob } 2255103285Sikob 2256103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2257103285Sikob ch, 2258103285Sikob "Current", 2259103285Sikob "OP ", 2260103285Sikob "KEY", 2261103285Sikob "INT", 2262103285Sikob "BR ", 2263103285Sikob "len", 2264103285Sikob "Addr", 2265103285Sikob "Depend", 2266103285Sikob "Stat", 2267103285Sikob "Cnt"); 2268103285Sikob for( i = 0 ; i <= max ; i ++){ 2269109892Ssimokawa key = db[i].db.desc.control & OHCI_KEY_MASK; 2270108712Ssimokawa#if __FreeBSD_version >= 500000 2271106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2272108712Ssimokawa#else 2273108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2274108712Ssimokawa#endif 2275103285Sikob vtophys(&db[i]), 2276109892Ssimokawa dbcode[(db[i].db.desc.control >> 12) & 0xf], 2277109892Ssimokawa dbkey[(db[i].db.desc.control >> 8) & 0x7], 2278109892Ssimokawa dbcond[(db[i].db.desc.control >> 4) & 0x3], 2279109892Ssimokawa dbcond[(db[i].db.desc.control >> 2) & 0x3], 2280109892Ssimokawa db[i].db.desc.reqcount, 2281103285Sikob db[i].db.desc.addr, 2282103285Sikob db[i].db.desc.depend, 2283103285Sikob db[i].db.desc.status, 2284103285Sikob db[i].db.desc.count); 2285103285Sikob stat = db[i].db.desc.status; 2286103285Sikob if(stat & 0xff00){ 2287103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2288103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2289103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2290103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2291103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2292103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2293103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2294103285Sikob fwohcicode[stat & 0x1f], 2295103285Sikob stat & 0x1f 2296103285Sikob ); 2297103285Sikob }else{ 2298103285Sikob printf(" Nostat\n"); 2299103285Sikob } 2300103285Sikob if(key == OHCI_KEY_ST2 ){ 2301103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2302103285Sikob db[i+1].db.immed[0], 2303103285Sikob db[i+1].db.immed[1], 2304103285Sikob db[i+1].db.immed[2], 2305103285Sikob db[i+1].db.immed[3]); 2306103285Sikob } 2307103285Sikob if(key == OHCI_KEY_DEVICE){ 2308103285Sikob return; 2309103285Sikob } 2310109892Ssimokawa if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2311103285Sikob == OHCI_BRANCH_ALWAYS){ 2312103285Sikob return; 2313103285Sikob } 2314109892Ssimokawa if((db[i].db.desc.control & OHCI_CMD_MASK) 2315103285Sikob == OHCI_OUTPUT_LAST){ 2316103285Sikob return; 2317103285Sikob } 2318109892Ssimokawa if((db[i].db.desc.control & OHCI_CMD_MASK) 2319103285Sikob == OHCI_INPUT_LAST){ 2320103285Sikob return; 2321103285Sikob } 2322103285Sikob if(key == OHCI_KEY_ST2 ){ 2323103285Sikob i++; 2324103285Sikob } 2325103285Sikob } 2326103285Sikob return; 2327103285Sikob} 2328106790Ssimokawa 2329106790Ssimokawavoid 2330106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2331103285Sikob{ 2332103285Sikob struct fwohci_softc *sc; 2333103285Sikob u_int32_t fun; 2334103285Sikob 2335110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2336103285Sikob sc = (struct fwohci_softc *)fc; 2337108276Ssimokawa 2338108276Ssimokawa /* 2339108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2340108276Ssimokawa * shouldn't became the root node. 2341108276Ssimokawa */ 2342103285Sikob#if 1 2343103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2344109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2345103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2346109280Ssimokawa#else /* Short bus reset */ 2347103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2348109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2349103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2350103285Sikob#endif 2351103285Sikob} 2352106790Ssimokawa 2353106790Ssimokawavoid 2354106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2355103285Sikob{ 2356103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2357103285Sikob struct fwohci_dbch *dbch; 2358109892Ssimokawa volatile struct fwohcidb *db; 2359103285Sikob struct fw_pkt *fp; 2360103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2361103285Sikob unsigned short chtag; 2362103285Sikob int idb; 2363103285Sikob 2364103285Sikob dbch = &sc->it[dmach]; 2365103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2366103285Sikob 2367103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2368103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2369103285Sikob/* 2370103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2371103285Sikob*/ 2372103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2373109892Ssimokawa db = db_tr->db; 2374109892Ssimokawa#if 0 2375109892Ssimokawa db[0].db.desc.control 2376109892Ssimokawa = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2377109892Ssimokawa db[0].db.desc.reqcount = 8; 2378109892Ssimokawa#endif 2379103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2380109892Ssimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2381103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2382103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2383103285Sikob ohcifp->mode.stream.chtag = chtag; 2384103285Sikob ohcifp->mode.stream.tcode = 0xa; 2385109890Ssimokawa ohcifp->mode.stream.spd = 0; 2386103285Sikob 2387109892Ssimokawa db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2388109892Ssimokawa db[2].db.desc.status = 0; 2389109892Ssimokawa db[2].db.desc.count = 0; 2390109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2391109892Ssimokawa db[2].db.desc.control = OHCI_OUTPUT_LAST 2392103285Sikob | OHCI_UPDATE 2393109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2394109892Ssimokawa db[0].db.desc.depend = 2395109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2396109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2397109892Ssimokawa#else 2398109892Ssimokawa db[0].db.desc.depend |= dbch->ndesc; 2399109892Ssimokawa db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2400109892Ssimokawa#endif 2401103285Sikob bulkxfer->end = (caddr_t)db_tr; 2402103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2403103285Sikob } 2404109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2405109892Ssimokawa db[0].db.desc.depend &= ~0xf; 2406109892Ssimokawa db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2407109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2408109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2409109280Ssimokawa /* OHCI 1.1 and above */ 2410109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2411109892Ssimokawa#endif 2412109892Ssimokawa/* 2413103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2414103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2415103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2416103285Sikob*/ 2417103285Sikob return; 2418103285Sikob} 2419106790Ssimokawa 2420106790Ssimokawastatic int 2421106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2422106790Ssimokawa int mode, void *buf) 2423103285Sikob{ 2424103285Sikob volatile struct fwohcidb *db = db_tr->db; 2425103285Sikob int err = 0; 2426103285Sikob if(buf == 0){ 2427103285Sikob err = EINVAL; 2428103285Sikob return err; 2429103285Sikob } 2430103285Sikob db_tr->buf = buf; 2431103285Sikob db_tr->dbcnt = 3; 2432103285Sikob db_tr->dummy = NULL; 2433103285Sikob 2434109892Ssimokawa db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2435109892Ssimokawa db[0].db.desc.reqcount = 8; 2436103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2437109892Ssimokawa db[2].db.desc.control = 2438109892Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2439109892Ssimokawa#if 1 2440103285Sikob db[0].db.desc.status = 0; 2441103285Sikob db[0].db.desc.count = 0; 2442103285Sikob db[2].db.desc.status = 0; 2443103285Sikob db[2].db.desc.count = 0; 2444109892Ssimokawa#endif 2445103285Sikob if( mode & FWXFERQ_STREAM ){ 2446103285Sikob if(mode & FWXFERQ_PACKET ){ 2447109892Ssimokawa db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2448103285Sikob } 2449109892Ssimokawa } else { 2450109892Ssimokawa printf("fwohci_add_tx_buf: who calls me?"); 2451103285Sikob } 2452103285Sikob return 1; 2453103285Sikob} 2454106790Ssimokawa 2455106790Ssimokawaint 2456106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2457106790Ssimokawa void *buf, void *dummy) 2458103285Sikob{ 2459103285Sikob volatile struct fwohcidb *db = db_tr->db; 2460103285Sikob int i; 2461103285Sikob void *dbuf[2]; 2462103285Sikob int dsiz[2]; 2463103285Sikob 2464103285Sikob if(buf == 0){ 2465110195Ssimokawa buf = malloc(size, M_FW, M_NOWAIT); 2466103285Sikob if(buf == NULL) return 0; 2467103285Sikob db_tr->buf = buf; 2468103285Sikob db_tr->dbcnt = 1; 2469103285Sikob db_tr->dummy = NULL; 2470103285Sikob dsiz[0] = size; 2471103285Sikob dbuf[0] = buf; 2472103285Sikob }else if(dummy == NULL){ 2473103285Sikob db_tr->buf = buf; 2474103285Sikob db_tr->dbcnt = 1; 2475103285Sikob db_tr->dummy = NULL; 2476103285Sikob dsiz[0] = size; 2477103285Sikob dbuf[0] = buf; 2478103285Sikob }else{ 2479103285Sikob db_tr->buf = buf; 2480103285Sikob db_tr->dbcnt = 2; 2481103285Sikob db_tr->dummy = dummy; 2482103285Sikob dsiz[0] = sizeof(u_int32_t); 2483103285Sikob dsiz[1] = size; 2484103285Sikob dbuf[0] = dummy; 2485103285Sikob dbuf[1] = buf; 2486103285Sikob } 2487103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2488103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2489109892Ssimokawa db[i].db.desc.control = OHCI_INPUT_MORE; 2490109892Ssimokawa db[i].db.desc.reqcount = dsiz[i]; 2491103285Sikob if( mode & FWXFERQ_STREAM ){ 2492109892Ssimokawa db[i].db.desc.control |= OHCI_UPDATE; 2493103285Sikob } 2494103285Sikob db[i].db.desc.status = 0; 2495103285Sikob db[i].db.desc.count = dsiz[i]; 2496103285Sikob } 2497103285Sikob if( mode & FWXFERQ_STREAM ){ 2498109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2499103285Sikob if(mode & FWXFERQ_PACKET ){ 2500109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control 2501103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2502103285Sikob } 2503103285Sikob } 2504109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2505103285Sikob return 1; 2506103285Sikob} 2507106790Ssimokawa 2508106790Ssimokawastatic void 2509106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2510103285Sikob{ 2511103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2512103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2513103285Sikob int z = 1; 2514103285Sikob struct fw_pkt *fp; 2515103285Sikob u_int8_t *ld; 2516103285Sikob u_int32_t off = NULL; 2517103285Sikob u_int32_t stat; 2518103285Sikob u_int32_t *qld; 2519103285Sikob u_int32_t reg; 2520103285Sikob u_int spd; 2521103285Sikob u_int dmach; 2522103285Sikob int len, i, plen; 2523103285Sikob caddr_t buf; 2524103285Sikob 2525103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2526103285Sikob if( &sc->ir[dmach] == dbch){ 2527103285Sikob off = OHCI_IROFF(dmach); 2528103285Sikob break; 2529103285Sikob } 2530103285Sikob } 2531103285Sikob if(off == NULL){ 2532103285Sikob return; 2533103285Sikob } 2534103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2535103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2536103285Sikob return; 2537103285Sikob } 2538103285Sikob 2539103285Sikob odb_tr = NULL; 2540103285Sikob db_tr = dbch->top; 2541103285Sikob i = 0; 2542103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2543106789Ssimokawa if (count >= 0 && count-- == 0) 2544106789Ssimokawa break; 2545103285Sikob ld = (u_int8_t *)db_tr->buf; 2546103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2547103285Sikob /* skip timeStamp */ 2548103285Sikob ld += sizeof(struct fwohci_trailer); 2549103285Sikob } 2550103285Sikob qld = (u_int32_t *)ld; 2551103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2552103285Sikob/* 2553103285Sikob{ 2554103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2555103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2556103285Sikob} 2557103285Sikob*/ 2558103285Sikob fp=(struct fw_pkt *)ld; 2559103285Sikob qld[0] = htonl(qld[0]); 2560103285Sikob plen = sizeof(struct fw_isohdr) 2561103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2562103285Sikob ld += plen; 2563103285Sikob len -= plen; 2564103285Sikob buf = db_tr->buf; 2565103285Sikob db_tr->buf = NULL; 2566103285Sikob stat = reg & 0x1f; 2567103285Sikob spd = reg & 0x3; 2568103285Sikob switch(stat){ 2569103285Sikob case FWOHCIEV_ACKCOMPL: 2570103285Sikob case FWOHCIEV_ACKPEND: 2571103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2572103285Sikob break; 2573103285Sikob default: 2574110195Ssimokawa free(buf, M_FW); 2575103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2576103285Sikob break; 2577103285Sikob } 2578103285Sikob i++; 2579103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2580103285Sikob dbch->xferq.flag, 0, NULL); 2581103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2582103285Sikob if(dbch->pdb_tr != NULL){ 2583103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2584103285Sikob } else { 2585103285Sikob /* XXX should be rewritten in better way */ 2586103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2587103285Sikob } 2588103285Sikob dbch->pdb_tr = db_tr; 2589103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2590103285Sikob } 2591103285Sikob dbch->top = db_tr; 2592103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2593103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2594103285Sikob return; 2595103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2596103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2597103285Sikob dbch->top = db_tr; 2598103285Sikob fwohci_irx_enable(fc, dmach); 2599103285Sikob} 2600103285Sikob 2601110798Ssimokawa#define PLEN(x) roundup2(ntohs(x), sizeof(u_int32_t)) 2602103285Sikobstatic int 2603110798Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp, int hlen) 2604103285Sikob{ 2605110798Ssimokawa int i, r; 2606103285Sikob 2607103285Sikob for( i = 4; i < hlen ; i+=4){ 2608103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2609103285Sikob } 2610103285Sikob 2611103285Sikob switch(fp->mode.common.tcode){ 2612103285Sikob case FWTCODE_RREQQ: 2613110798Ssimokawa r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2614110798Ssimokawa break; 2615103285Sikob case FWTCODE_WRES: 2616110798Ssimokawa r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2617110798Ssimokawa break; 2618103285Sikob case FWTCODE_WREQQ: 2619110798Ssimokawa r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2620110798Ssimokawa break; 2621103285Sikob case FWTCODE_RREQB: 2622110798Ssimokawa r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2623110798Ssimokawa break; 2624103285Sikob case FWTCODE_RRESQ: 2625110798Ssimokawa r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2626110798Ssimokawa break; 2627103285Sikob case FWTCODE_WREQB: 2628110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2629103285Sikob + sizeof(u_int32_t); 2630110798Ssimokawa break; 2631103285Sikob case FWTCODE_LREQ: 2632110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2633103285Sikob + sizeof(u_int32_t); 2634110798Ssimokawa break; 2635103285Sikob case FWTCODE_RRESB: 2636110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2637103285Sikob + sizeof(u_int32_t); 2638110798Ssimokawa break; 2639103285Sikob case FWTCODE_LRES: 2640110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2641103285Sikob + sizeof(u_int32_t); 2642110798Ssimokawa break; 2643103285Sikob case FWOHCITCODE_PHY: 2644110798Ssimokawa r = 16; 2645110798Ssimokawa break; 2646110798Ssimokawa default: 2647110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2648110798Ssimokawa fp->mode.common.tcode); 2649110798Ssimokawa r = 0; 2650103285Sikob } 2651110798Ssimokawa if (r > dbch->xferq.psize) { 2652110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2653110798Ssimokawa /* panic ? */ 2654110798Ssimokawa } 2655110798Ssimokawa return r; 2656103285Sikob} 2657103285Sikob 2658106790Ssimokawastatic void 2659106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2660103285Sikob{ 2661103285Sikob struct fwohcidb_tr *db_tr; 2662103285Sikob int z = 1; 2663103285Sikob struct fw_pkt *fp; 2664103285Sikob u_int8_t *ld; 2665103285Sikob u_int32_t stat, off; 2666103285Sikob u_int spd; 2667103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2668103285Sikob int s; 2669103285Sikob caddr_t buf; 2670103285Sikob int resCount; 2671103285Sikob 2672103285Sikob if(&sc->arrq == dbch){ 2673103285Sikob off = OHCI_ARQOFF; 2674103285Sikob }else if(&sc->arrs == dbch){ 2675103285Sikob off = OHCI_ARSOFF; 2676103285Sikob }else{ 2677103285Sikob return; 2678103285Sikob } 2679103285Sikob 2680103285Sikob s = splfw(); 2681103285Sikob db_tr = dbch->top; 2682103285Sikob pcnt = 0; 2683103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2684103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2685103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2686103285Sikob resCount = db_tr->db[0].db.desc.count; 2687103285Sikob len = dbch->xferq.psize - resCount 2688103285Sikob - dbch->buf_offset; 2689103285Sikob while (len > 0 ) { 2690106789Ssimokawa if (count >= 0 && count-- == 0) 2691106789Ssimokawa goto out; 2692103285Sikob if(dbch->frag.buf != NULL){ 2693103285Sikob buf = dbch->frag.buf; 2694103285Sikob if (dbch->frag.plen < 0) { 2695103285Sikob /* incomplete header */ 2696103285Sikob int hlen; 2697103285Sikob 2698103285Sikob hlen = - dbch->frag.plen; 2699103285Sikob rlen = hlen - dbch->frag.len; 2700103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2701103285Sikob ld += rlen; 2702103285Sikob len -= rlen; 2703103285Sikob dbch->frag.len += rlen; 2704103285Sikob#if 0 2705103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2706103285Sikob#endif 2707103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2708103285Sikob dbch->frag.plen 2709110798Ssimokawa = fwohci_get_plen(sc, 2710110798Ssimokawa dbch, fp, hlen); 2711103285Sikob if (dbch->frag.plen == 0) 2712103285Sikob goto out; 2713103285Sikob } 2714103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2715103285Sikob#if 0 2716103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2717103285Sikob#endif 2718103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2719103285Sikob rlen); 2720103285Sikob ld += rlen; 2721103285Sikob len -= rlen; 2722103285Sikob plen = dbch->frag.plen; 2723103285Sikob dbch->frag.buf = NULL; 2724103285Sikob dbch->frag.plen = 0; 2725103285Sikob dbch->frag.len = 0; 2726103285Sikob poff = 0; 2727103285Sikob }else{ 2728103285Sikob fp=(struct fw_pkt *)ld; 2729103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2730103285Sikob switch(fp->mode.common.tcode){ 2731103285Sikob case FWTCODE_RREQQ: 2732103285Sikob case FWTCODE_WRES: 2733103285Sikob case FWTCODE_WREQQ: 2734103285Sikob case FWTCODE_RRESQ: 2735103285Sikob case FWOHCITCODE_PHY: 2736103285Sikob hlen = 12; 2737103285Sikob break; 2738103285Sikob case FWTCODE_RREQB: 2739103285Sikob case FWTCODE_WREQB: 2740103285Sikob case FWTCODE_LREQ: 2741103285Sikob case FWTCODE_RRESB: 2742103285Sikob case FWTCODE_LRES: 2743103285Sikob hlen = 16; 2744103285Sikob break; 2745103285Sikob default: 2746103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2747103285Sikob goto out; 2748103285Sikob } 2749103285Sikob if (len >= hlen) { 2750110798Ssimokawa plen = fwohci_get_plen(sc, 2751110798Ssimokawa dbch, fp, hlen); 2752103285Sikob if (plen == 0) 2753103285Sikob goto out; 2754103285Sikob plen = (plen + 3) & ~3; 2755103285Sikob len -= plen; 2756103285Sikob } else { 2757103285Sikob plen = -hlen; 2758103285Sikob len -= hlen; 2759103285Sikob } 2760103285Sikob if(resCount > 0 || len > 0){ 2761110798Ssimokawa buf = malloc(plen, M_FW, M_NOWAIT); 2762103285Sikob if(buf == NULL){ 2763103285Sikob printf("cannot malloc!\n"); 2764110195Ssimokawa free(db_tr->buf, M_FW); 2765103285Sikob goto out; 2766103285Sikob } 2767103285Sikob bcopy(ld, buf, plen); 2768103285Sikob poff = 0; 2769103285Sikob dbch->frag.buf = NULL; 2770103285Sikob dbch->frag.plen = 0; 2771103285Sikob dbch->frag.len = 0; 2772103285Sikob }else if(len < 0){ 2773103285Sikob dbch->frag.buf = db_tr->buf; 2774103285Sikob if (plen < 0) { 2775103285Sikob#if 0 2776103285Sikob printf("plen < 0:" 2777103285Sikob "hlen: %d len: %d\n", 2778103285Sikob hlen, len); 2779103285Sikob#endif 2780103285Sikob dbch->frag.len = hlen + len; 2781103285Sikob dbch->frag.plen = -hlen; 2782103285Sikob } else { 2783103285Sikob dbch->frag.len = plen + len; 2784103285Sikob dbch->frag.plen = plen; 2785103285Sikob } 2786103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2787103285Sikob buf = NULL; 2788103285Sikob }else{ 2789103285Sikob buf = db_tr->buf; 2790103285Sikob poff = ld - (u_int8_t *)buf; 2791103285Sikob dbch->frag.buf = NULL; 2792103285Sikob dbch->frag.plen = 0; 2793103285Sikob dbch->frag.len = 0; 2794103285Sikob } 2795103285Sikob ld += plen; 2796103285Sikob } 2797103285Sikob if( buf != NULL){ 2798103285Sikob/* DMA result-code will be written at the tail of packet */ 2799103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2800103285Sikob spd = (stat >> 5) & 0x3; 2801103285Sikob stat &= 0x1f; 2802103285Sikob switch(stat){ 2803103285Sikob case FWOHCIEV_ACKPEND: 2804110577Ssimokawa#if 0 2805112523Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2806103285Sikob#endif 2807103285Sikob /* fall through */ 2808103285Sikob case FWOHCIEV_ACKCOMPL: 2809103285Sikob if( poff != 0 ) 2810103285Sikob bcopy(buf+poff, buf, plen - 4); 2811103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2812103285Sikob break; 2813103285Sikob case FWOHCIEV_BUSRST: 2814110195Ssimokawa free(buf, M_FW); 2815103285Sikob if (sc->fc.status != FWBUSRESET) 2816103285Sikob printf("got BUSRST packet!?\n"); 2817103285Sikob break; 2818103285Sikob default: 2819103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2820103285Sikob#if 0 /* XXX */ 2821103285Sikob goto out; 2822103285Sikob#endif 2823103285Sikob break; 2824103285Sikob } 2825103285Sikob } 2826103285Sikob pcnt ++; 2827103285Sikob }; 2828103285Sikobout: 2829103285Sikob if (resCount == 0) { 2830103285Sikob /* done on this buffer */ 2831103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2832103285Sikob dbch->xferq.flag, 0, NULL); 2833103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2834103285Sikob dbch->bottom = db_tr; 2835103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2836103285Sikob dbch->top = db_tr; 2837103285Sikob dbch->buf_offset = 0; 2838103285Sikob } else { 2839103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2840103285Sikob break; 2841103285Sikob } 2842103285Sikob /* XXX make sure DMA is not dead */ 2843103285Sikob } 2844103285Sikob#if 0 2845103285Sikob if (pcnt < 1) 2846103285Sikob printf("fwohci_arcv: no packets\n"); 2847103285Sikob#endif 2848103285Sikob splx(s); 2849103285Sikob} 2850